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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
1d737c8a | 21 | #include "mmu.h" |
7837699f | 22 | #include "i8254.h" |
37817f29 | 23 | #include "tss.h" |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
26eef70c | 25 | #include "x86.h" |
00b27a3e | 26 | #include "cpuid.h" |
474a5bb9 | 27 | #include "pmu.h" |
e83d5887 | 28 | #include "hyperv.h" |
313a3dc7 | 29 | |
18068523 | 30 | #include <linux/clocksource.h> |
4d5c5d0f | 31 | #include <linux/interrupt.h> |
313a3dc7 CO |
32 | #include <linux/kvm.h> |
33 | #include <linux/fs.h> | |
34 | #include <linux/vmalloc.h> | |
1767e931 PG |
35 | #include <linux/export.h> |
36 | #include <linux/moduleparam.h> | |
0de10343 | 37 | #include <linux/mman.h> |
2bacc55c | 38 | #include <linux/highmem.h> |
19de40a8 | 39 | #include <linux/iommu.h> |
62c476c7 | 40 | #include <linux/intel-iommu.h> |
c8076604 | 41 | #include <linux/cpufreq.h> |
18863bdd | 42 | #include <linux/user-return-notifier.h> |
a983fb23 | 43 | #include <linux/srcu.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
ff9d07a0 | 45 | #include <linux/perf_event.h> |
7bee342a | 46 | #include <linux/uaccess.h> |
af585b92 | 47 | #include <linux/hash.h> |
a1b60c1c | 48 | #include <linux/pci.h> |
16e8d74d MT |
49 | #include <linux/timekeeper_internal.h> |
50 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
51 | #include <linux/kvm_irqfd.h> |
52 | #include <linux/irqbypass.h> | |
3905f9ad | 53 | #include <linux/sched/stat.h> |
0c5f81da | 54 | #include <linux/sched/isolation.h> |
d0ec49d4 | 55 | #include <linux/mem_encrypt.h> |
3905f9ad | 56 | |
aec51dc4 | 57 | #include <trace/events/kvm.h> |
2ed152af | 58 | |
24f1e32c | 59 | #include <asm/debugreg.h> |
d825ed0a | 60 | #include <asm/msr.h> |
a5f61300 | 61 | #include <asm/desc.h> |
890ca9ae | 62 | #include <asm/mce.h> |
f89e32e0 | 63 | #include <linux/kernel_stat.h> |
78f7f1e5 | 64 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 65 | #include <asm/pvclock.h> |
217fc9cf | 66 | #include <asm/div64.h> |
efc64404 | 67 | #include <asm/irq_remapping.h> |
b0c39dc6 | 68 | #include <asm/mshyperv.h> |
0092e434 | 69 | #include <asm/hypervisor.h> |
bf8c55d8 | 70 | #include <asm/intel_pt.h> |
dd2cb348 | 71 | #include <clocksource/hyperv_timer.h> |
043405e1 | 72 | |
d1898b73 DH |
73 | #define CREATE_TRACE_POINTS |
74 | #include "trace.h" | |
75 | ||
313a3dc7 | 76 | #define MAX_IO_MSRS 256 |
890ca9ae | 77 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
78 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
79 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 80 | |
0f65dd70 AK |
81 | #define emul_to_vcpu(ctxt) \ |
82 | container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) | |
83 | ||
50a37eb4 JR |
84 | /* EFER defaults: |
85 | * - enable syscall per default because its emulated by KVM | |
86 | * - enable LME and LMA per default on 64 bit KVM | |
87 | */ | |
88 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
89 | static |
90 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 91 | #else |
1260edbe | 92 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 93 | #endif |
313a3dc7 | 94 | |
ba1389b7 AK |
95 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
96 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 97 | |
c519265f RK |
98 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
99 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 100 | |
cb142eb7 | 101 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 102 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 103 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 104 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
105 | static void store_regs(struct kvm_vcpu *vcpu); |
106 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 107 | |
893590c7 | 108 | struct kvm_x86_ops *kvm_x86_ops __read_mostly; |
5fdbf976 | 109 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 110 | |
893590c7 | 111 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 112 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 113 | |
fab0aa3b EM |
114 | static bool __read_mostly report_ignored_msrs = true; |
115 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
116 | ||
4c27625b | 117 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
118 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
119 | ||
630994b3 MT |
120 | static bool __read_mostly kvmclock_periodic_sync = true; |
121 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
122 | ||
893590c7 | 123 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 124 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 125 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 126 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
127 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
128 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
129 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
130 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
131 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
132 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 133 | |
cc578287 | 134 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 135 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
136 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
137 | ||
c3941d9e SC |
138 | /* |
139 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
140 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
141 | * advancement entirely. Any other value is used as-is and disables adaptive | |
142 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
143 | */ | |
144 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 145 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 146 | |
52004014 FW |
147 | static bool __read_mostly vector_hashing = true; |
148 | module_param(vector_hashing, bool, S_IRUGO); | |
149 | ||
c4ae60e4 LA |
150 | bool __read_mostly enable_vmware_backdoor = false; |
151 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
152 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
153 | ||
6c86eedc WL |
154 | static bool __read_mostly force_emulation_prefix = false; |
155 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
156 | ||
0c5f81da WL |
157 | int __read_mostly pi_inject_timer = -1; |
158 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
159 | ||
18863bdd AK |
160 | #define KVM_NR_SHARED_MSRS 16 |
161 | ||
162 | struct kvm_shared_msrs_global { | |
163 | int nr; | |
2bf78fa7 | 164 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
165 | }; |
166 | ||
167 | struct kvm_shared_msrs { | |
168 | struct user_return_notifier urn; | |
169 | bool registered; | |
2bf78fa7 SY |
170 | struct kvm_shared_msr_values { |
171 | u64 host; | |
172 | u64 curr; | |
173 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
174 | }; |
175 | ||
176 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 177 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 178 | |
417bc304 | 179 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
180 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
181 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
182 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
183 | { "invlpg", VCPU_STAT(invlpg) }, | |
184 | { "exits", VCPU_STAT(exits) }, | |
185 | { "io_exits", VCPU_STAT(io_exits) }, | |
186 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
187 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
188 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 189 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 | 190 | { "halt_exits", VCPU_STAT(halt_exits) }, |
f7819512 | 191 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, |
62bea5bf | 192 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, |
3491caf2 | 193 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, |
ba1389b7 | 194 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, |
f11c3a8d | 195 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
196 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
197 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
198 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
ba1389b7 AK |
199 | { "fpu_reload", VCPU_STAT(fpu_reload) }, |
200 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
201 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 202 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 203 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
0f1e261e | 204 | { "req_event", VCPU_STAT(req_event) }, |
c595ceee | 205 | { "l1d_flush", VCPU_STAT(l1d_flush) }, |
4cee5764 AK |
206 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
207 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
208 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
209 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
210 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
211 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 212 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 213 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 214 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 215 | { "largepages", VM_STAT(lpages) }, |
f3414bc7 DM |
216 | { "max_mmu_page_hash_collisions", |
217 | VM_STAT(max_mmu_page_hash_collisions) }, | |
417bc304 HB |
218 | { NULL } |
219 | }; | |
220 | ||
2acf923e DC |
221 | u64 __read_mostly host_xcr0; |
222 | ||
b666a4b6 MO |
223 | struct kmem_cache *x86_fpu_cache; |
224 | EXPORT_SYMBOL_GPL(x86_fpu_cache); | |
225 | ||
b6785def | 226 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 227 | |
af585b92 GN |
228 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
229 | { | |
230 | int i; | |
231 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) | |
232 | vcpu->arch.apf.gfns[i] = ~0; | |
233 | } | |
234 | ||
18863bdd AK |
235 | static void kvm_on_user_return(struct user_return_notifier *urn) |
236 | { | |
237 | unsigned slot; | |
18863bdd AK |
238 | struct kvm_shared_msrs *locals |
239 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 240 | struct kvm_shared_msr_values *values; |
1650b4eb IA |
241 | unsigned long flags; |
242 | ||
243 | /* | |
244 | * Disabling irqs at this point since the following code could be | |
245 | * interrupted and executed through kvm_arch_hardware_disable() | |
246 | */ | |
247 | local_irq_save(flags); | |
248 | if (locals->registered) { | |
249 | locals->registered = false; | |
250 | user_return_notifier_unregister(urn); | |
251 | } | |
252 | local_irq_restore(flags); | |
18863bdd | 253 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { |
2bf78fa7 SY |
254 | values = &locals->values[slot]; |
255 | if (values->host != values->curr) { | |
256 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
257 | values->curr = values->host; | |
18863bdd AK |
258 | } |
259 | } | |
18863bdd AK |
260 | } |
261 | ||
2bf78fa7 | 262 | static void shared_msr_update(unsigned slot, u32 msr) |
18863bdd | 263 | { |
18863bdd | 264 | u64 value; |
013f6a5d MT |
265 | unsigned int cpu = smp_processor_id(); |
266 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
18863bdd | 267 | |
2bf78fa7 SY |
268 | /* only read, and nobody should modify it at this time, |
269 | * so don't need lock */ | |
270 | if (slot >= shared_msrs_global.nr) { | |
271 | printk(KERN_ERR "kvm: invalid MSR slot!"); | |
272 | return; | |
273 | } | |
274 | rdmsrl_safe(msr, &value); | |
275 | smsr->values[slot].host = value; | |
276 | smsr->values[slot].curr = value; | |
277 | } | |
278 | ||
279 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
280 | { | |
0123be42 | 281 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 282 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
283 | if (slot >= shared_msrs_global.nr) |
284 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
285 | } |
286 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
287 | ||
288 | static void kvm_shared_msr_cpu_online(void) | |
289 | { | |
290 | unsigned i; | |
18863bdd AK |
291 | |
292 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
2bf78fa7 | 293 | shared_msr_update(i, shared_msrs_global.msrs[i]); |
18863bdd AK |
294 | } |
295 | ||
8b3c3104 | 296 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 297 | { |
013f6a5d MT |
298 | unsigned int cpu = smp_processor_id(); |
299 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 300 | int err; |
18863bdd | 301 | |
2bf78fa7 | 302 | if (((value ^ smsr->values[slot].curr) & mask) == 0) |
8b3c3104 | 303 | return 0; |
2bf78fa7 | 304 | smsr->values[slot].curr = value; |
8b3c3104 AH |
305 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
306 | if (err) | |
307 | return 1; | |
308 | ||
18863bdd AK |
309 | if (!smsr->registered) { |
310 | smsr->urn.on_user_return = kvm_on_user_return; | |
311 | user_return_notifier_register(&smsr->urn); | |
312 | smsr->registered = true; | |
313 | } | |
8b3c3104 | 314 | return 0; |
18863bdd AK |
315 | } |
316 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
317 | ||
13a34e06 | 318 | static void drop_user_return_notifiers(void) |
3548bab5 | 319 | { |
013f6a5d MT |
320 | unsigned int cpu = smp_processor_id(); |
321 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
322 | |
323 | if (smsr->registered) | |
324 | kvm_on_user_return(&smsr->urn); | |
325 | } | |
326 | ||
6866b83e CO |
327 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
328 | { | |
8a5a87d9 | 329 | return vcpu->arch.apic_base; |
6866b83e CO |
330 | } |
331 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
332 | ||
58871649 JM |
333 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
334 | { | |
335 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
336 | } | |
337 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
338 | ||
58cb628d JK |
339 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
340 | { | |
58871649 JM |
341 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
342 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
343 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
344 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 345 | |
58871649 | 346 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 347 | return 1; |
58871649 JM |
348 | if (!msr_info->host_initiated) { |
349 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
350 | return 1; | |
351 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
352 | return 1; | |
353 | } | |
58cb628d JK |
354 | |
355 | kvm_lapic_set_base(vcpu, msr_info->data); | |
356 | return 0; | |
6866b83e CO |
357 | } |
358 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
359 | ||
2605fc21 | 360 | asmlinkage __visible void kvm_spurious_fault(void) |
e3ba45b8 GL |
361 | { |
362 | /* Fault while not rebooting. We want the trace. */ | |
363 | BUG(); | |
364 | } | |
365 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
366 | ||
3fd28fce ED |
367 | #define EXCPT_BENIGN 0 |
368 | #define EXCPT_CONTRIBUTORY 1 | |
369 | #define EXCPT_PF 2 | |
370 | ||
371 | static int exception_class(int vector) | |
372 | { | |
373 | switch (vector) { | |
374 | case PF_VECTOR: | |
375 | return EXCPT_PF; | |
376 | case DE_VECTOR: | |
377 | case TS_VECTOR: | |
378 | case NP_VECTOR: | |
379 | case SS_VECTOR: | |
380 | case GP_VECTOR: | |
381 | return EXCPT_CONTRIBUTORY; | |
382 | default: | |
383 | break; | |
384 | } | |
385 | return EXCPT_BENIGN; | |
386 | } | |
387 | ||
d6e8c854 NA |
388 | #define EXCPT_FAULT 0 |
389 | #define EXCPT_TRAP 1 | |
390 | #define EXCPT_ABORT 2 | |
391 | #define EXCPT_INTERRUPT 3 | |
392 | ||
393 | static int exception_type(int vector) | |
394 | { | |
395 | unsigned int mask; | |
396 | ||
397 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
398 | return EXCPT_INTERRUPT; | |
399 | ||
400 | mask = 1 << vector; | |
401 | ||
402 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
403 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
404 | return EXCPT_TRAP; | |
405 | ||
406 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
407 | return EXCPT_ABORT; | |
408 | ||
409 | /* Reserved exceptions will result in fault */ | |
410 | return EXCPT_FAULT; | |
411 | } | |
412 | ||
da998b46 JM |
413 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
414 | { | |
415 | unsigned nr = vcpu->arch.exception.nr; | |
416 | bool has_payload = vcpu->arch.exception.has_payload; | |
417 | unsigned long payload = vcpu->arch.exception.payload; | |
418 | ||
419 | if (!has_payload) | |
420 | return; | |
421 | ||
422 | switch (nr) { | |
f10c729f JM |
423 | case DB_VECTOR: |
424 | /* | |
425 | * "Certain debug exceptions may clear bit 0-3. The | |
426 | * remaining contents of the DR6 register are never | |
427 | * cleared by the processor". | |
428 | */ | |
429 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
430 | /* | |
431 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
432 | */ | |
433 | vcpu->arch.dr6 |= DR6_RTM; | |
434 | vcpu->arch.dr6 |= payload; | |
435 | /* | |
436 | * Bit 16 should be set in the payload whenever the #DB | |
437 | * exception should clear DR6.RTM. This makes the payload | |
438 | * compatible with the pending debug exceptions under VMX. | |
439 | * Though not currently documented in the SDM, this also | |
440 | * makes the payload compatible with the exit qualification | |
441 | * for #DB exceptions under VMX. | |
442 | */ | |
443 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
444 | break; | |
da998b46 JM |
445 | case PF_VECTOR: |
446 | vcpu->arch.cr2 = payload; | |
447 | break; | |
448 | } | |
449 | ||
450 | vcpu->arch.exception.has_payload = false; | |
451 | vcpu->arch.exception.payload = 0; | |
452 | } | |
453 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
454 | ||
3fd28fce | 455 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 456 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 457 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
458 | { |
459 | u32 prev_nr; | |
460 | int class1, class2; | |
461 | ||
3842d135 AK |
462 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
463 | ||
664f8e26 | 464 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 465 | queue: |
3ffb2468 NA |
466 | if (has_error && !is_protmode(vcpu)) |
467 | has_error = false; | |
664f8e26 WL |
468 | if (reinject) { |
469 | /* | |
470 | * On vmentry, vcpu->arch.exception.pending is only | |
471 | * true if an event injection was blocked by | |
472 | * nested_run_pending. In that case, however, | |
473 | * vcpu_enter_guest requests an immediate exit, | |
474 | * and the guest shouldn't proceed far enough to | |
475 | * need reinjection. | |
476 | */ | |
477 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
478 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
479 | if (WARN_ON_ONCE(has_payload)) { |
480 | /* | |
481 | * A reinjected event has already | |
482 | * delivered its payload. | |
483 | */ | |
484 | has_payload = false; | |
485 | payload = 0; | |
486 | } | |
664f8e26 WL |
487 | } else { |
488 | vcpu->arch.exception.pending = true; | |
489 | vcpu->arch.exception.injected = false; | |
490 | } | |
3fd28fce ED |
491 | vcpu->arch.exception.has_error_code = has_error; |
492 | vcpu->arch.exception.nr = nr; | |
493 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
494 | vcpu->arch.exception.has_payload = has_payload; |
495 | vcpu->arch.exception.payload = payload; | |
da998b46 JM |
496 | /* |
497 | * In guest mode, payload delivery should be deferred, | |
498 | * so that the L1 hypervisor can intercept #PF before | |
f10c729f JM |
499 | * CR2 is modified (or intercept #DB before DR6 is |
500 | * modified under nVMX). However, for ABI | |
501 | * compatibility with KVM_GET_VCPU_EVENTS and | |
502 | * KVM_SET_VCPU_EVENTS, we can't delay payload | |
503 | * delivery unless userspace has enabled this | |
504 | * functionality via the per-VM capability, | |
505 | * KVM_CAP_EXCEPTION_PAYLOAD. | |
da998b46 JM |
506 | */ |
507 | if (!vcpu->kvm->arch.exception_payload_enabled || | |
508 | !is_guest_mode(vcpu)) | |
509 | kvm_deliver_exception_payload(vcpu); | |
3fd28fce ED |
510 | return; |
511 | } | |
512 | ||
513 | /* to check exception */ | |
514 | prev_nr = vcpu->arch.exception.nr; | |
515 | if (prev_nr == DF_VECTOR) { | |
516 | /* triple fault -> shutdown */ | |
a8eeb04a | 517 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
518 | return; |
519 | } | |
520 | class1 = exception_class(prev_nr); | |
521 | class2 = exception_class(nr); | |
522 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
523 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
524 | /* |
525 | * Generate double fault per SDM Table 5-5. Set | |
526 | * exception.pending = true so that the double fault | |
527 | * can trigger a nested vmexit. | |
528 | */ | |
3fd28fce | 529 | vcpu->arch.exception.pending = true; |
664f8e26 | 530 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
531 | vcpu->arch.exception.has_error_code = true; |
532 | vcpu->arch.exception.nr = DF_VECTOR; | |
533 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
534 | vcpu->arch.exception.has_payload = false; |
535 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
536 | } else |
537 | /* replace previous exception with a new one in a hope | |
538 | that instruction re-execution will regenerate lost | |
539 | exception */ | |
540 | goto queue; | |
541 | } | |
542 | ||
298101da AK |
543 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
544 | { | |
91e86d22 | 545 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
546 | } |
547 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
548 | ||
ce7ddec4 JR |
549 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
550 | { | |
91e86d22 | 551 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
552 | } |
553 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
554 | ||
f10c729f JM |
555 | static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
556 | unsigned long payload) | |
557 | { | |
558 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
559 | } | |
560 | ||
da998b46 JM |
561 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
562 | u32 error_code, unsigned long payload) | |
563 | { | |
564 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
565 | true, payload, false); | |
566 | } | |
567 | ||
6affcbed | 568 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 569 | { |
db8fcefa AP |
570 | if (err) |
571 | kvm_inject_gp(vcpu, 0); | |
572 | else | |
6affcbed KH |
573 | return kvm_skip_emulated_instruction(vcpu); |
574 | ||
575 | return 1; | |
db8fcefa AP |
576 | } |
577 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 578 | |
6389ee94 | 579 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
580 | { |
581 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
582 | vcpu->arch.exception.nested_apf = |
583 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 584 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 585 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
586 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
587 | } else { | |
588 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
589 | fault->address); | |
590 | } | |
c3c91fee | 591 | } |
27d6c865 | 592 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 593 | |
ef54bcfe | 594 | static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
d4f8cf66 | 595 | { |
6389ee94 AK |
596 | if (mmu_is_nested(vcpu) && !fault->nested_page_fault) |
597 | vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); | |
d4f8cf66 | 598 | else |
44dd3ffa | 599 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
ef54bcfe PB |
600 | |
601 | return fault->nested_page_fault; | |
d4f8cf66 JR |
602 | } |
603 | ||
3419ffc8 SY |
604 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
605 | { | |
7460fb4a AK |
606 | atomic_inc(&vcpu->arch.nmi_queued); |
607 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
608 | } |
609 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
610 | ||
298101da AK |
611 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
612 | { | |
91e86d22 | 613 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
614 | } |
615 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
616 | ||
ce7ddec4 JR |
617 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
618 | { | |
91e86d22 | 619 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
620 | } |
621 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
622 | ||
0a79b009 AK |
623 | /* |
624 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
625 | * a #GP and return false. | |
626 | */ | |
627 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 628 | { |
0a79b009 AK |
629 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
630 | return true; | |
631 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
632 | return false; | |
298101da | 633 | } |
0a79b009 | 634 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 635 | |
16f8a6f9 NA |
636 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
637 | { | |
638 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
639 | return true; | |
640 | ||
641 | kvm_queue_exception(vcpu, UD_VECTOR); | |
642 | return false; | |
643 | } | |
644 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
645 | ||
ec92fe44 JR |
646 | /* |
647 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 648 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
649 | * can read from guest physical or from the guest's guest physical memory. |
650 | */ | |
651 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
652 | gfn_t ngfn, void *data, int offset, int len, | |
653 | u32 access) | |
654 | { | |
54987b7a | 655 | struct x86_exception exception; |
ec92fe44 JR |
656 | gfn_t real_gfn; |
657 | gpa_t ngpa; | |
658 | ||
659 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 660 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
661 | if (real_gfn == UNMAPPED_GVA) |
662 | return -EFAULT; | |
663 | ||
664 | real_gfn = gpa_to_gfn(real_gfn); | |
665 | ||
54bf36aa | 666 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
667 | } |
668 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
669 | ||
69b0049a | 670 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
671 | void *data, int offset, int len, u32 access) |
672 | { | |
673 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
674 | data, offset, len, access); | |
675 | } | |
676 | ||
a03490ed CO |
677 | /* |
678 | * Load the pae pdptrs. Return true is they are all valid. | |
679 | */ | |
ff03a073 | 680 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
681 | { |
682 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
683 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
684 | int i; | |
685 | int ret; | |
ff03a073 | 686 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 687 | |
ff03a073 JR |
688 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
689 | offset * sizeof(u64), sizeof(pdpte), | |
690 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
691 | if (ret < 0) { |
692 | ret = 0; | |
693 | goto out; | |
694 | } | |
695 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 696 | if ((pdpte[i] & PT_PRESENT_MASK) && |
a0a64f50 | 697 | (pdpte[i] & |
44dd3ffa | 698 | vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) { |
a03490ed CO |
699 | ret = 0; |
700 | goto out; | |
701 | } | |
702 | } | |
703 | ret = 1; | |
704 | ||
ff03a073 | 705 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
6de4f3ad AK |
706 | __set_bit(VCPU_EXREG_PDPTR, |
707 | (unsigned long *)&vcpu->arch.regs_avail); | |
708 | __set_bit(VCPU_EXREG_PDPTR, | |
709 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 710 | out: |
a03490ed CO |
711 | |
712 | return ret; | |
713 | } | |
cc4b6871 | 714 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 715 | |
9ed38ffa | 716 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 717 | { |
ff03a073 | 718 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
d835dfec | 719 | bool changed = true; |
3d06b8bf JR |
720 | int offset; |
721 | gfn_t gfn; | |
d835dfec AK |
722 | int r; |
723 | ||
bf03d4f9 | 724 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
725 | return false; |
726 | ||
6de4f3ad AK |
727 | if (!test_bit(VCPU_EXREG_PDPTR, |
728 | (unsigned long *)&vcpu->arch.regs_avail)) | |
729 | return true; | |
730 | ||
a512177e PB |
731 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
732 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
733 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
734 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec AK |
735 | if (r < 0) |
736 | goto out; | |
ff03a073 | 737 | changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 738 | out: |
d835dfec AK |
739 | |
740 | return changed; | |
741 | } | |
9ed38ffa | 742 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 743 | |
49a9b07e | 744 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 745 | { |
aad82703 | 746 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d81135a5 | 747 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 748 | |
f9a48e6a AK |
749 | cr0 |= X86_CR0_ET; |
750 | ||
ab344828 | 751 | #ifdef CONFIG_X86_64 |
0f12244f GN |
752 | if (cr0 & 0xffffffff00000000UL) |
753 | return 1; | |
ab344828 GN |
754 | #endif |
755 | ||
756 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 757 | |
0f12244f GN |
758 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
759 | return 1; | |
a03490ed | 760 | |
0f12244f GN |
761 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
762 | return 1; | |
a03490ed CO |
763 | |
764 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
765 | #ifdef CONFIG_X86_64 | |
f6801dff | 766 | if ((vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
767 | int cs_db, cs_l; |
768 | ||
0f12244f GN |
769 | if (!is_pae(vcpu)) |
770 | return 1; | |
a03490ed | 771 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
772 | if (cs_l) |
773 | return 1; | |
a03490ed CO |
774 | } else |
775 | #endif | |
ff03a073 | 776 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
9f8fe504 | 777 | kvm_read_cr3(vcpu))) |
0f12244f | 778 | return 1; |
a03490ed CO |
779 | } |
780 | ||
ad756a16 MJ |
781 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
782 | return 1; | |
783 | ||
a03490ed | 784 | kvm_x86_ops->set_cr0(vcpu, cr0); |
a03490ed | 785 | |
d170c419 | 786 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 787 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
788 | kvm_async_pf_hash_reset(vcpu); |
789 | } | |
e5f3f027 | 790 | |
aad82703 SY |
791 | if ((cr0 ^ old_cr0) & update_bits) |
792 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 793 | |
879ae188 LE |
794 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
795 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
796 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
797 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
798 | ||
0f12244f GN |
799 | return 0; |
800 | } | |
2d3ad1f4 | 801 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 802 | |
2d3ad1f4 | 803 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 804 | { |
49a9b07e | 805 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 806 | } |
2d3ad1f4 | 807 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 808 | |
1811d979 | 809 | void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) |
42bdf991 MT |
810 | { |
811 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && | |
812 | !vcpu->guest_xcr0_loaded) { | |
813 | /* kvm_set_xcr() also depends on this */ | |
476b7ada PB |
814 | if (vcpu->arch.xcr0 != host_xcr0) |
815 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
42bdf991 MT |
816 | vcpu->guest_xcr0_loaded = 1; |
817 | } | |
818 | } | |
1811d979 | 819 | EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); |
42bdf991 | 820 | |
1811d979 | 821 | void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) |
42bdf991 MT |
822 | { |
823 | if (vcpu->guest_xcr0_loaded) { | |
824 | if (vcpu->arch.xcr0 != host_xcr0) | |
825 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
826 | vcpu->guest_xcr0_loaded = 0; | |
827 | } | |
828 | } | |
1811d979 | 829 | EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); |
42bdf991 | 830 | |
69b0049a | 831 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 832 | { |
56c103ec LJ |
833 | u64 xcr0 = xcr; |
834 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 835 | u64 valid_bits; |
2acf923e DC |
836 | |
837 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
838 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
839 | return 1; | |
d91cab78 | 840 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 841 | return 1; |
d91cab78 | 842 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 843 | return 1; |
46c34cb0 PB |
844 | |
845 | /* | |
846 | * Do not allow the guest to set bits that we do not support | |
847 | * saving. However, xcr0 bit 0 is always set, even if the | |
848 | * emulated CPU does not support XSAVE (see fx_init). | |
849 | */ | |
d91cab78 | 850 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 851 | if (xcr0 & ~valid_bits) |
2acf923e | 852 | return 1; |
46c34cb0 | 853 | |
d91cab78 DH |
854 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
855 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
856 | return 1; |
857 | ||
d91cab78 DH |
858 | if (xcr0 & XFEATURE_MASK_AVX512) { |
859 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 860 | return 1; |
d91cab78 | 861 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
862 | return 1; |
863 | } | |
2acf923e | 864 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 865 | |
d91cab78 | 866 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
56c103ec | 867 | kvm_update_cpuid(vcpu); |
2acf923e DC |
868 | return 0; |
869 | } | |
870 | ||
871 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
872 | { | |
764bcbc5 Z |
873 | if (kvm_x86_ops->get_cpl(vcpu) != 0 || |
874 | __kvm_set_xcr(vcpu, index, xcr)) { | |
2acf923e DC |
875 | kvm_inject_gp(vcpu, 0); |
876 | return 1; | |
877 | } | |
878 | return 0; | |
879 | } | |
880 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
881 | ||
a83b29c6 | 882 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 883 | { |
fc78f519 | 884 | unsigned long old_cr4 = kvm_read_cr4(vcpu); |
0be0226f | 885 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | |
b9baba86 | 886 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; |
0be0226f | 887 | |
0f12244f GN |
888 | if (cr4 & CR4_RESERVED_BITS) |
889 | return 1; | |
a03490ed | 890 | |
d6321d49 | 891 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) |
2acf923e DC |
892 | return 1; |
893 | ||
d6321d49 | 894 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) |
2acf923e DC |
895 | return 1; |
896 | ||
d6321d49 | 897 | if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) |
c68b734f YW |
898 | return 1; |
899 | ||
d6321d49 | 900 | if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) |
97ec8c06 FW |
901 | return 1; |
902 | ||
d6321d49 | 903 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) |
74dc2b4f YW |
904 | return 1; |
905 | ||
fd8cb433 | 906 | if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) |
b9baba86 HH |
907 | return 1; |
908 | ||
ae3e61e1 PB |
909 | if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) |
910 | return 1; | |
911 | ||
a03490ed | 912 | if (is_long_mode(vcpu)) { |
0f12244f GN |
913 | if (!(cr4 & X86_CR4_PAE)) |
914 | return 1; | |
a2edf57f AK |
915 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
916 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
917 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
918 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
919 | return 1; |
920 | ||
ad756a16 | 921 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 922 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
923 | return 1; |
924 | ||
925 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
926 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
927 | return 1; | |
928 | } | |
929 | ||
5e1746d6 | 930 | if (kvm_x86_ops->set_cr4(vcpu, cr4)) |
0f12244f | 931 | return 1; |
a03490ed | 932 | |
ad756a16 MJ |
933 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
934 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 935 | kvm_mmu_reset_context(vcpu); |
0f12244f | 936 | |
b9baba86 | 937 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
00b27a3e | 938 | kvm_update_cpuid(vcpu); |
2acf923e | 939 | |
0f12244f GN |
940 | return 0; |
941 | } | |
2d3ad1f4 | 942 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 943 | |
2390218b | 944 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 945 | { |
ade61e28 | 946 | bool skip_tlb_flush = false; |
ac146235 | 947 | #ifdef CONFIG_X86_64 |
c19986fe JS |
948 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
949 | ||
ade61e28 | 950 | if (pcid_enabled) { |
208320ba JS |
951 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
952 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 953 | } |
ac146235 | 954 | #endif |
9d88fca7 | 955 | |
9f8fe504 | 956 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
957 | if (!skip_tlb_flush) { |
958 | kvm_mmu_sync_roots(vcpu); | |
ade61e28 | 959 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
956bf353 | 960 | } |
0f12244f | 961 | return 0; |
d835dfec AK |
962 | } |
963 | ||
d1cd3ce9 | 964 | if (is_long_mode(vcpu) && |
a780a3ea | 965 | (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) |
d1cd3ce9 | 966 | return 1; |
bf03d4f9 PB |
967 | else if (is_pae_paging(vcpu) && |
968 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 969 | return 1; |
a03490ed | 970 | |
ade61e28 | 971 | kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); |
0f12244f | 972 | vcpu->arch.cr3 = cr3; |
aff48baa | 973 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
7c390d35 | 974 | |
0f12244f GN |
975 | return 0; |
976 | } | |
2d3ad1f4 | 977 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 978 | |
eea1cff9 | 979 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 980 | { |
0f12244f GN |
981 | if (cr8 & CR8_RESERVED_BITS) |
982 | return 1; | |
35754c98 | 983 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
984 | kvm_lapic_set_tpr(vcpu, cr8); |
985 | else | |
ad312c7c | 986 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
987 | return 0; |
988 | } | |
2d3ad1f4 | 989 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 990 | |
2d3ad1f4 | 991 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 992 | { |
35754c98 | 993 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
994 | return kvm_lapic_get_cr8(vcpu); |
995 | else | |
ad312c7c | 996 | return vcpu->arch.cr8; |
a03490ed | 997 | } |
2d3ad1f4 | 998 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 999 | |
ae561ede NA |
1000 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1001 | { | |
1002 | int i; | |
1003 | ||
1004 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1005 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1006 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1007 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1008 | } | |
1009 | } | |
1010 | ||
73aaf249 JK |
1011 | static void kvm_update_dr6(struct kvm_vcpu *vcpu) |
1012 | { | |
1013 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1014 | kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); | |
1015 | } | |
1016 | ||
c8639010 JK |
1017 | static void kvm_update_dr7(struct kvm_vcpu *vcpu) |
1018 | { | |
1019 | unsigned long dr7; | |
1020 | ||
1021 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1022 | dr7 = vcpu->arch.guest_debug_dr7; | |
1023 | else | |
1024 | dr7 = vcpu->arch.dr7; | |
1025 | kvm_x86_ops->set_dr7(vcpu, dr7); | |
360b948d PB |
1026 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1027 | if (dr7 & DR7_BP_EN_MASK) | |
1028 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 JK |
1029 | } |
1030 | ||
6f43ed01 NA |
1031 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1032 | { | |
1033 | u64 fixed = DR6_FIXED_1; | |
1034 | ||
d6321d49 | 1035 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1036 | fixed |= DR6_RTM; |
1037 | return fixed; | |
1038 | } | |
1039 | ||
338dbc97 | 1040 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 GN |
1041 | { |
1042 | switch (dr) { | |
1043 | case 0 ... 3: | |
1044 | vcpu->arch.db[dr] = val; | |
1045 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1046 | vcpu->arch.eff_db[dr] = val; | |
1047 | break; | |
1048 | case 4: | |
020df079 GN |
1049 | /* fall through */ |
1050 | case 6: | |
338dbc97 GN |
1051 | if (val & 0xffffffff00000000ULL) |
1052 | return -1; /* #GP */ | |
6f43ed01 | 1053 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
73aaf249 | 1054 | kvm_update_dr6(vcpu); |
020df079 GN |
1055 | break; |
1056 | case 5: | |
020df079 GN |
1057 | /* fall through */ |
1058 | default: /* 7 */ | |
338dbc97 GN |
1059 | if (val & 0xffffffff00000000ULL) |
1060 | return -1; /* #GP */ | |
020df079 | 1061 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1062 | kvm_update_dr7(vcpu); |
020df079 GN |
1063 | break; |
1064 | } | |
1065 | ||
1066 | return 0; | |
1067 | } | |
338dbc97 GN |
1068 | |
1069 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1070 | { | |
16f8a6f9 | 1071 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1072 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1073 | return 1; |
1074 | } | |
1075 | return 0; | |
338dbc97 | 1076 | } |
020df079 GN |
1077 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1078 | ||
16f8a6f9 | 1079 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 GN |
1080 | { |
1081 | switch (dr) { | |
1082 | case 0 ... 3: | |
1083 | *val = vcpu->arch.db[dr]; | |
1084 | break; | |
1085 | case 4: | |
020df079 GN |
1086 | /* fall through */ |
1087 | case 6: | |
73aaf249 JK |
1088 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1089 | *val = vcpu->arch.dr6; | |
1090 | else | |
1091 | *val = kvm_x86_ops->get_dr6(vcpu); | |
020df079 GN |
1092 | break; |
1093 | case 5: | |
020df079 GN |
1094 | /* fall through */ |
1095 | default: /* 7 */ | |
1096 | *val = vcpu->arch.dr7; | |
1097 | break; | |
1098 | } | |
338dbc97 GN |
1099 | return 0; |
1100 | } | |
020df079 GN |
1101 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1102 | ||
022cd0e8 AK |
1103 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1104 | { | |
de3cd117 | 1105 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1106 | u64 data; |
1107 | int err; | |
1108 | ||
c6702c9d | 1109 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1110 | if (err) |
1111 | return err; | |
de3cd117 SC |
1112 | kvm_rax_write(vcpu, (u32)data); |
1113 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1114 | return err; |
1115 | } | |
1116 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1117 | ||
043405e1 CO |
1118 | /* |
1119 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1120 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1121 | * | |
1122 | * This list is modified at module load time to reflect the | |
e3267cbb | 1123 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
62ef68bb PB |
1124 | * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs |
1125 | * may depend on host virtualization features rather than host cpu features. | |
043405e1 | 1126 | */ |
e3267cbb | 1127 | |
043405e1 CO |
1128 | static u32 msrs_to_save[] = { |
1129 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
8c06585d | 1130 | MSR_STAR, |
043405e1 CO |
1131 | #ifdef CONFIG_X86_64 |
1132 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1133 | #endif | |
b3897a49 | 1134 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
9dbe6cf9 | 1135 | MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1136 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1137 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1138 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1139 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1140 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1141 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1142 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
043405e1 CO |
1143 | }; |
1144 | ||
1145 | static unsigned num_msrs_to_save; | |
1146 | ||
62ef68bb PB |
1147 | static u32 emulated_msrs[] = { |
1148 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, | |
1149 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1150 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1151 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1152 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1153 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1154 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1155 | HV_X64_MSR_RESET, |
11c4b1ca | 1156 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1157 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1158 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1159 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1160 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1161 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1162 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
1163 | ||
1164 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
62ef68bb PB |
1165 | MSR_KVM_PV_EOI_EN, |
1166 | ||
ba904635 | 1167 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1168 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1169 | MSR_IA32_ARCH_CAPABILITIES, |
043405e1 | 1170 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1171 | MSR_IA32_MCG_STATUS, |
1172 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1173 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1174 | MSR_IA32_SMBASE, |
52797bf9 | 1175 | MSR_SMI_COUNT, |
db2336a8 KH |
1176 | MSR_PLATFORM_INFO, |
1177 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1178 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1179 | MSR_IA32_POWER_CTL, |
191c8137 | 1180 | |
95c5c7c7 PB |
1181 | /* |
1182 | * The following list leaves out MSRs whose values are determined | |
1183 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1184 | * We always support the "true" VMX control MSRs, even if the host | |
1185 | * processor does not, so I am putting these registers here rather | |
1186 | * than in msrs_to_save. | |
1187 | */ | |
1188 | MSR_IA32_VMX_BASIC, | |
1189 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1190 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1191 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1192 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1193 | MSR_IA32_VMX_MISC, | |
1194 | MSR_IA32_VMX_CR0_FIXED0, | |
1195 | MSR_IA32_VMX_CR4_FIXED0, | |
1196 | MSR_IA32_VMX_VMCS_ENUM, | |
1197 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1198 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1199 | MSR_IA32_VMX_VMFUNC, | |
1200 | ||
191c8137 | 1201 | MSR_K7_HWCR, |
2d5ba19b | 1202 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1203 | }; |
1204 | ||
62ef68bb PB |
1205 | static unsigned num_emulated_msrs; |
1206 | ||
801e459a TL |
1207 | /* |
1208 | * List of msr numbers which are used to expose MSR-based features that | |
1209 | * can be used by a hypervisor to validate requested CPU features. | |
1210 | */ | |
1211 | static u32 msr_based_features[] = { | |
1389309c PB |
1212 | MSR_IA32_VMX_BASIC, |
1213 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1214 | MSR_IA32_VMX_PINBASED_CTLS, | |
1215 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1216 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1217 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1218 | MSR_IA32_VMX_EXIT_CTLS, | |
1219 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1220 | MSR_IA32_VMX_ENTRY_CTLS, | |
1221 | MSR_IA32_VMX_MISC, | |
1222 | MSR_IA32_VMX_CR0_FIXED0, | |
1223 | MSR_IA32_VMX_CR0_FIXED1, | |
1224 | MSR_IA32_VMX_CR4_FIXED0, | |
1225 | MSR_IA32_VMX_CR4_FIXED1, | |
1226 | MSR_IA32_VMX_VMCS_ENUM, | |
1227 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1228 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1229 | MSR_IA32_VMX_VMFUNC, | |
1230 | ||
d1d93fa9 | 1231 | MSR_F10H_DECFG, |
518e7b94 | 1232 | MSR_IA32_UCODE_REV, |
cd283252 | 1233 | MSR_IA32_ARCH_CAPABILITIES, |
801e459a TL |
1234 | }; |
1235 | ||
1236 | static unsigned int num_msr_based_features; | |
1237 | ||
4d22c17c | 1238 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1239 | { |
4d22c17c | 1240 | u64 data = 0; |
5b76a3cf | 1241 | |
4d22c17c XL |
1242 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1243 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf PB |
1244 | |
1245 | /* | |
1246 | * If we're doing cache flushes (either "always" or "cond") | |
1247 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1248 | * If an outer hypervisor is doing the cache flush for us | |
1249 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1250 | * capability to the guest too, and if EPT is disabled we're not | |
1251 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1252 | * require a nested hypervisor to do a flush of its own. | |
1253 | */ | |
1254 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1255 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1256 | ||
1257 | return data; | |
1258 | } | |
5b76a3cf | 1259 | |
66421c1e WL |
1260 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1261 | { | |
1262 | switch (msr->index) { | |
cd283252 | 1263 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1264 | msr->data = kvm_get_arch_capabilities(); |
1265 | break; | |
1266 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1267 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1268 | break; |
66421c1e WL |
1269 | default: |
1270 | if (kvm_x86_ops->get_msr_feature(msr)) | |
1271 | return 1; | |
1272 | } | |
1273 | return 0; | |
1274 | } | |
1275 | ||
801e459a TL |
1276 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1277 | { | |
1278 | struct kvm_msr_entry msr; | |
66421c1e | 1279 | int r; |
801e459a TL |
1280 | |
1281 | msr.index = index; | |
66421c1e WL |
1282 | r = kvm_get_msr_feature(&msr); |
1283 | if (r) | |
1284 | return r; | |
801e459a TL |
1285 | |
1286 | *data = msr.data; | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
11988499 | 1291 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1292 | { |
1b4d56b8 | 1293 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1294 | return false; |
1b2fd70c | 1295 | |
1b4d56b8 | 1296 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1297 | return false; |
d8017474 | 1298 | |
0a629563 SC |
1299 | if (efer & (EFER_LME | EFER_LMA) && |
1300 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1301 | return false; | |
1302 | ||
1303 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1304 | return false; | |
d8017474 | 1305 | |
384bb783 | 1306 | return true; |
11988499 SC |
1307 | |
1308 | } | |
1309 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1310 | { | |
1311 | if (efer & efer_reserved_bits) | |
1312 | return false; | |
1313 | ||
1314 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1315 | } |
1316 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1317 | ||
11988499 | 1318 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1319 | { |
1320 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1321 | u64 efer = msr_info->data; |
384bb783 | 1322 | |
11988499 | 1323 | if (efer & efer_reserved_bits) |
66f61c92 | 1324 | return 1; |
384bb783 | 1325 | |
11988499 SC |
1326 | if (!msr_info->host_initiated) { |
1327 | if (!__kvm_valid_efer(vcpu, efer)) | |
1328 | return 1; | |
1329 | ||
1330 | if (is_paging(vcpu) && | |
1331 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1332 | return 1; | |
1333 | } | |
384bb783 | 1334 | |
15c4a640 | 1335 | efer &= ~EFER_LMA; |
f6801dff | 1336 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1337 | |
a3d204e2 SY |
1338 | kvm_x86_ops->set_efer(vcpu, efer); |
1339 | ||
aad82703 SY |
1340 | /* Update reserved bits */ |
1341 | if ((efer ^ old_efer) & EFER_NX) | |
1342 | kvm_mmu_reset_context(vcpu); | |
1343 | ||
b69e8cae | 1344 | return 0; |
15c4a640 CO |
1345 | } |
1346 | ||
f2b4b7dd JR |
1347 | void kvm_enable_efer_bits(u64 mask) |
1348 | { | |
1349 | efer_reserved_bits &= ~mask; | |
1350 | } | |
1351 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1352 | ||
15c4a640 CO |
1353 | /* |
1354 | * Writes msr value into into the appropriate "register". | |
1355 | * Returns 0 on success, non-0 otherwise. | |
1356 | * Assumes vcpu_load() was already called. | |
1357 | */ | |
8fe8ab46 | 1358 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 1359 | { |
854e8bb1 NA |
1360 | switch (msr->index) { |
1361 | case MSR_FS_BASE: | |
1362 | case MSR_GS_BASE: | |
1363 | case MSR_KERNEL_GS_BASE: | |
1364 | case MSR_CSTAR: | |
1365 | case MSR_LSTAR: | |
fd8cb433 | 1366 | if (is_noncanonical_address(msr->data, vcpu)) |
854e8bb1 NA |
1367 | return 1; |
1368 | break; | |
1369 | case MSR_IA32_SYSENTER_EIP: | |
1370 | case MSR_IA32_SYSENTER_ESP: | |
1371 | /* | |
1372 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1373 | * non-canonical address is written on Intel but not on | |
1374 | * AMD (which ignores the top 32-bits, because it does | |
1375 | * not implement 64-bit SYSENTER). | |
1376 | * | |
1377 | * 64-bit code should hence be able to write a non-canonical | |
1378 | * value on AMD. Making the address canonical ensures that | |
1379 | * vmentry does not fail on Intel after writing a non-canonical | |
1380 | * value, and that something deterministic happens if the guest | |
1381 | * invokes 64-bit SYSENTER. | |
1382 | */ | |
fd8cb433 | 1383 | msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1384 | } |
8fe8ab46 | 1385 | return kvm_x86_ops->set_msr(vcpu, msr); |
15c4a640 | 1386 | } |
854e8bb1 | 1387 | EXPORT_SYMBOL_GPL(kvm_set_msr); |
15c4a640 | 1388 | |
313a3dc7 CO |
1389 | /* |
1390 | * Adapt set_msr() to msr_io()'s calling convention | |
1391 | */ | |
609e36d3 PB |
1392 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1393 | { | |
1394 | struct msr_data msr; | |
1395 | int r; | |
1396 | ||
1397 | msr.index = index; | |
1398 | msr.host_initiated = true; | |
1399 | r = kvm_get_msr(vcpu, &msr); | |
1400 | if (r) | |
1401 | return r; | |
1402 | ||
1403 | *data = msr.data; | |
1404 | return 0; | |
1405 | } | |
1406 | ||
313a3dc7 CO |
1407 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1408 | { | |
8fe8ab46 WA |
1409 | struct msr_data msr; |
1410 | ||
1411 | msr.data = *data; | |
1412 | msr.index = index; | |
1413 | msr.host_initiated = true; | |
1414 | return kvm_set_msr(vcpu, &msr); | |
313a3dc7 CO |
1415 | } |
1416 | ||
16e8d74d MT |
1417 | #ifdef CONFIG_X86_64 |
1418 | struct pvclock_gtod_data { | |
1419 | seqcount_t seq; | |
1420 | ||
1421 | struct { /* extract of a clocksource struct */ | |
1422 | int vclock_mode; | |
a5a1d1c2 TG |
1423 | u64 cycle_last; |
1424 | u64 mask; | |
16e8d74d MT |
1425 | u32 mult; |
1426 | u32 shift; | |
1427 | } clock; | |
1428 | ||
cbcf2dd3 TG |
1429 | u64 boot_ns; |
1430 | u64 nsec_base; | |
55dd00a7 | 1431 | u64 wall_time_sec; |
16e8d74d MT |
1432 | }; |
1433 | ||
1434 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1435 | ||
1436 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1437 | { | |
1438 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
cbcf2dd3 TG |
1439 | u64 boot_ns; |
1440 | ||
876e7881 | 1441 | boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); |
16e8d74d MT |
1442 | |
1443 | write_seqcount_begin(&vdata->seq); | |
1444 | ||
1445 | /* copy pvclock gtod data */ | |
876e7881 PZ |
1446 | vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; |
1447 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; | |
1448 | vdata->clock.mask = tk->tkr_mono.mask; | |
1449 | vdata->clock.mult = tk->tkr_mono.mult; | |
1450 | vdata->clock.shift = tk->tkr_mono.shift; | |
16e8d74d | 1451 | |
cbcf2dd3 | 1452 | vdata->boot_ns = boot_ns; |
876e7881 | 1453 | vdata->nsec_base = tk->tkr_mono.xtime_nsec; |
16e8d74d | 1454 | |
55dd00a7 MT |
1455 | vdata->wall_time_sec = tk->xtime_sec; |
1456 | ||
16e8d74d MT |
1457 | write_seqcount_end(&vdata->seq); |
1458 | } | |
1459 | #endif | |
1460 | ||
bab5bb39 NK |
1461 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1462 | { | |
bab5bb39 | 1463 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); |
4d151bf3 | 1464 | kvm_vcpu_kick(vcpu); |
bab5bb39 | 1465 | } |
16e8d74d | 1466 | |
18068523 GOC |
1467 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1468 | { | |
9ed3c444 AK |
1469 | int version; |
1470 | int r; | |
50d0a0f9 | 1471 | struct pvclock_wall_clock wc; |
87aeb54f | 1472 | struct timespec64 boot; |
18068523 GOC |
1473 | |
1474 | if (!wall_clock) | |
1475 | return; | |
1476 | ||
9ed3c444 AK |
1477 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1478 | if (r) | |
1479 | return; | |
1480 | ||
1481 | if (version & 1) | |
1482 | ++version; /* first time write, random junk */ | |
1483 | ||
1484 | ++version; | |
18068523 | 1485 | |
1dab1345 NK |
1486 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1487 | return; | |
18068523 | 1488 | |
50d0a0f9 GH |
1489 | /* |
1490 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1491 | * system time (updated by kvm_guest_time_update below) to the |
50d0a0f9 GH |
1492 | * wall clock specified here. guest system time equals host |
1493 | * system time for us, thus we must fill in host boot time here. | |
1494 | */ | |
87aeb54f | 1495 | getboottime64(&boot); |
50d0a0f9 | 1496 | |
4b648665 | 1497 | if (kvm->arch.kvmclock_offset) { |
87aeb54f AB |
1498 | struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); |
1499 | boot = timespec64_sub(boot, ts); | |
4b648665 | 1500 | } |
87aeb54f | 1501 | wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ |
50d0a0f9 GH |
1502 | wc.nsec = boot.tv_nsec; |
1503 | wc.version = version; | |
18068523 GOC |
1504 | |
1505 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1506 | ||
1507 | version++; | |
1508 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1509 | } |
1510 | ||
50d0a0f9 GH |
1511 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1512 | { | |
b51012de PB |
1513 | do_shl32_div32(dividend, divisor); |
1514 | return dividend; | |
50d0a0f9 GH |
1515 | } |
1516 | ||
3ae13faa | 1517 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1518 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1519 | { |
5f4e3f88 | 1520 | uint64_t scaled64; |
50d0a0f9 GH |
1521 | int32_t shift = 0; |
1522 | uint64_t tps64; | |
1523 | uint32_t tps32; | |
1524 | ||
3ae13faa PB |
1525 | tps64 = base_hz; |
1526 | scaled64 = scaled_hz; | |
50933623 | 1527 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1528 | tps64 >>= 1; |
1529 | shift--; | |
1530 | } | |
1531 | ||
1532 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1533 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1534 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1535 | scaled64 >>= 1; |
1536 | else | |
1537 | tps32 <<= 1; | |
50d0a0f9 GH |
1538 | shift++; |
1539 | } | |
1540 | ||
5f4e3f88 ZA |
1541 | *pshift = shift; |
1542 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
1543 | } |
1544 | ||
d828199e | 1545 | #ifdef CONFIG_X86_64 |
16e8d74d | 1546 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1547 | #endif |
16e8d74d | 1548 | |
c8076604 | 1549 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1550 | static unsigned long max_tsc_khz; |
c8076604 | 1551 | |
cc578287 | 1552 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1553 | { |
cc578287 ZA |
1554 | u64 v = (u64)khz * (1000000 + ppm); |
1555 | do_div(v, 1000000); | |
1556 | return v; | |
1e993611 JR |
1557 | } |
1558 | ||
381d585c HZ |
1559 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1560 | { | |
1561 | u64 ratio; | |
1562 | ||
1563 | /* Guest TSC same frequency as host TSC? */ | |
1564 | if (!scale) { | |
1565 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | /* TSC scaling supported? */ | |
1570 | if (!kvm_has_tsc_control) { | |
1571 | if (user_tsc_khz > tsc_khz) { | |
1572 | vcpu->arch.tsc_catchup = 1; | |
1573 | vcpu->arch.tsc_always_catchup = 1; | |
1574 | return 0; | |
1575 | } else { | |
3f16a5c3 | 1576 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
1577 | return -1; |
1578 | } | |
1579 | } | |
1580 | ||
1581 | /* TSC scaling required - calculate ratio */ | |
1582 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1583 | user_tsc_khz, tsc_khz); | |
1584 | ||
1585 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
1586 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
1587 | user_tsc_khz); | |
381d585c HZ |
1588 | return -1; |
1589 | } | |
1590 | ||
1591 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1592 | return 0; | |
1593 | } | |
1594 | ||
4941b8cb | 1595 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1596 | { |
cc578287 ZA |
1597 | u32 thresh_lo, thresh_hi; |
1598 | int use_scaling = 0; | |
217fc9cf | 1599 | |
03ba32ca | 1600 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1601 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1602 | /* set tsc_scaling_ratio to a safe value */ |
1603 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1604 | return -1; |
ad721883 | 1605 | } |
03ba32ca | 1606 | |
c285545f | 1607 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1608 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1609 | &vcpu->arch.virtual_tsc_shift, |
1610 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1611 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1612 | |
1613 | /* | |
1614 | * Compute the variation in TSC rate which is acceptable | |
1615 | * within the range of tolerance and decide if the | |
1616 | * rate being applied is within that bounds of the hardware | |
1617 | * rate. If so, no scaling or compensation need be done. | |
1618 | */ | |
1619 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1620 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1621 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1622 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1623 | use_scaling = 1; |
1624 | } | |
4941b8cb | 1625 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1626 | } |
1627 | ||
1628 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1629 | { | |
e26101b1 | 1630 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1631 | vcpu->arch.virtual_tsc_mult, |
1632 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1633 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1634 | return tsc; |
1635 | } | |
1636 | ||
b0c39dc6 VK |
1637 | static inline int gtod_is_based_on_tsc(int mode) |
1638 | { | |
1639 | return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; | |
1640 | } | |
1641 | ||
69b0049a | 1642 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1643 | { |
1644 | #ifdef CONFIG_X86_64 | |
1645 | bool vcpus_matched; | |
b48aa97e MT |
1646 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1647 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1648 | ||
1649 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1650 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1651 | ||
7f187922 MT |
1652 | /* |
1653 | * Once the masterclock is enabled, always perform request in | |
1654 | * order to update it. | |
1655 | * | |
1656 | * In order to enable masterclock, the host clocksource must be TSC | |
1657 | * and the vcpus need to have matched TSCs. When that happens, | |
1658 | * perform request to enable masterclock. | |
1659 | */ | |
1660 | if (ka->use_master_clock || | |
b0c39dc6 | 1661 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
1662 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1663 | ||
1664 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1665 | atomic_read(&vcpu->kvm->online_vcpus), | |
1666 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1667 | #endif | |
1668 | } | |
1669 | ||
ba904635 WA |
1670 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1671 | { | |
e79f245d | 1672 | u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
ba904635 WA |
1673 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; |
1674 | } | |
1675 | ||
35181e86 HZ |
1676 | /* |
1677 | * Multiply tsc by a fixed point number represented by ratio. | |
1678 | * | |
1679 | * The most significant 64-N bits (mult) of ratio represent the | |
1680 | * integral part of the fixed point number; the remaining N bits | |
1681 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1682 | * point number (mult + frac * 2^(-N)). | |
1683 | * | |
1684 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1685 | */ | |
1686 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1687 | { | |
1688 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
1689 | } | |
1690 | ||
1691 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
1692 | { | |
1693 | u64 _tsc = tsc; | |
1694 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
1695 | ||
1696 | if (ratio != kvm_default_tsc_scaling_ratio) | |
1697 | _tsc = __scale_tsc(ratio, tsc); | |
1698 | ||
1699 | return _tsc; | |
1700 | } | |
1701 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
1702 | ||
07c1419a HZ |
1703 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1704 | { | |
1705 | u64 tsc; | |
1706 | ||
1707 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
1708 | ||
1709 | return target_tsc - tsc; | |
1710 | } | |
1711 | ||
4ba76538 HZ |
1712 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
1713 | { | |
e79f245d KA |
1714 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
1715 | ||
1716 | return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); | |
4ba76538 HZ |
1717 | } |
1718 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
1719 | ||
a545ab6a LC |
1720 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
1721 | { | |
326e7425 | 1722 | vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
1723 | } |
1724 | ||
b0c39dc6 VK |
1725 | static inline bool kvm_check_tsc_unstable(void) |
1726 | { | |
1727 | #ifdef CONFIG_X86_64 | |
1728 | /* | |
1729 | * TSC is marked unstable when we're running on Hyper-V, | |
1730 | * 'TSC page' clocksource is good. | |
1731 | */ | |
1732 | if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) | |
1733 | return false; | |
1734 | #endif | |
1735 | return check_tsc_unstable(); | |
1736 | } | |
1737 | ||
8fe8ab46 | 1738 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
1739 | { |
1740 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 1741 | u64 offset, ns, elapsed; |
99e3e30a | 1742 | unsigned long flags; |
b48aa97e | 1743 | bool matched; |
0d3da0d2 | 1744 | bool already_matched; |
8fe8ab46 | 1745 | u64 data = msr->data; |
c5e8ec8e | 1746 | bool synchronizing = false; |
99e3e30a | 1747 | |
038f8c11 | 1748 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 1749 | offset = kvm_compute_tsc_offset(vcpu, data); |
9285ec4c | 1750 | ns = ktime_get_boottime_ns(); |
f38e098f | 1751 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 1752 | |
03ba32ca | 1753 | if (vcpu->arch.virtual_tsc_khz) { |
bd8fab39 DP |
1754 | if (data == 0 && msr->host_initiated) { |
1755 | /* | |
1756 | * detection of vcpu initialization -- need to sync | |
1757 | * with other vCPUs. This particularly helps to keep | |
1758 | * kvm_clock stable after CPU hotplug | |
1759 | */ | |
1760 | synchronizing = true; | |
1761 | } else { | |
1762 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
1763 | nsec_to_cycles(vcpu, elapsed); | |
1764 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
1765 | /* | |
1766 | * Special case: TSC write with a small delta (1 second) | |
1767 | * of virtual cycle time against real time is | |
1768 | * interpreted as an attempt to synchronize the CPU. | |
1769 | */ | |
1770 | synchronizing = data < tsc_exp + tsc_hz && | |
1771 | data + tsc_hz > tsc_exp; | |
1772 | } | |
c5e8ec8e | 1773 | } |
f38e098f ZA |
1774 | |
1775 | /* | |
5d3cb0f6 ZA |
1776 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
1777 | * TSC, we add elapsed time in this computation. We could let the | |
1778 | * compensation code attempt to catch up if we fall behind, but | |
1779 | * it's better to try to match offsets from the beginning. | |
1780 | */ | |
c5e8ec8e | 1781 | if (synchronizing && |
5d3cb0f6 | 1782 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 1783 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 1784 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 1785 | } else { |
857e4099 | 1786 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 1787 | data += delta; |
07c1419a | 1788 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 1789 | } |
b48aa97e | 1790 | matched = true; |
0d3da0d2 | 1791 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
1792 | } else { |
1793 | /* | |
1794 | * We split periods of matched TSC writes into generations. | |
1795 | * For each generation, we track the original measured | |
1796 | * nanosecond time, offset, and write, so if TSCs are in | |
1797 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 1798 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
1799 | * |
1800 | * These values are tracked in kvm->arch.cur_xxx variables. | |
1801 | */ | |
1802 | kvm->arch.cur_tsc_generation++; | |
1803 | kvm->arch.cur_tsc_nsec = ns; | |
1804 | kvm->arch.cur_tsc_write = data; | |
1805 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 1806 | matched = false; |
f38e098f | 1807 | } |
e26101b1 ZA |
1808 | |
1809 | /* | |
1810 | * We also track th most recent recorded KHZ, write and time to | |
1811 | * allow the matching interval to be extended at each write. | |
1812 | */ | |
f38e098f ZA |
1813 | kvm->arch.last_tsc_nsec = ns; |
1814 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 1815 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 1816 | |
b183aa58 | 1817 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
1818 | |
1819 | /* Keep track of which generation this VCPU has synchronized to */ | |
1820 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
1821 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
1822 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
1823 | ||
d6321d49 | 1824 | if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) |
ba904635 | 1825 | update_ia32_tsc_adjust_msr(vcpu, offset); |
d6321d49 | 1826 | |
a545ab6a | 1827 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 1828 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
1829 | |
1830 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 1831 | if (!matched) { |
b48aa97e | 1832 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
1833 | } else if (!already_matched) { |
1834 | kvm->arch.nr_vcpus_matched_tsc++; | |
1835 | } | |
b48aa97e MT |
1836 | |
1837 | kvm_track_tsc_matching(vcpu); | |
1838 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 1839 | } |
e26101b1 | 1840 | |
99e3e30a ZA |
1841 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
1842 | ||
58ea6767 HZ |
1843 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
1844 | s64 adjustment) | |
1845 | { | |
326e7425 LS |
1846 | u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); |
1847 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); | |
58ea6767 HZ |
1848 | } |
1849 | ||
1850 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
1851 | { | |
1852 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
1853 | WARN_ON(adjustment < 0); | |
1854 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 1855 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
1856 | } |
1857 | ||
d828199e MT |
1858 | #ifdef CONFIG_X86_64 |
1859 | ||
a5a1d1c2 | 1860 | static u64 read_tsc(void) |
d828199e | 1861 | { |
a5a1d1c2 | 1862 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 1863 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
1864 | |
1865 | if (likely(ret >= last)) | |
1866 | return ret; | |
1867 | ||
1868 | /* | |
1869 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 1870 | * predictable (it's just a function of time and the likely is |
d828199e MT |
1871 | * very likely) and there's a data dependence, so force GCC |
1872 | * to generate a branch instead. I don't barrier() because | |
1873 | * we don't actually need a barrier, and if this function | |
1874 | * ever gets inlined it will generate worse code. | |
1875 | */ | |
1876 | asm volatile (""); | |
1877 | return last; | |
1878 | } | |
1879 | ||
b0c39dc6 | 1880 | static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) |
d828199e MT |
1881 | { |
1882 | long v; | |
1883 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
b0c39dc6 VK |
1884 | u64 tsc_pg_val; |
1885 | ||
1886 | switch (gtod->clock.vclock_mode) { | |
1887 | case VCLOCK_HVCLOCK: | |
1888 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), | |
1889 | tsc_timestamp); | |
1890 | if (tsc_pg_val != U64_MAX) { | |
1891 | /* TSC page valid */ | |
1892 | *mode = VCLOCK_HVCLOCK; | |
1893 | v = (tsc_pg_val - gtod->clock.cycle_last) & | |
1894 | gtod->clock.mask; | |
1895 | } else { | |
1896 | /* TSC page invalid */ | |
1897 | *mode = VCLOCK_NONE; | |
1898 | } | |
1899 | break; | |
1900 | case VCLOCK_TSC: | |
1901 | *mode = VCLOCK_TSC; | |
1902 | *tsc_timestamp = read_tsc(); | |
1903 | v = (*tsc_timestamp - gtod->clock.cycle_last) & | |
1904 | gtod->clock.mask; | |
1905 | break; | |
1906 | default: | |
1907 | *mode = VCLOCK_NONE; | |
1908 | } | |
d828199e | 1909 | |
b0c39dc6 VK |
1910 | if (*mode == VCLOCK_NONE) |
1911 | *tsc_timestamp = v = 0; | |
d828199e | 1912 | |
d828199e MT |
1913 | return v * gtod->clock.mult; |
1914 | } | |
1915 | ||
b0c39dc6 | 1916 | static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) |
d828199e | 1917 | { |
cbcf2dd3 | 1918 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 1919 | unsigned long seq; |
d828199e | 1920 | int mode; |
cbcf2dd3 | 1921 | u64 ns; |
d828199e | 1922 | |
d828199e MT |
1923 | do { |
1924 | seq = read_seqcount_begin(>od->seq); | |
cbcf2dd3 | 1925 | ns = gtod->nsec_base; |
b0c39dc6 | 1926 | ns += vgettsc(tsc_timestamp, &mode); |
d828199e | 1927 | ns >>= gtod->clock.shift; |
cbcf2dd3 | 1928 | ns += gtod->boot_ns; |
d828199e | 1929 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 1930 | *t = ns; |
d828199e MT |
1931 | |
1932 | return mode; | |
1933 | } | |
1934 | ||
899a31f5 | 1935 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
1936 | { |
1937 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1938 | unsigned long seq; | |
1939 | int mode; | |
1940 | u64 ns; | |
1941 | ||
1942 | do { | |
1943 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 MT |
1944 | ts->tv_sec = gtod->wall_time_sec; |
1945 | ns = gtod->nsec_base; | |
b0c39dc6 | 1946 | ns += vgettsc(tsc_timestamp, &mode); |
55dd00a7 MT |
1947 | ns >>= gtod->clock.shift; |
1948 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
1949 | ||
1950 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
1951 | ts->tv_nsec = ns; | |
1952 | ||
1953 | return mode; | |
1954 | } | |
1955 | ||
b0c39dc6 VK |
1956 | /* returns true if host is using TSC based clocksource */ |
1957 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 1958 | { |
d828199e | 1959 | /* checked again under seqlock below */ |
b0c39dc6 | 1960 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
1961 | return false; |
1962 | ||
b0c39dc6 VK |
1963 | return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, |
1964 | tsc_timestamp)); | |
d828199e | 1965 | } |
55dd00a7 | 1966 | |
b0c39dc6 | 1967 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 1968 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 1969 | u64 *tsc_timestamp) |
55dd00a7 MT |
1970 | { |
1971 | /* checked again under seqlock below */ | |
b0c39dc6 | 1972 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
1973 | return false; |
1974 | ||
b0c39dc6 | 1975 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 1976 | } |
d828199e MT |
1977 | #endif |
1978 | ||
1979 | /* | |
1980 | * | |
b48aa97e MT |
1981 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
1982 | * across virtual CPUs, the following condition is possible. | |
1983 | * Each numbered line represents an event visible to both | |
d828199e MT |
1984 | * CPUs at the next numbered event. |
1985 | * | |
1986 | * "timespecX" represents host monotonic time. "tscX" represents | |
1987 | * RDTSC value. | |
1988 | * | |
1989 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
1990 | * | |
1991 | * 1. read timespec0,tsc0 | |
1992 | * 2. | timespec1 = timespec0 + N | |
1993 | * | tsc1 = tsc0 + M | |
1994 | * 3. transition to guest | transition to guest | |
1995 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
1996 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
1997 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
1998 | * | |
1999 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2000 | * | |
2001 | * - ret0 < ret1 | |
2002 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2003 | * ... | |
2004 | * - 0 < N - M => M < N | |
2005 | * | |
2006 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2007 | * always the case (the difference between two distinct xtime instances | |
2008 | * might be smaller then the difference between corresponding TSC reads, | |
2009 | * when updating guest vcpus pvclock areas). | |
2010 | * | |
2011 | * To avoid that problem, do not allow visibility of distinct | |
2012 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2013 | * copy of host monotonic time values. Update that master copy | |
2014 | * in lockstep. | |
2015 | * | |
b48aa97e | 2016 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2017 | * |
2018 | */ | |
2019 | ||
2020 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2021 | { | |
2022 | #ifdef CONFIG_X86_64 | |
2023 | struct kvm_arch *ka = &kvm->arch; | |
2024 | int vclock_mode; | |
b48aa97e MT |
2025 | bool host_tsc_clocksource, vcpus_matched; |
2026 | ||
2027 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2028 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2029 | |
2030 | /* | |
2031 | * If the host uses TSC clock, then passthrough TSC as stable | |
2032 | * to the guest. | |
2033 | */ | |
b48aa97e | 2034 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2035 | &ka->master_kernel_ns, |
2036 | &ka->master_cycle_now); | |
2037 | ||
16a96021 | 2038 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2039 | && !ka->backwards_tsc_observed |
54750f2c | 2040 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2041 | |
d828199e MT |
2042 | if (ka->use_master_clock) |
2043 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2044 | ||
2045 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2046 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2047 | vcpus_matched); | |
d828199e MT |
2048 | #endif |
2049 | } | |
2050 | ||
2860c4b1 PB |
2051 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2052 | { | |
2053 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2054 | } | |
2055 | ||
2e762ff7 MT |
2056 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2057 | { | |
2058 | #ifdef CONFIG_X86_64 | |
2059 | int i; | |
2060 | struct kvm_vcpu *vcpu; | |
2061 | struct kvm_arch *ka = &kvm->arch; | |
2062 | ||
2063 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2064 | kvm_make_mclock_inprogress_request(kvm); | |
2065 | /* no guest entries from this point */ | |
2066 | pvclock_update_vm_gtod_copy(kvm); | |
2067 | ||
2068 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2069 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2070 | |
2071 | /* guest entries allowed */ | |
2072 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2073 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2074 | |
2075 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2076 | #endif | |
2077 | } | |
2078 | ||
e891a32e | 2079 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2080 | { |
108b249c | 2081 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2082 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2083 | u64 ret; |
108b249c | 2084 | |
8b953440 PB |
2085 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2086 | if (!ka->use_master_clock) { | |
2087 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
9285ec4c | 2088 | return ktime_get_boottime_ns() + ka->kvmclock_offset; |
108b249c PB |
2089 | } |
2090 | ||
8b953440 PB |
2091 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2092 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2093 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2094 | ||
e2c2206a WL |
2095 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2096 | get_cpu(); | |
2097 | ||
e70b57a6 WL |
2098 | if (__this_cpu_read(cpu_tsc_khz)) { |
2099 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2100 | &hv_clock.tsc_shift, | |
2101 | &hv_clock.tsc_to_system_mul); | |
2102 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2103 | } else | |
9285ec4c | 2104 | ret = ktime_get_boottime_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2105 | |
2106 | put_cpu(); | |
2107 | ||
2108 | return ret; | |
108b249c PB |
2109 | } |
2110 | ||
0d6dd2ff PB |
2111 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2112 | { | |
2113 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2114 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2115 | ||
4e335d9e | 2116 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2117 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2118 | return; | |
2119 | ||
2120 | /* This VCPU is paused, but it's legal for a guest to read another | |
2121 | * VCPU's kvmclock, so we really have to follow the specification where | |
2122 | * it says that version is odd if data is being modified, and even after | |
2123 | * it is consistent. | |
2124 | * | |
2125 | * Version field updates must be kept separate. This is because | |
2126 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2127 | * writes within a string instruction are weakly ordered. So there | |
2128 | * are three writes overall. | |
2129 | * | |
2130 | * As a small optimization, only write the version field in the first | |
2131 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2132 | * version field is the first in the struct. | |
2133 | */ | |
2134 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2135 | ||
51c4b8bb LA |
2136 | if (guest_hv_clock.version & 1) |
2137 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2138 | ||
0d6dd2ff | 2139 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2140 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2141 | &vcpu->hv_clock, | |
2142 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2143 | |
2144 | smp_wmb(); | |
2145 | ||
2146 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2147 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2148 | ||
2149 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2150 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2151 | vcpu->pvclock_set_guest_stopped_request = false; | |
2152 | } | |
2153 | ||
2154 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2155 | ||
4e335d9e PB |
2156 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2157 | &vcpu->hv_clock, | |
2158 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2159 | |
2160 | smp_wmb(); | |
2161 | ||
2162 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2163 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2164 | &vcpu->hv_clock, | |
2165 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2166 | } |
2167 | ||
34c238a1 | 2168 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2169 | { |
78db6a50 | 2170 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2171 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2172 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2173 | s64 kernel_ns; |
d828199e | 2174 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2175 | u8 pvclock_flags; |
d828199e MT |
2176 | bool use_master_clock; |
2177 | ||
2178 | kernel_ns = 0; | |
2179 | host_tsc = 0; | |
18068523 | 2180 | |
d828199e MT |
2181 | /* |
2182 | * If the host uses TSC clock, then passthrough TSC as stable | |
2183 | * to the guest. | |
2184 | */ | |
2185 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2186 | use_master_clock = ka->use_master_clock; | |
2187 | if (use_master_clock) { | |
2188 | host_tsc = ka->master_cycle_now; | |
2189 | kernel_ns = ka->master_kernel_ns; | |
2190 | } | |
2191 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2192 | |
2193 | /* Keep irq disabled to prevent changes to the clock */ | |
2194 | local_irq_save(flags); | |
78db6a50 PB |
2195 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2196 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2197 | local_irq_restore(flags); |
2198 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2199 | return 1; | |
2200 | } | |
d828199e | 2201 | if (!use_master_clock) { |
4ea1636b | 2202 | host_tsc = rdtsc(); |
9285ec4c | 2203 | kernel_ns = ktime_get_boottime_ns(); |
d828199e MT |
2204 | } |
2205 | ||
4ba76538 | 2206 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2207 | |
c285545f ZA |
2208 | /* |
2209 | * We may have to catch up the TSC to match elapsed wall clock | |
2210 | * time for two reasons, even if kvmclock is used. | |
2211 | * 1) CPU could have been running below the maximum TSC rate | |
2212 | * 2) Broken TSC compensation resets the base at each VCPU | |
2213 | * entry to avoid unknown leaps of TSC even when running | |
2214 | * again on the same CPU. This may cause apparent elapsed | |
2215 | * time to disappear, and the guest to stand still or run | |
2216 | * very slowly. | |
2217 | */ | |
2218 | if (vcpu->tsc_catchup) { | |
2219 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2220 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2221 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2222 | tsc_timestamp = tsc; |
2223 | } | |
50d0a0f9 GH |
2224 | } |
2225 | ||
18068523 GOC |
2226 | local_irq_restore(flags); |
2227 | ||
0d6dd2ff | 2228 | /* With all the info we got, fill in the values */ |
18068523 | 2229 | |
78db6a50 PB |
2230 | if (kvm_has_tsc_control) |
2231 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2232 | ||
2233 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2234 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2235 | &vcpu->hv_clock.tsc_shift, |
2236 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2237 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2238 | } |
2239 | ||
1d5f066e | 2240 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2241 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2242 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2243 | |
d828199e | 2244 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2245 | pvclock_flags = 0; |
d828199e MT |
2246 | if (use_master_clock) |
2247 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2248 | ||
78c0337a MT |
2249 | vcpu->hv_clock.flags = pvclock_flags; |
2250 | ||
095cf55d PB |
2251 | if (vcpu->pv_time_enabled) |
2252 | kvm_setup_pvclock_page(v); | |
2253 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2254 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2255 | return 0; |
c8076604 GH |
2256 | } |
2257 | ||
0061d53d MT |
2258 | /* |
2259 | * kvmclock updates which are isolated to a given vcpu, such as | |
2260 | * vcpu->cpu migration, should not allow system_timestamp from | |
2261 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2262 | * correction applies to one vcpu's system_timestamp but not | |
2263 | * the others. | |
2264 | * | |
2265 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2266 | * We need to rate-limit these requests though, as they can |
2267 | * considerably slow guests that have a large number of vcpus. | |
2268 | * The time for a remote vcpu to update its kvmclock is bound | |
2269 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2270 | */ |
2271 | ||
7e44e449 AJ |
2272 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2273 | ||
2274 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2275 | { |
2276 | int i; | |
7e44e449 AJ |
2277 | struct delayed_work *dwork = to_delayed_work(work); |
2278 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2279 | kvmclock_update_work); | |
2280 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2281 | struct kvm_vcpu *vcpu; |
2282 | ||
2283 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2284 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2285 | kvm_vcpu_kick(vcpu); |
2286 | } | |
2287 | } | |
2288 | ||
7e44e449 AJ |
2289 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2290 | { | |
2291 | struct kvm *kvm = v->kvm; | |
2292 | ||
105b21bb | 2293 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2294 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2295 | KVMCLOCK_UPDATE_DELAY); | |
2296 | } | |
2297 | ||
332967a3 AJ |
2298 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2299 | ||
2300 | static void kvmclock_sync_fn(struct work_struct *work) | |
2301 | { | |
2302 | struct delayed_work *dwork = to_delayed_work(work); | |
2303 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2304 | kvmclock_sync_work); | |
2305 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2306 | ||
630994b3 MT |
2307 | if (!kvmclock_periodic_sync) |
2308 | return; | |
2309 | ||
332967a3 AJ |
2310 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2311 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2312 | KVMCLOCK_SYNC_PERIOD); | |
2313 | } | |
2314 | ||
191c8137 BP |
2315 | /* |
2316 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2317 | */ | |
2318 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2319 | { | |
2320 | /* McStatusWrEn enabled? */ | |
2321 | if (guest_cpuid_is_amd(vcpu)) | |
2322 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); | |
2323 | ||
2324 | return false; | |
2325 | } | |
2326 | ||
9ffd986c | 2327 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2328 | { |
890ca9ae HY |
2329 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2330 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2331 | u32 msr = msr_info->index; |
2332 | u64 data = msr_info->data; | |
890ca9ae | 2333 | |
15c4a640 | 2334 | switch (msr) { |
15c4a640 | 2335 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2336 | vcpu->arch.mcg_status = data; |
15c4a640 | 2337 | break; |
c7ac679c | 2338 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2339 | if (!(mcg_cap & MCG_CTL_P) && |
2340 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2341 | return 1; |
2342 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2343 | return 1; |
890ca9ae HY |
2344 | vcpu->arch.mcg_ctl = data; |
2345 | break; | |
2346 | default: | |
2347 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2348 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae | 2349 | u32 offset = msr - MSR_IA32_MC0_CTL; |
114be429 AP |
2350 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2351 | * some Linux kernels though clear bit 10 in bank 4 to | |
2352 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2353 | * this to avoid an uncatched #GP in the guest | |
2354 | */ | |
890ca9ae | 2355 | if ((offset & 0x3) == 0 && |
114be429 | 2356 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2357 | return -1; |
191c8137 BP |
2358 | |
2359 | /* MCi_STATUS */ | |
9ffd986c | 2360 | if (!msr_info->host_initiated && |
191c8137 BP |
2361 | (offset & 0x3) == 1 && data != 0) { |
2362 | if (!can_set_mci_status(vcpu)) | |
2363 | return -1; | |
2364 | } | |
2365 | ||
890ca9ae HY |
2366 | vcpu->arch.mce_banks[offset] = data; |
2367 | break; | |
2368 | } | |
2369 | return 1; | |
2370 | } | |
2371 | return 0; | |
2372 | } | |
2373 | ||
ffde22ac ES |
2374 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2375 | { | |
2376 | struct kvm *kvm = vcpu->kvm; | |
2377 | int lm = is_long_mode(vcpu); | |
2378 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2379 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2380 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2381 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2382 | u32 page_num = data & ~PAGE_MASK; | |
2383 | u64 page_addr = data & PAGE_MASK; | |
2384 | u8 *page; | |
2385 | int r; | |
2386 | ||
2387 | r = -E2BIG; | |
2388 | if (page_num >= blob_size) | |
2389 | goto out; | |
2390 | r = -ENOMEM; | |
ff5c2c03 SL |
2391 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2392 | if (IS_ERR(page)) { | |
2393 | r = PTR_ERR(page); | |
ffde22ac | 2394 | goto out; |
ff5c2c03 | 2395 | } |
54bf36aa | 2396 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
2397 | goto out_free; |
2398 | r = 0; | |
2399 | out_free: | |
2400 | kfree(page); | |
2401 | out: | |
2402 | return r; | |
2403 | } | |
2404 | ||
344d9588 GN |
2405 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2406 | { | |
2407 | gpa_t gpa = data & ~0x3f; | |
2408 | ||
52a5c155 WL |
2409 | /* Bits 3:5 are reserved, Should be zero */ |
2410 | if (data & 0x38) | |
344d9588 GN |
2411 | return 1; |
2412 | ||
2413 | vcpu->arch.apf.msr_val = data; | |
2414 | ||
2415 | if (!(data & KVM_ASYNC_PF_ENABLED)) { | |
2416 | kvm_clear_async_pf_completion_queue(vcpu); | |
2417 | kvm_async_pf_hash_reset(vcpu); | |
2418 | return 0; | |
2419 | } | |
2420 | ||
4e335d9e | 2421 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
8f964525 | 2422 | sizeof(u32))) |
344d9588 GN |
2423 | return 1; |
2424 | ||
6adba527 | 2425 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2426 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
344d9588 GN |
2427 | kvm_async_pf_wakeup_all(vcpu); |
2428 | return 0; | |
2429 | } | |
2430 | ||
12f9a48f GC |
2431 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2432 | { | |
0b79459b | 2433 | vcpu->arch.pv_time_enabled = false; |
12f9a48f GC |
2434 | } |
2435 | ||
f38a7b75 WL |
2436 | static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) |
2437 | { | |
2438 | ++vcpu->stat.tlb_flush; | |
2439 | kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); | |
2440 | } | |
2441 | ||
c9aaa895 GC |
2442 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2443 | { | |
2444 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
2445 | return; | |
2446 | ||
4e335d9e | 2447 | if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2448 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) |
2449 | return; | |
2450 | ||
f38a7b75 WL |
2451 | /* |
2452 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2453 | * expensive IPIs. | |
2454 | */ | |
2455 | if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
2456 | kvm_vcpu_flush_tlb(vcpu, false); | |
0b9f6c46 | 2457 | |
35f3fae1 WL |
2458 | if (vcpu->arch.st.steal.version & 1) |
2459 | vcpu->arch.st.steal.version += 1; /* first time write, random junk */ | |
2460 | ||
2461 | vcpu->arch.st.steal.version += 1; | |
2462 | ||
4e335d9e | 2463 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2464 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2465 | ||
2466 | smp_wmb(); | |
2467 | ||
c54cdf14 LC |
2468 | vcpu->arch.st.steal.steal += current->sched_info.run_delay - |
2469 | vcpu->arch.st.last_steal; | |
2470 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2471 | |
4e335d9e | 2472 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
35f3fae1 WL |
2473 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2474 | ||
2475 | smp_wmb(); | |
2476 | ||
2477 | vcpu->arch.st.steal.version += 1; | |
c9aaa895 | 2478 | |
4e335d9e | 2479 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, |
c9aaa895 GC |
2480 | &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); |
2481 | } | |
2482 | ||
8fe8ab46 | 2483 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2484 | { |
5753785f | 2485 | bool pr = false; |
8fe8ab46 WA |
2486 | u32 msr = msr_info->index; |
2487 | u64 data = msr_info->data; | |
5753785f | 2488 | |
15c4a640 | 2489 | switch (msr) { |
2e32b719 | 2490 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
2491 | case MSR_IA32_UCODE_WRITE: |
2492 | case MSR_VM_HSAVE_PA: | |
2493 | case MSR_AMD64_PATCH_LOADER: | |
2494 | case MSR_AMD64_BU_CFG2: | |
405a353a | 2495 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2496 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
2497 | break; |
2498 | ||
518e7b94 WL |
2499 | case MSR_IA32_UCODE_REV: |
2500 | if (msr_info->host_initiated) | |
2501 | vcpu->arch.microcode_version = data; | |
2502 | break; | |
0cf9135b SC |
2503 | case MSR_IA32_ARCH_CAPABILITIES: |
2504 | if (!msr_info->host_initiated) | |
2505 | return 1; | |
2506 | vcpu->arch.arch_capabilities = data; | |
2507 | break; | |
15c4a640 | 2508 | case MSR_EFER: |
11988499 | 2509 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
2510 | case MSR_K7_HWCR: |
2511 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2512 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2513 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
2514 | |
2515 | /* Handle McStatusWrEn */ | |
2516 | if (data == BIT_ULL(18)) { | |
2517 | vcpu->arch.msr_hwcr = data; | |
2518 | } else if (data != 0) { | |
a737f256 CD |
2519 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2520 | data); | |
8f1589d9 AP |
2521 | return 1; |
2522 | } | |
15c4a640 | 2523 | break; |
f7c6d140 AP |
2524 | case MSR_FAM10H_MMIO_CONF_BASE: |
2525 | if (data != 0) { | |
a737f256 CD |
2526 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2527 | "0x%llx\n", data); | |
f7c6d140 AP |
2528 | return 1; |
2529 | } | |
15c4a640 | 2530 | break; |
b5e2fec0 AG |
2531 | case MSR_IA32_DEBUGCTLMSR: |
2532 | if (!data) { | |
2533 | /* We support the non-activated case already */ | |
2534 | break; | |
2535 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2536 | /* Values other than LBR and BTF are vendor-specific, | |
2537 | thus reserved and should throw a #GP */ | |
2538 | return 1; | |
2539 | } | |
a737f256 CD |
2540 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2541 | __func__, data); | |
b5e2fec0 | 2542 | break; |
9ba075a6 | 2543 | case 0x200 ... 0x2ff: |
ff53604b | 2544 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2545 | case MSR_IA32_APICBASE: |
58cb628d | 2546 | return kvm_set_apic_base(vcpu, msr_info); |
0105d1a5 GN |
2547 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
2548 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
a3e06bbe LJ |
2549 | case MSR_IA32_TSCDEADLINE: |
2550 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2551 | break; | |
ba904635 | 2552 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 2553 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 2554 | if (!msr_info->host_initiated) { |
d913b904 | 2555 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2556 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2557 | } |
2558 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2559 | } | |
2560 | break; | |
15c4a640 | 2561 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
2562 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
2563 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
2564 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
2565 | return 1; | |
2566 | vcpu->arch.ia32_misc_enable_msr = data; | |
2567 | kvm_update_cpuid(vcpu); | |
2568 | } else { | |
2569 | vcpu->arch.ia32_misc_enable_msr = data; | |
2570 | } | |
15c4a640 | 2571 | break; |
64d60670 PB |
2572 | case MSR_IA32_SMBASE: |
2573 | if (!msr_info->host_initiated) | |
2574 | return 1; | |
2575 | vcpu->arch.smbase = data; | |
2576 | break; | |
73f624f4 PB |
2577 | case MSR_IA32_POWER_CTL: |
2578 | vcpu->arch.msr_ia32_power_ctl = data; | |
2579 | break; | |
dd259935 PB |
2580 | case MSR_IA32_TSC: |
2581 | kvm_write_tsc(vcpu, msr_info); | |
2582 | break; | |
52797bf9 LA |
2583 | case MSR_SMI_COUNT: |
2584 | if (!msr_info->host_initiated) | |
2585 | return 1; | |
2586 | vcpu->arch.smi_count = data; | |
2587 | break; | |
11c6bffa | 2588 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2589 | case MSR_KVM_WALL_CLOCK: |
2590 | vcpu->kvm->arch.wall_clock = data; | |
2591 | kvm_write_wall_clock(vcpu->kvm, data); | |
2592 | break; | |
11c6bffa | 2593 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2594 | case MSR_KVM_SYSTEM_TIME: { |
54750f2c MT |
2595 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2596 | ||
12f9a48f | 2597 | kvmclock_reset(vcpu); |
18068523 | 2598 | |
54750f2c MT |
2599 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2600 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2601 | ||
2602 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
1bd2009e | 2603 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
54750f2c MT |
2604 | |
2605 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2606 | } | |
2607 | ||
18068523 | 2608 | vcpu->arch.time = data; |
0061d53d | 2609 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2610 | |
2611 | /* we verify if the enable bit is set... */ | |
2612 | if (!(data & 1)) | |
2613 | break; | |
2614 | ||
4e335d9e | 2615 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2616 | &vcpu->arch.pv_time, data & ~1ULL, |
2617 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b AH |
2618 | vcpu->arch.pv_time_enabled = false; |
2619 | else | |
2620 | vcpu->arch.pv_time_enabled = true; | |
32cad84f | 2621 | |
18068523 GOC |
2622 | break; |
2623 | } | |
344d9588 GN |
2624 | case MSR_KVM_ASYNC_PF_EN: |
2625 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
2626 | return 1; | |
2627 | break; | |
c9aaa895 GC |
2628 | case MSR_KVM_STEAL_TIME: |
2629 | ||
2630 | if (unlikely(!sched_info_on())) | |
2631 | return 1; | |
2632 | ||
2633 | if (data & KVM_STEAL_RESERVED_MASK) | |
2634 | return 1; | |
2635 | ||
4e335d9e | 2636 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, |
8f964525 AH |
2637 | data & KVM_STEAL_VALID_BITS, |
2638 | sizeof(struct kvm_steal_time))) | |
c9aaa895 GC |
2639 | return 1; |
2640 | ||
2641 | vcpu->arch.st.msr_val = data; | |
2642 | ||
2643 | if (!(data & KVM_MSR_ENABLED)) | |
2644 | break; | |
2645 | ||
c9aaa895 GC |
2646 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
2647 | ||
2648 | break; | |
ae7a2a3f | 2649 | case MSR_KVM_PV_EOI_EN: |
72bbf935 | 2650 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
2651 | return 1; |
2652 | break; | |
c9aaa895 | 2653 | |
2d5ba19b MT |
2654 | case MSR_KVM_POLL_CONTROL: |
2655 | /* only enable bit supported */ | |
2656 | if (data & (-1ULL << 1)) | |
2657 | return 1; | |
2658 | ||
2659 | vcpu->arch.msr_kvm_poll_control = data; | |
2660 | break; | |
2661 | ||
890ca9ae HY |
2662 | case MSR_IA32_MCG_CTL: |
2663 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2664 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 2665 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 2666 | |
6912ac32 WH |
2667 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
2668 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2669 | pr = true; /* fall through */ | |
2670 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
2671 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2672 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2673 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
2674 | |
2675 | if (pr || data != 0) | |
a737f256 CD |
2676 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
2677 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 2678 | break; |
84e0cefa JS |
2679 | case MSR_K7_CLK_CTL: |
2680 | /* | |
2681 | * Ignore all writes to this no longer documented MSR. | |
2682 | * Writes are only relevant for old K7 processors, | |
2683 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 2684 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
2685 | * affected processor models on the command line, hence |
2686 | * the need to ignore the workaround. | |
2687 | */ | |
2688 | break; | |
55cd8e5a | 2689 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2690 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2691 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2692 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2693 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2694 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2695 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
2696 | return kvm_hv_set_msr_common(vcpu, msr, data, |
2697 | msr_info->host_initiated); | |
91c9c3ed | 2698 | case MSR_IA32_BBL_CR_CTL3: |
2699 | /* Drop writes to this legacy MSR -- see rdmsr | |
2700 | * counterpart for further detail. | |
2701 | */ | |
fab0aa3b EM |
2702 | if (report_ignored_msrs) |
2703 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
2704 | msr, data); | |
91c9c3ed | 2705 | break; |
2b036c6b | 2706 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2707 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2708 | return 1; |
2709 | vcpu->arch.osvw.length = data; | |
2710 | break; | |
2711 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2712 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
2713 | return 1; |
2714 | vcpu->arch.osvw.status = data; | |
2715 | break; | |
db2336a8 KH |
2716 | case MSR_PLATFORM_INFO: |
2717 | if (!msr_info->host_initiated || | |
db2336a8 KH |
2718 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
2719 | cpuid_fault_enabled(vcpu))) | |
2720 | return 1; | |
2721 | vcpu->arch.msr_platform_info = data; | |
2722 | break; | |
2723 | case MSR_MISC_FEATURES_ENABLES: | |
2724 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
2725 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
2726 | !supports_cpuid_fault(vcpu))) | |
2727 | return 1; | |
2728 | vcpu->arch.msr_misc_features_enables = data; | |
2729 | break; | |
15c4a640 | 2730 | default: |
ffde22ac ES |
2731 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
2732 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 2733 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 2734 | return kvm_pmu_set_msr(vcpu, msr_info); |
ed85c068 | 2735 | if (!ignore_msrs) { |
ae0f5499 | 2736 | vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", |
a737f256 | 2737 | msr, data); |
ed85c068 AP |
2738 | return 1; |
2739 | } else { | |
fab0aa3b EM |
2740 | if (report_ignored_msrs) |
2741 | vcpu_unimpl(vcpu, | |
2742 | "ignored wrmsr: 0x%x data 0x%llx\n", | |
2743 | msr, data); | |
ed85c068 AP |
2744 | break; |
2745 | } | |
15c4a640 CO |
2746 | } |
2747 | return 0; | |
2748 | } | |
2749 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
2750 | ||
2751 | ||
2752 | /* | |
2753 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2754 | * Returns 0 on success, non-0 otherwise. | |
2755 | * Assumes vcpu_load() was already called. | |
2756 | */ | |
609e36d3 | 2757 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) |
15c4a640 | 2758 | { |
609e36d3 | 2759 | return kvm_x86_ops->get_msr(vcpu, msr); |
15c4a640 | 2760 | } |
ff651cb6 | 2761 | EXPORT_SYMBOL_GPL(kvm_get_msr); |
15c4a640 | 2762 | |
44883f01 | 2763 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
2764 | { |
2765 | u64 data; | |
890ca9ae HY |
2766 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2767 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
2768 | |
2769 | switch (msr) { | |
15c4a640 CO |
2770 | case MSR_IA32_P5_MC_ADDR: |
2771 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
2772 | data = 0; |
2773 | break; | |
15c4a640 | 2774 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
2775 | data = vcpu->arch.mcg_cap; |
2776 | break; | |
c7ac679c | 2777 | case MSR_IA32_MCG_CTL: |
44883f01 | 2778 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
2779 | return 1; |
2780 | data = vcpu->arch.mcg_ctl; | |
2781 | break; | |
2782 | case MSR_IA32_MCG_STATUS: | |
2783 | data = vcpu->arch.mcg_status; | |
2784 | break; | |
2785 | default: | |
2786 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2787 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
890ca9ae HY |
2788 | u32 offset = msr - MSR_IA32_MC0_CTL; |
2789 | data = vcpu->arch.mce_banks[offset]; | |
2790 | break; | |
2791 | } | |
2792 | return 1; | |
2793 | } | |
2794 | *pdata = data; | |
2795 | return 0; | |
2796 | } | |
2797 | ||
609e36d3 | 2798 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 2799 | { |
609e36d3 | 2800 | switch (msr_info->index) { |
890ca9ae | 2801 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 2802 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
2803 | case MSR_IA32_DEBUGCTLMSR: |
2804 | case MSR_IA32_LASTBRANCHFROMIP: | |
2805 | case MSR_IA32_LASTBRANCHTOIP: | |
2806 | case MSR_IA32_LASTINTFROMIP: | |
2807 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 2808 | case MSR_K8_SYSCFG: |
3afb1121 PB |
2809 | case MSR_K8_TSEG_ADDR: |
2810 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 2811 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 2812 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 2813 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 2814 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 2815 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 2816 | case MSR_IA32_PERF_CTL: |
405a353a | 2817 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2818 | case MSR_F15H_EX_CFG: |
609e36d3 | 2819 | msr_info->data = 0; |
15c4a640 | 2820 | break; |
c51eb52b | 2821 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
2822 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
2823 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
2824 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
2825 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 2826 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 PB |
2827 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
2828 | msr_info->data = 0; | |
5753785f | 2829 | break; |
742bc670 | 2830 | case MSR_IA32_UCODE_REV: |
518e7b94 | 2831 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 2832 | break; |
0cf9135b SC |
2833 | case MSR_IA32_ARCH_CAPABILITIES: |
2834 | if (!msr_info->host_initiated && | |
2835 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
2836 | return 1; | |
2837 | msr_info->data = vcpu->arch.arch_capabilities; | |
2838 | break; | |
73f624f4 PB |
2839 | case MSR_IA32_POWER_CTL: |
2840 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
2841 | break; | |
dd259935 PB |
2842 | case MSR_IA32_TSC: |
2843 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; | |
2844 | break; | |
9ba075a6 | 2845 | case MSR_MTRRcap: |
9ba075a6 | 2846 | case 0x200 ... 0x2ff: |
ff53604b | 2847 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 2848 | case 0xcd: /* fsb frequency */ |
609e36d3 | 2849 | msr_info->data = 3; |
15c4a640 | 2850 | break; |
7b914098 JS |
2851 | /* |
2852 | * MSR_EBC_FREQUENCY_ID | |
2853 | * Conservative value valid for even the basic CPU models. | |
2854 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
2855 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
2856 | * and 266MHz for model 3, or 4. Set Core Clock | |
2857 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
2858 | * 31:24) even though these are only valid for CPU | |
2859 | * models > 2, however guests may end up dividing or | |
2860 | * multiplying by zero otherwise. | |
2861 | */ | |
2862 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 2863 | msr_info->data = 1 << 24; |
7b914098 | 2864 | break; |
15c4a640 | 2865 | case MSR_IA32_APICBASE: |
609e36d3 | 2866 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 2867 | break; |
0105d1a5 | 2868 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
609e36d3 | 2869 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
0105d1a5 | 2870 | break; |
a3e06bbe | 2871 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 2872 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 2873 | break; |
ba904635 | 2874 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 2875 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 2876 | break; |
15c4a640 | 2877 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 2878 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 2879 | break; |
64d60670 PB |
2880 | case MSR_IA32_SMBASE: |
2881 | if (!msr_info->host_initiated) | |
2882 | return 1; | |
2883 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 2884 | break; |
52797bf9 LA |
2885 | case MSR_SMI_COUNT: |
2886 | msr_info->data = vcpu->arch.smi_count; | |
2887 | break; | |
847f0ad8 AG |
2888 | case MSR_IA32_PERF_STATUS: |
2889 | /* TSC increment by tick */ | |
609e36d3 | 2890 | msr_info->data = 1000ULL; |
847f0ad8 | 2891 | /* CPU multiplier */ |
b0996ae4 | 2892 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 2893 | break; |
15c4a640 | 2894 | case MSR_EFER: |
609e36d3 | 2895 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 2896 | break; |
18068523 | 2897 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 2898 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 2899 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
2900 | break; |
2901 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 2902 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 2903 | msr_info->data = vcpu->arch.time; |
18068523 | 2904 | break; |
344d9588 | 2905 | case MSR_KVM_ASYNC_PF_EN: |
609e36d3 | 2906 | msr_info->data = vcpu->arch.apf.msr_val; |
344d9588 | 2907 | break; |
c9aaa895 | 2908 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 2909 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 2910 | break; |
1d92128f | 2911 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 2912 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 2913 | break; |
2d5ba19b MT |
2914 | case MSR_KVM_POLL_CONTROL: |
2915 | msr_info->data = vcpu->arch.msr_kvm_poll_control; | |
2916 | break; | |
890ca9ae HY |
2917 | case MSR_IA32_P5_MC_ADDR: |
2918 | case MSR_IA32_P5_MC_TYPE: | |
2919 | case MSR_IA32_MCG_CAP: | |
2920 | case MSR_IA32_MCG_CTL: | |
2921 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 2922 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
2923 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
2924 | msr_info->host_initiated); | |
84e0cefa JS |
2925 | case MSR_K7_CLK_CTL: |
2926 | /* | |
2927 | * Provide expected ramp-up count for K7. All other | |
2928 | * are set to zero, indicating minimum divisors for | |
2929 | * every field. | |
2930 | * | |
2931 | * This prevents guest kernels on AMD host with CPU | |
2932 | * type 6, model 8 and higher from exploding due to | |
2933 | * the rdmsr failing. | |
2934 | */ | |
609e36d3 | 2935 | msr_info->data = 0x20000000; |
84e0cefa | 2936 | break; |
55cd8e5a | 2937 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
e7d9513b AS |
2938 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
2939 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 2940 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
2941 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
2942 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
2943 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 2944 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
2945 | msr_info->index, &msr_info->data, |
2946 | msr_info->host_initiated); | |
55cd8e5a | 2947 | break; |
91c9c3ed | 2948 | case MSR_IA32_BBL_CR_CTL3: |
2949 | /* This legacy MSR exists but isn't fully documented in current | |
2950 | * silicon. It is however accessed by winxp in very narrow | |
2951 | * scenarios where it sets bit #19, itself documented as | |
2952 | * a "reserved" bit. Best effort attempt to source coherent | |
2953 | * read data here should the balance of the register be | |
2954 | * interpreted by the guest: | |
2955 | * | |
2956 | * L2 cache control register 3: 64GB range, 256KB size, | |
2957 | * enabled, latency 0x1, configured | |
2958 | */ | |
609e36d3 | 2959 | msr_info->data = 0xbe702111; |
91c9c3ed | 2960 | break; |
2b036c6b | 2961 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 2962 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 2963 | return 1; |
609e36d3 | 2964 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
2965 | break; |
2966 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 2967 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 2968 | return 1; |
609e36d3 | 2969 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 2970 | break; |
db2336a8 | 2971 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
2972 | if (!msr_info->host_initiated && |
2973 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
2974 | return 1; | |
db2336a8 KH |
2975 | msr_info->data = vcpu->arch.msr_platform_info; |
2976 | break; | |
2977 | case MSR_MISC_FEATURES_ENABLES: | |
2978 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
2979 | break; | |
191c8137 BP |
2980 | case MSR_K7_HWCR: |
2981 | msr_info->data = vcpu->arch.msr_hwcr; | |
2982 | break; | |
15c4a640 | 2983 | default: |
c6702c9d | 2984 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
609e36d3 | 2985 | return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); |
ed85c068 | 2986 | if (!ignore_msrs) { |
ae0f5499 BD |
2987 | vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", |
2988 | msr_info->index); | |
ed85c068 AP |
2989 | return 1; |
2990 | } else { | |
fab0aa3b EM |
2991 | if (report_ignored_msrs) |
2992 | vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", | |
2993 | msr_info->index); | |
609e36d3 | 2994 | msr_info->data = 0; |
ed85c068 AP |
2995 | } |
2996 | break; | |
15c4a640 | 2997 | } |
15c4a640 CO |
2998 | return 0; |
2999 | } | |
3000 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3001 | ||
313a3dc7 CO |
3002 | /* |
3003 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3004 | * | |
3005 | * @return number of msrs set successfully. | |
3006 | */ | |
3007 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3008 | struct kvm_msr_entry *entries, | |
3009 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3010 | unsigned index, u64 *data)) | |
3011 | { | |
801e459a | 3012 | int i; |
313a3dc7 | 3013 | |
313a3dc7 CO |
3014 | for (i = 0; i < msrs->nmsrs; ++i) |
3015 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3016 | break; | |
3017 | ||
313a3dc7 CO |
3018 | return i; |
3019 | } | |
3020 | ||
3021 | /* | |
3022 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3023 | * | |
3024 | * @return number of msrs set successfully. | |
3025 | */ | |
3026 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3027 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3028 | unsigned index, u64 *data), | |
3029 | int writeback) | |
3030 | { | |
3031 | struct kvm_msrs msrs; | |
3032 | struct kvm_msr_entry *entries; | |
3033 | int r, n; | |
3034 | unsigned size; | |
3035 | ||
3036 | r = -EFAULT; | |
0e96f31e | 3037 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3038 | goto out; |
3039 | ||
3040 | r = -E2BIG; | |
3041 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3042 | goto out; | |
3043 | ||
313a3dc7 | 3044 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3045 | entries = memdup_user(user_msrs->entries, size); |
3046 | if (IS_ERR(entries)) { | |
3047 | r = PTR_ERR(entries); | |
313a3dc7 | 3048 | goto out; |
ff5c2c03 | 3049 | } |
313a3dc7 CO |
3050 | |
3051 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3052 | if (r < 0) | |
3053 | goto out_free; | |
3054 | ||
3055 | r = -EFAULT; | |
3056 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3057 | goto out_free; | |
3058 | ||
3059 | r = n; | |
3060 | ||
3061 | out_free: | |
7a73c028 | 3062 | kfree(entries); |
313a3dc7 CO |
3063 | out: |
3064 | return r; | |
3065 | } | |
3066 | ||
4d5422ce WL |
3067 | static inline bool kvm_can_mwait_in_guest(void) |
3068 | { | |
3069 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3070 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3071 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3072 | } |
3073 | ||
784aa3d7 | 3074 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3075 | { |
4d5422ce | 3076 | int r = 0; |
018d00d2 ZX |
3077 | |
3078 | switch (ext) { | |
3079 | case KVM_CAP_IRQCHIP: | |
3080 | case KVM_CAP_HLT: | |
3081 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3082 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3083 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3084 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3085 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3086 | case KVM_CAP_PIT: |
a28e4f5a | 3087 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3088 | case KVM_CAP_MP_STATE: |
ed848624 | 3089 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3090 | case KVM_CAP_USER_NMI: |
52d939a0 | 3091 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3092 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3093 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3094 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3095 | case KVM_CAP_PIT2: |
e9f42757 | 3096 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3097 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3098 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3099 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3100 | case KVM_CAP_HYPERV: |
10388a07 | 3101 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3102 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3103 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3104 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3105 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3106 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3107 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3108 | case KVM_CAP_HYPERV_SEND_IPI: |
57b119da | 3109 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
2bc39970 | 3110 | case KVM_CAP_HYPERV_CPUID: |
ab9f4ecb | 3111 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3112 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3113 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3114 | case KVM_CAP_XSAVE: |
344d9588 | 3115 | case KVM_CAP_ASYNC_PF: |
92a1f12d | 3116 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3117 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3118 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3119 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3120 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3121 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3122 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3123 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3124 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3125 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3126 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3127 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3128 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3129 | case KVM_CAP_EXCEPTION_PAYLOAD: |
018d00d2 ZX |
3130 | r = 1; |
3131 | break; | |
01643c51 KH |
3132 | case KVM_CAP_SYNC_REGS: |
3133 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3134 | break; | |
e3fd9a93 PB |
3135 | case KVM_CAP_ADJUST_CLOCK: |
3136 | r = KVM_CLOCK_TSC_STABLE; | |
3137 | break; | |
4d5422ce | 3138 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3139 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3140 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3141 | if(kvm_can_mwait_in_guest()) |
3142 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3143 | break; |
6d396b55 PB |
3144 | case KVM_CAP_X86_SMM: |
3145 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3146 | * and SMM handlers might indeed rely on 4G segment limits, | |
3147 | * so do not report SMM to be available if real mode is | |
3148 | * emulated via vm86 mode. Still, do not go to great lengths | |
3149 | * to avoid userspace's usage of the feature, because it is a | |
3150 | * fringe case that is not enabled except via specific settings | |
3151 | * of the module parameters. | |
3152 | */ | |
bc226f07 | 3153 | r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); |
6d396b55 | 3154 | break; |
774ead3a AK |
3155 | case KVM_CAP_VAPIC: |
3156 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
3157 | break; | |
f725230a | 3158 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3159 | r = KVM_SOFT_MAX_VCPUS; |
3160 | break; | |
3161 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3162 | r = KVM_MAX_VCPUS; |
3163 | break; | |
a86cb413 TH |
3164 | case KVM_CAP_MAX_VCPU_ID: |
3165 | r = KVM_MAX_VCPU_ID; | |
3166 | break; | |
a68a6a72 MT |
3167 | case KVM_CAP_PV_MMU: /* obsolete */ |
3168 | r = 0; | |
2f333bcb | 3169 | break; |
890ca9ae HY |
3170 | case KVM_CAP_MCE: |
3171 | r = KVM_MAX_MCE_BANKS; | |
3172 | break; | |
2d5b5a66 | 3173 | case KVM_CAP_XCRS: |
d366bf7e | 3174 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3175 | break; |
92a1f12d JR |
3176 | case KVM_CAP_TSC_CONTROL: |
3177 | r = kvm_has_tsc_control; | |
3178 | break; | |
37131313 RK |
3179 | case KVM_CAP_X2APIC_API: |
3180 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3181 | break; | |
8fcc4b59 JM |
3182 | case KVM_CAP_NESTED_STATE: |
3183 | r = kvm_x86_ops->get_nested_state ? | |
be43c440 | 3184 | kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; |
8fcc4b59 | 3185 | break; |
018d00d2 | 3186 | default: |
018d00d2 ZX |
3187 | break; |
3188 | } | |
3189 | return r; | |
3190 | ||
3191 | } | |
3192 | ||
043405e1 CO |
3193 | long kvm_arch_dev_ioctl(struct file *filp, |
3194 | unsigned int ioctl, unsigned long arg) | |
3195 | { | |
3196 | void __user *argp = (void __user *)arg; | |
3197 | long r; | |
3198 | ||
3199 | switch (ioctl) { | |
3200 | case KVM_GET_MSR_INDEX_LIST: { | |
3201 | struct kvm_msr_list __user *user_msr_list = argp; | |
3202 | struct kvm_msr_list msr_list; | |
3203 | unsigned n; | |
3204 | ||
3205 | r = -EFAULT; | |
0e96f31e | 3206 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3207 | goto out; |
3208 | n = msr_list.nmsrs; | |
62ef68bb | 3209 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3210 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3211 | goto out; |
3212 | r = -E2BIG; | |
e125e7b6 | 3213 | if (n < msr_list.nmsrs) |
043405e1 CO |
3214 | goto out; |
3215 | r = -EFAULT; | |
3216 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3217 | num_msrs_to_save * sizeof(u32))) | |
3218 | goto out; | |
e125e7b6 | 3219 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3220 | &emulated_msrs, |
62ef68bb | 3221 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3222 | goto out; |
3223 | r = 0; | |
3224 | break; | |
3225 | } | |
9c15bb1d BP |
3226 | case KVM_GET_SUPPORTED_CPUID: |
3227 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3228 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3229 | struct kvm_cpuid2 cpuid; | |
3230 | ||
3231 | r = -EFAULT; | |
0e96f31e | 3232 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3233 | goto out; |
9c15bb1d BP |
3234 | |
3235 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3236 | ioctl); | |
674eea0f AK |
3237 | if (r) |
3238 | goto out; | |
3239 | ||
3240 | r = -EFAULT; | |
0e96f31e | 3241 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3242 | goto out; |
3243 | r = 0; | |
3244 | break; | |
3245 | } | |
890ca9ae | 3246 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
890ca9ae | 3247 | r = -EFAULT; |
c45dcc71 AR |
3248 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3249 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3250 | goto out; |
3251 | r = 0; | |
3252 | break; | |
801e459a TL |
3253 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3254 | struct kvm_msr_list __user *user_msr_list = argp; | |
3255 | struct kvm_msr_list msr_list; | |
3256 | unsigned int n; | |
3257 | ||
3258 | r = -EFAULT; | |
3259 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3260 | goto out; | |
3261 | n = msr_list.nmsrs; | |
3262 | msr_list.nmsrs = num_msr_based_features; | |
3263 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3264 | goto out; | |
3265 | r = -E2BIG; | |
3266 | if (n < msr_list.nmsrs) | |
3267 | goto out; | |
3268 | r = -EFAULT; | |
3269 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3270 | num_msr_based_features * sizeof(u32))) | |
3271 | goto out; | |
3272 | r = 0; | |
3273 | break; | |
3274 | } | |
3275 | case KVM_GET_MSRS: | |
3276 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3277 | break; | |
890ca9ae | 3278 | } |
043405e1 CO |
3279 | default: |
3280 | r = -EINVAL; | |
3281 | } | |
3282 | out: | |
3283 | return r; | |
3284 | } | |
3285 | ||
f5f48ee1 SY |
3286 | static void wbinvd_ipi(void *garbage) |
3287 | { | |
3288 | wbinvd(); | |
3289 | } | |
3290 | ||
3291 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3292 | { | |
e0f0bbc5 | 3293 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3294 | } |
3295 | ||
313a3dc7 CO |
3296 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3297 | { | |
f5f48ee1 SY |
3298 | /* Address WBINVD may be executed by guest */ |
3299 | if (need_emulate_wbinvd(vcpu)) { | |
3300 | if (kvm_x86_ops->has_wbinvd_exit()) | |
3301 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
3302 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3303 | smp_call_function_single(vcpu->cpu, | |
3304 | wbinvd_ipi, NULL, 1); | |
3305 | } | |
3306 | ||
313a3dc7 | 3307 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
8f6055cb | 3308 | |
e7517324 WL |
3309 | fpregs_assert_state_consistent(); |
3310 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
3311 | switch_fpu_return(); | |
3312 | ||
0dd6a6ed ZA |
3313 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3314 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3315 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3316 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3317 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3318 | } |
8f6055cb | 3319 | |
b0c39dc6 | 3320 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3321 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3322 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3323 | if (tsc_delta < 0) |
3324 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3325 | |
b0c39dc6 | 3326 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3327 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3328 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3329 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3330 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3331 | } |
a749e247 PB |
3332 | |
3333 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3334 | kvm_lapic_restart_hv_timer(vcpu); | |
3335 | ||
d98d07ca MT |
3336 | /* |
3337 | * On a host with synchronized TSC, there is no need to update | |
3338 | * kvmclock on vcpu->cpu migration | |
3339 | */ | |
3340 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3341 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3342 | if (vcpu->cpu != cpu) |
1bd2009e | 3343 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3344 | vcpu->cpu = cpu; |
6b7d7e76 | 3345 | } |
c9aaa895 | 3346 | |
c9aaa895 | 3347 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3348 | } |
3349 | ||
0b9f6c46 PX |
3350 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3351 | { | |
3352 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) | |
3353 | return; | |
3354 | ||
fa55eedd | 3355 | vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3356 | |
4e335d9e | 3357 | kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, |
0b9f6c46 PX |
3358 | &vcpu->arch.st.steal.preempted, |
3359 | offsetof(struct kvm_steal_time, preempted), | |
3360 | sizeof(vcpu->arch.st.steal.preempted)); | |
3361 | } | |
3362 | ||
313a3dc7 CO |
3363 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3364 | { | |
cc0d907c | 3365 | int idx; |
de63ad4c LM |
3366 | |
3367 | if (vcpu->preempted) | |
3368 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); | |
3369 | ||
931f261b AA |
3370 | /* |
3371 | * Disable page faults because we're in atomic context here. | |
3372 | * kvm_write_guest_offset_cached() would call might_fault() | |
3373 | * that relies on pagefault_disable() to tell if there's a | |
3374 | * bug. NOTE: the write to guest memory may not go through if | |
3375 | * during postcopy live migration or if there's heavy guest | |
3376 | * paging. | |
3377 | */ | |
3378 | pagefault_disable(); | |
cc0d907c AA |
3379 | /* |
3380 | * kvm_memslots() will be called by | |
3381 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
3382 | */ | |
3383 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 3384 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 3385 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 3386 | pagefault_enable(); |
02daab21 | 3387 | kvm_x86_ops->vcpu_put(vcpu); |
4ea1636b | 3388 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 3389 | /* |
f9dcf08e RK |
3390 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
3391 | * on every vmexit, but if not, we might have a stale dr6 from the | |
3392 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 3393 | */ |
f9dcf08e | 3394 | set_debugreg(0, 6); |
313a3dc7 CO |
3395 | } |
3396 | ||
313a3dc7 CO |
3397 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3398 | struct kvm_lapic_state *s) | |
3399 | { | |
fa59cc00 | 3400 | if (vcpu->arch.apicv_active) |
d62caabb AS |
3401 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
3402 | ||
a92e2543 | 3403 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
3404 | } |
3405 | ||
3406 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3407 | struct kvm_lapic_state *s) | |
3408 | { | |
a92e2543 RK |
3409 | int r; |
3410 | ||
3411 | r = kvm_apic_set_state(vcpu, s); | |
3412 | if (r) | |
3413 | return r; | |
cb142eb7 | 3414 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3415 | |
3416 | return 0; | |
3417 | } | |
3418 | ||
127a457a MG |
3419 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
3420 | { | |
3421 | return (!lapic_in_kernel(vcpu) || | |
3422 | kvm_apic_accept_pic_intr(vcpu)); | |
3423 | } | |
3424 | ||
782d422b MG |
3425 | /* |
3426 | * if userspace requested an interrupt window, check that the | |
3427 | * interrupt window is open. | |
3428 | * | |
3429 | * No need to exit to userspace if we already have an interrupt queued. | |
3430 | */ | |
3431 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
3432 | { | |
3433 | return kvm_arch_interrupt_allowed(vcpu) && | |
3434 | !kvm_cpu_has_interrupt(vcpu) && | |
3435 | !kvm_event_needs_reinjection(vcpu) && | |
3436 | kvm_cpu_accept_dm_intr(vcpu); | |
3437 | } | |
3438 | ||
f77bc6a4 ZX |
3439 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3440 | struct kvm_interrupt *irq) | |
3441 | { | |
02cdb50f | 3442 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 3443 | return -EINVAL; |
1c1a9ce9 SR |
3444 | |
3445 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
3446 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
3447 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
3448 | return 0; | |
3449 | } | |
3450 | ||
3451 | /* | |
3452 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
3453 | * fail for in-kernel 8259. | |
3454 | */ | |
3455 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 3456 | return -ENXIO; |
f77bc6a4 | 3457 | |
1c1a9ce9 SR |
3458 | if (vcpu->arch.pending_external_vector != -1) |
3459 | return -EEXIST; | |
f77bc6a4 | 3460 | |
1c1a9ce9 | 3461 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 3462 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
3463 | return 0; |
3464 | } | |
3465 | ||
c4abb7c9 JK |
3466 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3467 | { | |
c4abb7c9 | 3468 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3469 | |
3470 | return 0; | |
3471 | } | |
3472 | ||
f077825a PB |
3473 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3474 | { | |
64d60670 PB |
3475 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3476 | ||
f077825a PB |
3477 | return 0; |
3478 | } | |
3479 | ||
b209749f AK |
3480 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3481 | struct kvm_tpr_access_ctl *tac) | |
3482 | { | |
3483 | if (tac->flags) | |
3484 | return -EINVAL; | |
3485 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3486 | return 0; | |
3487 | } | |
3488 | ||
890ca9ae HY |
3489 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3490 | u64 mcg_cap) | |
3491 | { | |
3492 | int r; | |
3493 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3494 | ||
3495 | r = -EINVAL; | |
a9e38c3e | 3496 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae | 3497 | goto out; |
c45dcc71 | 3498 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
3499 | goto out; |
3500 | r = 0; | |
3501 | vcpu->arch.mcg_cap = mcg_cap; | |
3502 | /* Init IA32_MCG_CTL to all 1s */ | |
3503 | if (mcg_cap & MCG_CTL_P) | |
3504 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3505 | /* Init IA32_MCi_CTL to all 1s */ | |
3506 | for (bank = 0; bank < bank_num; bank++) | |
3507 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 AR |
3508 | |
3509 | if (kvm_x86_ops->setup_mce) | |
3510 | kvm_x86_ops->setup_mce(vcpu); | |
890ca9ae HY |
3511 | out: |
3512 | return r; | |
3513 | } | |
3514 | ||
3515 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3516 | struct kvm_x86_mce *mce) | |
3517 | { | |
3518 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3519 | unsigned bank_num = mcg_cap & 0xff; | |
3520 | u64 *banks = vcpu->arch.mce_banks; | |
3521 | ||
3522 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3523 | return -EINVAL; | |
3524 | /* | |
3525 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3526 | * reporting is disabled | |
3527 | */ | |
3528 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3529 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3530 | return 0; | |
3531 | banks += 4 * mce->bank; | |
3532 | /* | |
3533 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3534 | * reporting is disabled for the bank | |
3535 | */ | |
3536 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3537 | return 0; | |
3538 | if (mce->status & MCI_STATUS_UC) { | |
3539 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3540 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3541 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3542 | return 0; |
3543 | } | |
3544 | if (banks[1] & MCI_STATUS_VAL) | |
3545 | mce->status |= MCI_STATUS_OVER; | |
3546 | banks[2] = mce->addr; | |
3547 | banks[3] = mce->misc; | |
3548 | vcpu->arch.mcg_status = mce->mcg_status; | |
3549 | banks[1] = mce->status; | |
3550 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3551 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3552 | || !(banks[1] & MCI_STATUS_UC)) { | |
3553 | if (banks[1] & MCI_STATUS_VAL) | |
3554 | mce->status |= MCI_STATUS_OVER; | |
3555 | banks[2] = mce->addr; | |
3556 | banks[3] = mce->misc; | |
3557 | banks[1] = mce->status; | |
3558 | } else | |
3559 | banks[1] |= MCI_STATUS_OVER; | |
3560 | return 0; | |
3561 | } | |
3562 | ||
3cfc3092 JK |
3563 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3564 | struct kvm_vcpu_events *events) | |
3565 | { | |
7460fb4a | 3566 | process_nmi(vcpu); |
59073aaf | 3567 | |
664f8e26 | 3568 | /* |
59073aaf JM |
3569 | * The API doesn't provide the instruction length for software |
3570 | * exceptions, so don't report them. As long as the guest RIP | |
3571 | * isn't advanced, we should expect to encounter the exception | |
3572 | * again. | |
664f8e26 | 3573 | */ |
59073aaf JM |
3574 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
3575 | events->exception.injected = 0; | |
3576 | events->exception.pending = 0; | |
3577 | } else { | |
3578 | events->exception.injected = vcpu->arch.exception.injected; | |
3579 | events->exception.pending = vcpu->arch.exception.pending; | |
3580 | /* | |
3581 | * For ABI compatibility, deliberately conflate | |
3582 | * pending and injected exceptions when | |
3583 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
3584 | */ | |
3585 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3586 | events->exception.injected |= | |
3587 | vcpu->arch.exception.pending; | |
3588 | } | |
3cfc3092 JK |
3589 | events->exception.nr = vcpu->arch.exception.nr; |
3590 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
3591 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
3592 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
3593 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 3594 | |
03b82a30 | 3595 | events->interrupt.injected = |
04140b41 | 3596 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 3597 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 3598 | events->interrupt.soft = 0; |
37ccdcbe | 3599 | events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
3cfc3092 JK |
3600 | |
3601 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 3602 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
3cfc3092 | 3603 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); |
97e69aa6 | 3604 | events->nmi.pad = 0; |
3cfc3092 | 3605 | |
66450a21 | 3606 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 3607 | |
f077825a PB |
3608 | events->smi.smm = is_smm(vcpu); |
3609 | events->smi.pending = vcpu->arch.smi_pending; | |
3610 | events->smi.smm_inside_nmi = | |
3611 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
3612 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
3613 | ||
dab4b911 | 3614 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
3615 | | KVM_VCPUEVENT_VALID_SHADOW |
3616 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
3617 | if (vcpu->kvm->arch.exception_payload_enabled) |
3618 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
3619 | ||
97e69aa6 | 3620 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
3621 | } |
3622 | ||
c5833c7a | 3623 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 3624 | |
3cfc3092 JK |
3625 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
3626 | struct kvm_vcpu_events *events) | |
3627 | { | |
dab4b911 | 3628 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 3629 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 3630 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
3631 | | KVM_VCPUEVENT_VALID_SMM |
3632 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
3633 | return -EINVAL; |
3634 | ||
59073aaf JM |
3635 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
3636 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
3637 | return -EINVAL; | |
3638 | if (events->exception.pending) | |
3639 | events->exception.injected = 0; | |
3640 | else | |
3641 | events->exception_has_payload = 0; | |
3642 | } else { | |
3643 | events->exception.pending = 0; | |
3644 | events->exception_has_payload = 0; | |
3645 | } | |
3646 | ||
3647 | if ((events->exception.injected || events->exception.pending) && | |
3648 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
3649 | return -EINVAL; |
3650 | ||
28bf2888 DH |
3651 | /* INITs are latched while in SMM */ |
3652 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
3653 | (events->smi.smm || events->smi.pending) && | |
3654 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
3655 | return -EINVAL; | |
3656 | ||
7460fb4a | 3657 | process_nmi(vcpu); |
59073aaf JM |
3658 | vcpu->arch.exception.injected = events->exception.injected; |
3659 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
3660 | vcpu->arch.exception.nr = events->exception.nr; |
3661 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
3662 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
3663 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
3664 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 3665 | |
04140b41 | 3666 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
3667 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
3668 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 JK |
3669 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
3670 | kvm_x86_ops->set_interrupt_shadow(vcpu, | |
3671 | events->interrupt.shadow); | |
3cfc3092 JK |
3672 | |
3673 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
3674 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
3675 | vcpu->arch.nmi_pending = events->nmi.pending; | |
3cfc3092 JK |
3676 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); |
3677 | ||
66450a21 | 3678 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 3679 | lapic_in_kernel(vcpu)) |
66450a21 | 3680 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 3681 | |
f077825a | 3682 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
3683 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
3684 | if (events->smi.smm) | |
3685 | vcpu->arch.hflags |= HF_SMM_MASK; | |
3686 | else | |
3687 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
3688 | kvm_smm_changed(vcpu); | |
3689 | } | |
6ef4e07e | 3690 | |
f077825a | 3691 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
3692 | |
3693 | if (events->smi.smm) { | |
3694 | if (events->smi.smm_inside_nmi) | |
3695 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 3696 | else |
f4ef1910 WL |
3697 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
3698 | if (lapic_in_kernel(vcpu)) { | |
3699 | if (events->smi.latched_init) | |
3700 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3701 | else | |
3702 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
3703 | } | |
f077825a PB |
3704 | } |
3705 | } | |
3706 | ||
3842d135 AK |
3707 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3708 | ||
3cfc3092 JK |
3709 | return 0; |
3710 | } | |
3711 | ||
a1efbe77 JK |
3712 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
3713 | struct kvm_debugregs *dbgregs) | |
3714 | { | |
73aaf249 JK |
3715 | unsigned long val; |
3716 | ||
a1efbe77 | 3717 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 3718 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 3719 | dbgregs->dr6 = val; |
a1efbe77 JK |
3720 | dbgregs->dr7 = vcpu->arch.dr7; |
3721 | dbgregs->flags = 0; | |
97e69aa6 | 3722 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
3723 | } |
3724 | ||
3725 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
3726 | struct kvm_debugregs *dbgregs) | |
3727 | { | |
3728 | if (dbgregs->flags) | |
3729 | return -EINVAL; | |
3730 | ||
d14bdb55 PB |
3731 | if (dbgregs->dr6 & ~0xffffffffull) |
3732 | return -EINVAL; | |
3733 | if (dbgregs->dr7 & ~0xffffffffull) | |
3734 | return -EINVAL; | |
3735 | ||
a1efbe77 | 3736 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 3737 | kvm_update_dr0123(vcpu); |
a1efbe77 | 3738 | vcpu->arch.dr6 = dbgregs->dr6; |
73aaf249 | 3739 | kvm_update_dr6(vcpu); |
a1efbe77 | 3740 | vcpu->arch.dr7 = dbgregs->dr7; |
9926c9fd | 3741 | kvm_update_dr7(vcpu); |
a1efbe77 | 3742 | |
a1efbe77 JK |
3743 | return 0; |
3744 | } | |
3745 | ||
df1daba7 PB |
3746 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
3747 | ||
3748 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
3749 | { | |
b666a4b6 | 3750 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 3751 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
3752 | u64 valid; |
3753 | ||
3754 | /* | |
3755 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3756 | * leaves 0 and 1 in the loop below. | |
3757 | */ | |
3758 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
3759 | ||
3760 | /* Set XSTATE_BV */ | |
00c87e9a | 3761 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
3762 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
3763 | ||
3764 | /* | |
3765 | * Copy each region from the possibly compacted offset to the | |
3766 | * non-compacted offset. | |
3767 | */ | |
d91cab78 | 3768 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 3769 | while (valid) { |
abd16d68 SAS |
3770 | u64 xfeature_mask = valid & -valid; |
3771 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
3772 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
3773 | |
3774 | if (src) { | |
3775 | u32 size, offset, ecx, edx; | |
abd16d68 | 3776 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 3777 | &size, &offset, &ecx, &edx); |
abd16d68 | 3778 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
3779 | memcpy(dest + offset, &vcpu->arch.pkru, |
3780 | sizeof(vcpu->arch.pkru)); | |
3781 | else | |
3782 | memcpy(dest + offset, src, size); | |
3783 | ||
df1daba7 PB |
3784 | } |
3785 | ||
abd16d68 | 3786 | valid -= xfeature_mask; |
df1daba7 PB |
3787 | } |
3788 | } | |
3789 | ||
3790 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
3791 | { | |
b666a4b6 | 3792 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
3793 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
3794 | u64 valid; | |
3795 | ||
3796 | /* | |
3797 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
3798 | * leaves 0 and 1 in the loop below. | |
3799 | */ | |
3800 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
3801 | ||
3802 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 3803 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 3804 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 3805 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
3806 | |
3807 | /* | |
3808 | * Copy each region from the non-compacted offset to the | |
3809 | * possibly compacted offset. | |
3810 | */ | |
d91cab78 | 3811 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 3812 | while (valid) { |
abd16d68 SAS |
3813 | u64 xfeature_mask = valid & -valid; |
3814 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
3815 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
3816 | |
3817 | if (dest) { | |
3818 | u32 size, offset, ecx, edx; | |
abd16d68 | 3819 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 3820 | &size, &offset, &ecx, &edx); |
abd16d68 | 3821 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
3822 | memcpy(&vcpu->arch.pkru, src + offset, |
3823 | sizeof(vcpu->arch.pkru)); | |
3824 | else | |
3825 | memcpy(dest, src + offset, size); | |
ee4100da | 3826 | } |
df1daba7 | 3827 | |
abd16d68 | 3828 | valid -= xfeature_mask; |
df1daba7 PB |
3829 | } |
3830 | } | |
3831 | ||
2d5b5a66 SY |
3832 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
3833 | struct kvm_xsave *guest_xsave) | |
3834 | { | |
d366bf7e | 3835 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
3836 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
3837 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 3838 | } else { |
2d5b5a66 | 3839 | memcpy(guest_xsave->region, |
b666a4b6 | 3840 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 3841 | sizeof(struct fxregs_state)); |
2d5b5a66 | 3842 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 3843 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
3844 | } |
3845 | } | |
3846 | ||
a575813b WL |
3847 | #define XSAVE_MXCSR_OFFSET 24 |
3848 | ||
2d5b5a66 SY |
3849 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
3850 | struct kvm_xsave *guest_xsave) | |
3851 | { | |
3852 | u64 xstate_bv = | |
3853 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 3854 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 3855 | |
d366bf7e | 3856 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
3857 | /* |
3858 | * Here we allow setting states that are not present in | |
3859 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
3860 | * with old userspace. | |
3861 | */ | |
a575813b WL |
3862 | if (xstate_bv & ~kvm_supported_xcr0() || |
3863 | mxcsr & ~mxcsr_feature_mask) | |
d7876f1b | 3864 | return -EINVAL; |
df1daba7 | 3865 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 3866 | } else { |
a575813b WL |
3867 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
3868 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 3869 | return -EINVAL; |
b666a4b6 | 3870 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 3871 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
3872 | } |
3873 | return 0; | |
3874 | } | |
3875 | ||
3876 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
3877 | struct kvm_xcrs *guest_xcrs) | |
3878 | { | |
d366bf7e | 3879 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
3880 | guest_xcrs->nr_xcrs = 0; |
3881 | return; | |
3882 | } | |
3883 | ||
3884 | guest_xcrs->nr_xcrs = 1; | |
3885 | guest_xcrs->flags = 0; | |
3886 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
3887 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
3888 | } | |
3889 | ||
3890 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
3891 | struct kvm_xcrs *guest_xcrs) | |
3892 | { | |
3893 | int i, r = 0; | |
3894 | ||
d366bf7e | 3895 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
3896 | return -EINVAL; |
3897 | ||
3898 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
3899 | return -EINVAL; | |
3900 | ||
3901 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
3902 | /* Only support XCR0 currently */ | |
c67a04cb | 3903 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 3904 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 3905 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
3906 | break; |
3907 | } | |
3908 | if (r) | |
3909 | r = -EINVAL; | |
3910 | return r; | |
3911 | } | |
3912 | ||
1c0b28c2 EM |
3913 | /* |
3914 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
3915 | * stopped by the hypervisor. This function will be called from the host only. | |
3916 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
3917 | * does not support pv clocks. | |
3918 | */ | |
3919 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
3920 | { | |
0b79459b | 3921 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 3922 | return -EINVAL; |
51d59c6b | 3923 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
3924 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
3925 | return 0; | |
3926 | } | |
3927 | ||
5c919412 AS |
3928 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
3929 | struct kvm_enable_cap *cap) | |
3930 | { | |
57b119da VK |
3931 | int r; |
3932 | uint16_t vmcs_version; | |
3933 | void __user *user_ptr; | |
3934 | ||
5c919412 AS |
3935 | if (cap->flags) |
3936 | return -EINVAL; | |
3937 | ||
3938 | switch (cap->cap) { | |
efc479e6 RK |
3939 | case KVM_CAP_HYPERV_SYNIC2: |
3940 | if (cap->args[0]) | |
3941 | return -EINVAL; | |
b2869f28 GS |
3942 | /* fall through */ |
3943 | ||
5c919412 | 3944 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
3945 | if (!irqchip_in_kernel(vcpu->kvm)) |
3946 | return -EINVAL; | |
efc479e6 RK |
3947 | return kvm_hv_activate_synic(vcpu, cap->cap == |
3948 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 3949 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
5158917c SC |
3950 | if (!kvm_x86_ops->nested_enable_evmcs) |
3951 | return -ENOTTY; | |
57b119da VK |
3952 | r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); |
3953 | if (!r) { | |
3954 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
3955 | if (copy_to_user(user_ptr, &vmcs_version, | |
3956 | sizeof(vmcs_version))) | |
3957 | r = -EFAULT; | |
3958 | } | |
3959 | return r; | |
3960 | ||
5c919412 AS |
3961 | default: |
3962 | return -EINVAL; | |
3963 | } | |
3964 | } | |
3965 | ||
313a3dc7 CO |
3966 | long kvm_arch_vcpu_ioctl(struct file *filp, |
3967 | unsigned int ioctl, unsigned long arg) | |
3968 | { | |
3969 | struct kvm_vcpu *vcpu = filp->private_data; | |
3970 | void __user *argp = (void __user *)arg; | |
3971 | int r; | |
d1ac91d8 AK |
3972 | union { |
3973 | struct kvm_lapic_state *lapic; | |
3974 | struct kvm_xsave *xsave; | |
3975 | struct kvm_xcrs *xcrs; | |
3976 | void *buffer; | |
3977 | } u; | |
3978 | ||
9b062471 CD |
3979 | vcpu_load(vcpu); |
3980 | ||
d1ac91d8 | 3981 | u.buffer = NULL; |
313a3dc7 CO |
3982 | switch (ioctl) { |
3983 | case KVM_GET_LAPIC: { | |
2204ae3c | 3984 | r = -EINVAL; |
bce87cce | 3985 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 3986 | goto out; |
254272ce BG |
3987 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
3988 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 3989 | |
b772ff36 | 3990 | r = -ENOMEM; |
d1ac91d8 | 3991 | if (!u.lapic) |
b772ff36 | 3992 | goto out; |
d1ac91d8 | 3993 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
3994 | if (r) |
3995 | goto out; | |
3996 | r = -EFAULT; | |
d1ac91d8 | 3997 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
3998 | goto out; |
3999 | r = 0; | |
4000 | break; | |
4001 | } | |
4002 | case KVM_SET_LAPIC: { | |
2204ae3c | 4003 | r = -EINVAL; |
bce87cce | 4004 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4005 | goto out; |
ff5c2c03 | 4006 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4007 | if (IS_ERR(u.lapic)) { |
4008 | r = PTR_ERR(u.lapic); | |
4009 | goto out_nofree; | |
4010 | } | |
ff5c2c03 | 4011 | |
d1ac91d8 | 4012 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4013 | break; |
4014 | } | |
f77bc6a4 ZX |
4015 | case KVM_INTERRUPT: { |
4016 | struct kvm_interrupt irq; | |
4017 | ||
4018 | r = -EFAULT; | |
0e96f31e | 4019 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4020 | goto out; |
4021 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4022 | break; |
4023 | } | |
c4abb7c9 JK |
4024 | case KVM_NMI: { |
4025 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4026 | break; |
4027 | } | |
f077825a PB |
4028 | case KVM_SMI: { |
4029 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4030 | break; | |
4031 | } | |
313a3dc7 CO |
4032 | case KVM_SET_CPUID: { |
4033 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4034 | struct kvm_cpuid cpuid; | |
4035 | ||
4036 | r = -EFAULT; | |
0e96f31e | 4037 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4038 | goto out; |
4039 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4040 | break; |
4041 | } | |
07716717 DK |
4042 | case KVM_SET_CPUID2: { |
4043 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4044 | struct kvm_cpuid2 cpuid; | |
4045 | ||
4046 | r = -EFAULT; | |
0e96f31e | 4047 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4048 | goto out; |
4049 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4050 | cpuid_arg->entries); |
07716717 DK |
4051 | break; |
4052 | } | |
4053 | case KVM_GET_CPUID2: { | |
4054 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4055 | struct kvm_cpuid2 cpuid; | |
4056 | ||
4057 | r = -EFAULT; | |
0e96f31e | 4058 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4059 | goto out; |
4060 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4061 | cpuid_arg->entries); |
07716717 DK |
4062 | if (r) |
4063 | goto out; | |
4064 | r = -EFAULT; | |
0e96f31e | 4065 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4066 | goto out; |
4067 | r = 0; | |
4068 | break; | |
4069 | } | |
801e459a TL |
4070 | case KVM_GET_MSRS: { |
4071 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4072 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4073 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4074 | break; |
801e459a TL |
4075 | } |
4076 | case KVM_SET_MSRS: { | |
4077 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4078 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4079 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4080 | break; |
801e459a | 4081 | } |
b209749f AK |
4082 | case KVM_TPR_ACCESS_REPORTING: { |
4083 | struct kvm_tpr_access_ctl tac; | |
4084 | ||
4085 | r = -EFAULT; | |
0e96f31e | 4086 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4087 | goto out; |
4088 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4089 | if (r) | |
4090 | goto out; | |
4091 | r = -EFAULT; | |
0e96f31e | 4092 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4093 | goto out; |
4094 | r = 0; | |
4095 | break; | |
4096 | }; | |
b93463aa AK |
4097 | case KVM_SET_VAPIC_ADDR: { |
4098 | struct kvm_vapic_addr va; | |
7301d6ab | 4099 | int idx; |
b93463aa AK |
4100 | |
4101 | r = -EINVAL; | |
35754c98 | 4102 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4103 | goto out; |
4104 | r = -EFAULT; | |
0e96f31e | 4105 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4106 | goto out; |
7301d6ab | 4107 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4108 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4109 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4110 | break; |
4111 | } | |
890ca9ae HY |
4112 | case KVM_X86_SETUP_MCE: { |
4113 | u64 mcg_cap; | |
4114 | ||
4115 | r = -EFAULT; | |
0e96f31e | 4116 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4117 | goto out; |
4118 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4119 | break; | |
4120 | } | |
4121 | case KVM_X86_SET_MCE: { | |
4122 | struct kvm_x86_mce mce; | |
4123 | ||
4124 | r = -EFAULT; | |
0e96f31e | 4125 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4126 | goto out; |
4127 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4128 | break; | |
4129 | } | |
3cfc3092 JK |
4130 | case KVM_GET_VCPU_EVENTS: { |
4131 | struct kvm_vcpu_events events; | |
4132 | ||
4133 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4134 | ||
4135 | r = -EFAULT; | |
4136 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4137 | break; | |
4138 | r = 0; | |
4139 | break; | |
4140 | } | |
4141 | case KVM_SET_VCPU_EVENTS: { | |
4142 | struct kvm_vcpu_events events; | |
4143 | ||
4144 | r = -EFAULT; | |
4145 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4146 | break; | |
4147 | ||
4148 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4149 | break; | |
4150 | } | |
a1efbe77 JK |
4151 | case KVM_GET_DEBUGREGS: { |
4152 | struct kvm_debugregs dbgregs; | |
4153 | ||
4154 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4155 | ||
4156 | r = -EFAULT; | |
4157 | if (copy_to_user(argp, &dbgregs, | |
4158 | sizeof(struct kvm_debugregs))) | |
4159 | break; | |
4160 | r = 0; | |
4161 | break; | |
4162 | } | |
4163 | case KVM_SET_DEBUGREGS: { | |
4164 | struct kvm_debugregs dbgregs; | |
4165 | ||
4166 | r = -EFAULT; | |
4167 | if (copy_from_user(&dbgregs, argp, | |
4168 | sizeof(struct kvm_debugregs))) | |
4169 | break; | |
4170 | ||
4171 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4172 | break; | |
4173 | } | |
2d5b5a66 | 4174 | case KVM_GET_XSAVE: { |
254272ce | 4175 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4176 | r = -ENOMEM; |
d1ac91d8 | 4177 | if (!u.xsave) |
2d5b5a66 SY |
4178 | break; |
4179 | ||
d1ac91d8 | 4180 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4181 | |
4182 | r = -EFAULT; | |
d1ac91d8 | 4183 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4184 | break; |
4185 | r = 0; | |
4186 | break; | |
4187 | } | |
4188 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4189 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4190 | if (IS_ERR(u.xsave)) { |
4191 | r = PTR_ERR(u.xsave); | |
4192 | goto out_nofree; | |
4193 | } | |
2d5b5a66 | 4194 | |
d1ac91d8 | 4195 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4196 | break; |
4197 | } | |
4198 | case KVM_GET_XCRS: { | |
254272ce | 4199 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4200 | r = -ENOMEM; |
d1ac91d8 | 4201 | if (!u.xcrs) |
2d5b5a66 SY |
4202 | break; |
4203 | ||
d1ac91d8 | 4204 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4205 | |
4206 | r = -EFAULT; | |
d1ac91d8 | 4207 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4208 | sizeof(struct kvm_xcrs))) |
4209 | break; | |
4210 | r = 0; | |
4211 | break; | |
4212 | } | |
4213 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4214 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4215 | if (IS_ERR(u.xcrs)) { |
4216 | r = PTR_ERR(u.xcrs); | |
4217 | goto out_nofree; | |
4218 | } | |
2d5b5a66 | 4219 | |
d1ac91d8 | 4220 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4221 | break; |
4222 | } | |
92a1f12d JR |
4223 | case KVM_SET_TSC_KHZ: { |
4224 | u32 user_tsc_khz; | |
4225 | ||
4226 | r = -EINVAL; | |
92a1f12d JR |
4227 | user_tsc_khz = (u32)arg; |
4228 | ||
4229 | if (user_tsc_khz >= kvm_max_guest_tsc_khz) | |
4230 | goto out; | |
4231 | ||
cc578287 ZA |
4232 | if (user_tsc_khz == 0) |
4233 | user_tsc_khz = tsc_khz; | |
4234 | ||
381d585c HZ |
4235 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4236 | r = 0; | |
92a1f12d | 4237 | |
92a1f12d JR |
4238 | goto out; |
4239 | } | |
4240 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4241 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4242 | goto out; |
4243 | } | |
1c0b28c2 EM |
4244 | case KVM_KVMCLOCK_CTRL: { |
4245 | r = kvm_set_guest_paused(vcpu); | |
4246 | goto out; | |
4247 | } | |
5c919412 AS |
4248 | case KVM_ENABLE_CAP: { |
4249 | struct kvm_enable_cap cap; | |
4250 | ||
4251 | r = -EFAULT; | |
4252 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4253 | goto out; | |
4254 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4255 | break; | |
4256 | } | |
8fcc4b59 JM |
4257 | case KVM_GET_NESTED_STATE: { |
4258 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4259 | u32 user_data_size; | |
4260 | ||
4261 | r = -EINVAL; | |
4262 | if (!kvm_x86_ops->get_nested_state) | |
4263 | break; | |
4264 | ||
4265 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4266 | r = -EFAULT; |
8fcc4b59 | 4267 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4268 | break; |
8fcc4b59 JM |
4269 | |
4270 | r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, | |
4271 | user_data_size); | |
4272 | if (r < 0) | |
26b471c7 | 4273 | break; |
8fcc4b59 JM |
4274 | |
4275 | if (r > user_data_size) { | |
4276 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4277 | r = -EFAULT; |
4278 | else | |
4279 | r = -E2BIG; | |
4280 | break; | |
8fcc4b59 | 4281 | } |
26b471c7 | 4282 | |
8fcc4b59 JM |
4283 | r = 0; |
4284 | break; | |
4285 | } | |
4286 | case KVM_SET_NESTED_STATE: { | |
4287 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4288 | struct kvm_nested_state kvm_state; | |
4289 | ||
4290 | r = -EINVAL; | |
4291 | if (!kvm_x86_ops->set_nested_state) | |
4292 | break; | |
4293 | ||
26b471c7 | 4294 | r = -EFAULT; |
8fcc4b59 | 4295 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 4296 | break; |
8fcc4b59 | 4297 | |
26b471c7 | 4298 | r = -EINVAL; |
8fcc4b59 | 4299 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 4300 | break; |
8fcc4b59 JM |
4301 | |
4302 | if (kvm_state.flags & | |
8cab6507 VK |
4303 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
4304 | | KVM_STATE_NESTED_EVMCS)) | |
26b471c7 | 4305 | break; |
8fcc4b59 JM |
4306 | |
4307 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
4308 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
4309 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 4310 | break; |
8fcc4b59 JM |
4311 | |
4312 | r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); | |
4313 | break; | |
4314 | } | |
2bc39970 VK |
4315 | case KVM_GET_SUPPORTED_HV_CPUID: { |
4316 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4317 | struct kvm_cpuid2 cpuid; | |
4318 | ||
4319 | r = -EFAULT; | |
4320 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4321 | goto out; | |
4322 | ||
4323 | r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, | |
4324 | cpuid_arg->entries); | |
4325 | if (r) | |
4326 | goto out; | |
4327 | ||
4328 | r = -EFAULT; | |
4329 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4330 | goto out; | |
4331 | r = 0; | |
4332 | break; | |
4333 | } | |
313a3dc7 CO |
4334 | default: |
4335 | r = -EINVAL; | |
4336 | } | |
4337 | out: | |
d1ac91d8 | 4338 | kfree(u.buffer); |
9b062471 CD |
4339 | out_nofree: |
4340 | vcpu_put(vcpu); | |
313a3dc7 CO |
4341 | return r; |
4342 | } | |
4343 | ||
1499fa80 | 4344 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
4345 | { |
4346 | return VM_FAULT_SIGBUS; | |
4347 | } | |
4348 | ||
1fe779f8 CO |
4349 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
4350 | { | |
4351 | int ret; | |
4352 | ||
4353 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 4354 | return -EINVAL; |
1fe779f8 CO |
4355 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); |
4356 | return ret; | |
4357 | } | |
4358 | ||
b927a3ce SY |
4359 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
4360 | u64 ident_addr) | |
4361 | { | |
2ac52ab8 | 4362 | return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
4363 | } |
4364 | ||
1fe779f8 | 4365 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 4366 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
4367 | { |
4368 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
4369 | return -EINVAL; | |
4370 | ||
79fac95e | 4371 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
4372 | |
4373 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 4374 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 4375 | |
79fac95e | 4376 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
4377 | return 0; |
4378 | } | |
4379 | ||
bc8a3d89 | 4380 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 4381 | { |
39de71ec | 4382 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
4383 | } |
4384 | ||
1fe779f8 CO |
4385 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
4386 | { | |
90bca052 | 4387 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4388 | int r; |
4389 | ||
4390 | r = 0; | |
4391 | switch (chip->chip_id) { | |
4392 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 4393 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
4394 | sizeof(struct kvm_pic_state)); |
4395 | break; | |
4396 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 4397 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
4398 | sizeof(struct kvm_pic_state)); |
4399 | break; | |
4400 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4401 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4402 | break; |
4403 | default: | |
4404 | r = -EINVAL; | |
4405 | break; | |
4406 | } | |
4407 | return r; | |
4408 | } | |
4409 | ||
4410 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
4411 | { | |
90bca052 | 4412 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4413 | int r; |
4414 | ||
4415 | r = 0; | |
4416 | switch (chip->chip_id) { | |
4417 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
4418 | spin_lock(&pic->lock); |
4419 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 4420 | sizeof(struct kvm_pic_state)); |
90bca052 | 4421 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4422 | break; |
4423 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
4424 | spin_lock(&pic->lock); |
4425 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 4426 | sizeof(struct kvm_pic_state)); |
90bca052 | 4427 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4428 | break; |
4429 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4430 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4431 | break; |
4432 | default: | |
4433 | r = -EINVAL; | |
4434 | break; | |
4435 | } | |
90bca052 | 4436 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
4437 | return r; |
4438 | } | |
4439 | ||
e0f63cb9 SY |
4440 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
4441 | { | |
34f3941c RK |
4442 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
4443 | ||
4444 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
4445 | ||
4446 | mutex_lock(&kps->lock); | |
4447 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
4448 | mutex_unlock(&kps->lock); | |
2da29bcc | 4449 | return 0; |
e0f63cb9 SY |
4450 | } |
4451 | ||
4452 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
4453 | { | |
0185604c | 4454 | int i; |
09edea72 RK |
4455 | struct kvm_pit *pit = kvm->arch.vpit; |
4456 | ||
4457 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 4458 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 4459 | for (i = 0; i < 3; i++) |
09edea72 RK |
4460 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
4461 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 4462 | return 0; |
e9f42757 BK |
4463 | } |
4464 | ||
4465 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4466 | { | |
e9f42757 BK |
4467 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
4468 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
4469 | sizeof(ps->channels)); | |
4470 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
4471 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 4472 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 4473 | return 0; |
e9f42757 BK |
4474 | } |
4475 | ||
4476 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4477 | { | |
2da29bcc | 4478 | int start = 0; |
0185604c | 4479 | int i; |
e9f42757 | 4480 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
4481 | struct kvm_pit *pit = kvm->arch.vpit; |
4482 | ||
4483 | mutex_lock(&pit->pit_state.lock); | |
4484 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
4485 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
4486 | if (!prev_legacy && cur_legacy) | |
4487 | start = 1; | |
09edea72 RK |
4488 | memcpy(&pit->pit_state.channels, &ps->channels, |
4489 | sizeof(pit->pit_state.channels)); | |
4490 | pit->pit_state.flags = ps->flags; | |
0185604c | 4491 | for (i = 0; i < 3; i++) |
09edea72 | 4492 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 4493 | start && i == 0); |
09edea72 | 4494 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 4495 | return 0; |
e0f63cb9 SY |
4496 | } |
4497 | ||
52d939a0 MT |
4498 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
4499 | struct kvm_reinject_control *control) | |
4500 | { | |
71474e2f RK |
4501 | struct kvm_pit *pit = kvm->arch.vpit; |
4502 | ||
4503 | if (!pit) | |
52d939a0 | 4504 | return -ENXIO; |
b39c90b6 | 4505 | |
71474e2f RK |
4506 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
4507 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
4508 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
4509 | */ | |
4510 | mutex_lock(&pit->pit_state.lock); | |
4511 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
4512 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 4513 | |
52d939a0 MT |
4514 | return 0; |
4515 | } | |
4516 | ||
95d4c16c | 4517 | /** |
60c34612 TY |
4518 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot |
4519 | * @kvm: kvm instance | |
4520 | * @log: slot id and address to which we copy the log | |
95d4c16c | 4521 | * |
e108ff2f PB |
4522 | * Steps 1-4 below provide general overview of dirty page logging. See |
4523 | * kvm_get_dirty_log_protect() function description for additional details. | |
4524 | * | |
4525 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
4526 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
4527 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
4528 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
4529 | * writes will be marked dirty for next log read. | |
95d4c16c | 4530 | * |
60c34612 TY |
4531 | * 1. Take a snapshot of the bit and clear it if needed. |
4532 | * 2. Write protect the corresponding page. | |
e108ff2f PB |
4533 | * 3. Copy the snapshot to the userspace. |
4534 | * 4. Flush TLB's if needed. | |
5bb064dc | 4535 | */ |
60c34612 | 4536 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
5bb064dc | 4537 | { |
8fe65a82 | 4538 | bool flush = false; |
e108ff2f | 4539 | int r; |
5bb064dc | 4540 | |
79fac95e | 4541 | mutex_lock(&kvm->slots_lock); |
5bb064dc | 4542 | |
88178fd4 KH |
4543 | /* |
4544 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4545 | */ | |
4546 | if (kvm_x86_ops->flush_log_dirty) | |
4547 | kvm_x86_ops->flush_log_dirty(kvm); | |
4548 | ||
8fe65a82 | 4549 | r = kvm_get_dirty_log_protect(kvm, log, &flush); |
198c74f4 XG |
4550 | |
4551 | /* | |
4552 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4553 | * kvm_mmu_slot_remove_write_access(). | |
4554 | */ | |
e108ff2f | 4555 | lockdep_assert_held(&kvm->slots_lock); |
8fe65a82 | 4556 | if (flush) |
2a31b9db PB |
4557 | kvm_flush_remote_tlbs(kvm); |
4558 | ||
4559 | mutex_unlock(&kvm->slots_lock); | |
4560 | return r; | |
4561 | } | |
4562 | ||
4563 | int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) | |
4564 | { | |
4565 | bool flush = false; | |
4566 | int r; | |
4567 | ||
4568 | mutex_lock(&kvm->slots_lock); | |
4569 | ||
4570 | /* | |
4571 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4572 | */ | |
4573 | if (kvm_x86_ops->flush_log_dirty) | |
4574 | kvm_x86_ops->flush_log_dirty(kvm); | |
4575 | ||
4576 | r = kvm_clear_dirty_log_protect(kvm, log, &flush); | |
4577 | ||
4578 | /* | |
4579 | * All the TLBs can be flushed out of mmu lock, see the comments in | |
4580 | * kvm_mmu_slot_remove_write_access(). | |
4581 | */ | |
4582 | lockdep_assert_held(&kvm->slots_lock); | |
4583 | if (flush) | |
198c74f4 XG |
4584 | kvm_flush_remote_tlbs(kvm); |
4585 | ||
79fac95e | 4586 | mutex_unlock(&kvm->slots_lock); |
5bb064dc ZX |
4587 | return r; |
4588 | } | |
4589 | ||
aa2fbe6d YZ |
4590 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
4591 | bool line_status) | |
23d43cf9 CD |
4592 | { |
4593 | if (!irqchip_in_kernel(kvm)) | |
4594 | return -ENXIO; | |
4595 | ||
4596 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
4597 | irq_event->irq, irq_event->level, |
4598 | line_status); | |
23d43cf9 CD |
4599 | return 0; |
4600 | } | |
4601 | ||
e5d83c74 PB |
4602 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
4603 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
4604 | { |
4605 | int r; | |
4606 | ||
4607 | if (cap->flags) | |
4608 | return -EINVAL; | |
4609 | ||
4610 | switch (cap->cap) { | |
4611 | case KVM_CAP_DISABLE_QUIRKS: | |
4612 | kvm->arch.disabled_quirks = cap->args[0]; | |
4613 | r = 0; | |
4614 | break; | |
49df6397 SR |
4615 | case KVM_CAP_SPLIT_IRQCHIP: { |
4616 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
4617 | r = -EINVAL; |
4618 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
4619 | goto split_irqchip_unlock; | |
49df6397 SR |
4620 | r = -EEXIST; |
4621 | if (irqchip_in_kernel(kvm)) | |
4622 | goto split_irqchip_unlock; | |
557abc40 | 4623 | if (kvm->created_vcpus) |
49df6397 SR |
4624 | goto split_irqchip_unlock; |
4625 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 4626 | if (r) |
49df6397 SR |
4627 | goto split_irqchip_unlock; |
4628 | /* Pairs with irqchip_in_kernel. */ | |
4629 | smp_wmb(); | |
49776faf | 4630 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 4631 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
4632 | r = 0; |
4633 | split_irqchip_unlock: | |
4634 | mutex_unlock(&kvm->lock); | |
4635 | break; | |
4636 | } | |
37131313 RK |
4637 | case KVM_CAP_X2APIC_API: |
4638 | r = -EINVAL; | |
4639 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
4640 | break; | |
4641 | ||
4642 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
4643 | kvm->arch.x2apic_format = true; | |
c519265f RK |
4644 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
4645 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
4646 | |
4647 | r = 0; | |
4648 | break; | |
4d5422ce WL |
4649 | case KVM_CAP_X86_DISABLE_EXITS: |
4650 | r = -EINVAL; | |
4651 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
4652 | break; | |
4653 | ||
4654 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
4655 | kvm_can_mwait_in_guest()) | |
4656 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 4657 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 4658 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
4659 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
4660 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
4661 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
4662 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
4663 | r = 0; |
4664 | break; | |
6fbbde9a DS |
4665 | case KVM_CAP_MSR_PLATFORM_INFO: |
4666 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
4667 | r = 0; | |
c4f55198 JM |
4668 | break; |
4669 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
4670 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
4671 | r = 0; | |
6fbbde9a | 4672 | break; |
90de4a18 NA |
4673 | default: |
4674 | r = -EINVAL; | |
4675 | break; | |
4676 | } | |
4677 | return r; | |
4678 | } | |
4679 | ||
1fe779f8 CO |
4680 | long kvm_arch_vm_ioctl(struct file *filp, |
4681 | unsigned int ioctl, unsigned long arg) | |
4682 | { | |
4683 | struct kvm *kvm = filp->private_data; | |
4684 | void __user *argp = (void __user *)arg; | |
367e1319 | 4685 | int r = -ENOTTY; |
f0d66275 DH |
4686 | /* |
4687 | * This union makes it completely explicit to gcc-3.x | |
4688 | * that these two variables' stack usage should be | |
4689 | * combined, not added together. | |
4690 | */ | |
4691 | union { | |
4692 | struct kvm_pit_state ps; | |
e9f42757 | 4693 | struct kvm_pit_state2 ps2; |
c5ff41ce | 4694 | struct kvm_pit_config pit_config; |
f0d66275 | 4695 | } u; |
1fe779f8 CO |
4696 | |
4697 | switch (ioctl) { | |
4698 | case KVM_SET_TSS_ADDR: | |
4699 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 4700 | break; |
b927a3ce SY |
4701 | case KVM_SET_IDENTITY_MAP_ADDR: { |
4702 | u64 ident_addr; | |
4703 | ||
1af1ac91 DH |
4704 | mutex_lock(&kvm->lock); |
4705 | r = -EINVAL; | |
4706 | if (kvm->created_vcpus) | |
4707 | goto set_identity_unlock; | |
b927a3ce | 4708 | r = -EFAULT; |
0e96f31e | 4709 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 4710 | goto set_identity_unlock; |
b927a3ce | 4711 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
4712 | set_identity_unlock: |
4713 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
4714 | break; |
4715 | } | |
1fe779f8 CO |
4716 | case KVM_SET_NR_MMU_PAGES: |
4717 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
4718 | break; |
4719 | case KVM_GET_NR_MMU_PAGES: | |
4720 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
4721 | break; | |
3ddea128 | 4722 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 4723 | mutex_lock(&kvm->lock); |
09941366 | 4724 | |
3ddea128 | 4725 | r = -EEXIST; |
35e6eaa3 | 4726 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 4727 | goto create_irqchip_unlock; |
09941366 | 4728 | |
3e515705 | 4729 | r = -EINVAL; |
557abc40 | 4730 | if (kvm->created_vcpus) |
3e515705 | 4731 | goto create_irqchip_unlock; |
09941366 RK |
4732 | |
4733 | r = kvm_pic_init(kvm); | |
4734 | if (r) | |
3ddea128 | 4735 | goto create_irqchip_unlock; |
09941366 RK |
4736 | |
4737 | r = kvm_ioapic_init(kvm); | |
4738 | if (r) { | |
09941366 | 4739 | kvm_pic_destroy(kvm); |
3ddea128 | 4740 | goto create_irqchip_unlock; |
09941366 RK |
4741 | } |
4742 | ||
399ec807 AK |
4743 | r = kvm_setup_default_irq_routing(kvm); |
4744 | if (r) { | |
72bb2fcd | 4745 | kvm_ioapic_destroy(kvm); |
09941366 | 4746 | kvm_pic_destroy(kvm); |
71ba994c | 4747 | goto create_irqchip_unlock; |
399ec807 | 4748 | } |
49776faf | 4749 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 4750 | smp_wmb(); |
49776faf | 4751 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
4752 | create_irqchip_unlock: |
4753 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 4754 | break; |
3ddea128 | 4755 | } |
7837699f | 4756 | case KVM_CREATE_PIT: |
c5ff41ce JK |
4757 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
4758 | goto create_pit; | |
4759 | case KVM_CREATE_PIT2: | |
4760 | r = -EFAULT; | |
4761 | if (copy_from_user(&u.pit_config, argp, | |
4762 | sizeof(struct kvm_pit_config))) | |
4763 | goto out; | |
4764 | create_pit: | |
250715a6 | 4765 | mutex_lock(&kvm->lock); |
269e05e4 AK |
4766 | r = -EEXIST; |
4767 | if (kvm->arch.vpit) | |
4768 | goto create_pit_unlock; | |
7837699f | 4769 | r = -ENOMEM; |
c5ff41ce | 4770 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
4771 | if (kvm->arch.vpit) |
4772 | r = 0; | |
269e05e4 | 4773 | create_pit_unlock: |
250715a6 | 4774 | mutex_unlock(&kvm->lock); |
7837699f | 4775 | break; |
1fe779f8 CO |
4776 | case KVM_GET_IRQCHIP: { |
4777 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4778 | struct kvm_irqchip *chip; |
1fe779f8 | 4779 | |
ff5c2c03 SL |
4780 | chip = memdup_user(argp, sizeof(*chip)); |
4781 | if (IS_ERR(chip)) { | |
4782 | r = PTR_ERR(chip); | |
1fe779f8 | 4783 | goto out; |
ff5c2c03 SL |
4784 | } |
4785 | ||
1fe779f8 | 4786 | r = -ENXIO; |
826da321 | 4787 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4788 | goto get_irqchip_out; |
4789 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 4790 | if (r) |
f0d66275 | 4791 | goto get_irqchip_out; |
1fe779f8 | 4792 | r = -EFAULT; |
0e96f31e | 4793 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 4794 | goto get_irqchip_out; |
1fe779f8 | 4795 | r = 0; |
f0d66275 DH |
4796 | get_irqchip_out: |
4797 | kfree(chip); | |
1fe779f8 CO |
4798 | break; |
4799 | } | |
4800 | case KVM_SET_IRQCHIP: { | |
4801 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 4802 | struct kvm_irqchip *chip; |
1fe779f8 | 4803 | |
ff5c2c03 SL |
4804 | chip = memdup_user(argp, sizeof(*chip)); |
4805 | if (IS_ERR(chip)) { | |
4806 | r = PTR_ERR(chip); | |
1fe779f8 | 4807 | goto out; |
ff5c2c03 SL |
4808 | } |
4809 | ||
1fe779f8 | 4810 | r = -ENXIO; |
826da321 | 4811 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
4812 | goto set_irqchip_out; |
4813 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 4814 | if (r) |
f0d66275 | 4815 | goto set_irqchip_out; |
1fe779f8 | 4816 | r = 0; |
f0d66275 DH |
4817 | set_irqchip_out: |
4818 | kfree(chip); | |
1fe779f8 CO |
4819 | break; |
4820 | } | |
e0f63cb9 | 4821 | case KVM_GET_PIT: { |
e0f63cb9 | 4822 | r = -EFAULT; |
f0d66275 | 4823 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4824 | goto out; |
4825 | r = -ENXIO; | |
4826 | if (!kvm->arch.vpit) | |
4827 | goto out; | |
f0d66275 | 4828 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
4829 | if (r) |
4830 | goto out; | |
4831 | r = -EFAULT; | |
f0d66275 | 4832 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
4833 | goto out; |
4834 | r = 0; | |
4835 | break; | |
4836 | } | |
4837 | case KVM_SET_PIT: { | |
e0f63cb9 | 4838 | r = -EFAULT; |
0e96f31e | 4839 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 SY |
4840 | goto out; |
4841 | r = -ENXIO; | |
4842 | if (!kvm->arch.vpit) | |
4843 | goto out; | |
f0d66275 | 4844 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
4845 | break; |
4846 | } | |
e9f42757 BK |
4847 | case KVM_GET_PIT2: { |
4848 | r = -ENXIO; | |
4849 | if (!kvm->arch.vpit) | |
4850 | goto out; | |
4851 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
4852 | if (r) | |
4853 | goto out; | |
4854 | r = -EFAULT; | |
4855 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
4856 | goto out; | |
4857 | r = 0; | |
4858 | break; | |
4859 | } | |
4860 | case KVM_SET_PIT2: { | |
4861 | r = -EFAULT; | |
4862 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
4863 | goto out; | |
4864 | r = -ENXIO; | |
4865 | if (!kvm->arch.vpit) | |
4866 | goto out; | |
4867 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
e9f42757 BK |
4868 | break; |
4869 | } | |
52d939a0 MT |
4870 | case KVM_REINJECT_CONTROL: { |
4871 | struct kvm_reinject_control control; | |
4872 | r = -EFAULT; | |
4873 | if (copy_from_user(&control, argp, sizeof(control))) | |
4874 | goto out; | |
4875 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
52d939a0 MT |
4876 | break; |
4877 | } | |
d71ba788 PB |
4878 | case KVM_SET_BOOT_CPU_ID: |
4879 | r = 0; | |
4880 | mutex_lock(&kvm->lock); | |
557abc40 | 4881 | if (kvm->created_vcpus) |
d71ba788 PB |
4882 | r = -EBUSY; |
4883 | else | |
4884 | kvm->arch.bsp_vcpu_id = arg; | |
4885 | mutex_unlock(&kvm->lock); | |
4886 | break; | |
ffde22ac | 4887 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 4888 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 4889 | r = -EFAULT; |
51776043 | 4890 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
4891 | goto out; |
4892 | r = -EINVAL; | |
51776043 | 4893 | if (xhc.flags) |
ffde22ac | 4894 | goto out; |
51776043 | 4895 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
4896 | r = 0; |
4897 | break; | |
4898 | } | |
afbcf7ab | 4899 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
4900 | struct kvm_clock_data user_ns; |
4901 | u64 now_ns; | |
afbcf7ab GC |
4902 | |
4903 | r = -EFAULT; | |
4904 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
4905 | goto out; | |
4906 | ||
4907 | r = -EINVAL; | |
4908 | if (user_ns.flags) | |
4909 | goto out; | |
4910 | ||
4911 | r = 0; | |
0bc48bea RK |
4912 | /* |
4913 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
4914 | * kvm_gen_update_masterclock() can be cut down to locked | |
4915 | * pvclock_update_vm_gtod_copy(). | |
4916 | */ | |
4917 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 4918 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 4919 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 4920 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
4921 | break; |
4922 | } | |
4923 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
4924 | struct kvm_clock_data user_ns; |
4925 | u64 now_ns; | |
4926 | ||
e891a32e | 4927 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 4928 | user_ns.clock = now_ns; |
e3fd9a93 | 4929 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 4930 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
4931 | |
4932 | r = -EFAULT; | |
4933 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
4934 | goto out; | |
4935 | r = 0; | |
4936 | break; | |
4937 | } | |
5acc5c06 BS |
4938 | case KVM_MEMORY_ENCRYPT_OP: { |
4939 | r = -ENOTTY; | |
4940 | if (kvm_x86_ops->mem_enc_op) | |
4941 | r = kvm_x86_ops->mem_enc_op(kvm, argp); | |
4942 | break; | |
4943 | } | |
69eaedee BS |
4944 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
4945 | struct kvm_enc_region region; | |
4946 | ||
4947 | r = -EFAULT; | |
4948 | if (copy_from_user(®ion, argp, sizeof(region))) | |
4949 | goto out; | |
4950 | ||
4951 | r = -ENOTTY; | |
4952 | if (kvm_x86_ops->mem_enc_reg_region) | |
4953 | r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); | |
4954 | break; | |
4955 | } | |
4956 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
4957 | struct kvm_enc_region region; | |
4958 | ||
4959 | r = -EFAULT; | |
4960 | if (copy_from_user(®ion, argp, sizeof(region))) | |
4961 | goto out; | |
4962 | ||
4963 | r = -ENOTTY; | |
4964 | if (kvm_x86_ops->mem_enc_unreg_region) | |
4965 | r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); | |
4966 | break; | |
4967 | } | |
faeb7833 RK |
4968 | case KVM_HYPERV_EVENTFD: { |
4969 | struct kvm_hyperv_eventfd hvevfd; | |
4970 | ||
4971 | r = -EFAULT; | |
4972 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
4973 | goto out; | |
4974 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
4975 | break; | |
4976 | } | |
66bb8a06 EH |
4977 | case KVM_SET_PMU_EVENT_FILTER: |
4978 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
4979 | break; | |
1fe779f8 | 4980 | default: |
ad6260da | 4981 | r = -ENOTTY; |
1fe779f8 CO |
4982 | } |
4983 | out: | |
4984 | return r; | |
4985 | } | |
4986 | ||
a16b043c | 4987 | static void kvm_init_msr_list(void) |
043405e1 CO |
4988 | { |
4989 | u32 dummy[2]; | |
4990 | unsigned i, j; | |
4991 | ||
62ef68bb | 4992 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { |
043405e1 CO |
4993 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
4994 | continue; | |
93c4adc7 PB |
4995 | |
4996 | /* | |
4997 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 4998 | * to the guests in some cases. |
93c4adc7 PB |
4999 | */ |
5000 | switch (msrs_to_save[i]) { | |
5001 | case MSR_IA32_BNDCFGS: | |
503234b3 | 5002 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5003 | continue; |
5004 | break; | |
9dbe6cf9 PB |
5005 | case MSR_TSC_AUX: |
5006 | if (!kvm_x86_ops->rdtscp_supported()) | |
5007 | continue; | |
5008 | break; | |
bf8c55d8 CP |
5009 | case MSR_IA32_RTIT_CTL: |
5010 | case MSR_IA32_RTIT_STATUS: | |
5011 | if (!kvm_x86_ops->pt_supported()) | |
5012 | continue; | |
5013 | break; | |
5014 | case MSR_IA32_RTIT_CR3_MATCH: | |
5015 | if (!kvm_x86_ops->pt_supported() || | |
5016 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) | |
5017 | continue; | |
5018 | break; | |
5019 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5020 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
5021 | if (!kvm_x86_ops->pt_supported() || | |
5022 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && | |
5023 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5024 | continue; | |
5025 | break; | |
5026 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { | |
5027 | if (!kvm_x86_ops->pt_supported() || | |
5028 | msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >= | |
5029 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) | |
5030 | continue; | |
5031 | break; | |
5032 | } | |
93c4adc7 PB |
5033 | default: |
5034 | break; | |
5035 | } | |
5036 | ||
043405e1 CO |
5037 | if (j < i) |
5038 | msrs_to_save[j] = msrs_to_save[i]; | |
5039 | j++; | |
5040 | } | |
5041 | num_msrs_to_save = j; | |
62ef68bb PB |
5042 | |
5043 | for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { | |
bc226f07 TL |
5044 | if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i])) |
5045 | continue; | |
62ef68bb PB |
5046 | |
5047 | if (j < i) | |
5048 | emulated_msrs[j] = emulated_msrs[i]; | |
5049 | j++; | |
5050 | } | |
5051 | num_emulated_msrs = j; | |
801e459a TL |
5052 | |
5053 | for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { | |
5054 | struct kvm_msr_entry msr; | |
5055 | ||
5056 | msr.index = msr_based_features[i]; | |
66421c1e | 5057 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5058 | continue; |
5059 | ||
5060 | if (j < i) | |
5061 | msr_based_features[j] = msr_based_features[i]; | |
5062 | j++; | |
5063 | } | |
5064 | num_msr_based_features = j; | |
043405e1 CO |
5065 | } |
5066 | ||
bda9020e MT |
5067 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5068 | const void *v) | |
bbd9b64e | 5069 | { |
70252a10 AK |
5070 | int handled = 0; |
5071 | int n; | |
5072 | ||
5073 | do { | |
5074 | n = min(len, 8); | |
bce87cce | 5075 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5076 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5077 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5078 | break; |
5079 | handled += n; | |
5080 | addr += n; | |
5081 | len -= n; | |
5082 | v += n; | |
5083 | } while (len); | |
bbd9b64e | 5084 | |
70252a10 | 5085 | return handled; |
bbd9b64e CO |
5086 | } |
5087 | ||
bda9020e | 5088 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5089 | { |
70252a10 AK |
5090 | int handled = 0; |
5091 | int n; | |
5092 | ||
5093 | do { | |
5094 | n = min(len, 8); | |
bce87cce | 5095 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5096 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5097 | addr, n, v)) | |
5098 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5099 | break; |
e39d200f | 5100 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5101 | handled += n; |
5102 | addr += n; | |
5103 | len -= n; | |
5104 | v += n; | |
5105 | } while (len); | |
bbd9b64e | 5106 | |
70252a10 | 5107 | return handled; |
bbd9b64e CO |
5108 | } |
5109 | ||
2dafc6c2 GN |
5110 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5111 | struct kvm_segment *var, int seg) | |
5112 | { | |
5113 | kvm_x86_ops->set_segment(vcpu, var, seg); | |
5114 | } | |
5115 | ||
5116 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5117 | struct kvm_segment *var, int seg) | |
5118 | { | |
5119 | kvm_x86_ops->get_segment(vcpu, var, seg); | |
5120 | } | |
5121 | ||
54987b7a PB |
5122 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5123 | struct x86_exception *exception) | |
02f59dc9 JR |
5124 | { |
5125 | gpa_t t_gpa; | |
02f59dc9 JR |
5126 | |
5127 | BUG_ON(!mmu_is_nested(vcpu)); | |
5128 | ||
5129 | /* NPT walks are always user-walks */ | |
5130 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5131 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5132 | |
5133 | return t_gpa; | |
5134 | } | |
5135 | ||
ab9ae313 AK |
5136 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5137 | struct x86_exception *exception) | |
1871c602 GN |
5138 | { |
5139 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
ab9ae313 | 5140 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5141 | } |
5142 | ||
ab9ae313 AK |
5143 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5144 | struct x86_exception *exception) | |
1871c602 GN |
5145 | { |
5146 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5147 | access |= PFERR_FETCH_MASK; | |
ab9ae313 | 5148 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5149 | } |
5150 | ||
ab9ae313 AK |
5151 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5152 | struct x86_exception *exception) | |
1871c602 GN |
5153 | { |
5154 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
5155 | access |= PFERR_WRITE_MASK; | |
ab9ae313 | 5156 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5157 | } |
5158 | ||
5159 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5160 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5161 | struct x86_exception *exception) | |
1871c602 | 5162 | { |
ab9ae313 | 5163 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5164 | } |
5165 | ||
5166 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5167 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5168 | struct x86_exception *exception) |
bbd9b64e CO |
5169 | { |
5170 | void *data = val; | |
10589a46 | 5171 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5172 | |
5173 | while (bytes) { | |
14dfe855 | 5174 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5175 | exception); |
bbd9b64e | 5176 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5177 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5178 | int ret; |
5179 | ||
bcc55cba | 5180 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5181 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5182 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5183 | offset, toread); | |
10589a46 | 5184 | if (ret < 0) { |
c3cd7ffa | 5185 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5186 | goto out; |
5187 | } | |
bbd9b64e | 5188 | |
77c2002e IE |
5189 | bytes -= toread; |
5190 | data += toread; | |
5191 | addr += toread; | |
bbd9b64e | 5192 | } |
10589a46 | 5193 | out: |
10589a46 | 5194 | return r; |
bbd9b64e | 5195 | } |
77c2002e | 5196 | |
1871c602 | 5197 | /* used for instruction fetching */ |
0f65dd70 AK |
5198 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5199 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5200 | struct x86_exception *exception) |
1871c602 | 5201 | { |
0f65dd70 | 5202 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1871c602 | 5203 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5204 | unsigned offset; |
5205 | int ret; | |
0f65dd70 | 5206 | |
44583cba PB |
5207 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5208 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5209 | exception); | |
5210 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5211 | return X86EMUL_PROPAGATE_FAULT; | |
5212 | ||
5213 | offset = addr & (PAGE_SIZE-1); | |
5214 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5215 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5216 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5217 | offset, bytes); | |
44583cba PB |
5218 | if (unlikely(ret < 0)) |
5219 | return X86EMUL_IO_NEEDED; | |
5220 | ||
5221 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5222 | } |
5223 | ||
ce14e868 | 5224 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5225 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5226 | struct x86_exception *exception) |
1871c602 GN |
5227 | { |
5228 | u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; | |
0f65dd70 | 5229 | |
353c0956 PB |
5230 | /* |
5231 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5232 | * is returned, but our callers are not ready for that and they blindly | |
5233 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5234 | * uninitialized kernel stack memory into cr2 and error code. | |
5235 | */ | |
5236 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5237 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5238 | exception); |
1871c602 | 5239 | } |
064aea77 | 5240 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5241 | |
ce14e868 PB |
5242 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5243 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 5244 | struct x86_exception *exception, bool system) |
1871c602 | 5245 | { |
0f65dd70 | 5246 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
5247 | u32 access = 0; |
5248 | ||
5249 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5250 | access |= PFERR_USER_MASK; | |
5251 | ||
5252 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
5253 | } |
5254 | ||
7a036a6f RK |
5255 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
5256 | unsigned long addr, void *val, unsigned int bytes) | |
5257 | { | |
5258 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5259 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
5260 | ||
5261 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
5262 | } | |
5263 | ||
ce14e868 PB |
5264 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5265 | struct kvm_vcpu *vcpu, u32 access, | |
5266 | struct x86_exception *exception) | |
77c2002e IE |
5267 | { |
5268 | void *data = val; | |
5269 | int r = X86EMUL_CONTINUE; | |
5270 | ||
5271 | while (bytes) { | |
14dfe855 | 5272 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 5273 | access, |
ab9ae313 | 5274 | exception); |
77c2002e IE |
5275 | unsigned offset = addr & (PAGE_SIZE-1); |
5276 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
5277 | int ret; | |
5278 | ||
bcc55cba | 5279 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5280 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 5281 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 5282 | if (ret < 0) { |
c3cd7ffa | 5283 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
5284 | goto out; |
5285 | } | |
5286 | ||
5287 | bytes -= towrite; | |
5288 | data += towrite; | |
5289 | addr += towrite; | |
5290 | } | |
5291 | out: | |
5292 | return r; | |
5293 | } | |
ce14e868 PB |
5294 | |
5295 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
5296 | unsigned int bytes, struct x86_exception *exception, |
5297 | bool system) | |
ce14e868 PB |
5298 | { |
5299 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
5300 | u32 access = PFERR_WRITE_MASK; |
5301 | ||
5302 | if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) | |
5303 | access |= PFERR_USER_MASK; | |
ce14e868 PB |
5304 | |
5305 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 5306 | access, exception); |
ce14e868 PB |
5307 | } |
5308 | ||
5309 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
5310 | unsigned int bytes, struct x86_exception *exception) | |
5311 | { | |
c595ceee PB |
5312 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
5313 | vcpu->arch.l1tf_flush_l1d = true; | |
5314 | ||
ce14e868 PB |
5315 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
5316 | PFERR_WRITE_MASK, exception); | |
5317 | } | |
6a4d7550 | 5318 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 5319 | |
082d06ed WL |
5320 | int handle_ud(struct kvm_vcpu *vcpu) |
5321 | { | |
6c86eedc | 5322 | int emul_type = EMULTYPE_TRAP_UD; |
082d06ed | 5323 | enum emulation_result er; |
6c86eedc WL |
5324 | char sig[5]; /* ud2; .ascii "kvm" */ |
5325 | struct x86_exception e; | |
5326 | ||
5327 | if (force_emulation_prefix && | |
3c9fa24c PB |
5328 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
5329 | sig, sizeof(sig), &e) == 0 && | |
6c86eedc WL |
5330 | memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { |
5331 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); | |
5332 | emul_type = 0; | |
5333 | } | |
082d06ed | 5334 | |
0ce97a2b | 5335 | er = kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
5336 | if (er == EMULATE_USER_EXIT) |
5337 | return 0; | |
5338 | if (er != EMULATE_DONE) | |
5339 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5340 | return 1; | |
5341 | } | |
5342 | EXPORT_SYMBOL_GPL(handle_ud); | |
5343 | ||
0f89b207 TL |
5344 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5345 | gpa_t gpa, bool write) | |
5346 | { | |
5347 | /* For APIC access vmexit */ | |
5348 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5349 | return 1; | |
5350 | ||
5351 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
5352 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
5353 | return 1; | |
5354 | } | |
5355 | ||
5356 | return 0; | |
5357 | } | |
5358 | ||
af7cc7d1 XG |
5359 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5360 | gpa_t *gpa, struct x86_exception *exception, | |
5361 | bool write) | |
5362 | { | |
97d64b78 AK |
5363 | u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
5364 | | (write ? PFERR_WRITE_MASK : 0); | |
af7cc7d1 | 5365 | |
be94f6b7 HH |
5366 | /* |
5367 | * currently PKRU is only applied to ept enabled guest so | |
5368 | * there is no pkey in EPT page table for L1 guest or EPT | |
5369 | * shadow page table for L2 guest. | |
5370 | */ | |
97d64b78 | 5371 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 5372 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
be94f6b7 | 5373 | vcpu->arch.access, 0, access)) { |
bebb106a XG |
5374 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
5375 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 5376 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
5377 | return 1; |
5378 | } | |
5379 | ||
af7cc7d1 XG |
5380 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
5381 | ||
5382 | if (*gpa == UNMAPPED_GVA) | |
5383 | return -1; | |
5384 | ||
0f89b207 | 5385 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
5386 | } |
5387 | ||
3200f405 | 5388 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 5389 | const void *val, int bytes) |
bbd9b64e CO |
5390 | { |
5391 | int ret; | |
5392 | ||
54bf36aa | 5393 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 5394 | if (ret < 0) |
bbd9b64e | 5395 | return 0; |
0eb05bf2 | 5396 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
5397 | return 1; |
5398 | } | |
5399 | ||
77d197b2 XG |
5400 | struct read_write_emulator_ops { |
5401 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
5402 | int bytes); | |
5403 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5404 | void *val, int bytes); | |
5405 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5406 | int bytes, void *val); | |
5407 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5408 | void *val, int bytes); | |
5409 | bool write; | |
5410 | }; | |
5411 | ||
5412 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
5413 | { | |
5414 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 5415 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 5416 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
5417 | vcpu->mmio_read_completed = 0; |
5418 | return 1; | |
5419 | } | |
5420 | ||
5421 | return 0; | |
5422 | } | |
5423 | ||
5424 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5425 | void *val, int bytes) | |
5426 | { | |
54bf36aa | 5427 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
5428 | } |
5429 | ||
5430 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5431 | void *val, int bytes) | |
5432 | { | |
5433 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
5434 | } | |
5435 | ||
5436 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
5437 | { | |
e39d200f | 5438 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
5439 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
5440 | } | |
5441 | ||
5442 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5443 | void *val, int bytes) | |
5444 | { | |
e39d200f | 5445 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
5446 | return X86EMUL_IO_NEEDED; |
5447 | } | |
5448 | ||
5449 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5450 | void *val, int bytes) | |
5451 | { | |
f78146b0 AK |
5452 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
5453 | ||
87da7e66 | 5454 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
5455 | return X86EMUL_CONTINUE; |
5456 | } | |
5457 | ||
0fbe9b0b | 5458 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
5459 | .read_write_prepare = read_prepare, |
5460 | .read_write_emulate = read_emulate, | |
5461 | .read_write_mmio = vcpu_mmio_read, | |
5462 | .read_write_exit_mmio = read_exit_mmio, | |
5463 | }; | |
5464 | ||
0fbe9b0b | 5465 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
5466 | .read_write_emulate = write_emulate, |
5467 | .read_write_mmio = write_mmio, | |
5468 | .read_write_exit_mmio = write_exit_mmio, | |
5469 | .write = true, | |
5470 | }; | |
5471 | ||
22388a3c XG |
5472 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
5473 | unsigned int bytes, | |
5474 | struct x86_exception *exception, | |
5475 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 5476 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5477 | { |
af7cc7d1 XG |
5478 | gpa_t gpa; |
5479 | int handled, ret; | |
22388a3c | 5480 | bool write = ops->write; |
f78146b0 | 5481 | struct kvm_mmio_fragment *frag; |
0f89b207 TL |
5482 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
5483 | ||
5484 | /* | |
5485 | * If the exit was due to a NPF we may already have a GPA. | |
5486 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
5487 | * Note, this cannot be used on string operations since string | |
5488 | * operation using rep will only have the initial GPA from the NPF | |
5489 | * occurred. | |
5490 | */ | |
5491 | if (vcpu->arch.gpa_available && | |
5492 | emulator_can_use_gpa(ctxt) && | |
618232e2 BS |
5493 | (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { |
5494 | gpa = vcpu->arch.gpa_val; | |
5495 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); | |
5496 | } else { | |
5497 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
5498 | if (ret < 0) | |
5499 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 5500 | } |
10589a46 | 5501 | |
618232e2 | 5502 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
5503 | return X86EMUL_CONTINUE; |
5504 | ||
bbd9b64e CO |
5505 | /* |
5506 | * Is this MMIO handled locally? | |
5507 | */ | |
22388a3c | 5508 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 5509 | if (handled == bytes) |
bbd9b64e | 5510 | return X86EMUL_CONTINUE; |
bbd9b64e | 5511 | |
70252a10 AK |
5512 | gpa += handled; |
5513 | bytes -= handled; | |
5514 | val += handled; | |
5515 | ||
87da7e66 XG |
5516 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
5517 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
5518 | frag->gpa = gpa; | |
5519 | frag->data = val; | |
5520 | frag->len = bytes; | |
f78146b0 | 5521 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
5522 | } |
5523 | ||
52eb5a6d XL |
5524 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
5525 | unsigned long addr, | |
22388a3c XG |
5526 | void *val, unsigned int bytes, |
5527 | struct x86_exception *exception, | |
0fbe9b0b | 5528 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5529 | { |
0f65dd70 | 5530 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
5531 | gpa_t gpa; |
5532 | int rc; | |
5533 | ||
5534 | if (ops->read_write_prepare && | |
5535 | ops->read_write_prepare(vcpu, val, bytes)) | |
5536 | return X86EMUL_CONTINUE; | |
5537 | ||
5538 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 5539 | |
bbd9b64e CO |
5540 | /* Crossing a page boundary? */ |
5541 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 5542 | int now; |
bbd9b64e CO |
5543 | |
5544 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
5545 | rc = emulator_read_write_onepage(addr, val, now, exception, |
5546 | vcpu, ops); | |
5547 | ||
bbd9b64e CO |
5548 | if (rc != X86EMUL_CONTINUE) |
5549 | return rc; | |
5550 | addr += now; | |
bac15531 NA |
5551 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
5552 | addr = (u32)addr; | |
bbd9b64e CO |
5553 | val += now; |
5554 | bytes -= now; | |
5555 | } | |
22388a3c | 5556 | |
f78146b0 AK |
5557 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
5558 | vcpu, ops); | |
5559 | if (rc != X86EMUL_CONTINUE) | |
5560 | return rc; | |
5561 | ||
5562 | if (!vcpu->mmio_nr_fragments) | |
5563 | return rc; | |
5564 | ||
5565 | gpa = vcpu->mmio_fragments[0].gpa; | |
5566 | ||
5567 | vcpu->mmio_needed = 1; | |
5568 | vcpu->mmio_cur_fragment = 0; | |
5569 | ||
87da7e66 | 5570 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
5571 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
5572 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
5573 | vcpu->run->mmio.phys_addr = gpa; | |
5574 | ||
5575 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
5576 | } |
5577 | ||
5578 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
5579 | unsigned long addr, | |
5580 | void *val, | |
5581 | unsigned int bytes, | |
5582 | struct x86_exception *exception) | |
5583 | { | |
5584 | return emulator_read_write(ctxt, addr, val, bytes, | |
5585 | exception, &read_emultor); | |
5586 | } | |
5587 | ||
52eb5a6d | 5588 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
5589 | unsigned long addr, |
5590 | const void *val, | |
5591 | unsigned int bytes, | |
5592 | struct x86_exception *exception) | |
5593 | { | |
5594 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
5595 | exception, &write_emultor); | |
bbd9b64e | 5596 | } |
bbd9b64e | 5597 | |
daea3e73 AK |
5598 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
5599 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
5600 | ||
5601 | #ifdef CONFIG_X86_64 | |
5602 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
5603 | #else | |
5604 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 5605 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
5606 | #endif |
5607 | ||
0f65dd70 AK |
5608 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
5609 | unsigned long addr, | |
bbd9b64e CO |
5610 | const void *old, |
5611 | const void *new, | |
5612 | unsigned int bytes, | |
0f65dd70 | 5613 | struct x86_exception *exception) |
bbd9b64e | 5614 | { |
42e35f80 | 5615 | struct kvm_host_map map; |
0f65dd70 | 5616 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
daea3e73 | 5617 | gpa_t gpa; |
daea3e73 AK |
5618 | char *kaddr; |
5619 | bool exchanged; | |
2bacc55c | 5620 | |
daea3e73 AK |
5621 | /* guests cmpxchg8b have to be emulated atomically */ |
5622 | if (bytes > 8 || (bytes & (bytes - 1))) | |
5623 | goto emul_write; | |
10589a46 | 5624 | |
daea3e73 | 5625 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 5626 | |
daea3e73 AK |
5627 | if (gpa == UNMAPPED_GVA || |
5628 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5629 | goto emul_write; | |
2bacc55c | 5630 | |
daea3e73 AK |
5631 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) |
5632 | goto emul_write; | |
72dc67a6 | 5633 | |
42e35f80 | 5634 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 5635 | goto emul_write; |
72dc67a6 | 5636 | |
42e35f80 KA |
5637 | kaddr = map.hva + offset_in_page(gpa); |
5638 | ||
daea3e73 AK |
5639 | switch (bytes) { |
5640 | case 1: | |
5641 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
5642 | break; | |
5643 | case 2: | |
5644 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
5645 | break; | |
5646 | case 4: | |
5647 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
5648 | break; | |
5649 | case 8: | |
5650 | exchanged = CMPXCHG64(kaddr, old, new); | |
5651 | break; | |
5652 | default: | |
5653 | BUG(); | |
2bacc55c | 5654 | } |
42e35f80 KA |
5655 | |
5656 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
5657 | |
5658 | if (!exchanged) | |
5659 | return X86EMUL_CMPXCHG_FAILED; | |
5660 | ||
0eb05bf2 | 5661 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
5662 | |
5663 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 5664 | |
3200f405 | 5665 | emul_write: |
daea3e73 | 5666 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 5667 | |
0f65dd70 | 5668 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
5669 | } |
5670 | ||
cf8f70bf GN |
5671 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
5672 | { | |
cbfc6c91 | 5673 | int r = 0, i; |
cf8f70bf | 5674 | |
cbfc6c91 WL |
5675 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
5676 | if (vcpu->arch.pio.in) | |
5677 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
5678 | vcpu->arch.pio.size, pd); | |
5679 | else | |
5680 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
5681 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
5682 | pd); | |
5683 | if (r) | |
5684 | break; | |
5685 | pd += vcpu->arch.pio.size; | |
5686 | } | |
cf8f70bf GN |
5687 | return r; |
5688 | } | |
5689 | ||
6f6fbe98 XG |
5690 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
5691 | unsigned short port, void *val, | |
5692 | unsigned int count, bool in) | |
cf8f70bf | 5693 | { |
cf8f70bf | 5694 | vcpu->arch.pio.port = port; |
6f6fbe98 | 5695 | vcpu->arch.pio.in = in; |
7972995b | 5696 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
5697 | vcpu->arch.pio.size = size; |
5698 | ||
5699 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 5700 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5701 | return 1; |
5702 | } | |
5703 | ||
5704 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 5705 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
5706 | vcpu->run->io.size = size; |
5707 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
5708 | vcpu->run->io.count = count; | |
5709 | vcpu->run->io.port = port; | |
5710 | ||
5711 | return 0; | |
5712 | } | |
5713 | ||
6f6fbe98 XG |
5714 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
5715 | int size, unsigned short port, void *val, | |
5716 | unsigned int count) | |
cf8f70bf | 5717 | { |
ca1d4a9e | 5718 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
6f6fbe98 | 5719 | int ret; |
ca1d4a9e | 5720 | |
6f6fbe98 XG |
5721 | if (vcpu->arch.pio.count) |
5722 | goto data_avail; | |
cf8f70bf | 5723 | |
cbfc6c91 WL |
5724 | memset(vcpu->arch.pio_data, 0, size * count); |
5725 | ||
6f6fbe98 XG |
5726 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
5727 | if (ret) { | |
5728 | data_avail: | |
5729 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 5730 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 5731 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
5732 | return 1; |
5733 | } | |
5734 | ||
cf8f70bf GN |
5735 | return 0; |
5736 | } | |
5737 | ||
6f6fbe98 XG |
5738 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
5739 | int size, unsigned short port, | |
5740 | const void *val, unsigned int count) | |
5741 | { | |
5742 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5743 | ||
5744 | memcpy(vcpu->arch.pio_data, val, size * count); | |
1171903d | 5745 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
5746 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
5747 | } | |
5748 | ||
bbd9b64e CO |
5749 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
5750 | { | |
5751 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
5752 | } | |
5753 | ||
3cb16fe7 | 5754 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 5755 | { |
3cb16fe7 | 5756 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
5757 | } |
5758 | ||
ae6a2375 | 5759 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
5760 | { |
5761 | if (!need_emulate_wbinvd(vcpu)) | |
5762 | return X86EMUL_CONTINUE; | |
5763 | ||
5764 | if (kvm_x86_ops->has_wbinvd_exit()) { | |
2eec7343 JK |
5765 | int cpu = get_cpu(); |
5766 | ||
5767 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
5768 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
5769 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 5770 | put_cpu(); |
f5f48ee1 | 5771 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
5772 | } else |
5773 | wbinvd(); | |
f5f48ee1 SY |
5774 | return X86EMUL_CONTINUE; |
5775 | } | |
5cb56059 JS |
5776 | |
5777 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
5778 | { | |
6affcbed KH |
5779 | kvm_emulate_wbinvd_noskip(vcpu); |
5780 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 5781 | } |
f5f48ee1 SY |
5782 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
5783 | ||
5cb56059 JS |
5784 | |
5785 | ||
bcaf5cc5 AK |
5786 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
5787 | { | |
5cb56059 | 5788 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
5789 | } |
5790 | ||
52eb5a6d XL |
5791 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5792 | unsigned long *dest) | |
bbd9b64e | 5793 | { |
16f8a6f9 | 5794 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
5795 | } |
5796 | ||
52eb5a6d XL |
5797 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
5798 | unsigned long value) | |
bbd9b64e | 5799 | { |
338dbc97 | 5800 | |
717746e3 | 5801 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
5802 | } |
5803 | ||
52a46617 | 5804 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 5805 | { |
52a46617 | 5806 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
5807 | } |
5808 | ||
717746e3 | 5809 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 5810 | { |
717746e3 | 5811 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
5812 | unsigned long value; |
5813 | ||
5814 | switch (cr) { | |
5815 | case 0: | |
5816 | value = kvm_read_cr0(vcpu); | |
5817 | break; | |
5818 | case 2: | |
5819 | value = vcpu->arch.cr2; | |
5820 | break; | |
5821 | case 3: | |
9f8fe504 | 5822 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
5823 | break; |
5824 | case 4: | |
5825 | value = kvm_read_cr4(vcpu); | |
5826 | break; | |
5827 | case 8: | |
5828 | value = kvm_get_cr8(vcpu); | |
5829 | break; | |
5830 | default: | |
a737f256 | 5831 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
5832 | return 0; |
5833 | } | |
5834 | ||
5835 | return value; | |
5836 | } | |
5837 | ||
717746e3 | 5838 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 5839 | { |
717746e3 | 5840 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
5841 | int res = 0; |
5842 | ||
52a46617 GN |
5843 | switch (cr) { |
5844 | case 0: | |
49a9b07e | 5845 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
5846 | break; |
5847 | case 2: | |
5848 | vcpu->arch.cr2 = val; | |
5849 | break; | |
5850 | case 3: | |
2390218b | 5851 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
5852 | break; |
5853 | case 4: | |
a83b29c6 | 5854 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
5855 | break; |
5856 | case 8: | |
eea1cff9 | 5857 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
5858 | break; |
5859 | default: | |
a737f256 | 5860 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 5861 | res = -1; |
52a46617 | 5862 | } |
0f12244f GN |
5863 | |
5864 | return res; | |
52a46617 GN |
5865 | } |
5866 | ||
717746e3 | 5867 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 5868 | { |
717746e3 | 5869 | return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
5870 | } |
5871 | ||
4bff1e86 | 5872 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 5873 | { |
4bff1e86 | 5874 | kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
5875 | } |
5876 | ||
4bff1e86 | 5877 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 5878 | { |
4bff1e86 | 5879 | kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
5880 | } |
5881 | ||
1ac9d0cf AK |
5882 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
5883 | { | |
5884 | kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); | |
5885 | } | |
5886 | ||
5887 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
5888 | { | |
5889 | kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); | |
5890 | } | |
5891 | ||
4bff1e86 AK |
5892 | static unsigned long emulator_get_cached_segment_base( |
5893 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 5894 | { |
4bff1e86 | 5895 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
5896 | } |
5897 | ||
1aa36616 AK |
5898 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
5899 | struct desc_struct *desc, u32 *base3, | |
5900 | int seg) | |
2dafc6c2 GN |
5901 | { |
5902 | struct kvm_segment var; | |
5903 | ||
4bff1e86 | 5904 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 5905 | *selector = var.selector; |
2dafc6c2 | 5906 | |
378a8b09 GN |
5907 | if (var.unusable) { |
5908 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
5909 | if (base3) |
5910 | *base3 = 0; | |
2dafc6c2 | 5911 | return false; |
378a8b09 | 5912 | } |
2dafc6c2 GN |
5913 | |
5914 | if (var.g) | |
5915 | var.limit >>= 12; | |
5916 | set_desc_limit(desc, var.limit); | |
5917 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
5918 | #ifdef CONFIG_X86_64 |
5919 | if (base3) | |
5920 | *base3 = var.base >> 32; | |
5921 | #endif | |
2dafc6c2 GN |
5922 | desc->type = var.type; |
5923 | desc->s = var.s; | |
5924 | desc->dpl = var.dpl; | |
5925 | desc->p = var.present; | |
5926 | desc->avl = var.avl; | |
5927 | desc->l = var.l; | |
5928 | desc->d = var.db; | |
5929 | desc->g = var.g; | |
5930 | ||
5931 | return true; | |
5932 | } | |
5933 | ||
1aa36616 AK |
5934 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
5935 | struct desc_struct *desc, u32 base3, | |
5936 | int seg) | |
2dafc6c2 | 5937 | { |
4bff1e86 | 5938 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
5939 | struct kvm_segment var; |
5940 | ||
1aa36616 | 5941 | var.selector = selector; |
2dafc6c2 | 5942 | var.base = get_desc_base(desc); |
5601d05b GN |
5943 | #ifdef CONFIG_X86_64 |
5944 | var.base |= ((u64)base3) << 32; | |
5945 | #endif | |
2dafc6c2 GN |
5946 | var.limit = get_desc_limit(desc); |
5947 | if (desc->g) | |
5948 | var.limit = (var.limit << 12) | 0xfff; | |
5949 | var.type = desc->type; | |
2dafc6c2 GN |
5950 | var.dpl = desc->dpl; |
5951 | var.db = desc->d; | |
5952 | var.s = desc->s; | |
5953 | var.l = desc->l; | |
5954 | var.g = desc->g; | |
5955 | var.avl = desc->avl; | |
5956 | var.present = desc->p; | |
5957 | var.unusable = !var.present; | |
5958 | var.padding = 0; | |
5959 | ||
5960 | kvm_set_segment(vcpu, &var, seg); | |
5961 | return; | |
5962 | } | |
5963 | ||
717746e3 AK |
5964 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
5965 | u32 msr_index, u64 *pdata) | |
5966 | { | |
609e36d3 PB |
5967 | struct msr_data msr; |
5968 | int r; | |
5969 | ||
5970 | msr.index = msr_index; | |
5971 | msr.host_initiated = false; | |
5972 | r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); | |
5973 | if (r) | |
5974 | return r; | |
5975 | ||
5976 | *pdata = msr.data; | |
5977 | return 0; | |
717746e3 AK |
5978 | } |
5979 | ||
5980 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
5981 | u32 msr_index, u64 data) | |
5982 | { | |
8fe8ab46 WA |
5983 | struct msr_data msr; |
5984 | ||
5985 | msr.data = data; | |
5986 | msr.index = msr_index; | |
5987 | msr.host_initiated = false; | |
5988 | return kvm_set_msr(emul_to_vcpu(ctxt), &msr); | |
717746e3 AK |
5989 | } |
5990 | ||
64d60670 PB |
5991 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
5992 | { | |
5993 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5994 | ||
5995 | return vcpu->arch.smbase; | |
5996 | } | |
5997 | ||
5998 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
5999 | { | |
6000 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6001 | ||
6002 | vcpu->arch.smbase = smbase; | |
6003 | } | |
6004 | ||
67f4d428 NA |
6005 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6006 | u32 pmc) | |
6007 | { | |
c6702c9d | 6008 | return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6009 | } |
6010 | ||
222d21aa AK |
6011 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6012 | u32 pmc, u64 *pdata) | |
6013 | { | |
c6702c9d | 6014 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6015 | } |
6016 | ||
6c3287f7 AK |
6017 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6018 | { | |
6019 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6020 | } | |
6021 | ||
2953538e | 6022 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6023 | struct x86_instruction_info *info, |
c4f035c6 AK |
6024 | enum x86_intercept_stage stage) |
6025 | { | |
2953538e | 6026 | return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); |
c4f035c6 AK |
6027 | } |
6028 | ||
e911eb3b YZ |
6029 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
6030 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) | |
bdb42f5a | 6031 | { |
e911eb3b | 6032 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); |
bdb42f5a SB |
6033 | } |
6034 | ||
dd856efa AK |
6035 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6036 | { | |
6037 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6038 | } | |
6039 | ||
6040 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6041 | { | |
6042 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6043 | } | |
6044 | ||
801806d9 NA |
6045 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6046 | { | |
6047 | kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); | |
6048 | } | |
6049 | ||
6ed071f0 LP |
6050 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6051 | { | |
6052 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6053 | } | |
6054 | ||
6055 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6056 | { | |
c5833c7a | 6057 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6058 | } |
6059 | ||
ed19321f SC |
6060 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6061 | const char *smstate) | |
0234bf88 | 6062 | { |
ed19321f | 6063 | return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6064 | } |
6065 | ||
c5833c7a SC |
6066 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6067 | { | |
6068 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6069 | } | |
6070 | ||
0225fb50 | 6071 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6072 | .read_gpr = emulator_read_gpr, |
6073 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6074 | .read_std = emulator_read_std, |
6075 | .write_std = emulator_write_std, | |
7a036a6f | 6076 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6077 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6078 | .read_emulated = emulator_read_emulated, |
6079 | .write_emulated = emulator_write_emulated, | |
6080 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6081 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6082 | .pio_in_emulated = emulator_pio_in_emulated, |
6083 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6084 | .get_segment = emulator_get_segment, |
6085 | .set_segment = emulator_set_segment, | |
5951c442 | 6086 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6087 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6088 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6089 | .set_gdt = emulator_set_gdt, |
6090 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6091 | .get_cr = emulator_get_cr, |
6092 | .set_cr = emulator_set_cr, | |
9c537244 | 6093 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6094 | .get_dr = emulator_get_dr, |
6095 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6096 | .get_smbase = emulator_get_smbase, |
6097 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6098 | .set_msr = emulator_set_msr, |
6099 | .get_msr = emulator_get_msr, | |
67f4d428 | 6100 | .check_pmc = emulator_check_pmc, |
222d21aa | 6101 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6102 | .halt = emulator_halt, |
bcaf5cc5 | 6103 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6104 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6105 | .intercept = emulator_intercept, |
bdb42f5a | 6106 | .get_cpuid = emulator_get_cpuid, |
801806d9 | 6107 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6108 | .get_hflags = emulator_get_hflags, |
6109 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6110 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6111 | .post_leave_smm = emulator_post_leave_smm, |
bbd9b64e CO |
6112 | }; |
6113 | ||
95cb2295 GN |
6114 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6115 | { | |
37ccdcbe | 6116 | u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); |
95cb2295 GN |
6117 | /* |
6118 | * an sti; sti; sequence only disable interrupts for the first | |
6119 | * instruction. So, if the last instruction, be it emulated or | |
6120 | * not, left the system with the INT_STI flag enabled, it | |
6121 | * means that the last instruction is an sti. We should not | |
6122 | * leave the flag on in this case. The same goes for mov ss | |
6123 | */ | |
37ccdcbe PB |
6124 | if (int_shadow & mask) |
6125 | mask = 0; | |
6addfc42 | 6126 | if (unlikely(int_shadow || mask)) { |
95cb2295 | 6127 | kvm_x86_ops->set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6128 | if (!mask) |
6129 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6130 | } | |
95cb2295 GN |
6131 | } |
6132 | ||
ef54bcfe | 6133 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f GN |
6134 | { |
6135 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; | |
da9cb575 | 6136 | if (ctxt->exception.vector == PF_VECTOR) |
ef54bcfe PB |
6137 | return kvm_propagate_fault(vcpu, &ctxt->exception); |
6138 | ||
6139 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6140 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6141 | ctxt->exception.error_code); | |
54b8486f | 6142 | else |
da9cb575 | 6143 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6144 | return false; |
54b8486f GN |
6145 | } |
6146 | ||
8ec4722d MG |
6147 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6148 | { | |
adf52235 | 6149 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6150 | int cs_db, cs_l; |
6151 | ||
8ec4722d MG |
6152 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
6153 | ||
adf52235 | 6154 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6155 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6156 | ||
adf52235 TY |
6157 | ctxt->eip = kvm_rip_read(vcpu); |
6158 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6159 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6160 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6161 | cs_db ? X86EMUL_MODE_PROT32 : |
6162 | X86EMUL_MODE_PROT16; | |
a584539b | 6163 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6164 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6165 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6166 | |
dd856efa | 6167 | init_decode_cache(ctxt); |
7ae441ea | 6168 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6169 | } |
6170 | ||
71f9833b | 6171 | int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6172 | { |
9d74191a | 6173 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
63995653 MG |
6174 | int ret; |
6175 | ||
6176 | init_emulate_ctxt(vcpu); | |
6177 | ||
9dac77fa AK |
6178 | ctxt->op_bytes = 2; |
6179 | ctxt->ad_bytes = 2; | |
6180 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 6181 | ret = emulate_int_real(ctxt, irq); |
63995653 MG |
6182 | |
6183 | if (ret != X86EMUL_CONTINUE) | |
6184 | return EMULATE_FAIL; | |
6185 | ||
9dac77fa | 6186 | ctxt->eip = ctxt->_eip; |
9d74191a TY |
6187 | kvm_rip_write(vcpu, ctxt->eip); |
6188 | kvm_set_rflags(vcpu, ctxt->eflags); | |
63995653 | 6189 | |
63995653 MG |
6190 | return EMULATE_DONE; |
6191 | } | |
6192 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
6193 | ||
e2366171 | 6194 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 6195 | { |
fc3a9157 JR |
6196 | int r = EMULATE_DONE; |
6197 | ||
6d77dbfc GN |
6198 | ++vcpu->stat.insn_emulation_fail; |
6199 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 LA |
6200 | |
6201 | if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) | |
6202 | return EMULATE_FAIL; | |
6203 | ||
a2b9e6c1 | 6204 | if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { |
fc3a9157 JR |
6205 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6206 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6207 | vcpu->run->internal.ndata = 0; | |
1f4dcb3b | 6208 | r = EMULATE_USER_EXIT; |
fc3a9157 | 6209 | } |
e2366171 | 6210 | |
6d77dbfc | 6211 | kvm_queue_exception(vcpu, UD_VECTOR); |
fc3a9157 JR |
6212 | |
6213 | return r; | |
6d77dbfc GN |
6214 | } |
6215 | ||
93c05d3e | 6216 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, |
991eebf9 GN |
6217 | bool write_fault_to_shadow_pgtable, |
6218 | int emulation_type) | |
a6f177ef | 6219 | { |
95b3cf69 | 6220 | gpa_t gpa = cr2; |
ba049e93 | 6221 | kvm_pfn_t pfn; |
a6f177ef | 6222 | |
384bf221 | 6223 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
991eebf9 GN |
6224 | return false; |
6225 | ||
6c3dfeb6 SC |
6226 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6227 | return false; | |
6228 | ||
44dd3ffa | 6229 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6230 | /* |
6231 | * Write permission should be allowed since only | |
6232 | * write access need to be emulated. | |
6233 | */ | |
6234 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); | |
a6f177ef | 6235 | |
95b3cf69 XG |
6236 | /* |
6237 | * If the mapping is invalid in guest, let cpu retry | |
6238 | * it to generate fault. | |
6239 | */ | |
6240 | if (gpa == UNMAPPED_GVA) | |
6241 | return true; | |
6242 | } | |
a6f177ef | 6243 | |
8e3d9d06 XG |
6244 | /* |
6245 | * Do not retry the unhandleable instruction if it faults on the | |
6246 | * readonly host memory, otherwise it will goto a infinite loop: | |
6247 | * retry instruction -> write #PF -> emulation fail -> retry | |
6248 | * instruction -> ... | |
6249 | */ | |
6250 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
6251 | |
6252 | /* | |
6253 | * If the instruction failed on the error pfn, it can not be fixed, | |
6254 | * report the error to userspace. | |
6255 | */ | |
6256 | if (is_error_noslot_pfn(pfn)) | |
6257 | return false; | |
6258 | ||
6259 | kvm_release_pfn_clean(pfn); | |
6260 | ||
6261 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 6262 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6263 | unsigned int indirect_shadow_pages; |
6264 | ||
6265 | spin_lock(&vcpu->kvm->mmu_lock); | |
6266 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
6267 | spin_unlock(&vcpu->kvm->mmu_lock); | |
6268 | ||
6269 | if (indirect_shadow_pages) | |
6270 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
6271 | ||
a6f177ef | 6272 | return true; |
8e3d9d06 | 6273 | } |
a6f177ef | 6274 | |
95b3cf69 XG |
6275 | /* |
6276 | * if emulation was due to access to shadowed page table | |
6277 | * and it failed try to unshadow page and re-enter the | |
6278 | * guest to let CPU execute the instruction. | |
6279 | */ | |
6280 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
6281 | |
6282 | /* | |
6283 | * If the access faults on its page table, it can not | |
6284 | * be fixed by unprotecting shadow page and it should | |
6285 | * be reported to userspace. | |
6286 | */ | |
6287 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
6288 | } |
6289 | ||
1cb3f3ae XG |
6290 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
6291 | unsigned long cr2, int emulation_type) | |
6292 | { | |
6293 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6294 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2; | |
6295 | ||
6296 | last_retry_eip = vcpu->arch.last_retry_eip; | |
6297 | last_retry_addr = vcpu->arch.last_retry_addr; | |
6298 | ||
6299 | /* | |
6300 | * If the emulation is caused by #PF and it is non-page_table | |
6301 | * writing instruction, it means the VM-EXIT is caused by shadow | |
6302 | * page protected, we can zap the shadow page and retry this | |
6303 | * instruction directly. | |
6304 | * | |
6305 | * Note: if the guest uses a non-page-table modifying instruction | |
6306 | * on the PDE that points to the instruction, then we will unmap | |
6307 | * the instruction and go to an infinite loop. So, we cache the | |
6308 | * last retried eip and the last fault address, if we meet the eip | |
6309 | * and the address again, we can break out of the potential infinite | |
6310 | * loop. | |
6311 | */ | |
6312 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
6313 | ||
384bf221 | 6314 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) |
1cb3f3ae XG |
6315 | return false; |
6316 | ||
6c3dfeb6 SC |
6317 | if (WARN_ON_ONCE(is_guest_mode(vcpu))) |
6318 | return false; | |
6319 | ||
1cb3f3ae XG |
6320 | if (x86_page_table_writing_insn(ctxt)) |
6321 | return false; | |
6322 | ||
6323 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) | |
6324 | return false; | |
6325 | ||
6326 | vcpu->arch.last_retry_eip = ctxt->eip; | |
6327 | vcpu->arch.last_retry_addr = cr2; | |
6328 | ||
44dd3ffa | 6329 | if (!vcpu->arch.mmu->direct_map) |
1cb3f3ae XG |
6330 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); |
6331 | ||
22368028 | 6332 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
6333 | |
6334 | return true; | |
6335 | } | |
6336 | ||
716d51ab GN |
6337 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
6338 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
6339 | ||
64d60670 | 6340 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 6341 | { |
64d60670 | 6342 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
6343 | /* This is a good place to trace that we are exiting SMM. */ |
6344 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
6345 | ||
c43203ca PB |
6346 | /* Process a latched INIT or SMI, if any. */ |
6347 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 6348 | } |
699023e2 PB |
6349 | |
6350 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6351 | } |
6352 | ||
4a1e10d5 PB |
6353 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
6354 | unsigned long *db) | |
6355 | { | |
6356 | u32 dr6 = 0; | |
6357 | int i; | |
6358 | u32 enable, rwlen; | |
6359 | ||
6360 | enable = dr7; | |
6361 | rwlen = dr7 >> 16; | |
6362 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
6363 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
6364 | dr6 |= (1 << i); | |
6365 | return dr6; | |
6366 | } | |
6367 | ||
c8401dda | 6368 | static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) |
663f4c61 PB |
6369 | { |
6370 | struct kvm_run *kvm_run = vcpu->run; | |
6371 | ||
c8401dda PB |
6372 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
6373 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
6374 | kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; | |
6375 | kvm_run->debug.arch.exception = DB_VECTOR; | |
6376 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
6377 | *r = EMULATE_USER_EXIT; | |
6378 | } else { | |
f10c729f | 6379 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
663f4c61 PB |
6380 | } |
6381 | } | |
6382 | ||
6affcbed KH |
6383 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6384 | { | |
6385 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); | |
6386 | int r = EMULATE_DONE; | |
6387 | ||
6388 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
c8401dda PB |
6389 | |
6390 | /* | |
6391 | * rflags is the old, "raw" value of the flags. The new value has | |
6392 | * not been saved yet. | |
6393 | * | |
6394 | * This is correct even for TF set by the guest, because "the | |
6395 | * processor will not generate this exception after the instruction | |
6396 | * that sets the TF flag". | |
6397 | */ | |
6398 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
6399 | kvm_vcpu_do_singlestep(vcpu, &r); | |
6affcbed KH |
6400 | return r == EMULATE_DONE; |
6401 | } | |
6402 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
6403 | ||
4a1e10d5 PB |
6404 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
6405 | { | |
4a1e10d5 PB |
6406 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
6407 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
6408 | struct kvm_run *kvm_run = vcpu->run; |
6409 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
6410 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6411 | vcpu->arch.guest_debug_dr7, |
6412 | vcpu->arch.eff_db); | |
6413 | ||
6414 | if (dr6 != 0) { | |
6f43ed01 | 6415 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 6416 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
6417 | kvm_run->debug.arch.exception = DB_VECTOR; |
6418 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
6419 | *r = EMULATE_USER_EXIT; | |
6420 | return true; | |
6421 | } | |
6422 | } | |
6423 | ||
4161a569 NA |
6424 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
6425 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
6426 | unsigned long eip = kvm_get_linear_rip(vcpu); |
6427 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6428 | vcpu->arch.dr7, |
6429 | vcpu->arch.db); | |
6430 | ||
6431 | if (dr6 != 0) { | |
1fc5d194 | 6432 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; |
6f43ed01 | 6433 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
4a1e10d5 PB |
6434 | kvm_queue_exception(vcpu, DB_VECTOR); |
6435 | *r = EMULATE_DONE; | |
6436 | return true; | |
6437 | } | |
6438 | } | |
6439 | ||
6440 | return false; | |
6441 | } | |
6442 | ||
04789b66 LA |
6443 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
6444 | { | |
2d7921c4 AM |
6445 | switch (ctxt->opcode_len) { |
6446 | case 1: | |
6447 | switch (ctxt->b) { | |
6448 | case 0xe4: /* IN */ | |
6449 | case 0xe5: | |
6450 | case 0xec: | |
6451 | case 0xed: | |
6452 | case 0xe6: /* OUT */ | |
6453 | case 0xe7: | |
6454 | case 0xee: | |
6455 | case 0xef: | |
6456 | case 0x6c: /* INS */ | |
6457 | case 0x6d: | |
6458 | case 0x6e: /* OUTS */ | |
6459 | case 0x6f: | |
6460 | return true; | |
6461 | } | |
6462 | break; | |
6463 | case 2: | |
6464 | switch (ctxt->b) { | |
6465 | case 0x33: /* RDPMC */ | |
6466 | return true; | |
6467 | } | |
6468 | break; | |
04789b66 LA |
6469 | } |
6470 | ||
6471 | return false; | |
6472 | } | |
6473 | ||
51d8b661 AP |
6474 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, |
6475 | unsigned long cr2, | |
dc25e89e AP |
6476 | int emulation_type, |
6477 | void *insn, | |
6478 | int insn_len) | |
bbd9b64e | 6479 | { |
95cb2295 | 6480 | int r; |
9d74191a | 6481 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
7ae441ea | 6482 | bool writeback = true; |
93c05d3e | 6483 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 6484 | |
c595ceee PB |
6485 | vcpu->arch.l1tf_flush_l1d = true; |
6486 | ||
93c05d3e XG |
6487 | /* |
6488 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
6489 | * never reused. | |
6490 | */ | |
6491 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 6492 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 6493 | |
571008da | 6494 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 6495 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
6496 | |
6497 | /* | |
6498 | * We will reenter on the same instruction since | |
6499 | * we do not set complete_userspace_io. This does not | |
6500 | * handle watchpoints yet, those would be handled in | |
6501 | * the emulate_ops. | |
6502 | */ | |
d391f120 VK |
6503 | if (!(emulation_type & EMULTYPE_SKIP) && |
6504 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
6505 | return r; |
6506 | ||
9d74191a TY |
6507 | ctxt->interruptibility = 0; |
6508 | ctxt->have_exception = false; | |
e0ad0b47 | 6509 | ctxt->exception.vector = -1; |
9d74191a | 6510 | ctxt->perm_ok = false; |
bbd9b64e | 6511 | |
b51e974f | 6512 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 6513 | |
9d74191a | 6514 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 6515 | |
e46479f8 | 6516 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 6517 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 6518 | if (r != EMULATION_OK) { |
4005996e AK |
6519 | if (emulation_type & EMULTYPE_TRAP_UD) |
6520 | return EMULATE_FAIL; | |
991eebf9 GN |
6521 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6522 | emulation_type)) | |
bbd9b64e | 6523 | return EMULATE_DONE; |
6ea6e843 PB |
6524 | if (ctxt->have_exception && inject_emulated_exception(vcpu)) |
6525 | return EMULATE_DONE; | |
6d77dbfc GN |
6526 | if (emulation_type & EMULTYPE_SKIP) |
6527 | return EMULATE_FAIL; | |
e2366171 | 6528 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6529 | } |
6530 | } | |
6531 | ||
04789b66 LA |
6532 | if ((emulation_type & EMULTYPE_VMWARE) && |
6533 | !is_vmware_backdoor_opcode(ctxt)) | |
6534 | return EMULATE_FAIL; | |
6535 | ||
ba8afb6b | 6536 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 6537 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
6538 | if (ctxt->eflags & X86_EFLAGS_RF) |
6539 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
ba8afb6b GN |
6540 | return EMULATE_DONE; |
6541 | } | |
6542 | ||
1cb3f3ae XG |
6543 | if (retry_instruction(ctxt, cr2, emulation_type)) |
6544 | return EMULATE_DONE; | |
6545 | ||
7ae441ea | 6546 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 6547 | changes registers values during IO operation */ |
7ae441ea GN |
6548 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
6549 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 6550 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 6551 | } |
4d2179e1 | 6552 | |
5cd21917 | 6553 | restart: |
0f89b207 TL |
6554 | /* Save the faulting GPA (cr2) in the address field */ |
6555 | ctxt->exception.address = cr2; | |
6556 | ||
9d74191a | 6557 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 6558 | |
775fde86 JR |
6559 | if (r == EMULATION_INTERCEPTED) |
6560 | return EMULATE_DONE; | |
6561 | ||
d2ddd1c4 | 6562 | if (r == EMULATION_FAILED) { |
991eebf9 GN |
6563 | if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, |
6564 | emulation_type)) | |
c3cd7ffa GN |
6565 | return EMULATE_DONE; |
6566 | ||
e2366171 | 6567 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6568 | } |
6569 | ||
9d74191a | 6570 | if (ctxt->have_exception) { |
d2ddd1c4 | 6571 | r = EMULATE_DONE; |
ef54bcfe PB |
6572 | if (inject_emulated_exception(vcpu)) |
6573 | return r; | |
d2ddd1c4 | 6574 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
6575 | if (!vcpu->arch.pio.in) { |
6576 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 6577 | vcpu->arch.pio.count = 0; |
0912c977 | 6578 | } else { |
7ae441ea | 6579 | writeback = false; |
716d51ab GN |
6580 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
6581 | } | |
ac0a48c3 | 6582 | r = EMULATE_USER_EXIT; |
7ae441ea GN |
6583 | } else if (vcpu->mmio_needed) { |
6584 | if (!vcpu->mmio_is_write) | |
6585 | writeback = false; | |
ac0a48c3 | 6586 | r = EMULATE_USER_EXIT; |
716d51ab | 6587 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 6588 | } else if (r == EMULATION_RESTART) |
5cd21917 | 6589 | goto restart; |
d2ddd1c4 GN |
6590 | else |
6591 | r = EMULATE_DONE; | |
f850e2e6 | 6592 | |
7ae441ea | 6593 | if (writeback) { |
6addfc42 | 6594 | unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); |
9d74191a | 6595 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 6596 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 6597 | if (!ctxt->have_exception || |
75ee23b3 SC |
6598 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
6599 | kvm_rip_write(vcpu, ctxt->eip); | |
6600 | if (r == EMULATE_DONE && ctxt->tf) | |
6601 | kvm_vcpu_do_singlestep(vcpu, &r); | |
38827dbd | 6602 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 6603 | } |
6addfc42 PB |
6604 | |
6605 | /* | |
6606 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
6607 | * do nothing, and it will be requested again as soon as | |
6608 | * the shadow expires. But we still need to check here, | |
6609 | * because POPF has no interrupt shadow. | |
6610 | */ | |
6611 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
6612 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
6613 | } else |
6614 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
6615 | |
6616 | return r; | |
de7d789a | 6617 | } |
c60658d1 SC |
6618 | |
6619 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
6620 | { | |
6621 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
6622 | } | |
6623 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
6624 | ||
6625 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
6626 | void *insn, int insn_len) | |
6627 | { | |
6628 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
6629 | } | |
6630 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 6631 | |
8764ed55 SC |
6632 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
6633 | { | |
6634 | vcpu->arch.pio.count = 0; | |
6635 | return 1; | |
6636 | } | |
6637 | ||
45def77e SC |
6638 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
6639 | { | |
6640 | vcpu->arch.pio.count = 0; | |
6641 | ||
6642 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
6643 | return 1; | |
6644 | ||
6645 | return kvm_skip_emulated_instruction(vcpu); | |
6646 | } | |
6647 | ||
dca7f128 SC |
6648 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
6649 | unsigned short port) | |
de7d789a | 6650 | { |
de3cd117 | 6651 | unsigned long val = kvm_rax_read(vcpu); |
ca1d4a9e AK |
6652 | int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, |
6653 | size, port, &val, 1); | |
8764ed55 SC |
6654 | if (ret) |
6655 | return ret; | |
45def77e | 6656 | |
8764ed55 SC |
6657 | /* |
6658 | * Workaround userspace that relies on old KVM behavior of %rip being | |
6659 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
6660 | */ | |
6661 | if (port == 0x7e && | |
6662 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
6663 | vcpu->arch.complete_userspace_io = | |
6664 | complete_fast_pio_out_port_0x7e; | |
6665 | kvm_skip_emulated_instruction(vcpu); | |
6666 | } else { | |
45def77e SC |
6667 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
6668 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
6669 | } | |
8764ed55 | 6670 | return 0; |
de7d789a | 6671 | } |
de7d789a | 6672 | |
8370c3d0 TL |
6673 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
6674 | { | |
6675 | unsigned long val; | |
6676 | ||
6677 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
6678 | BUG_ON(vcpu->arch.pio.count != 1); | |
6679 | ||
45def77e SC |
6680 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
6681 | vcpu->arch.pio.count = 0; | |
6682 | return 1; | |
6683 | } | |
6684 | ||
8370c3d0 | 6685 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 6686 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6687 | |
6688 | /* | |
6689 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform | |
6690 | * the copy and tracing | |
6691 | */ | |
6692 | emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, | |
6693 | vcpu->arch.pio.port, &val, 1); | |
de3cd117 | 6694 | kvm_rax_write(vcpu, val); |
8370c3d0 | 6695 | |
45def77e | 6696 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
6697 | } |
6698 | ||
dca7f128 SC |
6699 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
6700 | unsigned short port) | |
8370c3d0 TL |
6701 | { |
6702 | unsigned long val; | |
6703 | int ret; | |
6704 | ||
6705 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 6706 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
6707 | |
6708 | ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, | |
6709 | &val, 1); | |
6710 | if (ret) { | |
de3cd117 | 6711 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
6712 | return ret; |
6713 | } | |
6714 | ||
45def77e | 6715 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
6716 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
6717 | ||
6718 | return 0; | |
6719 | } | |
dca7f128 SC |
6720 | |
6721 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
6722 | { | |
45def77e | 6723 | int ret; |
dca7f128 | 6724 | |
dca7f128 | 6725 | if (in) |
45def77e | 6726 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 6727 | else |
45def77e SC |
6728 | ret = kvm_fast_pio_out(vcpu, size, port); |
6729 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
6730 | } |
6731 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 6732 | |
251a5fd6 | 6733 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 6734 | { |
0a3aee0d | 6735 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 6736 | return 0; |
8cfdc000 ZA |
6737 | } |
6738 | ||
6739 | static void tsc_khz_changed(void *data) | |
c8076604 | 6740 | { |
8cfdc000 ZA |
6741 | struct cpufreq_freqs *freq = data; |
6742 | unsigned long khz = 0; | |
6743 | ||
6744 | if (data) | |
6745 | khz = freq->new; | |
6746 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
6747 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
6748 | if (!khz) | |
6749 | khz = tsc_khz; | |
0a3aee0d | 6750 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
6751 | } |
6752 | ||
5fa4ec9c | 6753 | #ifdef CONFIG_X86_64 |
0092e434 VK |
6754 | static void kvm_hyperv_tsc_notifier(void) |
6755 | { | |
0092e434 VK |
6756 | struct kvm *kvm; |
6757 | struct kvm_vcpu *vcpu; | |
6758 | int cpu; | |
6759 | ||
0d9ce162 | 6760 | mutex_lock(&kvm_lock); |
0092e434 VK |
6761 | list_for_each_entry(kvm, &vm_list, vm_list) |
6762 | kvm_make_mclock_inprogress_request(kvm); | |
6763 | ||
6764 | hyperv_stop_tsc_emulation(); | |
6765 | ||
6766 | /* TSC frequency always matches when on Hyper-V */ | |
6767 | for_each_present_cpu(cpu) | |
6768 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
6769 | kvm_max_guest_tsc_khz = tsc_khz; | |
6770 | ||
6771 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
6772 | struct kvm_arch *ka = &kvm->arch; | |
6773 | ||
6774 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
6775 | ||
6776 | pvclock_update_vm_gtod_copy(kvm); | |
6777 | ||
6778 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6779 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
6780 | ||
6781 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
6782 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
6783 | ||
6784 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
6785 | } | |
0d9ce162 | 6786 | mutex_unlock(&kvm_lock); |
0092e434 | 6787 | } |
5fa4ec9c | 6788 | #endif |
0092e434 | 6789 | |
df24014a | 6790 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 6791 | { |
c8076604 GH |
6792 | struct kvm *kvm; |
6793 | struct kvm_vcpu *vcpu; | |
6794 | int i, send_ipi = 0; | |
6795 | ||
8cfdc000 ZA |
6796 | /* |
6797 | * We allow guests to temporarily run on slowing clocks, | |
6798 | * provided we notify them after, or to run on accelerating | |
6799 | * clocks, provided we notify them before. Thus time never | |
6800 | * goes backwards. | |
6801 | * | |
6802 | * However, we have a problem. We can't atomically update | |
6803 | * the frequency of a given CPU from this function; it is | |
6804 | * merely a notifier, which can be called from any CPU. | |
6805 | * Changing the TSC frequency at arbitrary points in time | |
6806 | * requires a recomputation of local variables related to | |
6807 | * the TSC for each VCPU. We must flag these local variables | |
6808 | * to be updated and be sure the update takes place with the | |
6809 | * new frequency before any guests proceed. | |
6810 | * | |
6811 | * Unfortunately, the combination of hotplug CPU and frequency | |
6812 | * change creates an intractable locking scenario; the order | |
6813 | * of when these callouts happen is undefined with respect to | |
6814 | * CPU hotplug, and they can race with each other. As such, | |
6815 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
6816 | * undefined; you can actually have a CPU frequency change take | |
6817 | * place in between the computation of X and the setting of the | |
6818 | * variable. To protect against this problem, all updates of | |
6819 | * the per_cpu tsc_khz variable are done in an interrupt | |
6820 | * protected IPI, and all callers wishing to update the value | |
6821 | * must wait for a synchronous IPI to complete (which is trivial | |
6822 | * if the caller is on the CPU already). This establishes the | |
6823 | * necessary total order on variable updates. | |
6824 | * | |
6825 | * Note that because a guest time update may take place | |
6826 | * anytime after the setting of the VCPU's request bit, the | |
6827 | * correct TSC value must be set before the request. However, | |
6828 | * to ensure the update actually makes it to any guest which | |
6829 | * starts running in hardware virtualization between the set | |
6830 | * and the acquisition of the spinlock, we must also ping the | |
6831 | * CPU after setting the request bit. | |
6832 | * | |
6833 | */ | |
6834 | ||
df24014a | 6835 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 6836 | |
0d9ce162 | 6837 | mutex_lock(&kvm_lock); |
c8076604 | 6838 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 6839 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 6840 | if (vcpu->cpu != cpu) |
c8076604 | 6841 | continue; |
c285545f | 6842 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 6843 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 6844 | send_ipi = 1; |
c8076604 GH |
6845 | } |
6846 | } | |
0d9ce162 | 6847 | mutex_unlock(&kvm_lock); |
c8076604 GH |
6848 | |
6849 | if (freq->old < freq->new && send_ipi) { | |
6850 | /* | |
6851 | * We upscale the frequency. Must make the guest | |
6852 | * doesn't see old kvmclock values while running with | |
6853 | * the new frequency, otherwise we risk the guest sees | |
6854 | * time go backwards. | |
6855 | * | |
6856 | * In case we update the frequency for another cpu | |
6857 | * (which might be in guest context) send an interrupt | |
6858 | * to kick the cpu out of guest context. Next time | |
6859 | * guest context is entered kvmclock will be updated, | |
6860 | * so the guest will not see stale values. | |
6861 | */ | |
df24014a | 6862 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 6863 | } |
df24014a VK |
6864 | } |
6865 | ||
6866 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
6867 | void *data) | |
6868 | { | |
6869 | struct cpufreq_freqs *freq = data; | |
6870 | int cpu; | |
6871 | ||
6872 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
6873 | return 0; | |
6874 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
6875 | return 0; | |
6876 | ||
6877 | for_each_cpu(cpu, freq->policy->cpus) | |
6878 | __kvmclock_cpufreq_notifier(freq, cpu); | |
6879 | ||
c8076604 GH |
6880 | return 0; |
6881 | } | |
6882 | ||
6883 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
6884 | .notifier_call = kvmclock_cpufreq_notifier |
6885 | }; | |
6886 | ||
251a5fd6 | 6887 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 6888 | { |
251a5fd6 SAS |
6889 | tsc_khz_changed(NULL); |
6890 | return 0; | |
8cfdc000 ZA |
6891 | } |
6892 | ||
b820cc0c ZA |
6893 | static void kvm_timer_init(void) |
6894 | { | |
c285545f | 6895 | max_tsc_khz = tsc_khz; |
460dd42e | 6896 | |
b820cc0c | 6897 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f ZA |
6898 | #ifdef CONFIG_CPU_FREQ |
6899 | struct cpufreq_policy policy; | |
758f588d BP |
6900 | int cpu; |
6901 | ||
c285545f | 6902 | memset(&policy, 0, sizeof(policy)); |
3e26f230 AK |
6903 | cpu = get_cpu(); |
6904 | cpufreq_get_policy(&policy, cpu); | |
c285545f ZA |
6905 | if (policy.cpuinfo.max_freq) |
6906 | max_tsc_khz = policy.cpuinfo.max_freq; | |
3e26f230 | 6907 | put_cpu(); |
c285545f | 6908 | #endif |
b820cc0c ZA |
6909 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
6910 | CPUFREQ_TRANSITION_NOTIFIER); | |
6911 | } | |
460dd42e | 6912 | |
73c1b41e | 6913 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 6914 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
6915 | } |
6916 | ||
dd60d217 AK |
6917 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
6918 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 6919 | |
f5132b01 | 6920 | int kvm_is_in_guest(void) |
ff9d07a0 | 6921 | { |
086c9855 | 6922 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
6923 | } |
6924 | ||
6925 | static int kvm_is_user_mode(void) | |
6926 | { | |
6927 | int user_mode = 3; | |
dcf46b94 | 6928 | |
086c9855 AS |
6929 | if (__this_cpu_read(current_vcpu)) |
6930 | user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 6931 | |
ff9d07a0 ZY |
6932 | return user_mode != 0; |
6933 | } | |
6934 | ||
6935 | static unsigned long kvm_get_guest_ip(void) | |
6936 | { | |
6937 | unsigned long ip = 0; | |
dcf46b94 | 6938 | |
086c9855 AS |
6939 | if (__this_cpu_read(current_vcpu)) |
6940 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 6941 | |
ff9d07a0 ZY |
6942 | return ip; |
6943 | } | |
6944 | ||
8479e04e LK |
6945 | static void kvm_handle_intel_pt_intr(void) |
6946 | { | |
6947 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
6948 | ||
6949 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
6950 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
6951 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
6952 | } | |
6953 | ||
ff9d07a0 ZY |
6954 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
6955 | .is_in_guest = kvm_is_in_guest, | |
6956 | .is_user_mode = kvm_is_user_mode, | |
6957 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 6958 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
6959 | }; |
6960 | ||
16e8d74d MT |
6961 | #ifdef CONFIG_X86_64 |
6962 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
6963 | { | |
d828199e MT |
6964 | struct kvm *kvm; |
6965 | ||
6966 | struct kvm_vcpu *vcpu; | |
6967 | int i; | |
6968 | ||
0d9ce162 | 6969 | mutex_lock(&kvm_lock); |
d828199e MT |
6970 | list_for_each_entry(kvm, &vm_list, vm_list) |
6971 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 6972 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 6973 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 6974 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
6975 | } |
6976 | ||
6977 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
6978 | ||
6979 | /* | |
6980 | * Notification about pvclock gtod data update. | |
6981 | */ | |
6982 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
6983 | void *priv) | |
6984 | { | |
6985 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
6986 | struct timekeeper *tk = priv; | |
6987 | ||
6988 | update_pvclock_gtod(tk); | |
6989 | ||
6990 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 6991 | * use, TSC based clocksource. |
16e8d74d | 6992 | */ |
b0c39dc6 | 6993 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
6994 | atomic_read(&kvm_guest_has_master_clock) != 0) |
6995 | queue_work(system_long_wq, &pvclock_gtod_work); | |
6996 | ||
6997 | return 0; | |
6998 | } | |
6999 | ||
7000 | static struct notifier_block pvclock_gtod_notifier = { | |
7001 | .notifier_call = pvclock_gtod_notify, | |
7002 | }; | |
7003 | #endif | |
7004 | ||
f8c16bba | 7005 | int kvm_arch_init(void *opaque) |
043405e1 | 7006 | { |
b820cc0c | 7007 | int r; |
6b61edf7 | 7008 | struct kvm_x86_ops *ops = opaque; |
f8c16bba | 7009 | |
f8c16bba ZX |
7010 | if (kvm_x86_ops) { |
7011 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
7012 | r = -EEXIST; |
7013 | goto out; | |
f8c16bba ZX |
7014 | } |
7015 | ||
7016 | if (!ops->cpu_has_kvm_support()) { | |
7017 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
7018 | r = -EOPNOTSUPP; |
7019 | goto out; | |
f8c16bba ZX |
7020 | } |
7021 | if (ops->disabled_by_bios()) { | |
7022 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
7023 | r = -EOPNOTSUPP; |
7024 | goto out; | |
f8c16bba ZX |
7025 | } |
7026 | ||
b666a4b6 MO |
7027 | /* |
7028 | * KVM explicitly assumes that the guest has an FPU and | |
7029 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7030 | * vCPU's FPU state as a fxregs_state struct. | |
7031 | */ | |
7032 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7033 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7034 | r = -EOPNOTSUPP; | |
7035 | goto out; | |
7036 | } | |
7037 | ||
013f6a5d | 7038 | r = -ENOMEM; |
ed8e4812 | 7039 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7040 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7041 | NULL); | |
7042 | if (!x86_fpu_cache) { | |
7043 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7044 | goto out; | |
7045 | } | |
7046 | ||
013f6a5d MT |
7047 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); |
7048 | if (!shared_msrs) { | |
7049 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
b666a4b6 | 7050 | goto out_free_x86_fpu_cache; |
013f6a5d MT |
7051 | } |
7052 | ||
97db56ce AK |
7053 | r = kvm_mmu_module_init(); |
7054 | if (r) | |
013f6a5d | 7055 | goto out_free_percpu; |
97db56ce | 7056 | |
f8c16bba | 7057 | kvm_x86_ops = ops; |
920c8377 | 7058 | |
7b52345e | 7059 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7060 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7061 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7062 | kvm_timer_init(); |
c8076604 | 7063 | |
ff9d07a0 ZY |
7064 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7065 | ||
d366bf7e | 7066 | if (boot_cpu_has(X86_FEATURE_XSAVE)) |
2acf923e DC |
7067 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
7068 | ||
c5cc421b | 7069 | kvm_lapic_init(); |
0c5f81da WL |
7070 | if (pi_inject_timer == -1) |
7071 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7072 | #ifdef CONFIG_X86_64 |
7073 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7074 | |
5fa4ec9c | 7075 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7076 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7077 | #endif |
7078 | ||
f8c16bba | 7079 | return 0; |
56c6d28a | 7080 | |
013f6a5d MT |
7081 | out_free_percpu: |
7082 | free_percpu(shared_msrs); | |
b666a4b6 MO |
7083 | out_free_x86_fpu_cache: |
7084 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7085 | out: |
56c6d28a | 7086 | return r; |
043405e1 | 7087 | } |
8776e519 | 7088 | |
f8c16bba ZX |
7089 | void kvm_arch_exit(void) |
7090 | { | |
0092e434 | 7091 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7092 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7093 | clear_hv_tscchange_cb(); |
7094 | #endif | |
cef84c30 | 7095 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7096 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7097 | ||
888d256e JK |
7098 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7099 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7100 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7101 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7102 | #ifdef CONFIG_X86_64 |
7103 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7104 | #endif | |
f8c16bba | 7105 | kvm_x86_ops = NULL; |
56c6d28a | 7106 | kvm_mmu_module_exit(); |
013f6a5d | 7107 | free_percpu(shared_msrs); |
b666a4b6 | 7108 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7109 | } |
f8c16bba | 7110 | |
5cb56059 | 7111 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
7112 | { |
7113 | ++vcpu->stat.halt_exits; | |
35754c98 | 7114 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 7115 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
7116 | return 1; |
7117 | } else { | |
7118 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
7119 | return 0; | |
7120 | } | |
7121 | } | |
5cb56059 JS |
7122 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
7123 | ||
7124 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
7125 | { | |
6affcbed KH |
7126 | int ret = kvm_skip_emulated_instruction(vcpu); |
7127 | /* | |
7128 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
7129 | * KVM_EXIT_DEBUG here. | |
7130 | */ | |
7131 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 7132 | } |
8776e519 HB |
7133 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
7134 | ||
8ef81a9a | 7135 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7136 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
7137 | unsigned long clock_type) | |
7138 | { | |
7139 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 7140 | struct timespec64 ts; |
80fbd89c | 7141 | u64 cycle; |
55dd00a7 MT |
7142 | int ret; |
7143 | ||
7144 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
7145 | return -KVM_EOPNOTSUPP; | |
7146 | ||
7147 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
7148 | return -KVM_EOPNOTSUPP; | |
7149 | ||
7150 | clock_pairing.sec = ts.tv_sec; | |
7151 | clock_pairing.nsec = ts.tv_nsec; | |
7152 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
7153 | clock_pairing.flags = 0; | |
bcbfbd8e | 7154 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
7155 | |
7156 | ret = 0; | |
7157 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
7158 | sizeof(struct kvm_clock_pairing))) | |
7159 | ret = -KVM_EFAULT; | |
7160 | ||
7161 | return ret; | |
7162 | } | |
8ef81a9a | 7163 | #endif |
55dd00a7 | 7164 | |
6aef266c SV |
7165 | /* |
7166 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
7167 | * | |
7168 | * @apicid - apicid of vcpu to be kicked. | |
7169 | */ | |
7170 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
7171 | { | |
24d2166b | 7172 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 7173 | |
24d2166b R |
7174 | lapic_irq.shorthand = 0; |
7175 | lapic_irq.dest_mode = 0; | |
ebd28fcb | 7176 | lapic_irq.level = 0; |
24d2166b | 7177 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 7178 | lapic_irq.msi_redir_hint = false; |
6aef266c | 7179 | |
24d2166b | 7180 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 7181 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
7182 | } |
7183 | ||
d62caabb AS |
7184 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) |
7185 | { | |
f7589cca PB |
7186 | if (!lapic_in_kernel(vcpu)) { |
7187 | WARN_ON_ONCE(vcpu->arch.apicv_active); | |
7188 | return; | |
7189 | } | |
7190 | if (!vcpu->arch.apicv_active) | |
7191 | return; | |
7192 | ||
d62caabb AS |
7193 | vcpu->arch.apicv_active = false; |
7194 | kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); | |
7195 | } | |
7196 | ||
71506297 WL |
7197 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
7198 | { | |
7199 | struct kvm_vcpu *target = NULL; | |
7200 | struct kvm_apic_map *map; | |
7201 | ||
7202 | rcu_read_lock(); | |
7203 | map = rcu_dereference(kvm->arch.apic_map); | |
7204 | ||
7205 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
7206 | target = map->phys_map[dest_id]->vcpu; | |
7207 | ||
7208 | rcu_read_unlock(); | |
7209 | ||
266e85a5 | 7210 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
7211 | kvm_vcpu_yield_to(target); |
7212 | } | |
7213 | ||
8776e519 HB |
7214 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
7215 | { | |
7216 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 7217 | int op_64_bit; |
8776e519 | 7218 | |
696ca779 RK |
7219 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
7220 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 7221 | |
de3cd117 SC |
7222 | nr = kvm_rax_read(vcpu); |
7223 | a0 = kvm_rbx_read(vcpu); | |
7224 | a1 = kvm_rcx_read(vcpu); | |
7225 | a2 = kvm_rdx_read(vcpu); | |
7226 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 7227 | |
229456fc | 7228 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 7229 | |
a449c7aa NA |
7230 | op_64_bit = is_64_bit_mode(vcpu); |
7231 | if (!op_64_bit) { | |
8776e519 HB |
7232 | nr &= 0xFFFFFFFF; |
7233 | a0 &= 0xFFFFFFFF; | |
7234 | a1 &= 0xFFFFFFFF; | |
7235 | a2 &= 0xFFFFFFFF; | |
7236 | a3 &= 0xFFFFFFFF; | |
7237 | } | |
7238 | ||
07708c4a JK |
7239 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
7240 | ret = -KVM_EPERM; | |
696ca779 | 7241 | goto out; |
07708c4a JK |
7242 | } |
7243 | ||
8776e519 | 7244 | switch (nr) { |
b93463aa AK |
7245 | case KVM_HC_VAPIC_POLL_IRQ: |
7246 | ret = 0; | |
7247 | break; | |
6aef266c SV |
7248 | case KVM_HC_KICK_CPU: |
7249 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
266e85a5 | 7250 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
7251 | ret = 0; |
7252 | break; | |
8ef81a9a | 7253 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7254 | case KVM_HC_CLOCK_PAIRING: |
7255 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
7256 | break; | |
1ed199a4 | 7257 | #endif |
4180bf1b WL |
7258 | case KVM_HC_SEND_IPI: |
7259 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); | |
7260 | break; | |
71506297 WL |
7261 | case KVM_HC_SCHED_YIELD: |
7262 | kvm_sched_yield(vcpu->kvm, a0); | |
7263 | ret = 0; | |
7264 | break; | |
8776e519 HB |
7265 | default: |
7266 | ret = -KVM_ENOSYS; | |
7267 | break; | |
7268 | } | |
696ca779 | 7269 | out: |
a449c7aa NA |
7270 | if (!op_64_bit) |
7271 | ret = (u32)ret; | |
de3cd117 | 7272 | kvm_rax_write(vcpu, ret); |
6356ee0c | 7273 | |
f11c3a8d | 7274 | ++vcpu->stat.hypercalls; |
6356ee0c | 7275 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
7276 | } |
7277 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
7278 | ||
b6785def | 7279 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 7280 | { |
d6aa1000 | 7281 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 7282 | char instruction[3]; |
5fdbf976 | 7283 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 7284 | |
8776e519 | 7285 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
8776e519 | 7286 | |
ce2e852e DV |
7287 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
7288 | &ctxt->exception); | |
8776e519 HB |
7289 | } |
7290 | ||
851ba692 | 7291 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7292 | { |
782d422b MG |
7293 | return vcpu->run->request_interrupt_window && |
7294 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
7295 | } |
7296 | ||
851ba692 | 7297 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7298 | { |
851ba692 AK |
7299 | struct kvm_run *kvm_run = vcpu->run; |
7300 | ||
91586a3b | 7301 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 7302 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 7303 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 7304 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
7305 | kvm_run->ready_for_interrupt_injection = |
7306 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 7307 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
7308 | } |
7309 | ||
95ba8273 GN |
7310 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
7311 | { | |
7312 | int max_irr, tpr; | |
7313 | ||
7314 | if (!kvm_x86_ops->update_cr8_intercept) | |
7315 | return; | |
7316 | ||
bce87cce | 7317 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
7318 | return; |
7319 | ||
d62caabb AS |
7320 | if (vcpu->arch.apicv_active) |
7321 | return; | |
7322 | ||
8db3baa2 GN |
7323 | if (!vcpu->arch.apic->vapic_addr) |
7324 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
7325 | else | |
7326 | max_irr = -1; | |
95ba8273 GN |
7327 | |
7328 | if (max_irr != -1) | |
7329 | max_irr >>= 4; | |
7330 | ||
7331 | tpr = kvm_lapic_get_cr8(vcpu); | |
7332 | ||
7333 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
7334 | } | |
7335 | ||
b6b8a145 | 7336 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) |
95ba8273 | 7337 | { |
b6b8a145 JK |
7338 | int r; |
7339 | ||
95ba8273 | 7340 | /* try to reinject previous events if any */ |
664f8e26 | 7341 | |
1a680e35 LA |
7342 | if (vcpu->arch.exception.injected) |
7343 | kvm_x86_ops->queue_exception(vcpu); | |
664f8e26 | 7344 | /* |
a042c26f LA |
7345 | * Do not inject an NMI or interrupt if there is a pending |
7346 | * exception. Exceptions and interrupts are recognized at | |
7347 | * instruction boundaries, i.e. the start of an instruction. | |
7348 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
7349 | * NMIs and interrupts, i.e. traps are recognized before an | |
7350 | * NMI/interrupt that's pending on the same instruction. | |
7351 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
7352 | * priority, but are only generated (pended) during instruction | |
7353 | * execution, i.e. a pending fault-like exception means the | |
7354 | * fault occurred on the *previous* instruction and must be | |
7355 | * serviced prior to recognizing any new events in order to | |
7356 | * fully complete the previous instruction. | |
664f8e26 | 7357 | */ |
1a680e35 LA |
7358 | else if (!vcpu->arch.exception.pending) { |
7359 | if (vcpu->arch.nmi_injected) | |
664f8e26 | 7360 | kvm_x86_ops->set_nmi(vcpu); |
1a680e35 | 7361 | else if (vcpu->arch.interrupt.injected) |
664f8e26 | 7362 | kvm_x86_ops->set_irq(vcpu); |
664f8e26 WL |
7363 | } |
7364 | ||
1a680e35 LA |
7365 | /* |
7366 | * Call check_nested_events() even if we reinjected a previous event | |
7367 | * in order for caller to determine if it should require immediate-exit | |
7368 | * from L2 to L1 due to pending L1 events which require exit | |
7369 | * from L2 to L1. | |
7370 | */ | |
664f8e26 WL |
7371 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { |
7372 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7373 | if (r != 0) | |
7374 | return r; | |
7375 | } | |
7376 | ||
7377 | /* try to inject new event if pending */ | |
b59bb7bd | 7378 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
7379 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
7380 | vcpu->arch.exception.has_error_code, | |
7381 | vcpu->arch.exception.error_code); | |
d6e8c854 | 7382 | |
1a680e35 | 7383 | WARN_ON_ONCE(vcpu->arch.exception.injected); |
664f8e26 WL |
7384 | vcpu->arch.exception.pending = false; |
7385 | vcpu->arch.exception.injected = true; | |
7386 | ||
d6e8c854 NA |
7387 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
7388 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
7389 | X86_EFLAGS_RF); | |
7390 | ||
f10c729f JM |
7391 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
7392 | /* | |
7393 | * This code assumes that nSVM doesn't use | |
7394 | * check_nested_events(). If it does, the | |
7395 | * DR6/DR7 changes should happen before L1 | |
7396 | * gets a #VMEXIT for an intercepted #DB in | |
7397 | * L2. (Under VMX, on the other hand, the | |
7398 | * DR6/DR7 changes should not happen in the | |
7399 | * event of a VM-exit to L1 for an intercepted | |
7400 | * #DB in L2.) | |
7401 | */ | |
7402 | kvm_deliver_exception_payload(vcpu); | |
7403 | if (vcpu->arch.dr7 & DR7_GD) { | |
7404 | vcpu->arch.dr7 &= ~DR7_GD; | |
7405 | kvm_update_dr7(vcpu); | |
7406 | } | |
6bdf0662 NA |
7407 | } |
7408 | ||
cfcd20e5 | 7409 | kvm_x86_ops->queue_exception(vcpu); |
1a680e35 LA |
7410 | } |
7411 | ||
7412 | /* Don't consider new event if we re-injected an event */ | |
7413 | if (kvm_event_needs_reinjection(vcpu)) | |
7414 | return 0; | |
7415 | ||
7416 | if (vcpu->arch.smi_pending && !is_smm(vcpu) && | |
7417 | kvm_x86_ops->smi_allowed(vcpu)) { | |
c43203ca | 7418 | vcpu->arch.smi_pending = false; |
52797bf9 | 7419 | ++vcpu->arch.smi_count; |
ee2cd4b7 | 7420 | enter_smm(vcpu); |
c43203ca | 7421 | } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { |
321c5658 YS |
7422 | --vcpu->arch.nmi_pending; |
7423 | vcpu->arch.nmi_injected = true; | |
7424 | kvm_x86_ops->set_nmi(vcpu); | |
c7c9c56c | 7425 | } else if (kvm_cpu_has_injectable_intr(vcpu)) { |
9242b5b6 BD |
7426 | /* |
7427 | * Because interrupts can be injected asynchronously, we are | |
7428 | * calling check_nested_events again here to avoid a race condition. | |
7429 | * See https://lkml.org/lkml/2014/7/2/60 for discussion about this | |
7430 | * proposal and current concerns. Perhaps we should be setting | |
7431 | * KVM_REQ_EVENT only on certain events and not unconditionally? | |
7432 | */ | |
7433 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { | |
7434 | r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); | |
7435 | if (r != 0) | |
7436 | return r; | |
7437 | } | |
95ba8273 | 7438 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { |
66fd3f7f GN |
7439 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
7440 | false); | |
7441 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
7442 | } |
7443 | } | |
ee2cd4b7 | 7444 | |
b6b8a145 | 7445 | return 0; |
95ba8273 GN |
7446 | } |
7447 | ||
7460fb4a AK |
7448 | static void process_nmi(struct kvm_vcpu *vcpu) |
7449 | { | |
7450 | unsigned limit = 2; | |
7451 | ||
7452 | /* | |
7453 | * x86 is limited to one NMI running, and one NMI pending after it. | |
7454 | * If an NMI is already in progress, limit further NMIs to just one. | |
7455 | * Otherwise, allow two (and we'll inject the first one immediately). | |
7456 | */ | |
7457 | if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) | |
7458 | limit = 1; | |
7459 | ||
7460 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
7461 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
7462 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7463 | } | |
7464 | ||
ee2cd4b7 | 7465 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
7466 | { |
7467 | u32 flags = 0; | |
7468 | flags |= seg->g << 23; | |
7469 | flags |= seg->db << 22; | |
7470 | flags |= seg->l << 21; | |
7471 | flags |= seg->avl << 20; | |
7472 | flags |= seg->present << 15; | |
7473 | flags |= seg->dpl << 13; | |
7474 | flags |= seg->s << 12; | |
7475 | flags |= seg->type << 8; | |
7476 | return flags; | |
7477 | } | |
7478 | ||
ee2cd4b7 | 7479 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7480 | { |
7481 | struct kvm_segment seg; | |
7482 | int offset; | |
7483 | ||
7484 | kvm_get_segment(vcpu, &seg, n); | |
7485 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
7486 | ||
7487 | if (n < 3) | |
7488 | offset = 0x7f84 + n * 12; | |
7489 | else | |
7490 | offset = 0x7f2c + (n - 3) * 12; | |
7491 | ||
7492 | put_smstate(u32, buf, offset + 8, seg.base); | |
7493 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 7494 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7495 | } |
7496 | ||
efbb288a | 7497 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7498 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7499 | { |
7500 | struct kvm_segment seg; | |
7501 | int offset; | |
7502 | u16 flags; | |
7503 | ||
7504 | kvm_get_segment(vcpu, &seg, n); | |
7505 | offset = 0x7e00 + n * 16; | |
7506 | ||
ee2cd4b7 | 7507 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
7508 | put_smstate(u16, buf, offset, seg.selector); |
7509 | put_smstate(u16, buf, offset + 2, flags); | |
7510 | put_smstate(u32, buf, offset + 4, seg.limit); | |
7511 | put_smstate(u64, buf, offset + 8, seg.base); | |
7512 | } | |
efbb288a | 7513 | #endif |
660a5d51 | 7514 | |
ee2cd4b7 | 7515 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
7516 | { |
7517 | struct desc_ptr dt; | |
7518 | struct kvm_segment seg; | |
7519 | unsigned long val; | |
7520 | int i; | |
7521 | ||
7522 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
7523 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
7524 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
7525 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
7526 | ||
7527 | for (i = 0; i < 8; i++) | |
7528 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
7529 | ||
7530 | kvm_get_dr(vcpu, 6, &val); | |
7531 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
7532 | kvm_get_dr(vcpu, 7, &val); | |
7533 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
7534 | ||
7535 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7536 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
7537 | put_smstate(u32, buf, 0x7f64, seg.base); | |
7538 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 7539 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7540 | |
7541 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7542 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
7543 | put_smstate(u32, buf, 0x7f80, seg.base); | |
7544 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 7545 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7546 | |
7547 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7548 | put_smstate(u32, buf, 0x7f74, dt.address); | |
7549 | put_smstate(u32, buf, 0x7f70, dt.size); | |
7550 | ||
7551 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7552 | put_smstate(u32, buf, 0x7f58, dt.address); | |
7553 | put_smstate(u32, buf, 0x7f54, dt.size); | |
7554 | ||
7555 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7556 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
7557 | |
7558 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
7559 | ||
7560 | /* revision id */ | |
7561 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
7562 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
7563 | } | |
7564 | ||
b68f3cc7 | 7565 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7566 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 7567 | { |
660a5d51 PB |
7568 | struct desc_ptr dt; |
7569 | struct kvm_segment seg; | |
7570 | unsigned long val; | |
7571 | int i; | |
7572 | ||
7573 | for (i = 0; i < 16; i++) | |
7574 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
7575 | ||
7576 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
7577 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
7578 | ||
7579 | kvm_get_dr(vcpu, 6, &val); | |
7580 | put_smstate(u64, buf, 0x7f68, val); | |
7581 | kvm_get_dr(vcpu, 7, &val); | |
7582 | put_smstate(u64, buf, 0x7f60, val); | |
7583 | ||
7584 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
7585 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
7586 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
7587 | ||
7588 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
7589 | ||
7590 | /* revision id */ | |
7591 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
7592 | ||
7593 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
7594 | ||
7595 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
7596 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 7597 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7598 | put_smstate(u32, buf, 0x7e94, seg.limit); |
7599 | put_smstate(u64, buf, 0x7e98, seg.base); | |
7600 | ||
7601 | kvm_x86_ops->get_idt(vcpu, &dt); | |
7602 | put_smstate(u32, buf, 0x7e84, dt.size); | |
7603 | put_smstate(u64, buf, 0x7e88, dt.address); | |
7604 | ||
7605 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
7606 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 7607 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
7608 | put_smstate(u32, buf, 0x7e74, seg.limit); |
7609 | put_smstate(u64, buf, 0x7e78, seg.base); | |
7610 | ||
7611 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
7612 | put_smstate(u32, buf, 0x7e64, dt.size); | |
7613 | put_smstate(u64, buf, 0x7e68, dt.address); | |
7614 | ||
7615 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 7616 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 7617 | } |
b68f3cc7 | 7618 | #endif |
660a5d51 | 7619 | |
ee2cd4b7 | 7620 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 7621 | { |
660a5d51 | 7622 | struct kvm_segment cs, ds; |
18c3626e | 7623 | struct desc_ptr dt; |
660a5d51 PB |
7624 | char buf[512]; |
7625 | u32 cr0; | |
7626 | ||
660a5d51 | 7627 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 7628 | memset(buf, 0, 512); |
b68f3cc7 | 7629 | #ifdef CONFIG_X86_64 |
d6321d49 | 7630 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 7631 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 7632 | else |
b68f3cc7 | 7633 | #endif |
ee2cd4b7 | 7634 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 7635 | |
0234bf88 LP |
7636 | /* |
7637 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
7638 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
7639 | * the SMM state-save area. | |
7640 | */ | |
7641 | kvm_x86_ops->pre_enter_smm(vcpu, buf); | |
7642 | ||
7643 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 7644 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 PB |
7645 | |
7646 | if (kvm_x86_ops->get_nmi_mask(vcpu)) | |
7647 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
7648 | else | |
7649 | kvm_x86_ops->set_nmi_mask(vcpu, true); | |
7650 | ||
7651 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
7652 | kvm_rip_write(vcpu, 0x8000); | |
7653 | ||
7654 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
7655 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
7656 | vcpu->arch.cr0 = cr0; | |
7657 | ||
7658 | kvm_x86_ops->set_cr4(vcpu, 0); | |
7659 | ||
18c3626e PB |
7660 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
7661 | dt.address = dt.size = 0; | |
7662 | kvm_x86_ops->set_idt(vcpu, &dt); | |
7663 | ||
660a5d51 PB |
7664 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
7665 | ||
7666 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
7667 | cs.base = vcpu->arch.smbase; | |
7668 | ||
7669 | ds.selector = 0; | |
7670 | ds.base = 0; | |
7671 | ||
7672 | cs.limit = ds.limit = 0xffffffff; | |
7673 | cs.type = ds.type = 0x3; | |
7674 | cs.dpl = ds.dpl = 0; | |
7675 | cs.db = ds.db = 0; | |
7676 | cs.s = ds.s = 1; | |
7677 | cs.l = ds.l = 0; | |
7678 | cs.g = ds.g = 1; | |
7679 | cs.avl = ds.avl = 0; | |
7680 | cs.present = ds.present = 1; | |
7681 | cs.unusable = ds.unusable = 0; | |
7682 | cs.padding = ds.padding = 0; | |
7683 | ||
7684 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
7685 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
7686 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
7687 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
7688 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
7689 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
7690 | ||
b68f3cc7 | 7691 | #ifdef CONFIG_X86_64 |
d6321d49 | 7692 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
660a5d51 | 7693 | kvm_x86_ops->set_efer(vcpu, 0); |
b68f3cc7 | 7694 | #endif |
660a5d51 PB |
7695 | |
7696 | kvm_update_cpuid(vcpu); | |
7697 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
7698 | } |
7699 | ||
ee2cd4b7 | 7700 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
7701 | { |
7702 | vcpu->arch.smi_pending = true; | |
7703 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7704 | } | |
7705 | ||
2860c4b1 PB |
7706 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
7707 | { | |
7708 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
7709 | } | |
7710 | ||
3d81bc7e | 7711 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 7712 | { |
dcbd3e49 | 7713 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 7714 | return; |
c7c9c56c | 7715 | |
6308630b | 7716 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 7717 | |
b053b2ae | 7718 | if (irqchip_split(vcpu->kvm)) |
6308630b | 7719 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 7720 | else { |
fa59cc00 | 7721 | if (vcpu->arch.apicv_active) |
d62caabb | 7722 | kvm_x86_ops->sync_pir_to_irr(vcpu); |
e97f852f WL |
7723 | if (ioapic_in_kernel(vcpu->kvm)) |
7724 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 7725 | } |
e40ff1d6 LA |
7726 | |
7727 | if (is_guest_mode(vcpu)) | |
7728 | vcpu->arch.load_eoi_exitmap_pending = true; | |
7729 | else | |
7730 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
7731 | } | |
7732 | ||
7733 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
7734 | { | |
7735 | u64 eoi_exit_bitmap[4]; | |
7736 | ||
7737 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
7738 | return; | |
7739 | ||
5c919412 AS |
7740 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
7741 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
7742 | kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); | |
c7c9c56c YZ |
7743 | } |
7744 | ||
93065ac7 MH |
7745 | int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
7746 | unsigned long start, unsigned long end, | |
7747 | bool blockable) | |
b1394e74 RK |
7748 | { |
7749 | unsigned long apic_address; | |
7750 | ||
7751 | /* | |
7752 | * The physical address of apic access page is stored in the VMCS. | |
7753 | * Update it when it becomes invalid. | |
7754 | */ | |
7755 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
7756 | if (start <= apic_address && apic_address < end) | |
7757 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
93065ac7 MH |
7758 | |
7759 | return 0; | |
b1394e74 RK |
7760 | } |
7761 | ||
4256f43f TC |
7762 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
7763 | { | |
c24ae0dc TC |
7764 | struct page *page = NULL; |
7765 | ||
35754c98 | 7766 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
7767 | return; |
7768 | ||
4256f43f TC |
7769 | if (!kvm_x86_ops->set_apic_access_page_addr) |
7770 | return; | |
7771 | ||
c24ae0dc | 7772 | page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
e8fd5e9e AA |
7773 | if (is_error_page(page)) |
7774 | return; | |
c24ae0dc TC |
7775 | kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); |
7776 | ||
7777 | /* | |
7778 | * Do not pin apic access page in memory, the MMU notifier | |
7779 | * will call us again if it is migrated or swapped out. | |
7780 | */ | |
7781 | put_page(page); | |
4256f43f TC |
7782 | } |
7783 | EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); | |
7784 | ||
d264ee0c SC |
7785 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
7786 | { | |
7787 | smp_send_reschedule(vcpu->cpu); | |
7788 | } | |
7789 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
7790 | ||
9357d939 | 7791 | /* |
362c698f | 7792 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
7793 | * exiting to the userspace. Otherwise, the value will be returned to the |
7794 | * userspace. | |
7795 | */ | |
851ba692 | 7796 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
7797 | { |
7798 | int r; | |
62a193ed MG |
7799 | bool req_int_win = |
7800 | dm_request_for_irq_injection(vcpu) && | |
7801 | kvm_cpu_accept_dm_intr(vcpu); | |
7802 | ||
730dca42 | 7803 | bool req_immediate_exit = false; |
b6c7a5dc | 7804 | |
2fa6e1e1 | 7805 | if (kvm_request_pending(vcpu)) { |
7f7f1ba3 PB |
7806 | if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) |
7807 | kvm_x86_ops->get_vmcs12_pages(vcpu); | |
a8eeb04a | 7808 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 7809 | kvm_mmu_unload(vcpu); |
a8eeb04a | 7810 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 7811 | __kvm_migrate_timers(vcpu); |
d828199e MT |
7812 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
7813 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
7814 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
7815 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
7816 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
7817 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
7818 | if (unlikely(r)) |
7819 | goto out; | |
7820 | } | |
a8eeb04a | 7821 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 7822 | kvm_mmu_sync_roots(vcpu); |
6e42782f JS |
7823 | if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) |
7824 | kvm_mmu_load_cr3(vcpu); | |
a8eeb04a | 7825 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) |
c2ba05cc | 7826 | kvm_vcpu_flush_tlb(vcpu, true); |
a8eeb04a | 7827 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 7828 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
7829 | r = 0; |
7830 | goto out; | |
7831 | } | |
a8eeb04a | 7832 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 7833 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 7834 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
7835 | r = 0; |
7836 | goto out; | |
7837 | } | |
af585b92 GN |
7838 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
7839 | /* Page is swapped out. Do synthetic halt */ | |
7840 | vcpu->arch.apf.halted = true; | |
7841 | r = 1; | |
7842 | goto out; | |
7843 | } | |
c9aaa895 GC |
7844 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
7845 | record_steal_time(vcpu); | |
64d60670 PB |
7846 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
7847 | process_smi(vcpu); | |
7460fb4a AK |
7848 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
7849 | process_nmi(vcpu); | |
f5132b01 | 7850 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 7851 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 7852 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 7853 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
7854 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
7855 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
7856 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 7857 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
7858 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
7859 | vcpu->run->eoi.vector = | |
7860 | vcpu->arch.pending_ioapic_eoi; | |
7861 | r = 0; | |
7862 | goto out; | |
7863 | } | |
7864 | } | |
3d81bc7e YZ |
7865 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
7866 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
7867 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
7868 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
7869 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
7870 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
7871 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
7872 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7873 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
7874 | r = 0; | |
7875 | goto out; | |
7876 | } | |
e516cebb AS |
7877 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
7878 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
7879 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
7880 | r = 0; | |
7881 | goto out; | |
7882 | } | |
db397571 AS |
7883 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
7884 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
7885 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
7886 | r = 0; | |
7887 | goto out; | |
7888 | } | |
f3b138c5 AS |
7889 | |
7890 | /* | |
7891 | * KVM_REQ_HV_STIMER has to be processed after | |
7892 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
7893 | * depend on the guest clock being up-to-date | |
7894 | */ | |
1f4b34f8 AS |
7895 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
7896 | kvm_hv_process_stimers(vcpu); | |
2f52d58c | 7897 | } |
b93463aa | 7898 | |
b463a6f7 | 7899 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 7900 | ++vcpu->stat.req_event; |
66450a21 JK |
7901 | kvm_apic_accept_events(vcpu); |
7902 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
7903 | r = 1; | |
7904 | goto out; | |
7905 | } | |
7906 | ||
b6b8a145 JK |
7907 | if (inject_pending_event(vcpu, req_int_win) != 0) |
7908 | req_immediate_exit = true; | |
321c5658 | 7909 | else { |
cc3d967f | 7910 | /* Enable SMI/NMI/IRQ window open exits if needed. |
c43203ca | 7911 | * |
cc3d967f LP |
7912 | * SMIs have three cases: |
7913 | * 1) They can be nested, and then there is nothing to | |
7914 | * do here because RSM will cause a vmexit anyway. | |
7915 | * 2) There is an ISA-specific reason why SMI cannot be | |
7916 | * injected, and the moment when this changes can be | |
7917 | * intercepted. | |
7918 | * 3) Or the SMI can be pending because | |
7919 | * inject_pending_event has completed the injection | |
7920 | * of an IRQ or NMI from the previous vmexit, and | |
7921 | * then we request an immediate exit to inject the | |
7922 | * SMI. | |
c43203ca PB |
7923 | */ |
7924 | if (vcpu->arch.smi_pending && !is_smm(vcpu)) | |
cc3d967f LP |
7925 | if (!kvm_x86_ops->enable_smi_window(vcpu)) |
7926 | req_immediate_exit = true; | |
321c5658 YS |
7927 | if (vcpu->arch.nmi_pending) |
7928 | kvm_x86_ops->enable_nmi_window(vcpu); | |
7929 | if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) | |
7930 | kvm_x86_ops->enable_irq_window(vcpu); | |
664f8e26 | 7931 | WARN_ON(vcpu->arch.exception.pending); |
321c5658 | 7932 | } |
b463a6f7 AK |
7933 | |
7934 | if (kvm_lapic_enabled(vcpu)) { | |
7935 | update_cr8_intercept(vcpu); | |
7936 | kvm_lapic_sync_to_vapic(vcpu); | |
7937 | } | |
7938 | } | |
7939 | ||
d8368af8 AK |
7940 | r = kvm_mmu_reload(vcpu); |
7941 | if (unlikely(r)) { | |
d905c069 | 7942 | goto cancel_injection; |
d8368af8 AK |
7943 | } |
7944 | ||
b6c7a5dc HB |
7945 | preempt_disable(); |
7946 | ||
7947 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
b95234c8 PB |
7948 | |
7949 | /* | |
7950 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
7951 | * IPI are then delayed after guest entry, which ensures that they | |
7952 | * result in virtual interrupt delivery. | |
7953 | */ | |
7954 | local_irq_disable(); | |
6b7e2d09 XG |
7955 | vcpu->mode = IN_GUEST_MODE; |
7956 | ||
01b71917 MT |
7957 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
7958 | ||
0f127d12 | 7959 | /* |
b95234c8 | 7960 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 7961 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 7962 | * |
81b01667 | 7963 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
7964 | * pairs with the memory barrier implicit in pi_test_and_set_on |
7965 | * (see vmx_deliver_posted_interrupt). | |
7966 | * | |
7967 | * 3) This also orders the write to mode from any reads to the page | |
7968 | * tables done while the VCPU is running. Please see the comment | |
7969 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 7970 | */ |
01b71917 | 7971 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 7972 | |
b95234c8 PB |
7973 | /* |
7974 | * This handles the case where a posted interrupt was | |
7975 | * notified with kvm_vcpu_kick. | |
7976 | */ | |
fa59cc00 LA |
7977 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
7978 | kvm_x86_ops->sync_pir_to_irr(vcpu); | |
32f88400 | 7979 | |
2fa6e1e1 | 7980 | if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) |
d94e1dc9 | 7981 | || need_resched() || signal_pending(current)) { |
6b7e2d09 | 7982 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 7983 | smp_wmb(); |
6c142801 AK |
7984 | local_irq_enable(); |
7985 | preempt_enable(); | |
01b71917 | 7986 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 7987 | r = 1; |
d905c069 | 7988 | goto cancel_injection; |
6c142801 AK |
7989 | } |
7990 | ||
c43203ca PB |
7991 | if (req_immediate_exit) { |
7992 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
d264ee0c | 7993 | kvm_x86_ops->request_immediate_exit(vcpu); |
c43203ca | 7994 | } |
d6185f20 | 7995 | |
8b89fe1f | 7996 | trace_kvm_entry(vcpu->vcpu_id); |
6edaa530 | 7997 | guest_enter_irqoff(); |
b6c7a5dc | 7998 | |
e7517324 WL |
7999 | /* The preempt notifier should have taken care of the FPU already. */ |
8000 | WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD)); | |
5f409e20 | 8001 | |
42dbaa5a | 8002 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
8003 | set_debugreg(0, 7); |
8004 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
8005 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
8006 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
8007 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 8008 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 8009 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 8010 | } |
b6c7a5dc | 8011 | |
851ba692 | 8012 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 8013 | |
c77fb5fe PB |
8014 | /* |
8015 | * Do this here before restoring debug registers on the host. And | |
8016 | * since we do this before handling the vmexit, a DR access vmexit | |
8017 | * can (a) read the correct value of the debug registers, (b) set | |
8018 | * KVM_DEBUGREG_WONT_EXIT again. | |
8019 | */ | |
8020 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe PB |
8021 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
8022 | kvm_x86_ops->sync_dirty_debug_regs(vcpu); | |
70e4da7a PB |
8023 | kvm_update_dr0123(vcpu); |
8024 | kvm_update_dr6(vcpu); | |
8025 | kvm_update_dr7(vcpu); | |
8026 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
8027 | } |
8028 | ||
24f1e32c FW |
8029 | /* |
8030 | * If the guest has used debug registers, at least dr7 | |
8031 | * will be disabled while returning to the host. | |
8032 | * If we don't have active breakpoints in the host, we don't | |
8033 | * care about the messed up debug address registers. But if | |
8034 | * we have some of them active, restore the old state. | |
8035 | */ | |
59d8eb53 | 8036 | if (hw_breakpoint_active()) |
24f1e32c | 8037 | hw_breakpoint_restore(); |
42dbaa5a | 8038 | |
4ba76538 | 8039 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 8040 | |
6b7e2d09 | 8041 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8042 | smp_wmb(); |
a547c6db | 8043 | |
95b5a48c | 8044 | kvm_x86_ops->handle_exit_irqoff(vcpu); |
b6c7a5dc | 8045 | |
d7a08882 SC |
8046 | /* |
8047 | * Consume any pending interrupts, including the possible source of | |
8048 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
8049 | * An instruction is required after local_irq_enable() to fully unblock | |
8050 | * interrupts on processors that implement an interrupt shadow, the | |
8051 | * stat.exits increment will do nicely. | |
8052 | */ | |
8053 | kvm_before_interrupt(vcpu); | |
8054 | local_irq_enable(); | |
b6c7a5dc | 8055 | ++vcpu->stat.exits; |
d7a08882 SC |
8056 | local_irq_disable(); |
8057 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 8058 | |
f2485b3e | 8059 | guest_exit_irqoff(); |
ec0671d5 WL |
8060 | if (lapic_in_kernel(vcpu)) { |
8061 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
8062 | if (delta != S64_MIN) { | |
8063 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
8064 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
8065 | } | |
8066 | } | |
b6c7a5dc | 8067 | |
f2485b3e | 8068 | local_irq_enable(); |
b6c7a5dc HB |
8069 | preempt_enable(); |
8070 | ||
f656ce01 | 8071 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 8072 | |
b6c7a5dc HB |
8073 | /* |
8074 | * Profile KVM exit RIPs: | |
8075 | */ | |
8076 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
8077 | unsigned long rip = kvm_rip_read(vcpu); |
8078 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
8079 | } |
8080 | ||
cc578287 ZA |
8081 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
8082 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 8083 | |
5cfb1d5a MT |
8084 | if (vcpu->arch.apic_attention) |
8085 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 8086 | |
618232e2 | 8087 | vcpu->arch.gpa_available = false; |
851ba692 | 8088 | r = kvm_x86_ops->handle_exit(vcpu); |
d905c069 MT |
8089 | return r; |
8090 | ||
8091 | cancel_injection: | |
8092 | kvm_x86_ops->cancel_injection(vcpu); | |
ae7a2a3f MT |
8093 | if (unlikely(vcpu->arch.apic_attention)) |
8094 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
8095 | out: |
8096 | return r; | |
8097 | } | |
b6c7a5dc | 8098 | |
362c698f PB |
8099 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
8100 | { | |
bf9f6ac8 FW |
8101 | if (!kvm_arch_vcpu_runnable(vcpu) && |
8102 | (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { | |
9c8fd1ba PB |
8103 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
8104 | kvm_vcpu_block(vcpu); | |
8105 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 FW |
8106 | |
8107 | if (kvm_x86_ops->post_block) | |
8108 | kvm_x86_ops->post_block(vcpu); | |
8109 | ||
9c8fd1ba PB |
8110 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
8111 | return 1; | |
8112 | } | |
362c698f PB |
8113 | |
8114 | kvm_apic_accept_events(vcpu); | |
8115 | switch(vcpu->arch.mp_state) { | |
8116 | case KVM_MP_STATE_HALTED: | |
8117 | vcpu->arch.pv.pv_unhalted = false; | |
8118 | vcpu->arch.mp_state = | |
8119 | KVM_MP_STATE_RUNNABLE; | |
b2869f28 | 8120 | /* fall through */ |
362c698f PB |
8121 | case KVM_MP_STATE_RUNNABLE: |
8122 | vcpu->arch.apf.halted = false; | |
8123 | break; | |
8124 | case KVM_MP_STATE_INIT_RECEIVED: | |
8125 | break; | |
8126 | default: | |
8127 | return -EINTR; | |
8128 | break; | |
8129 | } | |
8130 | return 1; | |
8131 | } | |
09cec754 | 8132 | |
5d9bc648 PB |
8133 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
8134 | { | |
0ad3bed6 PB |
8135 | if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) |
8136 | kvm_x86_ops->check_nested_events(vcpu, false); | |
8137 | ||
5d9bc648 PB |
8138 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8139 | !vcpu->arch.apf.halted); | |
8140 | } | |
8141 | ||
362c698f | 8142 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
8143 | { |
8144 | int r; | |
f656ce01 | 8145 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 8146 | |
f656ce01 | 8147 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 8148 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 8149 | |
362c698f | 8150 | for (;;) { |
58f800d5 | 8151 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 8152 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 8153 | } else { |
362c698f | 8154 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
8155 | } |
8156 | ||
09cec754 GN |
8157 | if (r <= 0) |
8158 | break; | |
8159 | ||
72875d8a | 8160 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
8161 | if (kvm_cpu_has_pending_timer(vcpu)) |
8162 | kvm_inject_pending_timer_irqs(vcpu); | |
8163 | ||
782d422b MG |
8164 | if (dm_request_for_irq_injection(vcpu) && |
8165 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
8166 | r = 0; |
8167 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 8168 | ++vcpu->stat.request_irq_exits; |
362c698f | 8169 | break; |
09cec754 | 8170 | } |
af585b92 GN |
8171 | |
8172 | kvm_check_async_pf_completion(vcpu); | |
8173 | ||
09cec754 GN |
8174 | if (signal_pending(current)) { |
8175 | r = -EINTR; | |
851ba692 | 8176 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 8177 | ++vcpu->stat.signal_exits; |
362c698f | 8178 | break; |
09cec754 GN |
8179 | } |
8180 | if (need_resched()) { | |
f656ce01 | 8181 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 8182 | cond_resched(); |
f656ce01 | 8183 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 8184 | } |
b6c7a5dc HB |
8185 | } |
8186 | ||
f656ce01 | 8187 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
8188 | |
8189 | return r; | |
8190 | } | |
8191 | ||
716d51ab GN |
8192 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
8193 | { | |
8194 | int r; | |
8195 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0ce97a2b | 8196 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab GN |
8197 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8198 | if (r != EMULATE_DONE) | |
8199 | return 0; | |
8200 | return 1; | |
8201 | } | |
8202 | ||
8203 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
8204 | { | |
8205 | BUG_ON(!vcpu->arch.pio.count); | |
8206 | ||
8207 | return complete_emulated_io(vcpu); | |
8208 | } | |
8209 | ||
f78146b0 AK |
8210 | /* |
8211 | * Implements the following, as a state machine: | |
8212 | * | |
8213 | * read: | |
8214 | * for each fragment | |
87da7e66 XG |
8215 | * for each mmio piece in the fragment |
8216 | * write gpa, len | |
8217 | * exit | |
8218 | * copy data | |
f78146b0 AK |
8219 | * execute insn |
8220 | * | |
8221 | * write: | |
8222 | * for each fragment | |
87da7e66 XG |
8223 | * for each mmio piece in the fragment |
8224 | * write gpa, len | |
8225 | * copy data | |
8226 | * exit | |
f78146b0 | 8227 | */ |
716d51ab | 8228 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
8229 | { |
8230 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 8231 | struct kvm_mmio_fragment *frag; |
87da7e66 | 8232 | unsigned len; |
5287f194 | 8233 | |
716d51ab | 8234 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 8235 | |
716d51ab | 8236 | /* Complete previous fragment */ |
87da7e66 XG |
8237 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
8238 | len = min(8u, frag->len); | |
716d51ab | 8239 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
8240 | memcpy(frag->data, run->mmio.data, len); |
8241 | ||
8242 | if (frag->len <= 8) { | |
8243 | /* Switch to the next fragment. */ | |
8244 | frag++; | |
8245 | vcpu->mmio_cur_fragment++; | |
8246 | } else { | |
8247 | /* Go forward to the next mmio piece. */ | |
8248 | frag->data += len; | |
8249 | frag->gpa += len; | |
8250 | frag->len -= len; | |
8251 | } | |
8252 | ||
a08d3b3b | 8253 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 8254 | vcpu->mmio_needed = 0; |
0912c977 PB |
8255 | |
8256 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 8257 | if (vcpu->mmio_is_write) |
716d51ab GN |
8258 | return 1; |
8259 | vcpu->mmio_read_completed = 1; | |
8260 | return complete_emulated_io(vcpu); | |
8261 | } | |
87da7e66 | 8262 | |
716d51ab GN |
8263 | run->exit_reason = KVM_EXIT_MMIO; |
8264 | run->mmio.phys_addr = frag->gpa; | |
8265 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
8266 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
8267 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
8268 | run->mmio.is_write = vcpu->mmio_is_write; |
8269 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
8270 | return 0; | |
5287f194 AK |
8271 | } |
8272 | ||
822f312d SAS |
8273 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
8274 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
8275 | { | |
5f409e20 RR |
8276 | fpregs_lock(); |
8277 | ||
d9a710e5 | 8278 | copy_fpregs_to_fpstate(vcpu->arch.user_fpu); |
822f312d | 8279 | /* PKRU is separately restored in kvm_x86_ops->run. */ |
b666a4b6 | 8280 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
822f312d | 8281 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
8282 | |
8283 | fpregs_mark_activate(); | |
8284 | fpregs_unlock(); | |
8285 | ||
822f312d SAS |
8286 | trace_kvm_fpu(1); |
8287 | } | |
8288 | ||
8289 | /* When vcpu_run ends, restore user space FPU context. */ | |
8290 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
8291 | { | |
5f409e20 RR |
8292 | fpregs_lock(); |
8293 | ||
b666a4b6 | 8294 | copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); |
d9a710e5 | 8295 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
8296 | |
8297 | fpregs_mark_activate(); | |
8298 | fpregs_unlock(); | |
8299 | ||
822f312d SAS |
8300 | ++vcpu->stat.fpu_reload; |
8301 | trace_kvm_fpu(0); | |
8302 | } | |
8303 | ||
b6c7a5dc HB |
8304 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
8305 | { | |
8306 | int r; | |
b6c7a5dc | 8307 | |
accb757d | 8308 | vcpu_load(vcpu); |
20b7035c | 8309 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
8310 | kvm_load_guest_fpu(vcpu); |
8311 | ||
a4535290 | 8312 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
8313 | if (kvm_run->immediate_exit) { |
8314 | r = -EINTR; | |
8315 | goto out; | |
8316 | } | |
b6c7a5dc | 8317 | kvm_vcpu_block(vcpu); |
66450a21 | 8318 | kvm_apic_accept_events(vcpu); |
72875d8a | 8319 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 8320 | r = -EAGAIN; |
a0595000 JS |
8321 | if (signal_pending(current)) { |
8322 | r = -EINTR; | |
8323 | vcpu->run->exit_reason = KVM_EXIT_INTR; | |
8324 | ++vcpu->stat.signal_exits; | |
8325 | } | |
ac9f6dc0 | 8326 | goto out; |
b6c7a5dc HB |
8327 | } |
8328 | ||
01643c51 KH |
8329 | if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
8330 | r = -EINVAL; | |
8331 | goto out; | |
8332 | } | |
8333 | ||
8334 | if (vcpu->run->kvm_dirty_regs) { | |
8335 | r = sync_regs(vcpu); | |
8336 | if (r != 0) | |
8337 | goto out; | |
8338 | } | |
8339 | ||
b6c7a5dc | 8340 | /* re-sync apic's tpr */ |
35754c98 | 8341 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
8342 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
8343 | r = -EINVAL; | |
8344 | goto out; | |
8345 | } | |
8346 | } | |
b6c7a5dc | 8347 | |
716d51ab GN |
8348 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
8349 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
8350 | vcpu->arch.complete_userspace_io = NULL; | |
8351 | r = cui(vcpu); | |
8352 | if (r <= 0) | |
5663d8f9 | 8353 | goto out; |
716d51ab GN |
8354 | } else |
8355 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 8356 | |
460df4c1 PB |
8357 | if (kvm_run->immediate_exit) |
8358 | r = -EINTR; | |
8359 | else | |
8360 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
8361 | |
8362 | out: | |
5663d8f9 | 8363 | kvm_put_guest_fpu(vcpu); |
01643c51 KH |
8364 | if (vcpu->run->kvm_valid_regs) |
8365 | store_regs(vcpu); | |
f1d86e46 | 8366 | post_kvm_run_save(vcpu); |
20b7035c | 8367 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 8368 | |
accb757d | 8369 | vcpu_put(vcpu); |
b6c7a5dc HB |
8370 | return r; |
8371 | } | |
8372 | ||
01643c51 | 8373 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8374 | { |
7ae441ea GN |
8375 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
8376 | /* | |
8377 | * We are here if userspace calls get_regs() in the middle of | |
8378 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 8379 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
8380 | * that usually, but some bad designed PV devices (vmware |
8381 | * backdoor interface) need this to work | |
8382 | */ | |
dd856efa | 8383 | emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); |
7ae441ea GN |
8384 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
8385 | } | |
de3cd117 SC |
8386 | regs->rax = kvm_rax_read(vcpu); |
8387 | regs->rbx = kvm_rbx_read(vcpu); | |
8388 | regs->rcx = kvm_rcx_read(vcpu); | |
8389 | regs->rdx = kvm_rdx_read(vcpu); | |
8390 | regs->rsi = kvm_rsi_read(vcpu); | |
8391 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 8392 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 8393 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 8394 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8395 | regs->r8 = kvm_r8_read(vcpu); |
8396 | regs->r9 = kvm_r9_read(vcpu); | |
8397 | regs->r10 = kvm_r10_read(vcpu); | |
8398 | regs->r11 = kvm_r11_read(vcpu); | |
8399 | regs->r12 = kvm_r12_read(vcpu); | |
8400 | regs->r13 = kvm_r13_read(vcpu); | |
8401 | regs->r14 = kvm_r14_read(vcpu); | |
8402 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
8403 | #endif |
8404 | ||
5fdbf976 | 8405 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 8406 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 8407 | } |
b6c7a5dc | 8408 | |
01643c51 KH |
8409 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8410 | { | |
8411 | vcpu_load(vcpu); | |
8412 | __get_regs(vcpu, regs); | |
1fc9b76b | 8413 | vcpu_put(vcpu); |
b6c7a5dc HB |
8414 | return 0; |
8415 | } | |
8416 | ||
01643c51 | 8417 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8418 | { |
7ae441ea GN |
8419 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
8420 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
8421 | ||
de3cd117 SC |
8422 | kvm_rax_write(vcpu, regs->rax); |
8423 | kvm_rbx_write(vcpu, regs->rbx); | |
8424 | kvm_rcx_write(vcpu, regs->rcx); | |
8425 | kvm_rdx_write(vcpu, regs->rdx); | |
8426 | kvm_rsi_write(vcpu, regs->rsi); | |
8427 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 8428 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 8429 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 8430 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8431 | kvm_r8_write(vcpu, regs->r8); |
8432 | kvm_r9_write(vcpu, regs->r9); | |
8433 | kvm_r10_write(vcpu, regs->r10); | |
8434 | kvm_r11_write(vcpu, regs->r11); | |
8435 | kvm_r12_write(vcpu, regs->r12); | |
8436 | kvm_r13_write(vcpu, regs->r13); | |
8437 | kvm_r14_write(vcpu, regs->r14); | |
8438 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
8439 | #endif |
8440 | ||
5fdbf976 | 8441 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 8442 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 8443 | |
b4f14abd JK |
8444 | vcpu->arch.exception.pending = false; |
8445 | ||
3842d135 | 8446 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 8447 | } |
3842d135 | 8448 | |
01643c51 KH |
8449 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8450 | { | |
8451 | vcpu_load(vcpu); | |
8452 | __set_regs(vcpu, regs); | |
875656fe | 8453 | vcpu_put(vcpu); |
b6c7a5dc HB |
8454 | return 0; |
8455 | } | |
8456 | ||
b6c7a5dc HB |
8457 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
8458 | { | |
8459 | struct kvm_segment cs; | |
8460 | ||
3e6e0aab | 8461 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
8462 | *db = cs.db; |
8463 | *l = cs.l; | |
8464 | } | |
8465 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
8466 | ||
01643c51 | 8467 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8468 | { |
89a27f4d | 8469 | struct desc_ptr dt; |
b6c7a5dc | 8470 | |
3e6e0aab GT |
8471 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
8472 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
8473 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
8474 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
8475 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
8476 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 8477 | |
3e6e0aab GT |
8478 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
8479 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
8480 | |
8481 | kvm_x86_ops->get_idt(vcpu, &dt); | |
89a27f4d GN |
8482 | sregs->idt.limit = dt.size; |
8483 | sregs->idt.base = dt.address; | |
b6c7a5dc | 8484 | kvm_x86_ops->get_gdt(vcpu, &dt); |
89a27f4d GN |
8485 | sregs->gdt.limit = dt.size; |
8486 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 8487 | |
4d4ec087 | 8488 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 8489 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 8490 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 8491 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 8492 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 8493 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
8494 | sregs->apic_base = kvm_get_apic_base(vcpu); |
8495 | ||
0e96f31e | 8496 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 8497 | |
04140b41 | 8498 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
8499 | set_bit(vcpu->arch.interrupt.nr, |
8500 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 8501 | } |
16d7a191 | 8502 | |
01643c51 KH |
8503 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
8504 | struct kvm_sregs *sregs) | |
8505 | { | |
8506 | vcpu_load(vcpu); | |
8507 | __get_sregs(vcpu, sregs); | |
bcdec41c | 8508 | vcpu_put(vcpu); |
b6c7a5dc HB |
8509 | return 0; |
8510 | } | |
8511 | ||
62d9f0db MT |
8512 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
8513 | struct kvm_mp_state *mp_state) | |
8514 | { | |
fd232561 CD |
8515 | vcpu_load(vcpu); |
8516 | ||
66450a21 | 8517 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
8518 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
8519 | vcpu->arch.pv.pv_unhalted) | |
8520 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
8521 | else | |
8522 | mp_state->mp_state = vcpu->arch.mp_state; | |
8523 | ||
fd232561 | 8524 | vcpu_put(vcpu); |
62d9f0db MT |
8525 | return 0; |
8526 | } | |
8527 | ||
8528 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
8529 | struct kvm_mp_state *mp_state) | |
8530 | { | |
e83dff5e CD |
8531 | int ret = -EINVAL; |
8532 | ||
8533 | vcpu_load(vcpu); | |
8534 | ||
bce87cce | 8535 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 8536 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 8537 | goto out; |
66450a21 | 8538 | |
28bf2888 DH |
8539 | /* INITs are latched while in SMM */ |
8540 | if ((is_smm(vcpu) || vcpu->arch.smi_pending) && | |
8541 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || | |
8542 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 8543 | goto out; |
28bf2888 | 8544 | |
66450a21 JK |
8545 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
8546 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
8547 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
8548 | } else | |
8549 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 8550 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
8551 | |
8552 | ret = 0; | |
8553 | out: | |
8554 | vcpu_put(vcpu); | |
8555 | return ret; | |
62d9f0db MT |
8556 | } |
8557 | ||
7f3d35fd KW |
8558 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
8559 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 8560 | { |
9d74191a | 8561 | struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; |
8ec4722d | 8562 | int ret; |
e01c2426 | 8563 | |
8ec4722d | 8564 | init_emulate_ctxt(vcpu); |
c697518a | 8565 | |
7f3d35fd | 8566 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 8567 | has_error_code, error_code); |
c697518a | 8568 | |
c697518a | 8569 | if (ret) |
19d04437 | 8570 | return EMULATE_FAIL; |
37817f29 | 8571 | |
9d74191a TY |
8572 | kvm_rip_write(vcpu, ctxt->eip); |
8573 | kvm_set_rflags(vcpu, ctxt->eflags); | |
3842d135 | 8574 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
19d04437 | 8575 | return EMULATE_DONE; |
37817f29 IE |
8576 | } |
8577 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
8578 | ||
3140c156 | 8579 | static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 8580 | { |
74fec5b9 TL |
8581 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && |
8582 | (sregs->cr4 & X86_CR4_OSXSAVE)) | |
8583 | return -EINVAL; | |
8584 | ||
37b95951 | 8585 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
8586 | /* |
8587 | * When EFER.LME and CR0.PG are set, the processor is in | |
8588 | * 64-bit mode (though maybe in a 32-bit code segment). | |
8589 | * CR4.PAE and EFER.LMA must be set. | |
8590 | */ | |
37b95951 | 8591 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
8592 | || !(sregs->efer & EFER_LMA)) |
8593 | return -EINVAL; | |
8594 | } else { | |
8595 | /* | |
8596 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
8597 | * segment cannot be 64-bit. | |
8598 | */ | |
8599 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
8600 | return -EINVAL; | |
8601 | } | |
8602 | ||
8603 | return 0; | |
8604 | } | |
8605 | ||
01643c51 | 8606 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 8607 | { |
58cb628d | 8608 | struct msr_data apic_base_msr; |
b6c7a5dc | 8609 | int mmu_reset_needed = 0; |
c4d21882 | 8610 | int cpuid_update_needed = 0; |
63f42e02 | 8611 | int pending_vec, max_bits, idx; |
89a27f4d | 8612 | struct desc_ptr dt; |
b4ef9d4e CD |
8613 | int ret = -EINVAL; |
8614 | ||
f2981033 | 8615 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 8616 | goto out; |
f2981033 | 8617 | |
d3802286 JM |
8618 | apic_base_msr.data = sregs->apic_base; |
8619 | apic_base_msr.host_initiated = true; | |
8620 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 8621 | goto out; |
6d1068b3 | 8622 | |
89a27f4d GN |
8623 | dt.size = sregs->idt.limit; |
8624 | dt.address = sregs->idt.base; | |
b6c7a5dc | 8625 | kvm_x86_ops->set_idt(vcpu, &dt); |
89a27f4d GN |
8626 | dt.size = sregs->gdt.limit; |
8627 | dt.address = sregs->gdt.base; | |
b6c7a5dc HB |
8628 | kvm_x86_ops->set_gdt(vcpu, &dt); |
8629 | ||
ad312c7c | 8630 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 8631 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 8632 | vcpu->arch.cr3 = sregs->cr3; |
aff48baa | 8633 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); |
b6c7a5dc | 8634 | |
2d3ad1f4 | 8635 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 8636 | |
f6801dff | 8637 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b6c7a5dc | 8638 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc | 8639 | |
4d4ec087 | 8640 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b6c7a5dc | 8641 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 8642 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 8643 | |
fc78f519 | 8644 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
c4d21882 WH |
8645 | cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & |
8646 | (X86_CR4_OSXSAVE | X86_CR4_PKE)); | |
b6c7a5dc | 8647 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
c4d21882 | 8648 | if (cpuid_update_needed) |
00b27a3e | 8649 | kvm_update_cpuid(vcpu); |
63f42e02 XG |
8650 | |
8651 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 8652 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 8653 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
8654 | mmu_reset_needed = 1; |
8655 | } | |
63f42e02 | 8656 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
8657 | |
8658 | if (mmu_reset_needed) | |
8659 | kvm_mmu_reset_context(vcpu); | |
8660 | ||
a50abc3b | 8661 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
8662 | pending_vec = find_first_bit( |
8663 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
8664 | if (pending_vec < max_bits) { | |
66fd3f7f | 8665 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 8666 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
8667 | } |
8668 | ||
3e6e0aab GT |
8669 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
8670 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
8671 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
8672 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
8673 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
8674 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 8675 | |
3e6e0aab GT |
8676 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
8677 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 8678 | |
5f0269f5 ME |
8679 | update_cr8_intercept(vcpu); |
8680 | ||
9c3e4aab | 8681 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 8682 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 8683 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 8684 | !is_protmode(vcpu)) |
9c3e4aab MT |
8685 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
8686 | ||
3842d135 AK |
8687 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
8688 | ||
b4ef9d4e CD |
8689 | ret = 0; |
8690 | out: | |
01643c51 KH |
8691 | return ret; |
8692 | } | |
8693 | ||
8694 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
8695 | struct kvm_sregs *sregs) | |
8696 | { | |
8697 | int ret; | |
8698 | ||
8699 | vcpu_load(vcpu); | |
8700 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
8701 | vcpu_put(vcpu); |
8702 | return ret; | |
b6c7a5dc HB |
8703 | } |
8704 | ||
d0bfb940 JK |
8705 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
8706 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 8707 | { |
355be0b9 | 8708 | unsigned long rflags; |
ae675ef0 | 8709 | int i, r; |
b6c7a5dc | 8710 | |
66b56562 CD |
8711 | vcpu_load(vcpu); |
8712 | ||
4f926bf2 JK |
8713 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
8714 | r = -EBUSY; | |
8715 | if (vcpu->arch.exception.pending) | |
2122ff5e | 8716 | goto out; |
4f926bf2 JK |
8717 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
8718 | kvm_queue_exception(vcpu, DB_VECTOR); | |
8719 | else | |
8720 | kvm_queue_exception(vcpu, BP_VECTOR); | |
8721 | } | |
8722 | ||
91586a3b JK |
8723 | /* |
8724 | * Read rflags as long as potentially injected trace flags are still | |
8725 | * filtered out. | |
8726 | */ | |
8727 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
8728 | |
8729 | vcpu->guest_debug = dbg->control; | |
8730 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
8731 | vcpu->guest_debug = 0; | |
8732 | ||
8733 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
8734 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
8735 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 8736 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
8737 | } else { |
8738 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
8739 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 8740 | } |
c8639010 | 8741 | kvm_update_dr7(vcpu); |
ae675ef0 | 8742 | |
f92653ee JK |
8743 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
8744 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
8745 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 8746 | |
91586a3b JK |
8747 | /* |
8748 | * Trigger an rflags update that will inject or remove the trace | |
8749 | * flags. | |
8750 | */ | |
8751 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 8752 | |
a96036b8 | 8753 | kvm_x86_ops->update_bp_intercept(vcpu); |
b6c7a5dc | 8754 | |
4f926bf2 | 8755 | r = 0; |
d0bfb940 | 8756 | |
2122ff5e | 8757 | out: |
66b56562 | 8758 | vcpu_put(vcpu); |
b6c7a5dc HB |
8759 | return r; |
8760 | } | |
8761 | ||
8b006791 ZX |
8762 | /* |
8763 | * Translate a guest virtual address to a guest physical address. | |
8764 | */ | |
8765 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
8766 | struct kvm_translation *tr) | |
8767 | { | |
8768 | unsigned long vaddr = tr->linear_address; | |
8769 | gpa_t gpa; | |
f656ce01 | 8770 | int idx; |
8b006791 | 8771 | |
1da5b61d CD |
8772 | vcpu_load(vcpu); |
8773 | ||
f656ce01 | 8774 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 8775 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 8776 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
8777 | tr->physical_address = gpa; |
8778 | tr->valid = gpa != UNMAPPED_GVA; | |
8779 | tr->writeable = 1; | |
8780 | tr->usermode = 0; | |
8b006791 | 8781 | |
1da5b61d | 8782 | vcpu_put(vcpu); |
8b006791 ZX |
8783 | return 0; |
8784 | } | |
8785 | ||
d0752060 HB |
8786 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
8787 | { | |
1393123e | 8788 | struct fxregs_state *fxsave; |
d0752060 | 8789 | |
1393123e | 8790 | vcpu_load(vcpu); |
d0752060 | 8791 | |
b666a4b6 | 8792 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
8793 | memcpy(fpu->fpr, fxsave->st_space, 128); |
8794 | fpu->fcw = fxsave->cwd; | |
8795 | fpu->fsw = fxsave->swd; | |
8796 | fpu->ftwx = fxsave->twd; | |
8797 | fpu->last_opcode = fxsave->fop; | |
8798 | fpu->last_ip = fxsave->rip; | |
8799 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 8800 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 8801 | |
1393123e | 8802 | vcpu_put(vcpu); |
d0752060 HB |
8803 | return 0; |
8804 | } | |
8805 | ||
8806 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
8807 | { | |
6a96bc7f CD |
8808 | struct fxregs_state *fxsave; |
8809 | ||
8810 | vcpu_load(vcpu); | |
8811 | ||
b666a4b6 | 8812 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 8813 | |
d0752060 HB |
8814 | memcpy(fxsave->st_space, fpu->fpr, 128); |
8815 | fxsave->cwd = fpu->fcw; | |
8816 | fxsave->swd = fpu->fsw; | |
8817 | fxsave->twd = fpu->ftwx; | |
8818 | fxsave->fop = fpu->last_opcode; | |
8819 | fxsave->rip = fpu->last_ip; | |
8820 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 8821 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 8822 | |
6a96bc7f | 8823 | vcpu_put(vcpu); |
d0752060 HB |
8824 | return 0; |
8825 | } | |
8826 | ||
01643c51 KH |
8827 | static void store_regs(struct kvm_vcpu *vcpu) |
8828 | { | |
8829 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
8830 | ||
8831 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
8832 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
8833 | ||
8834 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
8835 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
8836 | ||
8837 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
8838 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
8839 | vcpu, &vcpu->run->s.regs.events); | |
8840 | } | |
8841 | ||
8842 | static int sync_regs(struct kvm_vcpu *vcpu) | |
8843 | { | |
8844 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
8845 | return -EINVAL; | |
8846 | ||
8847 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
8848 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
8849 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
8850 | } | |
8851 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
8852 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
8853 | return -EINVAL; | |
8854 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
8855 | } | |
8856 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
8857 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
8858 | vcpu, &vcpu->run->s.regs.events)) | |
8859 | return -EINVAL; | |
8860 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
8861 | } | |
8862 | ||
8863 | return 0; | |
8864 | } | |
8865 | ||
0ee6a517 | 8866 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 8867 | { |
b666a4b6 | 8868 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 8869 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 8870 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 8871 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 8872 | |
2acf923e DC |
8873 | /* |
8874 | * Ensure guest xcr0 is valid for loading | |
8875 | */ | |
d91cab78 | 8876 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 8877 | |
ad312c7c | 8878 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 8879 | } |
d0752060 | 8880 | |
e9b11c17 ZX |
8881 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) |
8882 | { | |
bd768e14 IY |
8883 | void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; |
8884 | ||
12f9a48f | 8885 | kvmclock_reset(vcpu); |
7f1ea208 | 8886 | |
e9b11c17 | 8887 | kvm_x86_ops->vcpu_free(vcpu); |
bd768e14 | 8888 | free_cpumask_var(wbinvd_dirty_mask); |
e9b11c17 ZX |
8889 | } |
8890 | ||
8891 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
8892 | unsigned int id) | |
8893 | { | |
c447e76b LL |
8894 | struct kvm_vcpu *vcpu; |
8895 | ||
b0c39dc6 | 8896 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
6755bae8 ZA |
8897 | printk_once(KERN_WARNING |
8898 | "kvm: SMP vm created on host with unstable TSC; " | |
8899 | "guest TSC will not be reliable\n"); | |
c447e76b LL |
8900 | |
8901 | vcpu = kvm_x86_ops->vcpu_create(kvm, id); | |
8902 | ||
c447e76b | 8903 | return vcpu; |
26e5215f | 8904 | } |
e9b11c17 | 8905 | |
26e5215f AK |
8906 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
8907 | { | |
0cf9135b | 8908 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 8909 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 8910 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 8911 | vcpu_load(vcpu); |
d28bc9dd | 8912 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 8913 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 8914 | vcpu_put(vcpu); |
ec7660cc | 8915 | return 0; |
e9b11c17 ZX |
8916 | } |
8917 | ||
31928aa5 | 8918 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 8919 | { |
8fe8ab46 | 8920 | struct msr_data msr; |
332967a3 | 8921 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 8922 | |
d3457c87 RK |
8923 | kvm_hv_vcpu_postcreate(vcpu); |
8924 | ||
ec7660cc | 8925 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 8926 | return; |
ec7660cc | 8927 | vcpu_load(vcpu); |
8fe8ab46 WA |
8928 | msr.data = 0x0; |
8929 | msr.index = MSR_IA32_TSC; | |
8930 | msr.host_initiated = true; | |
8931 | kvm_write_tsc(vcpu, &msr); | |
42897d86 | 8932 | vcpu_put(vcpu); |
2d5ba19b MT |
8933 | |
8934 | /* poll control enabled by default */ | |
8935 | vcpu->arch.msr_kvm_poll_control = 1; | |
8936 | ||
ec7660cc | 8937 | mutex_unlock(&vcpu->mutex); |
42897d86 | 8938 | |
630994b3 MT |
8939 | if (!kvmclock_periodic_sync) |
8940 | return; | |
8941 | ||
332967a3 AJ |
8942 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, |
8943 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
8944 | } |
8945 | ||
d40ccc62 | 8946 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 8947 | { |
344d9588 GN |
8948 | vcpu->arch.apf.msr_val = 0; |
8949 | ||
ec7660cc | 8950 | vcpu_load(vcpu); |
e9b11c17 ZX |
8951 | kvm_mmu_unload(vcpu); |
8952 | vcpu_put(vcpu); | |
8953 | ||
8954 | kvm_x86_ops->vcpu_free(vcpu); | |
8955 | } | |
8956 | ||
d28bc9dd | 8957 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 8958 | { |
b7e31be3 RK |
8959 | kvm_lapic_reset(vcpu, init_event); |
8960 | ||
e69fab5d PB |
8961 | vcpu->arch.hflags = 0; |
8962 | ||
c43203ca | 8963 | vcpu->arch.smi_pending = 0; |
52797bf9 | 8964 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
8965 | atomic_set(&vcpu->arch.nmi_queued, 0); |
8966 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 8967 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
8968 | kvm_clear_interrupt_queue(vcpu); |
8969 | kvm_clear_exception_queue(vcpu); | |
664f8e26 | 8970 | vcpu->arch.exception.pending = false; |
448fa4a9 | 8971 | |
42dbaa5a | 8972 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 8973 | kvm_update_dr0123(vcpu); |
6f43ed01 | 8974 | vcpu->arch.dr6 = DR6_INIT; |
73aaf249 | 8975 | kvm_update_dr6(vcpu); |
42dbaa5a | 8976 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 8977 | kvm_update_dr7(vcpu); |
42dbaa5a | 8978 | |
1119022c NA |
8979 | vcpu->arch.cr2 = 0; |
8980 | ||
3842d135 | 8981 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
344d9588 | 8982 | vcpu->arch.apf.msr_val = 0; |
c9aaa895 | 8983 | vcpu->arch.st.msr_val = 0; |
3842d135 | 8984 | |
12f9a48f GC |
8985 | kvmclock_reset(vcpu); |
8986 | ||
af585b92 GN |
8987 | kvm_clear_async_pf_completion_queue(vcpu); |
8988 | kvm_async_pf_hash_reset(vcpu); | |
8989 | vcpu->arch.apf.halted = false; | |
3842d135 | 8990 | |
a554d207 WL |
8991 | if (kvm_mpx_supported()) { |
8992 | void *mpx_state_buffer; | |
8993 | ||
8994 | /* | |
8995 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
8996 | * called with loaded FPU and does not let userspace fix the state. | |
8997 | */ | |
f775b13e RR |
8998 | if (init_event) |
8999 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 9000 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9001 | XFEATURE_BNDREGS); |
a554d207 WL |
9002 | if (mpx_state_buffer) |
9003 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 9004 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9005 | XFEATURE_BNDCSR); |
a554d207 WL |
9006 | if (mpx_state_buffer) |
9007 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
9008 | if (init_event) |
9009 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
9010 | } |
9011 | ||
64d60670 | 9012 | if (!init_event) { |
d28bc9dd | 9013 | kvm_pmu_reset(vcpu); |
64d60670 | 9014 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 9015 | |
db2336a8 | 9016 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
9017 | |
9018 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 9019 | } |
f5132b01 | 9020 | |
66f7b72e JS |
9021 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
9022 | vcpu->arch.regs_avail = ~0; | |
9023 | vcpu->arch.regs_dirty = ~0; | |
9024 | ||
a554d207 WL |
9025 | vcpu->arch.ia32_xss = 0; |
9026 | ||
d28bc9dd | 9027 | kvm_x86_ops->vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
9028 | } |
9029 | ||
2b4a273b | 9030 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
9031 | { |
9032 | struct kvm_segment cs; | |
9033 | ||
9034 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
9035 | cs.selector = vector << 8; | |
9036 | cs.base = vector << 12; | |
9037 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9038 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
9039 | } |
9040 | ||
13a34e06 | 9041 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 9042 | { |
ca84d1a2 ZA |
9043 | struct kvm *kvm; |
9044 | struct kvm_vcpu *vcpu; | |
9045 | int i; | |
0dd6a6ed ZA |
9046 | int ret; |
9047 | u64 local_tsc; | |
9048 | u64 max_tsc = 0; | |
9049 | bool stable, backwards_tsc = false; | |
18863bdd AK |
9050 | |
9051 | kvm_shared_msr_cpu_online(); | |
13a34e06 | 9052 | ret = kvm_x86_ops->hardware_enable(); |
0dd6a6ed ZA |
9053 | if (ret != 0) |
9054 | return ret; | |
9055 | ||
4ea1636b | 9056 | local_tsc = rdtsc(); |
b0c39dc6 | 9057 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
9058 | list_for_each_entry(kvm, &vm_list, vm_list) { |
9059 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
9060 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 9061 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9062 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
9063 | backwards_tsc = true; | |
9064 | if (vcpu->arch.last_host_tsc > max_tsc) | |
9065 | max_tsc = vcpu->arch.last_host_tsc; | |
9066 | } | |
9067 | } | |
9068 | } | |
9069 | ||
9070 | /* | |
9071 | * Sometimes, even reliable TSCs go backwards. This happens on | |
9072 | * platforms that reset TSC during suspend or hibernate actions, but | |
9073 | * maintain synchronization. We must compensate. Fortunately, we can | |
9074 | * detect that condition here, which happens early in CPU bringup, | |
9075 | * before any KVM threads can be running. Unfortunately, we can't | |
9076 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
9077 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 9078 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
9079 | * variables that haven't been updated yet. |
9080 | * | |
9081 | * So we simply find the maximum observed TSC above, then record the | |
9082 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
9083 | * the adjustment will be applied. Note that we accumulate | |
9084 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
9085 | * gets a chance to run again. In the event that no KVM threads get a | |
9086 | * chance to run, we will miss the entire elapsed period, as we'll have | |
9087 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
9088 | * loose cycle time. This isn't too big a deal, since the loss will be | |
9089 | * uniform across all VCPUs (not to mention the scenario is extremely | |
9090 | * unlikely). It is possible that a second hibernate recovery happens | |
9091 | * much faster than a first, causing the observed TSC here to be | |
9092 | * smaller; this would require additional padding adjustment, which is | |
9093 | * why we set last_host_tsc to the local tsc observed here. | |
9094 | * | |
9095 | * N.B. - this code below runs only on platforms with reliable TSC, | |
9096 | * as that is the only way backwards_tsc is set above. Also note | |
9097 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
9098 | * have the same delta_cyc adjustment applied if backwards_tsc | |
9099 | * is detected. Note further, this adjustment is only done once, | |
9100 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
9101 | * called multiple times (one for each physical CPU bringup). | |
9102 | * | |
4a969980 | 9103 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
9104 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
9105 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
9106 | * guarantee that they stay in perfect synchronization. | |
9107 | */ | |
9108 | if (backwards_tsc) { | |
9109 | u64 delta_cyc = max_tsc - local_tsc; | |
9110 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 9111 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
9112 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9113 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
9114 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 9115 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9116 | } |
9117 | ||
9118 | /* | |
9119 | * We have to disable TSC offset matching.. if you were | |
9120 | * booting a VM while issuing an S4 host suspend.... | |
9121 | * you may have some problem. Solving this issue is | |
9122 | * left as an exercise to the reader. | |
9123 | */ | |
9124 | kvm->arch.last_tsc_nsec = 0; | |
9125 | kvm->arch.last_tsc_write = 0; | |
9126 | } | |
9127 | ||
9128 | } | |
9129 | return 0; | |
e9b11c17 ZX |
9130 | } |
9131 | ||
13a34e06 | 9132 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 9133 | { |
13a34e06 RK |
9134 | kvm_x86_ops->hardware_disable(); |
9135 | drop_user_return_notifiers(); | |
e9b11c17 ZX |
9136 | } |
9137 | ||
9138 | int kvm_arch_hardware_setup(void) | |
9139 | { | |
9e9c3fe4 NA |
9140 | int r; |
9141 | ||
9142 | r = kvm_x86_ops->hardware_setup(); | |
9143 | if (r != 0) | |
9144 | return r; | |
9145 | ||
35181e86 HZ |
9146 | if (kvm_has_tsc_control) { |
9147 | /* | |
9148 | * Make sure the user can only configure tsc_khz values that | |
9149 | * fit into a signed integer. | |
273ba457 | 9150 | * A min value is not calculated because it will always |
35181e86 HZ |
9151 | * be 1 on all machines. |
9152 | */ | |
9153 | u64 max = min(0x7fffffffULL, | |
9154 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
9155 | kvm_max_guest_tsc_khz = max; | |
9156 | ||
ad721883 | 9157 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 9158 | } |
ad721883 | 9159 | |
9e9c3fe4 NA |
9160 | kvm_init_msr_list(); |
9161 | return 0; | |
e9b11c17 ZX |
9162 | } |
9163 | ||
9164 | void kvm_arch_hardware_unsetup(void) | |
9165 | { | |
9166 | kvm_x86_ops->hardware_unsetup(); | |
9167 | } | |
9168 | ||
f257d6dc | 9169 | int kvm_arch_check_processor_compat(void) |
e9b11c17 | 9170 | { |
f257d6dc | 9171 | return kvm_x86_ops->check_processor_compatibility(); |
d71ba788 PB |
9172 | } |
9173 | ||
9174 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
9175 | { | |
9176 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
9177 | } | |
9178 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
9179 | ||
9180 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
9181 | { | |
9182 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
9183 | } |
9184 | ||
54e9818f | 9185 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 9186 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 9187 | |
e9b11c17 ZX |
9188 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) |
9189 | { | |
9190 | struct page *page; | |
e9b11c17 ZX |
9191 | int r; |
9192 | ||
9aabc88f | 9193 | vcpu->arch.emulate_ctxt.ops = &emulate_ops; |
26de7988 | 9194 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
a4535290 | 9195 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 9196 | else |
a4535290 | 9197 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
9198 | |
9199 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9200 | if (!page) { | |
9201 | r = -ENOMEM; | |
9202 | goto fail; | |
9203 | } | |
ad312c7c | 9204 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 | 9205 | |
cc578287 | 9206 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c285545f | 9207 | |
e9b11c17 ZX |
9208 | r = kvm_mmu_create(vcpu); |
9209 | if (r < 0) | |
9210 | goto fail_free_pio_data; | |
9211 | ||
26de7988 | 9212 | if (irqchip_in_kernel(vcpu->kvm)) { |
f7589cca | 9213 | vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); |
39497d76 | 9214 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
e9b11c17 ZX |
9215 | if (r < 0) |
9216 | goto fail_mmu_destroy; | |
54e9818f GN |
9217 | } else |
9218 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
e9b11c17 | 9219 | |
890ca9ae | 9220 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
254272ce | 9221 | GFP_KERNEL_ACCOUNT); |
890ca9ae HY |
9222 | if (!vcpu->arch.mce_banks) { |
9223 | r = -ENOMEM; | |
443c39bc | 9224 | goto fail_free_lapic; |
890ca9ae HY |
9225 | } |
9226 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9227 | ||
254272ce BG |
9228 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, |
9229 | GFP_KERNEL_ACCOUNT)) { | |
f1797359 | 9230 | r = -ENOMEM; |
f5f48ee1 | 9231 | goto fail_free_mce_banks; |
f1797359 | 9232 | } |
f5f48ee1 | 9233 | |
0ee6a517 | 9234 | fx_init(vcpu); |
66f7b72e | 9235 | |
4344ee98 | 9236 | vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; |
d7876f1b | 9237 | |
5a4f55cd EK |
9238 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
9239 | ||
74545705 RK |
9240 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; |
9241 | ||
af585b92 | 9242 | kvm_async_pf_hash_reset(vcpu); |
f5132b01 | 9243 | kvm_pmu_init(vcpu); |
af585b92 | 9244 | |
1c1a9ce9 | 9245 | vcpu->arch.pending_external_vector = -1; |
de63ad4c | 9246 | vcpu->arch.preempted_in_kernel = false; |
1c1a9ce9 | 9247 | |
5c919412 AS |
9248 | kvm_hv_vcpu_init(vcpu); |
9249 | ||
e9b11c17 | 9250 | return 0; |
0ee6a517 | 9251 | |
f5f48ee1 SY |
9252 | fail_free_mce_banks: |
9253 | kfree(vcpu->arch.mce_banks); | |
443c39bc WY |
9254 | fail_free_lapic: |
9255 | kvm_free_lapic(vcpu); | |
e9b11c17 ZX |
9256 | fail_mmu_destroy: |
9257 | kvm_mmu_destroy(vcpu); | |
9258 | fail_free_pio_data: | |
ad312c7c | 9259 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
9260 | fail: |
9261 | return r; | |
9262 | } | |
9263 | ||
9264 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
9265 | { | |
f656ce01 MT |
9266 | int idx; |
9267 | ||
1f4b34f8 | 9268 | kvm_hv_vcpu_uninit(vcpu); |
f5132b01 | 9269 | kvm_pmu_destroy(vcpu); |
36cb93fd | 9270 | kfree(vcpu->arch.mce_banks); |
e9b11c17 | 9271 | kvm_free_lapic(vcpu); |
f656ce01 | 9272 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
e9b11c17 | 9273 | kvm_mmu_destroy(vcpu); |
f656ce01 | 9274 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
ad312c7c | 9275 | free_page((unsigned long)vcpu->arch.pio_data); |
35754c98 | 9276 | if (!lapic_in_kernel(vcpu)) |
54e9818f | 9277 | static_key_slow_dec(&kvm_no_apic_vcpu); |
e9b11c17 | 9278 | } |
d19a9cd2 | 9279 | |
e790d9ef RK |
9280 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
9281 | { | |
c595ceee | 9282 | vcpu->arch.l1tf_flush_l1d = true; |
ae97a3b8 | 9283 | kvm_x86_ops->sched_in(vcpu, cpu); |
e790d9ef RK |
9284 | } |
9285 | ||
e08b9637 | 9286 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 9287 | { |
e08b9637 CO |
9288 | if (type) |
9289 | return -EINVAL; | |
9290 | ||
6ef768fa | 9291 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 9292 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 9293 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 9294 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 9295 | |
5550af4d SY |
9296 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
9297 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
9298 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
9299 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
9300 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 9301 | |
038f8c11 | 9302 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 9303 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
9304 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
9305 | ||
9285ec4c | 9306 | kvm->arch.kvmclock_offset = -ktime_get_boottime_ns(); |
d828199e | 9307 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 9308 | |
6fbbde9a DS |
9309 | kvm->arch.guest_can_read_msr_platform_info = true; |
9310 | ||
7e44e449 | 9311 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 9312 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 9313 | |
cbc0236a | 9314 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 9315 | kvm_page_track_init(kvm); |
13d268ca | 9316 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 9317 | |
03543133 SS |
9318 | if (kvm_x86_ops->vm_init) |
9319 | return kvm_x86_ops->vm_init(kvm); | |
9320 | ||
d89f5eff | 9321 | return 0; |
d19a9cd2 ZX |
9322 | } |
9323 | ||
9324 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
9325 | { | |
ec7660cc | 9326 | vcpu_load(vcpu); |
d19a9cd2 ZX |
9327 | kvm_mmu_unload(vcpu); |
9328 | vcpu_put(vcpu); | |
9329 | } | |
9330 | ||
9331 | static void kvm_free_vcpus(struct kvm *kvm) | |
9332 | { | |
9333 | unsigned int i; | |
988a2cae | 9334 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
9335 | |
9336 | /* | |
9337 | * Unpin any mmu pages first. | |
9338 | */ | |
af585b92 GN |
9339 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9340 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 9341 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 9342 | } |
988a2cae GN |
9343 | kvm_for_each_vcpu(i, vcpu, kvm) |
9344 | kvm_arch_vcpu_free(vcpu); | |
9345 | ||
9346 | mutex_lock(&kvm->lock); | |
9347 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
9348 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 9349 | |
988a2cae GN |
9350 | atomic_set(&kvm->online_vcpus, 0); |
9351 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
9352 | } |
9353 | ||
ad8ba2cd SY |
9354 | void kvm_arch_sync_events(struct kvm *kvm) |
9355 | { | |
332967a3 | 9356 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 9357 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 9358 | kvm_free_pit(kvm); |
ad8ba2cd SY |
9359 | } |
9360 | ||
1d8007bd | 9361 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9362 | { |
9363 | int i, r; | |
25188b99 | 9364 | unsigned long hva; |
f0d648bd PB |
9365 | struct kvm_memslots *slots = kvm_memslots(kvm); |
9366 | struct kvm_memory_slot *slot, old; | |
9da0e4d5 PB |
9367 | |
9368 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
9369 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
9370 | return -EINVAL; | |
9da0e4d5 | 9371 | |
f0d648bd PB |
9372 | slot = id_to_memslot(slots, id); |
9373 | if (size) { | |
b21629da | 9374 | if (slot->npages) |
f0d648bd PB |
9375 | return -EEXIST; |
9376 | ||
9377 | /* | |
9378 | * MAP_SHARED to prevent internal slot pages from being moved | |
9379 | * by fork()/COW. | |
9380 | */ | |
9381 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
9382 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
9383 | if (IS_ERR((void *)hva)) | |
9384 | return PTR_ERR((void *)hva); | |
9385 | } else { | |
9386 | if (!slot->npages) | |
9387 | return 0; | |
9388 | ||
9389 | hva = 0; | |
9390 | } | |
9391 | ||
9392 | old = *slot; | |
9da0e4d5 | 9393 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 9394 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 9395 | |
1d8007bd PB |
9396 | m.slot = id | (i << 16); |
9397 | m.flags = 0; | |
9398 | m.guest_phys_addr = gpa; | |
f0d648bd | 9399 | m.userspace_addr = hva; |
1d8007bd | 9400 | m.memory_size = size; |
9da0e4d5 PB |
9401 | r = __kvm_set_memory_region(kvm, &m); |
9402 | if (r < 0) | |
9403 | return r; | |
9404 | } | |
9405 | ||
103c763c EB |
9406 | if (!size) |
9407 | vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); | |
f0d648bd | 9408 | |
9da0e4d5 PB |
9409 | return 0; |
9410 | } | |
9411 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
9412 | ||
1d8007bd | 9413 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9414 | { |
9415 | int r; | |
9416 | ||
9417 | mutex_lock(&kvm->slots_lock); | |
1d8007bd | 9418 | r = __x86_set_memory_region(kvm, id, gpa, size); |
9da0e4d5 PB |
9419 | mutex_unlock(&kvm->slots_lock); |
9420 | ||
9421 | return r; | |
9422 | } | |
9423 | EXPORT_SYMBOL_GPL(x86_set_memory_region); | |
9424 | ||
d19a9cd2 ZX |
9425 | void kvm_arch_destroy_vm(struct kvm *kvm) |
9426 | { | |
27469d29 AH |
9427 | if (current->mm == kvm->mm) { |
9428 | /* | |
9429 | * Free memory regions allocated on behalf of userspace, | |
9430 | * unless the the memory map has changed due to process exit | |
9431 | * or fd copying. | |
9432 | */ | |
1d8007bd PB |
9433 | x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); |
9434 | x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); | |
9435 | x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
27469d29 | 9436 | } |
03543133 SS |
9437 | if (kvm_x86_ops->vm_destroy) |
9438 | kvm_x86_ops->vm_destroy(kvm); | |
c761159c PX |
9439 | kvm_pic_destroy(kvm); |
9440 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 9441 | kvm_free_vcpus(kvm); |
af1bae54 | 9442 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 9443 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 9444 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 9445 | kvm_page_track_cleanup(kvm); |
cbc0236a | 9446 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 9447 | } |
0de10343 | 9448 | |
5587027c | 9449 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, |
db3fe4eb TY |
9450 | struct kvm_memory_slot *dont) |
9451 | { | |
9452 | int i; | |
9453 | ||
d89cc617 TY |
9454 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
9455 | if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { | |
548ef284 | 9456 | kvfree(free->arch.rmap[i]); |
d89cc617 | 9457 | free->arch.rmap[i] = NULL; |
77d11309 | 9458 | } |
d89cc617 TY |
9459 | if (i == 0) |
9460 | continue; | |
9461 | ||
9462 | if (!dont || free->arch.lpage_info[i - 1] != | |
9463 | dont->arch.lpage_info[i - 1]) { | |
548ef284 | 9464 | kvfree(free->arch.lpage_info[i - 1]); |
d89cc617 | 9465 | free->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9466 | } |
9467 | } | |
21ebbeda XG |
9468 | |
9469 | kvm_page_track_free_memslot(free, dont); | |
db3fe4eb TY |
9470 | } |
9471 | ||
5587027c AK |
9472 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
9473 | unsigned long npages) | |
db3fe4eb TY |
9474 | { |
9475 | int i; | |
9476 | ||
d89cc617 | 9477 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 9478 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
9479 | unsigned long ugfn; |
9480 | int lpages; | |
d89cc617 | 9481 | int level = i + 1; |
db3fe4eb TY |
9482 | |
9483 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
9484 | slot->base_gfn, level) + 1; | |
9485 | ||
d89cc617 | 9486 | slot->arch.rmap[i] = |
778e1cdd | 9487 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 9488 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 9489 | if (!slot->arch.rmap[i]) |
77d11309 | 9490 | goto out_free; |
d89cc617 TY |
9491 | if (i == 0) |
9492 | continue; | |
77d11309 | 9493 | |
254272ce | 9494 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 9495 | if (!linfo) |
db3fe4eb TY |
9496 | goto out_free; |
9497 | ||
92f94f1e XG |
9498 | slot->arch.lpage_info[i - 1] = linfo; |
9499 | ||
db3fe4eb | 9500 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9501 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 9502 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 9503 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
9504 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
9505 | /* | |
9506 | * If the gfn and userspace address are not aligned wrt each | |
9507 | * other, or if explicitly asked to, disable large page | |
9508 | * support for this slot | |
9509 | */ | |
9510 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || | |
9511 | !kvm_largepages_enabled()) { | |
9512 | unsigned long j; | |
9513 | ||
9514 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 9515 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
9516 | } |
9517 | } | |
9518 | ||
21ebbeda XG |
9519 | if (kvm_page_track_create_memslot(slot, npages)) |
9520 | goto out_free; | |
9521 | ||
db3fe4eb TY |
9522 | return 0; |
9523 | ||
9524 | out_free: | |
d89cc617 | 9525 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 9526 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
9527 | slot->arch.rmap[i] = NULL; |
9528 | if (i == 0) | |
9529 | continue; | |
9530 | ||
548ef284 | 9531 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 9532 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
9533 | } |
9534 | return -ENOMEM; | |
9535 | } | |
9536 | ||
15248258 | 9537 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 9538 | { |
e6dff7d1 TY |
9539 | /* |
9540 | * memslots->generation has been incremented. | |
9541 | * mmio generation may have reached its maximum value. | |
9542 | */ | |
15248258 | 9543 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
e59dbe09 TY |
9544 | } |
9545 | ||
f7784b8e MT |
9546 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
9547 | struct kvm_memory_slot *memslot, | |
09170a49 | 9548 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 9549 | enum kvm_mr_change change) |
0de10343 | 9550 | { |
f7784b8e MT |
9551 | return 0; |
9552 | } | |
9553 | ||
88178fd4 KH |
9554 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
9555 | struct kvm_memory_slot *new) | |
9556 | { | |
9557 | /* Still write protect RO slot */ | |
9558 | if (new->flags & KVM_MEM_READONLY) { | |
9559 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9560 | return; | |
9561 | } | |
9562 | ||
9563 | /* | |
9564 | * Call kvm_x86_ops dirty logging hooks when they are valid. | |
9565 | * | |
9566 | * kvm_x86_ops->slot_disable_log_dirty is called when: | |
9567 | * | |
9568 | * - KVM_MR_CREATE with dirty logging is disabled | |
9569 | * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag | |
9570 | * | |
9571 | * The reason is, in case of PML, we need to set D-bit for any slots | |
9572 | * with dirty logging disabled in order to eliminate unnecessary GPA | |
9573 | * logging in PML buffer (and potential PML buffer full VMEXT). This | |
9574 | * guarantees leaving PML enabled during guest's lifetime won't have | |
bdd303cb | 9575 | * any additional overhead from PML when guest is running with dirty |
88178fd4 KH |
9576 | * logging disabled for memory slots. |
9577 | * | |
9578 | * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot | |
9579 | * to dirty logging mode. | |
9580 | * | |
9581 | * If kvm_x86_ops dirty logging hooks are invalid, use write protect. | |
9582 | * | |
9583 | * In case of write protect: | |
9584 | * | |
9585 | * Write protect all pages for dirty logging. | |
9586 | * | |
9587 | * All the sptes including the large sptes which point to this | |
9588 | * slot are set to readonly. We can not create any new large | |
9589 | * spte on this slot until the end of the logging. | |
9590 | * | |
9591 | * See the comments in fast_page_fault(). | |
9592 | */ | |
9593 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
9594 | if (kvm_x86_ops->slot_enable_log_dirty) | |
9595 | kvm_x86_ops->slot_enable_log_dirty(kvm, new); | |
9596 | else | |
9597 | kvm_mmu_slot_remove_write_access(kvm, new); | |
9598 | } else { | |
9599 | if (kvm_x86_ops->slot_disable_log_dirty) | |
9600 | kvm_x86_ops->slot_disable_log_dirty(kvm, new); | |
9601 | } | |
9602 | } | |
9603 | ||
f7784b8e | 9604 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 9605 | const struct kvm_userspace_memory_region *mem, |
8482644a | 9606 | const struct kvm_memory_slot *old, |
f36f3f28 | 9607 | const struct kvm_memory_slot *new, |
8482644a | 9608 | enum kvm_mr_change change) |
f7784b8e | 9609 | { |
48c0e4e9 | 9610 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
9611 | kvm_mmu_change_mmu_pages(kvm, |
9612 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 9613 | |
3ea3b7fa WL |
9614 | /* |
9615 | * Dirty logging tracks sptes in 4k granularity, meaning that large | |
9616 | * sptes have to be split. If live migration is successful, the guest | |
9617 | * in the source machine will be destroyed and large sptes will be | |
9618 | * created in the destination. However, if the guest continues to run | |
9619 | * in the source machine (for example if live migration fails), small | |
9620 | * sptes will remain around and cause bad performance. | |
9621 | * | |
9622 | * Scan sptes if dirty logging has been stopped, dropping those | |
9623 | * which can be collapsed into a single large-page spte. Later | |
9624 | * page faults will create the large-page sptes. | |
9625 | */ | |
9626 | if ((change != KVM_MR_DELETE) && | |
9627 | (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
9628 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
9629 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
9630 | ||
c972f3b1 | 9631 | /* |
88178fd4 | 9632 | * Set up write protection and/or dirty logging for the new slot. |
c126d94f | 9633 | * |
88178fd4 KH |
9634 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have |
9635 | * been zapped so no dirty logging staff is needed for old slot. For | |
9636 | * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the | |
9637 | * new and it's also covered when dealing with the new slot. | |
f36f3f28 PB |
9638 | * |
9639 | * FIXME: const-ify all uses of struct kvm_memory_slot. | |
c972f3b1 | 9640 | */ |
88178fd4 | 9641 | if (change != KVM_MR_DELETE) |
f36f3f28 | 9642 | kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); |
0de10343 | 9643 | } |
1d737c8a | 9644 | |
2df72e9b | 9645 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 9646 | { |
7390de1e | 9647 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
9648 | } |
9649 | ||
2df72e9b MT |
9650 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
9651 | struct kvm_memory_slot *slot) | |
9652 | { | |
ae7cd873 | 9653 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
9654 | } |
9655 | ||
e6c67d8c LA |
9656 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
9657 | { | |
9658 | return (is_guest_mode(vcpu) && | |
9659 | kvm_x86_ops->guest_apic_has_interrupt && | |
9660 | kvm_x86_ops->guest_apic_has_interrupt(vcpu)); | |
9661 | } | |
9662 | ||
5d9bc648 PB |
9663 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
9664 | { | |
9665 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
9666 | return true; | |
9667 | ||
9668 | if (kvm_apic_has_events(vcpu)) | |
9669 | return true; | |
9670 | ||
9671 | if (vcpu->arch.pv.pv_unhalted) | |
9672 | return true; | |
9673 | ||
a5f01f8e WL |
9674 | if (vcpu->arch.exception.pending) |
9675 | return true; | |
9676 | ||
47a66eed Z |
9677 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
9678 | (vcpu->arch.nmi_pending && | |
9679 | kvm_x86_ops->nmi_allowed(vcpu))) | |
5d9bc648 PB |
9680 | return true; |
9681 | ||
47a66eed Z |
9682 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
9683 | (vcpu->arch.smi_pending && !is_smm(vcpu))) | |
73917739 PB |
9684 | return true; |
9685 | ||
5d9bc648 | 9686 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
9687 | (kvm_cpu_has_interrupt(vcpu) || |
9688 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
9689 | return true; |
9690 | ||
1f4b34f8 AS |
9691 | if (kvm_hv_has_stimer_pending(vcpu)) |
9692 | return true; | |
9693 | ||
5d9bc648 PB |
9694 | return false; |
9695 | } | |
9696 | ||
1d737c8a ZX |
9697 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
9698 | { | |
5d9bc648 | 9699 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 9700 | } |
5736199a | 9701 | |
17e433b5 WL |
9702 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
9703 | { | |
9704 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
9705 | return true; | |
9706 | ||
9707 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
9708 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
9709 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
9710 | return true; | |
9711 | ||
9712 | if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu)) | |
9713 | return true; | |
9714 | ||
9715 | return false; | |
9716 | } | |
9717 | ||
199b5763 LM |
9718 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
9719 | { | |
de63ad4c | 9720 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
9721 | } |
9722 | ||
b6d33834 | 9723 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 9724 | { |
b6d33834 | 9725 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 9726 | } |
78646121 GN |
9727 | |
9728 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
9729 | { | |
9730 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
9731 | } | |
229456fc | 9732 | |
82b32774 | 9733 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 9734 | { |
82b32774 NA |
9735 | if (is_64_bit_mode(vcpu)) |
9736 | return kvm_rip_read(vcpu); | |
9737 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
9738 | kvm_rip_read(vcpu)); | |
9739 | } | |
9740 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 9741 | |
82b32774 NA |
9742 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
9743 | { | |
9744 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
9745 | } |
9746 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
9747 | ||
94fe45da JK |
9748 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
9749 | { | |
9750 | unsigned long rflags; | |
9751 | ||
9752 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
9753 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
c310bac5 | 9754 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
9755 | return rflags; |
9756 | } | |
9757 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
9758 | ||
6addfc42 | 9759 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
9760 | { |
9761 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 9762 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 9763 | rflags |= X86_EFLAGS_TF; |
94fe45da | 9764 | kvm_x86_ops->set_rflags(vcpu, rflags); |
6addfc42 PB |
9765 | } |
9766 | ||
9767 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
9768 | { | |
9769 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 9770 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
9771 | } |
9772 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
9773 | ||
56028d08 GN |
9774 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
9775 | { | |
9776 | int r; | |
9777 | ||
44dd3ffa | 9778 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 9779 | work->wakeup_all) |
56028d08 GN |
9780 | return; |
9781 | ||
9782 | r = kvm_mmu_reload(vcpu); | |
9783 | if (unlikely(r)) | |
9784 | return; | |
9785 | ||
44dd3ffa VK |
9786 | if (!vcpu->arch.mmu->direct_map && |
9787 | work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) | |
fb67e14f XG |
9788 | return; |
9789 | ||
44dd3ffa | 9790 | vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true); |
56028d08 GN |
9791 | } |
9792 | ||
af585b92 GN |
9793 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
9794 | { | |
9795 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); | |
9796 | } | |
9797 | ||
9798 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
9799 | { | |
9800 | return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); | |
9801 | } | |
9802 | ||
9803 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9804 | { | |
9805 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9806 | ||
9807 | while (vcpu->arch.apf.gfns[key] != ~0) | |
9808 | key = kvm_async_pf_next_probe(key); | |
9809 | ||
9810 | vcpu->arch.apf.gfns[key] = gfn; | |
9811 | } | |
9812 | ||
9813 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9814 | { | |
9815 | int i; | |
9816 | u32 key = kvm_async_pf_hash_fn(gfn); | |
9817 | ||
9818 | for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && | |
c7d28c24 XG |
9819 | (vcpu->arch.apf.gfns[key] != gfn && |
9820 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
9821 | key = kvm_async_pf_next_probe(key); |
9822 | ||
9823 | return key; | |
9824 | } | |
9825 | ||
9826 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9827 | { | |
9828 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
9829 | } | |
9830 | ||
9831 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
9832 | { | |
9833 | u32 i, j, k; | |
9834 | ||
9835 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
9836 | while (true) { | |
9837 | vcpu->arch.apf.gfns[i] = ~0; | |
9838 | do { | |
9839 | j = kvm_async_pf_next_probe(j); | |
9840 | if (vcpu->arch.apf.gfns[j] == ~0) | |
9841 | return; | |
9842 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
9843 | /* | |
9844 | * k lies cyclically in ]i,j] | |
9845 | * | i.k.j | | |
9846 | * |....j i.k.| or |.k..j i...| | |
9847 | */ | |
9848 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
9849 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
9850 | i = j; | |
9851 | } | |
9852 | } | |
9853 | ||
7c90705b GN |
9854 | static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) |
9855 | { | |
4e335d9e PB |
9856 | |
9857 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, | |
9858 | sizeof(val)); | |
7c90705b GN |
9859 | } |
9860 | ||
9a6e7c39 WL |
9861 | static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) |
9862 | { | |
9863 | ||
9864 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, | |
9865 | sizeof(u32)); | |
9866 | } | |
9867 | ||
1dfdb45e PB |
9868 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
9869 | { | |
9870 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
9871 | return false; | |
9872 | ||
9873 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || | |
9874 | (vcpu->arch.apf.send_user_only && | |
9875 | kvm_x86_ops->get_cpl(vcpu) == 0)) | |
9876 | return false; | |
9877 | ||
9878 | return true; | |
9879 | } | |
9880 | ||
9881 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
9882 | { | |
9883 | if (unlikely(!lapic_in_kernel(vcpu) || | |
9884 | kvm_event_needs_reinjection(vcpu) || | |
9885 | vcpu->arch.exception.pending)) | |
9886 | return false; | |
9887 | ||
9888 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
9889 | return false; | |
9890 | ||
9891 | /* | |
9892 | * If interrupts are off we cannot even use an artificial | |
9893 | * halt state. | |
9894 | */ | |
9895 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
9896 | } | |
9897 | ||
af585b92 GN |
9898 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
9899 | struct kvm_async_pf *work) | |
9900 | { | |
6389ee94 AK |
9901 | struct x86_exception fault; |
9902 | ||
7c90705b | 9903 | trace_kvm_async_pf_not_present(work->arch.token, work->gva); |
af585b92 | 9904 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 9905 | |
1dfdb45e PB |
9906 | if (kvm_can_deliver_async_pf(vcpu) && |
9907 | !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { | |
6389ee94 AK |
9908 | fault.vector = PF_VECTOR; |
9909 | fault.error_code_valid = true; | |
9910 | fault.error_code = 0; | |
9911 | fault.nested_page_fault = false; | |
9912 | fault.address = work->arch.token; | |
adfe20fb | 9913 | fault.async_page_fault = true; |
6389ee94 | 9914 | kvm_inject_page_fault(vcpu, &fault); |
1dfdb45e PB |
9915 | } else { |
9916 | /* | |
9917 | * It is not possible to deliver a paravirtualized asynchronous | |
9918 | * page fault, but putting the guest in an artificial halt state | |
9919 | * can be beneficial nevertheless: if an interrupt arrives, we | |
9920 | * can deliver it timely and perhaps the guest will schedule | |
9921 | * another process. When the instruction that triggered a page | |
9922 | * fault is retried, hopefully the page will be ready in the host. | |
9923 | */ | |
9924 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
7c90705b | 9925 | } |
af585b92 GN |
9926 | } |
9927 | ||
9928 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
9929 | struct kvm_async_pf *work) | |
9930 | { | |
6389ee94 | 9931 | struct x86_exception fault; |
9a6e7c39 | 9932 | u32 val; |
6389ee94 | 9933 | |
f2e10669 | 9934 | if (work->wakeup_all) |
7c90705b GN |
9935 | work->arch.token = ~0; /* broadcast wakeup */ |
9936 | else | |
9937 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
24dccf83 | 9938 | trace_kvm_async_pf_ready(work->arch.token, work->gva); |
7c90705b | 9939 | |
9a6e7c39 WL |
9940 | if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && |
9941 | !apf_get_user(vcpu, &val)) { | |
9942 | if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && | |
9943 | vcpu->arch.exception.pending && | |
9944 | vcpu->arch.exception.nr == PF_VECTOR && | |
9945 | !apf_put_user(vcpu, 0)) { | |
9946 | vcpu->arch.exception.injected = false; | |
9947 | vcpu->arch.exception.pending = false; | |
9948 | vcpu->arch.exception.nr = 0; | |
9949 | vcpu->arch.exception.has_error_code = false; | |
9950 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
9951 | vcpu->arch.exception.has_payload = false; |
9952 | vcpu->arch.exception.payload = 0; | |
9a6e7c39 WL |
9953 | } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { |
9954 | fault.vector = PF_VECTOR; | |
9955 | fault.error_code_valid = true; | |
9956 | fault.error_code = 0; | |
9957 | fault.nested_page_fault = false; | |
9958 | fault.address = work->arch.token; | |
9959 | fault.async_page_fault = true; | |
9960 | kvm_inject_page_fault(vcpu, &fault); | |
9961 | } | |
7c90705b | 9962 | } |
e6d53e3b | 9963 | vcpu->arch.apf.halted = false; |
a4fa1635 | 9964 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
9965 | } |
9966 | ||
9967 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) | |
9968 | { | |
9969 | if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) | |
9970 | return true; | |
9971 | else | |
9bc1f09f | 9972 | return kvm_can_do_async_pf(vcpu); |
af585b92 GN |
9973 | } |
9974 | ||
5544eb9b PB |
9975 | void kvm_arch_start_assignment(struct kvm *kvm) |
9976 | { | |
9977 | atomic_inc(&kvm->arch.assigned_device_count); | |
9978 | } | |
9979 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
9980 | ||
9981 | void kvm_arch_end_assignment(struct kvm *kvm) | |
9982 | { | |
9983 | atomic_dec(&kvm->arch.assigned_device_count); | |
9984 | } | |
9985 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
9986 | ||
9987 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
9988 | { | |
9989 | return atomic_read(&kvm->arch.assigned_device_count); | |
9990 | } | |
9991 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
9992 | ||
e0f0bbc5 AW |
9993 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
9994 | { | |
9995 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
9996 | } | |
9997 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
9998 | ||
9999 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
10000 | { | |
10001 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
10002 | } | |
10003 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
10004 | ||
10005 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
10006 | { | |
10007 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
10008 | } | |
10009 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
10010 | ||
14717e20 AW |
10011 | bool kvm_arch_has_irq_bypass(void) |
10012 | { | |
10013 | return kvm_x86_ops->update_pi_irte != NULL; | |
10014 | } | |
10015 | ||
87276880 FW |
10016 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
10017 | struct irq_bypass_producer *prod) | |
10018 | { | |
10019 | struct kvm_kernel_irqfd *irqfd = | |
10020 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10021 | ||
14717e20 | 10022 | irqfd->producer = prod; |
87276880 | 10023 | |
14717e20 AW |
10024 | return kvm_x86_ops->update_pi_irte(irqfd->kvm, |
10025 | prod->irq, irqfd->gsi, 1); | |
87276880 FW |
10026 | } |
10027 | ||
10028 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
10029 | struct irq_bypass_producer *prod) | |
10030 | { | |
10031 | int ret; | |
10032 | struct kvm_kernel_irqfd *irqfd = | |
10033 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10034 | ||
87276880 FW |
10035 | WARN_ON(irqfd->producer != prod); |
10036 | irqfd->producer = NULL; | |
10037 | ||
10038 | /* | |
10039 | * When producer of consumer is unregistered, we change back to | |
10040 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 10041 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
10042 | * int this case doesn't want to receive the interrupts. |
10043 | */ | |
10044 | ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); | |
10045 | if (ret) | |
10046 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
10047 | " fails: %d\n", irqfd->consumer.token, ret); | |
10048 | } | |
10049 | ||
10050 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
10051 | uint32_t guest_irq, bool set) | |
10052 | { | |
10053 | if (!kvm_x86_ops->update_pi_irte) | |
10054 | return -EINVAL; | |
10055 | ||
10056 | return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); | |
10057 | } | |
10058 | ||
52004014 FW |
10059 | bool kvm_vector_hashing_enabled(void) |
10060 | { | |
10061 | return vector_hashing; | |
10062 | } | |
10063 | EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); | |
10064 | ||
2d5ba19b MT |
10065 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
10066 | { | |
10067 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
10068 | } | |
10069 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
10070 | ||
10071 | ||
229456fc | 10072 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 10073 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
10074 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
10075 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
10076 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
10077 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 10078 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 10079 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 10080 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 10081 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 10082 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 10083 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 10084 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 10085 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
7b46268d | 10086 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); |
843e4330 | 10087 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 10088 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
10089 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
10090 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); |