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x86/asm/tsc: Remove rdtscl()
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
5fb76f9b 38#include <linux/module.h>
0de10343 39#include <linux/mman.h>
2bacc55c 40#include <linux/highmem.h>
19de40a8 41#include <linux/iommu.h>
62c476c7 42#include <linux/intel-iommu.h>
c8076604 43#include <linux/cpufreq.h>
18863bdd 44#include <linux/user-return-notifier.h>
a983fb23 45#include <linux/srcu.h>
5a0e3ad6 46#include <linux/slab.h>
ff9d07a0 47#include <linux/perf_event.h>
7bee342a 48#include <linux/uaccess.h>
af585b92 49#include <linux/hash.h>
a1b60c1c 50#include <linux/pci.h>
16e8d74d
MT		 51#include <linux/timekeeper_internal.h>
52#include <linux/pvclock_gtod.h>
aec51dc4 53#include <trace/events/kvm.h>
2ed152af 54
229456fc
MT		 55#define CREATE_TRACE_POINTS
56#include "trace.h"
043405e1 57
24f1e32c 58#include <asm/debugreg.h>
d825ed0a 59#include <asm/msr.h>
a5f61300 60#include <asm/desc.h>
890ca9ae 61#include <asm/mce.h>
f89e32e0 62#include <linux/kernel_stat.h>
78f7f1e5 63#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
630994b3
MT		 101static bool __read_mostly kvmclock_periodic_sync = true;
102module_param(kvmclock_periodic_sync, bool, S_IRUGO);
103
92a1f12d
JR		 104bool kvm_has_tsc_control;
105EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
106u32 kvm_max_guest_tsc_khz;
107EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
108
cc578287
ZA		 109/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
110static u32 tsc_tolerance_ppm = 250;
111module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
112
d0659d94
MT		 113/* lapic timer advance (tscdeadline mode only) in nanoseconds */
114unsigned int lapic_timer_advance_ns = 0;
115module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
116
16a96021
MT		 117static bool backwards_tsc_observed = false;
118
18863bdd
AK		 119#define KVM_NR_SHARED_MSRS 16
120
121struct kvm_shared_msrs_global {
122 int nr;
2bf78fa7 123 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 124};
125
126struct kvm_shared_msrs {
127 struct user_return_notifier urn;
128 bool registered;
2bf78fa7
SY		 129 struct kvm_shared_msr_values {
130 u64 host;
131 u64 curr;
132 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 136static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 137
417bc304 138struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 139 { "pf_fixed", VCPU_STAT(pf_fixed) },
140 { "pf_guest", VCPU_STAT(pf_guest) },
141 { "tlb_flush", VCPU_STAT(tlb_flush) },
142 { "invlpg", VCPU_STAT(invlpg) },
143 { "exits", VCPU_STAT(exits) },
144 { "io_exits", VCPU_STAT(io_exits) },
145 { "mmio_exits", VCPU_STAT(mmio_exits) },
146 { "signal_exits", VCPU_STAT(signal_exits) },
147 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 148 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 149 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 150 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 151 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 152 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 153 { "request_irq", VCPU_STAT(request_irq_exits) },
154 { "irq_exits", VCPU_STAT(irq_exits) },
155 { "host_state_reload", VCPU_STAT(host_state_reload) },
156 { "efer_reload", VCPU_STAT(efer_reload) },
157 { "fpu_reload", VCPU_STAT(fpu_reload) },
158 { "insn_emulation", VCPU_STAT(insn_emulation) },
159 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 160 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 161 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 162 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
163 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
164 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
165 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
166 { "mmu_flooded", VM_STAT(mmu_flooded) },
167 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 168 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 169 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 170 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 171 { "largepages", VM_STAT(lpages) },
417bc304
HB		 172 { NULL }
173};
174
2acf923e
DC		 175u64 __read_mostly host_xcr0;
176
b6785def 177static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 178
af585b92
GN		 179static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
180{
181 int i;
182 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
183 vcpu->arch.apf.gfns[i] = ~0;
184}
185
18863bdd
AK		 186static void kvm_on_user_return(struct user_return_notifier *urn)
187{
188 unsigned slot;
18863bdd
AK		 189 struct kvm_shared_msrs *locals
190 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 191 struct kvm_shared_msr_values *values;
18863bdd
AK		 192
193 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 194 values = &locals->values[slot];
195 if (values->host != values->curr) {
196 wrmsrl(shared_msrs_global.msrs[slot], values->host);
197 values->curr = values->host;
18863bdd
AK		 198 }
199 }
200 locals->registered = false;
201 user_return_notifier_unregister(urn);
202}
203
2bf78fa7 204static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 205{
18863bdd 206 u64 value;
013f6a5d
MT		 207 unsigned int cpu = smp_processor_id();
208 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 209
2bf78fa7
SY		 210 /* only read, and nobody should modify it at this time,
211 * so don't need lock */
212 if (slot >= shared_msrs_global.nr) {
213 printk(KERN_ERR "kvm: invalid MSR slot!");
214 return;
215 }
216 rdmsrl_safe(msr, &value);
217 smsr->values[slot].host = value;
218 smsr->values[slot].curr = value;
219}
220
221void kvm_define_shared_msr(unsigned slot, u32 msr)
222{
0123be42 223 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 224 if (slot >= shared_msrs_global.nr)
225 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 226 shared_msrs_global.msrs[slot] = msr;
227 /* we need ensured the shared_msr_global have been updated */
228 smp_wmb();
18863bdd
AK		 229}
230EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232static void kvm_shared_msr_cpu_online(void)
233{
234 unsigned i;
18863bdd
AK		 235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 237 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 238}
239
8b3c3104 240int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 241{
013f6a5d
MT		 242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 244 int err;
18863bdd 245
2bf78fa7 246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 247 return 0;
2bf78fa7 248 smsr->values[slot].curr = value;
8b3c3104
AH		 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
18863bdd
AK		 253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
8b3c3104 258 return 0;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
13a34e06 262static void drop_user_return_notifiers(void)
3548bab5 263{
013f6a5d
MT		 264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269}
270
6866b83e
CO		 271u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272{
8a5a87d9 273 return vcpu->arch.apic_base;
6866b83e
CO		 274}
275EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
58cb628d
JK		 277int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278{
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
6866b83e
CO		 297}
298EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
2605fc21 300asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 301{
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304}
305EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
3fd28fce
ED		 307#define EXCPT_BENIGN 0
308#define EXCPT_CONTRIBUTORY 1
309#define EXCPT_PF 2
310
311static int exception_class(int vector)
312{
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326}
327
d6e8c854
NA		 328#define EXCPT_FAULT 0
329#define EXCPT_TRAP 1
330#define EXCPT_ABORT 2
331#define EXCPT_INTERRUPT 3
332
333static int exception_type(int vector)
334{
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351}
352
3fd28fce 353static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
3fd28fce
ED		 356{
357 u32 prev_nr;
358 int class1, class2;
359
3842d135
AK		 360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
3fd28fce
ED		 362 if (!vcpu->arch.exception.pending) {
363 queue:
3ffb2468
NA		 364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
3fd28fce
ED		 366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
3f0fd292 370 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
a8eeb04a 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395}
396
298101da
AK		 397void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
ce7ddec4
JR		 403void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404{
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
db8fcefa 409void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 410{
db8fcefa
AP		 411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415}
416EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 417
6389ee94 418void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 419{
420 ++vcpu->stat.pf_guest;
6389ee94
AK		 421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 423}
27d6c865 424EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 425
ef54bcfe 426static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 427{
6389ee94
AK		 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 430 else
6389ee94 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 432
433 return fault->nested_page_fault;
d4f8cf66
JR		 434}
435
3419ffc8
SY		 436void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437{
7460fb4a
AK		 438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 440}
441EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
298101da
AK		 443void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444{
ce7ddec4 445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 446}
447EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
ce7ddec4
JR		 449void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450{
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452}
453EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
0a79b009
AK		 455/*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 460{
0a79b009
AK		 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
298101da 465}
0a79b009 466EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 467
16f8a6f9
NA		 468bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469{
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475}
476EXPORT_SYMBOL_GPL(kvm_require_dr);
477
ec92fe44
JR		 478/*
479 * This function will be used to read from the physical memory of the currently
54bf36aa 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 481 * can read from guest physical or from the guest's guest physical memory.
482 */
483int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486{
54987b7a 487 struct x86_exception exception;
ec92fe44
JR		 488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
54987b7a 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
54bf36aa 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 499}
500EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
69b0049a 502static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 503 void *data, int offset, int len, u32 access)
504{
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507}
508
a03490ed
CO		 509/*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
ff03a073 512int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 513{
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
ff03a073 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 519
ff03a073
JR		 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 528 if (is_present_gpte(pdpte[i]) &&
20c466b5 529 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 530 ret = 0;
531 goto out;
532 }
533 }
534 ret = 1;
535
ff03a073 536 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_avail);
539 __set_bit(VCPU_EXREG_PDPTR,
540 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 541out:
a03490ed
CO		 542
543 return ret;
544}
cc4b6871 545EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 546
d835dfec
AK		 547static bool pdptrs_changed(struct kvm_vcpu *vcpu)
548{
ff03a073 549 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 550 bool changed = true;
3d06b8bf
JR		 551 int offset;
552 gfn_t gfn;
d835dfec
AK		 553 int r;
554
555 if (is_long_mode(vcpu) || !is_pae(vcpu))
556 return false;
557
6de4f3ad
AK		 558 if (!test_bit(VCPU_EXREG_PDPTR,
559 (unsigned long *)&vcpu->arch.regs_avail))
560 return true;
561
9f8fe504
AK		 562 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
563 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 564 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
565 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 566 if (r < 0)
567 goto out;
ff03a073 568 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 569out:
d835dfec
AK		 570
571 return changed;
572}
573
49a9b07e 574int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 575{
aad82703 576 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 577 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 578
f9a48e6a
AK		 579 cr0 |= X86_CR0_ET;
580
ab344828 581#ifdef CONFIG_X86_64
0f12244f
GN		 582 if (cr0 & 0xffffffff00000000UL)
583 return 1;
ab344828
GN		 584#endif
585
586 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 587
0f12244f
GN		 588 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 return 1;
a03490ed 590
0f12244f
GN		 591 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 return 1;
a03490ed
CO		 593
594 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
595#ifdef CONFIG_X86_64
f6801dff 596 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 597 int cs_db, cs_l;
598
0f12244f
GN		 599 if (!is_pae(vcpu))
600 return 1;
a03490ed 601 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 602 if (cs_l)
603 return 1;
a03490ed
CO		 604 } else
605#endif
ff03a073 606 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 607 kvm_read_cr3(vcpu)))
0f12244f 608 return 1;
a03490ed
CO		 609 }
610
ad756a16
MJ		 611 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 return 1;
613
a03490ed 614 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 615
d170c419 616 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 617 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 618 kvm_async_pf_hash_reset(vcpu);
619 }
e5f3f027 620
aad82703
SY		 621 if ((cr0 ^ old_cr0) & update_bits)
622 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 623
624 if ((cr0 ^ old_cr0) & X86_CR0_CD)
625 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 630
2d3ad1f4 631void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 632{
49a9b07e 633 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 634}
2d3ad1f4 635EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 636
42bdf991
MT		 637static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
638{
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
640 !vcpu->guest_xcr0_loaded) {
641 /* kvm_set_xcr() also depends on this */
642 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
643 vcpu->guest_xcr0_loaded = 1;
644 }
645}
646
647static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
648{
649 if (vcpu->guest_xcr0_loaded) {
650 if (vcpu->arch.xcr0 != host_xcr0)
651 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
652 vcpu->guest_xcr0_loaded = 0;
653 }
654}
655
69b0049a 656static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 657{
56c103ec
LJ		 658 u64 xcr0 = xcr;
659 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 660 u64 valid_bits;
2acf923e
DC		 661
662 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
663 if (index != XCR_XFEATURE_ENABLED_MASK)
664 return 1;
2acf923e
DC		 665 if (!(xcr0 & XSTATE_FP))
666 return 1;
667 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
668 return 1;
46c34cb0
PB		 669
670 /*
671 * Do not allow the guest to set bits that we do not support
672 * saving. However, xcr0 bit 0 is always set, even if the
673 * emulated CPU does not support XSAVE (see fx_init).
674 */
675 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
676 if (xcr0 & ~valid_bits)
2acf923e 677 return 1;
46c34cb0 678
390bd528
LJ		 679 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
680 return 1;
681
612263b3
CP		 682 if (xcr0 & XSTATE_AVX512) {
683 if (!(xcr0 & XSTATE_YMM))
684 return 1;
685 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
686 return 1;
687 }
42bdf991 688 kvm_put_guest_xcr0(vcpu);
2acf923e 689 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 690
691 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
692 kvm_update_cpuid(vcpu);
2acf923e
DC		 693 return 0;
694}
695
696int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697{
764bcbc5
Z		 698 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
699 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 700 kvm_inject_gp(vcpu, 0);
701 return 1;
702 }
703 return 0;
704}
705EXPORT_SYMBOL_GPL(kvm_set_xcr);
706
a83b29c6 707int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 708{
fc78f519 709 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 710 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
711 X86_CR4_SMEP | X86_CR4_SMAP;
712
0f12244f
GN		 713 if (cr4 & CR4_RESERVED_BITS)
714 return 1;
a03490ed 715
2acf923e
DC		 716 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
717 return 1;
718
c68b734f
YW		 719 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
720 return 1;
721
97ec8c06
FW		 722 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
723 return 1;
724
afcbf13f 725 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 726 return 1;
727
a03490ed 728 if (is_long_mode(vcpu)) {
0f12244f
GN		 729 if (!(cr4 & X86_CR4_PAE))
730 return 1;
a2edf57f
AK		 731 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
732 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 733 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
734 kvm_read_cr3(vcpu)))
0f12244f
GN		 735 return 1;
736
ad756a16
MJ		 737 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
738 if (!guest_cpuid_has_pcid(vcpu))
739 return 1;
740
741 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
742 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
743 return 1;
744 }
745
5e1746d6 746 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 747 return 1;
a03490ed 748
ad756a16
MJ		 749 if (((cr4 ^ old_cr4) & pdptr_bits) ||
750 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 751 kvm_mmu_reset_context(vcpu);
0f12244f 752
2acf923e 753 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 754 kvm_update_cpuid(vcpu);
2acf923e 755
0f12244f
GN		 756 return 0;
757}
2d3ad1f4 758EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 759
2390218b 760int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 761{
ac146235 762#ifdef CONFIG_X86_64
9d88fca7 763 cr3 &= ~CR3_PCID_INVD;
ac146235 764#endif
9d88fca7 765
9f8fe504 766 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 767 kvm_mmu_sync_roots(vcpu);
77c3913b 768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 769 return 0;
d835dfec
AK		 770 }
771
a03490ed 772 if (is_long_mode(vcpu)) {
d9f89b88
JK		 773 if (cr3 & CR3_L_MODE_RESERVED_BITS)
774 return 1;
775 } else if (is_pae(vcpu) && is_paging(vcpu) &&
776 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 777 return 1;
a03490ed 778
0f12244f 779 vcpu->arch.cr3 = cr3;
aff48baa 780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 781 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 782 return 0;
783}
2d3ad1f4 784EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 785
eea1cff9 786int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 787{
0f12244f
GN		 788 if (cr8 & CR8_RESERVED_BITS)
789 return 1;
a03490ed
CO		 790 if (irqchip_in_kernel(vcpu->kvm))
791 kvm_lapic_set_tpr(vcpu, cr8);
792 else
ad312c7c 793 vcpu->arch.cr8 = cr8;
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 797
2d3ad1f4 798unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 799{
800 if (irqchip_in_kernel(vcpu->kvm))
801 return kvm_lapic_get_cr8(vcpu);
802 else
ad312c7c 803 return vcpu->arch.cr8;
a03490ed 804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 806
ae561ede
NA		 807static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
808{
809 int i;
810
811 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
812 for (i = 0; i < KVM_NR_DB_REGS; i++)
813 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
814 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
815 }
816}
817
73aaf249
JK		 818static void kvm_update_dr6(struct kvm_vcpu *vcpu)
819{
820 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
821 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
822}
823
c8639010
JK		 824static void kvm_update_dr7(struct kvm_vcpu *vcpu)
825{
826 unsigned long dr7;
827
828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
829 dr7 = vcpu->arch.guest_debug_dr7;
830 else
831 dr7 = vcpu->arch.dr7;
832 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 833 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
834 if (dr7 & DR7_BP_EN_MASK)
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 836}
837
6f43ed01
NA		 838static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
839{
840 u64 fixed = DR6_FIXED_1;
841
842 if (!guest_cpuid_has_rtm(vcpu))
843 fixed |= DR6_RTM;
844 return fixed;
845}
846
338dbc97 847static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 vcpu->arch.db[dr] = val;
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
853 vcpu->arch.eff_db[dr] = val;
854 break;
855 case 4:
020df079
GN		 856 /* fall through */
857 case 6:
338dbc97
GN		 858 if (val & 0xffffffff00000000ULL)
859 return -1; /* #GP */
6f43ed01 860 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 861 kvm_update_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
020df079
GN		 864 /* fall through */
865 default: /* 7 */
338dbc97
GN		 866 if (val & 0xffffffff00000000ULL)
867 return -1; /* #GP */
020df079 868 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 869 kvm_update_dr7(vcpu);
020df079
GN		 870 break;
871 }
872
873 return 0;
874}
338dbc97
GN		 875
876int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
877{
16f8a6f9 878 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 879 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 880 return 1;
881 }
882 return 0;
338dbc97 883}
020df079
GN		 884EXPORT_SYMBOL_GPL(kvm_set_dr);
885
16f8a6f9 886int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 887{
888 switch (dr) {
889 case 0 ... 3:
890 *val = vcpu->arch.db[dr];
891 break;
892 case 4:
020df079
GN		 893 /* fall through */
894 case 6:
73aaf249
JK		 895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 *val = vcpu->arch.dr6;
897 else
898 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 899 break;
900 case 5:
020df079
GN		 901 /* fall through */
902 default: /* 7 */
903 *val = vcpu->arch.dr7;
904 break;
905 }
338dbc97
GN		 906 return 0;
907}
020df079
GN		 908EXPORT_SYMBOL_GPL(kvm_get_dr);
909
022cd0e8
AK		 910bool kvm_rdpmc(struct kvm_vcpu *vcpu)
911{
912 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
913 u64 data;
914 int err;
915
c6702c9d 916 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 917 if (err)
918 return err;
919 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
920 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
921 return err;
922}
923EXPORT_SYMBOL_GPL(kvm_rdpmc);
924
043405e1
CO		 925/*
926 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
927 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
928 *
929 * This list is modified at module load time to reflect the
e3267cbb 930 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 931 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
932 * may depend on host virtualization features rather than host cpu features.
043405e1 933 */
e3267cbb 934
043405e1
CO		 935static u32 msrs_to_save[] = {
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 937 MSR_STAR,
043405e1
CO		 938#ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940#endif
b3897a49 941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 943};
944
945static unsigned num_msrs_to_save;
946
62ef68bb
PB		 947static u32 emulated_msrs[] = {
948 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
949 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
950 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
951 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
952 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
953 MSR_KVM_PV_EOI_EN,
954
ba904635 955 MSR_IA32_TSC_ADJUST,
a3e06bbe 956 MSR_IA32_TSCDEADLINE,
043405e1 957 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 958 MSR_IA32_MCG_STATUS,
959 MSR_IA32_MCG_CTL,
64d60670 960 MSR_IA32_SMBASE,
043405e1
CO		 961};
962
62ef68bb
PB		 963static unsigned num_emulated_msrs;
964
384bb783 965bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 966{
b69e8cae 967 if (efer & efer_reserved_bits)
384bb783 968 return false;
15c4a640 969
1b2fd70c
AG		 970 if (efer & EFER_FFXSR) {
971 struct kvm_cpuid_entry2 *feat;
972
973 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 974 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 975 return false;
1b2fd70c
AG		 976 }
977
d8017474
AG		 978 if (efer & EFER_SVME) {
979 struct kvm_cpuid_entry2 *feat;
980
981 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 982 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 983 return false;
d8017474
AG		 984 }
985
384bb783
JK		 986 return true;
987}
988EXPORT_SYMBOL_GPL(kvm_valid_efer);
989
990static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
991{
992 u64 old_efer = vcpu->arch.efer;
993
994 if (!kvm_valid_efer(vcpu, efer))
995 return 1;
996
997 if (is_paging(vcpu)
998 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
999 return 1;
1000
15c4a640 1001 efer &= ~EFER_LMA;
f6801dff 1002 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1003
a3d204e2
SY		 1004 kvm_x86_ops->set_efer(vcpu, efer);
1005
aad82703
SY		 1006 /* Update reserved bits */
1007 if ((efer ^ old_efer) & EFER_NX)
1008 kvm_mmu_reset_context(vcpu);
1009
b69e8cae 1010 return 0;
15c4a640
CO		 1011}
1012
f2b4b7dd
JR		 1013void kvm_enable_efer_bits(u64 mask)
1014{
1015 efer_reserved_bits &= ~mask;
1016}
1017EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1018
15c4a640
CO		 1019/*
1020 * Writes msr value into into the appropriate "register".
1021 * Returns 0 on success, non-0 otherwise.
1022 * Assumes vcpu_load() was already called.
1023 */
8fe8ab46 1024int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1025{
854e8bb1
NA		 1026 switch (msr->index) {
1027 case MSR_FS_BASE:
1028 case MSR_GS_BASE:
1029 case MSR_KERNEL_GS_BASE:
1030 case MSR_CSTAR:
1031 case MSR_LSTAR:
1032 if (is_noncanonical_address(msr->data))
1033 return 1;
1034 break;
1035 case MSR_IA32_SYSENTER_EIP:
1036 case MSR_IA32_SYSENTER_ESP:
1037 /*
1038 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1039 * non-canonical address is written on Intel but not on
1040 * AMD (which ignores the top 32-bits, because it does
1041 * not implement 64-bit SYSENTER).
1042 *
1043 * 64-bit code should hence be able to write a non-canonical
1044 * value on AMD. Making the address canonical ensures that
1045 * vmentry does not fail on Intel after writing a non-canonical
1046 * value, and that something deterministic happens if the guest
1047 * invokes 64-bit SYSENTER.
1048 */
1049 msr->data = get_canonical(msr->data);
1050 }
8fe8ab46 1051 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1052}
854e8bb1 1053EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1054
313a3dc7
CO		 1055/*
1056 * Adapt set_msr() to msr_io()'s calling convention
1057 */
609e36d3
PB		 1058static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1059{
1060 struct msr_data msr;
1061 int r;
1062
1063 msr.index = index;
1064 msr.host_initiated = true;
1065 r = kvm_get_msr(vcpu, &msr);
1066 if (r)
1067 return r;
1068
1069 *data = msr.data;
1070 return 0;
1071}
1072
313a3dc7
CO		 1073static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1074{
8fe8ab46
WA		 1075 struct msr_data msr;
1076
1077 msr.data = *data;
1078 msr.index = index;
1079 msr.host_initiated = true;
1080 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1081}
1082
16e8d74d
MT		 1083#ifdef CONFIG_X86_64
1084struct pvclock_gtod_data {
1085 seqcount_t seq;
1086
1087 struct { /* extract of a clocksource struct */
1088 int vclock_mode;
1089 cycle_t cycle_last;
1090 cycle_t mask;
1091 u32 mult;
1092 u32 shift;
1093 } clock;
1094
cbcf2dd3
TG		 1095 u64 boot_ns;
1096 u64 nsec_base;
16e8d74d
MT		 1097};
1098
1099static struct pvclock_gtod_data pvclock_gtod_data;
1100
1101static void update_pvclock_gtod(struct timekeeper *tk)
1102{
1103 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1104 u64 boot_ns;
1105
876e7881 1106 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1107
1108 write_seqcount_begin(&vdata->seq);
1109
1110 /* copy pvclock gtod data */
876e7881
PZ		 1111 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1112 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1113 vdata->clock.mask = tk->tkr_mono.mask;
1114 vdata->clock.mult = tk->tkr_mono.mult;
1115 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1116
cbcf2dd3 1117 vdata->boot_ns = boot_ns;
876e7881 1118 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1119
1120 write_seqcount_end(&vdata->seq);
1121}
1122#endif
1123
bab5bb39
NK		 1124void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1125{
1126 /*
1127 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1128 * vcpu_enter_guest. This function is only called from
1129 * the physical CPU that is running vcpu.
1130 */
1131 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1132}
16e8d74d 1133
18068523
GOC		 1134static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1135{
9ed3c444
AK		 1136 int version;
1137 int r;
50d0a0f9 1138 struct pvclock_wall_clock wc;
923de3cf 1139 struct timespec boot;
18068523
GOC		 1140
1141 if (!wall_clock)
1142 return;
1143
9ed3c444
AK		 1144 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1145 if (r)
1146 return;
1147
1148 if (version & 1)
1149 ++version; /* first time write, random junk */
1150
1151 ++version;
18068523 1152
18068523
GOC		 1153 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1154
50d0a0f9
GH		 1155 /*
1156 * The guest calculates current wall clock time by adding
34c238a1 1157 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1158 * wall clock specified here. guest system time equals host
1159 * system time for us, thus we must fill in host boot time here.
1160 */
923de3cf 1161 getboottime(&boot);
50d0a0f9 1162
4b648665
BR		 1163 if (kvm->arch.kvmclock_offset) {
1164 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1165 boot = timespec_sub(boot, ts);
1166 }
50d0a0f9
GH		 1167 wc.sec = boot.tv_sec;
1168 wc.nsec = boot.tv_nsec;
1169 wc.version = version;
18068523
GOC		 1170
1171 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1172
1173 version++;
1174 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1175}
1176
50d0a0f9
GH		 1177static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1178{
1179 uint32_t quotient, remainder;
1180
1181 /* Don't try to replace with do_div(), this one calculates
1182 * "(dividend << 32) / divisor" */
1183 __asm__ ( "divl %4"
1184 : "=a" (quotient), "=d" (remainder)
1185 : "0" (0), "1" (dividend), "r" (divisor) );
1186 return quotient;
1187}
1188
5f4e3f88
ZA		 1189static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1190 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1191{
5f4e3f88 1192 uint64_t scaled64;
50d0a0f9
GH		 1193 int32_t shift = 0;
1194 uint64_t tps64;
1195 uint32_t tps32;
1196
5f4e3f88
ZA		 1197 tps64 = base_khz * 1000LL;
1198 scaled64 = scaled_khz * 1000LL;
50933623 1199 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1200 tps64 >>= 1;
1201 shift--;
1202 }
1203
1204 tps32 = (uint32_t)tps64;
50933623
JK		 1205 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1206 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1207 scaled64 >>= 1;
1208 else
1209 tps32 <<= 1;
50d0a0f9
GH		 1210 shift++;
1211 }
1212
5f4e3f88
ZA		 1213 *pshift = shift;
1214 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1215
5f4e3f88
ZA		 1216 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1217 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1218}
1219
759379dd
ZA		 1220static inline u64 get_kernel_ns(void)
1221{
bb0b5812 1222 return ktime_get_boot_ns();
50d0a0f9
GH		 1223}
1224
d828199e 1225#ifdef CONFIG_X86_64
16e8d74d 1226static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1227#endif
16e8d74d 1228
c8076604 1229static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1230static unsigned long max_tsc_khz;
c8076604 1231
cc578287 1232static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1233{
cc578287
ZA		 1234 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1235 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1236}
1237
cc578287 1238static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1239{
cc578287
ZA		 1240 u64 v = (u64)khz * (1000000 + ppm);
1241 do_div(v, 1000000);
1242 return v;
1e993611
JR		 1243}
1244
cc578287 1245static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1246{
cc578287
ZA		 1247 u32 thresh_lo, thresh_hi;
1248 int use_scaling = 0;
217fc9cf 1249
03ba32ca
MT		 1250 /* tsc_khz can be zero if TSC calibration fails */
1251 if (this_tsc_khz == 0)
1252 return;
1253
c285545f
ZA		 1254 /* Compute a scale to convert nanoseconds in TSC cycles */
1255 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1256 &vcpu->arch.virtual_tsc_shift,
1257 &vcpu->arch.virtual_tsc_mult);
1258 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1259
1260 /*
1261 * Compute the variation in TSC rate which is acceptable
1262 * within the range of tolerance and decide if the
1263 * rate being applied is within that bounds of the hardware
1264 * rate. If so, no scaling or compensation need be done.
1265 */
1266 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1267 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1268 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1269 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1270 use_scaling = 1;
1271 }
1272 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1273}
1274
1275static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1276{
e26101b1 1277 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1278 vcpu->arch.virtual_tsc_mult,
1279 vcpu->arch.virtual_tsc_shift);
e26101b1 1280 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1281 return tsc;
1282}
1283
69b0049a 1284static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1285{
1286#ifdef CONFIG_X86_64
1287 bool vcpus_matched;
b48aa97e
MT		 1288 struct kvm_arch *ka = &vcpu->kvm->arch;
1289 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1290
1291 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1292 atomic_read(&vcpu->kvm->online_vcpus));
1293
7f187922
MT		 1294 /*
1295 * Once the masterclock is enabled, always perform request in
1296 * order to update it.
1297 *
1298 * In order to enable masterclock, the host clocksource must be TSC
1299 * and the vcpus need to have matched TSCs. When that happens,
1300 * perform request to enable masterclock.
1301 */
1302 if (ka->use_master_clock ||
1303 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1304 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1305
1306 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1307 atomic_read(&vcpu->kvm->online_vcpus),
1308 ka->use_master_clock, gtod->clock.vclock_mode);
1309#endif
1310}
1311
ba904635
WA		 1312static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1313{
1314 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1315 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1316}
1317
8fe8ab46 1318void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1319{
1320 struct kvm *kvm = vcpu->kvm;
f38e098f 1321 u64 offset, ns, elapsed;
99e3e30a 1322 unsigned long flags;
02626b6a 1323 s64 usdiff;
b48aa97e 1324 bool matched;
0d3da0d2 1325 bool already_matched;
8fe8ab46 1326 u64 data = msr->data;
99e3e30a 1327
038f8c11 1328 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1329 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1330 ns = get_kernel_ns();
f38e098f 1331 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1332
03ba32ca 1333 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1334 int faulted = 0;
1335
03ba32ca
MT		 1336 /* n.b - signed multiplication and division required */
1337 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1338#ifdef CONFIG_X86_64
03ba32ca 1339 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1340#else
03ba32ca 1341 /* do_div() only does unsigned */
8915aa27
MT		 1342 asm("1: idivl %[divisor]\n"
1343 "2: xor %%edx, %%edx\n"
1344 " movl $0, %[faulted]\n"
1345 "3:\n"
1346 ".section .fixup,\"ax\"\n"
1347 "4: movl $1, %[faulted]\n"
1348 " jmp 3b\n"
1349 ".previous\n"
1350
1351 _ASM_EXTABLE(1b, 4b)
1352
1353 : "=A"(usdiff), [faulted] "=r" (faulted)
1354 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1355
5d3cb0f6 1356#endif
03ba32ca
MT		 1357 do_div(elapsed, 1000);
1358 usdiff -= elapsed;
1359 if (usdiff < 0)
1360 usdiff = -usdiff;
8915aa27
MT		 1361
1362 /* idivl overflow => difference is larger than USEC_PER_SEC */
1363 if (faulted)
1364 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1365 } else
1366 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1367
1368 /*
5d3cb0f6
ZA		 1369 * Special case: TSC write with a small delta (1 second) of virtual
1370 * cycle time against real time is interpreted as an attempt to
1371 * synchronize the CPU.
1372 *
1373 * For a reliable TSC, we can match TSC offsets, and for an unstable
1374 * TSC, we add elapsed time in this computation. We could let the
1375 * compensation code attempt to catch up if we fall behind, but
1376 * it's better to try to match offsets from the beginning.
1377 */
02626b6a 1378 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1379 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1380 if (!check_tsc_unstable()) {
e26101b1 1381 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1382 pr_debug("kvm: matched tsc offset for %llu\n", data);
1383 } else {
857e4099 1384 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1385 data += delta;
1386 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1387 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1388 }
b48aa97e 1389 matched = true;
0d3da0d2 1390 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1391 } else {
1392 /*
1393 * We split periods of matched TSC writes into generations.
1394 * For each generation, we track the original measured
1395 * nanosecond time, offset, and write, so if TSCs are in
1396 * sync, we can match exact offset, and if not, we can match
4a969980 1397 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1398 *
1399 * These values are tracked in kvm->arch.cur_xxx variables.
1400 */
1401 kvm->arch.cur_tsc_generation++;
1402 kvm->arch.cur_tsc_nsec = ns;
1403 kvm->arch.cur_tsc_write = data;
1404 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1405 matched = false;
0d3da0d2 1406 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1407 kvm->arch.cur_tsc_generation, data);
f38e098f 1408 }
e26101b1
ZA		 1409
1410 /*
1411 * We also track th most recent recorded KHZ, write and time to
1412 * allow the matching interval to be extended at each write.
1413 */
f38e098f
ZA		 1414 kvm->arch.last_tsc_nsec = ns;
1415 kvm->arch.last_tsc_write = data;
5d3cb0f6 1416 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1417
b183aa58 1418 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1419
1420 /* Keep track of which generation this VCPU has synchronized to */
1421 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1422 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1423 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1424
ba904635
WA		 1425 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1426 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1427 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1428 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1429
1430 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1431 if (!matched) {
b48aa97e 1432 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1433 } else if (!already_matched) {
1434 kvm->arch.nr_vcpus_matched_tsc++;
1435 }
b48aa97e
MT		 1436
1437 kvm_track_tsc_matching(vcpu);
1438 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1439}
e26101b1 1440
99e3e30a
ZA		 1441EXPORT_SYMBOL_GPL(kvm_write_tsc);
1442
d828199e
MT		 1443#ifdef CONFIG_X86_64
1444
1445static cycle_t read_tsc(void)
1446{
1447 cycle_t ret;
1448 u64 last;
1449
1450 /*
1451 * Empirically, a fence (of type that depends on the CPU)
1452 * before rdtsc is enough to ensure that rdtsc is ordered
1453 * with respect to loads. The various CPU manuals are unclear
1454 * as to whether rdtsc can be reordered with later loads,
1455 * but no one has ever seen it happen.
1456 */
1457 rdtsc_barrier();
881d7bf8 1458 ret = (cycle_t)native_read_tsc();
d828199e
MT		 1459
1460 last = pvclock_gtod_data.clock.cycle_last;
1461
1462 if (likely(ret >= last))
1463 return ret;
1464
1465 /*
1466 * GCC likes to generate cmov here, but this branch is extremely
1467 * predictable (it's just a funciton of time and the likely is
1468 * very likely) and there's a data dependence, so force GCC
1469 * to generate a branch instead. I don't barrier() because
1470 * we don't actually need a barrier, and if this function
1471 * ever gets inlined it will generate worse code.
1472 */
1473 asm volatile ("");
1474 return last;
1475}
1476
1477static inline u64 vgettsc(cycle_t *cycle_now)
1478{
1479 long v;
1480 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1481
1482 *cycle_now = read_tsc();
1483
1484 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1485 return v * gtod->clock.mult;
1486}
1487
cbcf2dd3 1488static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1489{
cbcf2dd3 1490 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1491 unsigned long seq;
d828199e 1492 int mode;
cbcf2dd3 1493 u64 ns;
d828199e 1494
d828199e
MT		 1495 do {
1496 seq = read_seqcount_begin(&gtod->seq);
1497 mode = gtod->clock.vclock_mode;
cbcf2dd3 1498 ns = gtod->nsec_base;
d828199e
MT		 1499 ns += vgettsc(cycle_now);
1500 ns >>= gtod->clock.shift;
cbcf2dd3 1501 ns += gtod->boot_ns;
d828199e 1502 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1503 *t = ns;
d828199e
MT		 1504
1505 return mode;
1506}
1507
1508/* returns true if host is using tsc clocksource */
1509static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1510{
d828199e
MT		 1511 /* checked again under seqlock below */
1512 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1513 return false;
1514
cbcf2dd3 1515 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1516}
1517#endif
1518
1519/*
1520 *
b48aa97e
MT		 1521 * Assuming a stable TSC across physical CPUS, and a stable TSC
1522 * across virtual CPUs, the following condition is possible.
1523 * Each numbered line represents an event visible to both
d828199e
MT		 1524 * CPUs at the next numbered event.
1525 *
1526 * "timespecX" represents host monotonic time. "tscX" represents
1527 * RDTSC value.
1528 *
1529 * VCPU0 on CPU0 | VCPU1 on CPU1
1530 *
1531 * 1. read timespec0,tsc0
1532 * 2. | timespec1 = timespec0 + N
1533 * | tsc1 = tsc0 + M
1534 * 3. transition to guest | transition to guest
1535 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1536 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1537 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1538 *
1539 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1540 *
1541 * - ret0 < ret1
1542 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1543 * ...
1544 * - 0 < N - M => M < N
1545 *
1546 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1547 * always the case (the difference between two distinct xtime instances
1548 * might be smaller then the difference between corresponding TSC reads,
1549 * when updating guest vcpus pvclock areas).
1550 *
1551 * To avoid that problem, do not allow visibility of distinct
1552 * system_timestamp/tsc_timestamp values simultaneously: use a master
1553 * copy of host monotonic time values. Update that master copy
1554 * in lockstep.
1555 *
b48aa97e 1556 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1557 *
1558 */
1559
1560static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1561{
1562#ifdef CONFIG_X86_64
1563 struct kvm_arch *ka = &kvm->arch;
1564 int vclock_mode;
b48aa97e
MT		 1565 bool host_tsc_clocksource, vcpus_matched;
1566
1567 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1568 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1569
1570 /*
1571 * If the host uses TSC clock, then passthrough TSC as stable
1572 * to the guest.
1573 */
b48aa97e 1574 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1575 &ka->master_kernel_ns,
1576 &ka->master_cycle_now);
1577
16a96021 1578 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1579 && !backwards_tsc_observed
1580 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1581
d828199e
MT		 1582 if (ka->use_master_clock)
1583 atomic_set(&kvm_guest_has_master_clock, 1);
1584
1585 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1586 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1587 vcpus_matched);
d828199e
MT		 1588#endif
1589}
1590
2e762ff7
MT		 1591static void kvm_gen_update_masterclock(struct kvm *kvm)
1592{
1593#ifdef CONFIG_X86_64
1594 int i;
1595 struct kvm_vcpu *vcpu;
1596 struct kvm_arch *ka = &kvm->arch;
1597
1598 spin_lock(&ka->pvclock_gtod_sync_lock);
1599 kvm_make_mclock_inprogress_request(kvm);
1600 /* no guest entries from this point */
1601 pvclock_update_vm_gtod_copy(kvm);
1602
1603 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1605
1606 /* guest entries allowed */
1607 kvm_for_each_vcpu(i, vcpu, kvm)
1608 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1609
1610 spin_unlock(&ka->pvclock_gtod_sync_lock);
1611#endif
1612}
1613
34c238a1 1614static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1615{
d828199e 1616 unsigned long flags, this_tsc_khz;
18068523 1617 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1618 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1619 s64 kernel_ns;
d828199e 1620 u64 tsc_timestamp, host_tsc;
0b79459b 1621 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1622 u8 pvclock_flags;
d828199e
MT		 1623 bool use_master_clock;
1624
1625 kernel_ns = 0;
1626 host_tsc = 0;
18068523 1627
d828199e
MT		 1628 /*
1629 * If the host uses TSC clock, then passthrough TSC as stable
1630 * to the guest.
1631 */
1632 spin_lock(&ka->pvclock_gtod_sync_lock);
1633 use_master_clock = ka->use_master_clock;
1634 if (use_master_clock) {
1635 host_tsc = ka->master_cycle_now;
1636 kernel_ns = ka->master_kernel_ns;
1637 }
1638 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1639
1640 /* Keep irq disabled to prevent changes to the clock */
1641 local_irq_save(flags);
89cbc767 1642 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1643 if (unlikely(this_tsc_khz == 0)) {
1644 local_irq_restore(flags);
1645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1646 return 1;
1647 }
d828199e
MT		 1648 if (!use_master_clock) {
1649 host_tsc = native_read_tsc();
1650 kernel_ns = get_kernel_ns();
1651 }
1652
1653 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1654
c285545f
ZA		 1655 /*
1656 * We may have to catch up the TSC to match elapsed wall clock
1657 * time for two reasons, even if kvmclock is used.
1658 * 1) CPU could have been running below the maximum TSC rate
1659 * 2) Broken TSC compensation resets the base at each VCPU
1660 * entry to avoid unknown leaps of TSC even when running
1661 * again on the same CPU. This may cause apparent elapsed
1662 * time to disappear, and the guest to stand still or run
1663 * very slowly.
1664 */
1665 if (vcpu->tsc_catchup) {
1666 u64 tsc = compute_guest_tsc(v, kernel_ns);
1667 if (tsc > tsc_timestamp) {
f1e2b260 1668 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1669 tsc_timestamp = tsc;
1670 }
50d0a0f9
GH		 1671 }
1672
18068523
GOC		 1673 local_irq_restore(flags);
1674
0b79459b 1675 if (!vcpu->pv_time_enabled)
c285545f 1676 return 0;
18068523 1677
e48672fa 1678 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1679 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1680 &vcpu->hv_clock.tsc_shift,
1681 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1682 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1683 }
1684
1685 /* With all the info we got, fill in the values */
1d5f066e 1686 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1687 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1688 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1689
09a0c3f1
OH		 1690 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1691 &guest_hv_clock, sizeof(guest_hv_clock))))
1692 return 0;
1693
5dca0d91
RK		 1694 /* This VCPU is paused, but it's legal for a guest to read another
1695 * VCPU's kvmclock, so we really have to follow the specification where
1696 * it says that version is odd if data is being modified, and even after
1697 * it is consistent.
1698 *
1699 * Version field updates must be kept separate. This is because
1700 * kvm_write_guest_cached might use a "rep movs" instruction, and
1701 * writes within a string instruction are weakly ordered. So there
1702 * are three writes overall.
1703 *
1704 * As a small optimization, only write the version field in the first
1705 * and third write. The vcpu->pv_time cache is still valid, because the
1706 * version field is the first in the struct.
18068523 1707 */
5dca0d91
RK		 1708 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1709
1710 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712 &vcpu->hv_clock,
1713 sizeof(vcpu->hv_clock.version));
1714
1715 smp_wmb();
78c0337a
MT		 1716
1717 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1718 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1719
1720 if (vcpu->pvclock_set_guest_stopped_request) {
1721 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1722 vcpu->pvclock_set_guest_stopped_request = false;
1723 }
1724
b7e60c5a
MT		 1725 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1726
d828199e
MT		 1727 /* If the host uses TSC clocksource, then it is stable */
1728 if (use_master_clock)
1729 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1730
78c0337a
MT		 1731 vcpu->hv_clock.flags = pvclock_flags;
1732
ce1a5e60
DM		 1733 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1734
0b79459b
AH		 1735 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1736 &vcpu->hv_clock,
1737 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1738
1739 smp_wmb();
1740
1741 vcpu->hv_clock.version++;
1742 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1743 &vcpu->hv_clock,
1744 sizeof(vcpu->hv_clock.version));
8cfdc000 1745 return 0;
c8076604
GH		 1746}
1747
0061d53d
MT		 1748/*
1749 * kvmclock updates which are isolated to a given vcpu, such as
1750 * vcpu->cpu migration, should not allow system_timestamp from
1751 * the rest of the vcpus to remain static. Otherwise ntp frequency
1752 * correction applies to one vcpu's system_timestamp but not
1753 * the others.
1754 *
1755 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1756 * We need to rate-limit these requests though, as they can
1757 * considerably slow guests that have a large number of vcpus.
1758 * The time for a remote vcpu to update its kvmclock is bound
1759 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1760 */
1761
7e44e449
AJ		 1762#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1763
1764static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1765{
1766 int i;
7e44e449
AJ		 1767 struct delayed_work *dwork = to_delayed_work(work);
1768 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1769 kvmclock_update_work);
1770 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1771 struct kvm_vcpu *vcpu;
1772
1773 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1775 kvm_vcpu_kick(vcpu);
1776 }
1777}
1778
7e44e449
AJ		 1779static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1780{
1781 struct kvm *kvm = v->kvm;
1782
105b21bb 1783 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1785 KVMCLOCK_UPDATE_DELAY);
1786}
1787
332967a3
AJ		 1788#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1789
1790static void kvmclock_sync_fn(struct work_struct *work)
1791{
1792 struct delayed_work *dwork = to_delayed_work(work);
1793 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1794 kvmclock_sync_work);
1795 struct kvm *kvm = container_of(ka, struct kvm, arch);
1796
630994b3
MT		 1797 if (!kvmclock_periodic_sync)
1798 return;
1799
332967a3
AJ		 1800 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1801 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1802 KVMCLOCK_SYNC_PERIOD);
1803}
1804
890ca9ae 1805static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1806{
890ca9ae
HY		 1807 u64 mcg_cap = vcpu->arch.mcg_cap;
1808 unsigned bank_num = mcg_cap & 0xff;
1809
15c4a640 1810 switch (msr) {
15c4a640 1811 case MSR_IA32_MCG_STATUS:
890ca9ae 1812 vcpu->arch.mcg_status = data;
15c4a640 1813 break;
c7ac679c 1814 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1815 if (!(mcg_cap & MCG_CTL_P))
1816 return 1;
1817 if (data != 0 && data != ~(u64)0)
1818 return -1;
1819 vcpu->arch.mcg_ctl = data;
1820 break;
1821 default:
1822 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1823 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1824 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1825 /* only 0 or all 1s can be written to IA32_MCi_CTL
1826 * some Linux kernels though clear bit 10 in bank 4 to
1827 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1828 * this to avoid an uncatched #GP in the guest
1829 */
890ca9ae 1830 if ((offset & 0x3) == 0 &&
114be429 1831 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1832 return -1;
1833 vcpu->arch.mce_banks[offset] = data;
1834 break;
1835 }
1836 return 1;
1837 }
1838 return 0;
1839}
1840
ffde22ac
ES		 1841static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1842{
1843 struct kvm *kvm = vcpu->kvm;
1844 int lm = is_long_mode(vcpu);
1845 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1846 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1847 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1848 : kvm->arch.xen_hvm_config.blob_size_32;
1849 u32 page_num = data & ~PAGE_MASK;
1850 u64 page_addr = data & PAGE_MASK;
1851 u8 *page;
1852 int r;
1853
1854 r = -E2BIG;
1855 if (page_num >= blob_size)
1856 goto out;
1857 r = -ENOMEM;
ff5c2c03
SL		 1858 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1859 if (IS_ERR(page)) {
1860 r = PTR_ERR(page);
ffde22ac 1861 goto out;
ff5c2c03 1862 }
54bf36aa 1863 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1864 goto out_free;
1865 r = 0;
1866out_free:
1867 kfree(page);
1868out:
1869 return r;
1870}
1871
55cd8e5a
GN		 1872static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1873{
1874 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1875}
1876
1877static bool kvm_hv_msr_partition_wide(u32 msr)
1878{
1879 bool r = false;
1880 switch (msr) {
1881 case HV_X64_MSR_GUEST_OS_ID:
1882 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1883 case HV_X64_MSR_REFERENCE_TSC:
1884 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1885 r = true;
1886 break;
1887 }
1888
1889 return r;
1890}
1891
1892static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1893{
1894 struct kvm *kvm = vcpu->kvm;
1895
1896 switch (msr) {
1897 case HV_X64_MSR_GUEST_OS_ID:
1898 kvm->arch.hv_guest_os_id = data;
1899 /* setting guest os id to zero disables hypercall page */
1900 if (!kvm->arch.hv_guest_os_id)
1901 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1902 break;
1903 case HV_X64_MSR_HYPERCALL: {
1904 u64 gfn;
1905 unsigned long addr;
1906 u8 instructions[4];
1907
1908 /* if guest os id is not set hypercall should remain disabled */
1909 if (!kvm->arch.hv_guest_os_id)
1910 break;
1911 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1912 kvm->arch.hv_hypercall = data;
1913 break;
1914 }
1915 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1916 addr = gfn_to_hva(kvm, gfn);
1917 if (kvm_is_error_hva(addr))
1918 return 1;
1919 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1920 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1921 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1922 return 1;
1923 kvm->arch.hv_hypercall = data;
b94b64c9 1924 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1925 break;
1926 }
e984097b
VR		 1927 case HV_X64_MSR_REFERENCE_TSC: {
1928 u64 gfn;
1929 HV_REFERENCE_TSC_PAGE tsc_ref;
1930 memset(&tsc_ref, 0, sizeof(tsc_ref));
1931 kvm->arch.hv_tsc_page = data;
1932 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1933 break;
1934 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1935 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1936 &tsc_ref, sizeof(tsc_ref)))
1937 return 1;
1938 mark_page_dirty(kvm, gfn);
1939 break;
1940 }
55cd8e5a 1941 default:
a737f256
CD		 1942 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1943 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1944 return 1;
1945 }
1946 return 0;
1947}
1948
1949static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1950{
10388a07
GN		 1951 switch (msr) {
1952 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1953 u64 gfn;
10388a07 1954 unsigned long addr;
55cd8e5a 1955
10388a07
GN		 1956 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1957 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1958 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1959 return 1;
10388a07
GN		 1960 break;
1961 }
b3af1e88 1962 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
54bf36aa 1963 addr = kvm_vcpu_gfn_to_hva(vcpu, gfn);
10388a07
GN		 1964 if (kvm_is_error_hva(addr))
1965 return 1;
8b0cedff 1966 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1967 return 1;
1968 vcpu->arch.hv_vapic = data;
54bf36aa 1969 kvm_vcpu_mark_page_dirty(vcpu, gfn);
b63cf42f
MT		 1970 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1971 return 1;
10388a07
GN		 1972 break;
1973 }
1974 case HV_X64_MSR_EOI:
1975 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1976 case HV_X64_MSR_ICR:
1977 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1978 case HV_X64_MSR_TPR:
1979 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1980 default:
a737f256
CD		 1981 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1982 "data 0x%llx\n", msr, data);
10388a07
GN		 1983 return 1;
1984 }
1985
1986 return 0;
55cd8e5a
GN		 1987}
1988
344d9588
GN		 1989static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1990{
1991 gpa_t gpa = data & ~0x3f;
1992
4a969980 1993 /* Bits 2:5 are reserved, Should be zero */
6adba527 1994 if (data & 0x3c)
344d9588
GN		 1995 return 1;
1996
1997 vcpu->arch.apf.msr_val = data;
1998
1999 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2000 kvm_clear_async_pf_completion_queue(vcpu);
2001 kvm_async_pf_hash_reset(vcpu);
2002 return 0;
2003 }
2004
8f964525
AH		 2005 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2006 sizeof(u32)))
344d9588
GN		 2007 return 1;
2008
6adba527 2009 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2010 kvm_async_pf_wakeup_all(vcpu);
2011 return 0;
2012}
2013
12f9a48f
GC		 2014static void kvmclock_reset(struct kvm_vcpu *vcpu)
2015{
0b79459b 2016 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2017}
2018
c9aaa895
GC		 2019static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2020{
2021 u64 delta;
2022
2023 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2024 return;
2025
2026 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2028 vcpu->arch.st.accum_steal = delta;
2029}
2030
2031static void record_steal_time(struct kvm_vcpu *vcpu)
2032{
2033 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2034 return;
2035
2036 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2038 return;
2039
2040 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2041 vcpu->arch.st.steal.version += 2;
2042 vcpu->arch.st.accum_steal = 0;
2043
2044 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2045 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2046}
2047
8fe8ab46 2048int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2049{
5753785f 2050 bool pr = false;
8fe8ab46
WA		 2051 u32 msr = msr_info->index;
2052 u64 data = msr_info->data;
5753785f 2053
15c4a640 2054 switch (msr) {
2e32b719
BP		 2055 case MSR_AMD64_NB_CFG:
2056 case MSR_IA32_UCODE_REV:
2057 case MSR_IA32_UCODE_WRITE:
2058 case MSR_VM_HSAVE_PA:
2059 case MSR_AMD64_PATCH_LOADER:
2060 case MSR_AMD64_BU_CFG2:
2061 break;
2062
15c4a640 2063 case MSR_EFER:
b69e8cae 2064 return set_efer(vcpu, data);
8f1589d9
AP		 2065 case MSR_K7_HWCR:
2066 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2067 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2068 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2069 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2070 if (data != 0) {
a737f256
CD		 2071 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2072 data);
8f1589d9
AP		 2073 return 1;
2074 }
15c4a640 2075 break;
f7c6d140
AP		 2076 case MSR_FAM10H_MMIO_CONF_BASE:
2077 if (data != 0) {
a737f256
CD		 2078 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2079 "0x%llx\n", data);
f7c6d140
AP		 2080 return 1;
2081 }
15c4a640 2082 break;
b5e2fec0
AG		 2083 case MSR_IA32_DEBUGCTLMSR:
2084 if (!data) {
2085 /* We support the non-activated case already */
2086 break;
2087 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2088 /* Values other than LBR and BTF are vendor-specific,
2089 thus reserved and should throw a #GP */
2090 return 1;
2091 }
a737f256
CD		 2092 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2093 __func__, data);
b5e2fec0 2094 break;
9ba075a6 2095 case 0x200 ... 0x2ff:
ff53604b 2096 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2097 case MSR_IA32_APICBASE:
58cb628d 2098 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2099 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2100 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2101 case MSR_IA32_TSCDEADLINE:
2102 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2103 break;
ba904635
WA		 2104 case MSR_IA32_TSC_ADJUST:
2105 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2106 if (!msr_info->host_initiated) {
d913b904 2107 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2108 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2109 }
2110 vcpu->arch.ia32_tsc_adjust_msr = data;
2111 }
2112 break;
15c4a640 2113 case MSR_IA32_MISC_ENABLE:
ad312c7c 2114 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2115 break;
64d60670
PB		 2116 case MSR_IA32_SMBASE:
2117 if (!msr_info->host_initiated)
2118 return 1;
2119 vcpu->arch.smbase = data;
2120 break;
11c6bffa 2121 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2122 case MSR_KVM_WALL_CLOCK:
2123 vcpu->kvm->arch.wall_clock = data;
2124 kvm_write_wall_clock(vcpu->kvm, data);
2125 break;
11c6bffa 2126 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2127 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2128 u64 gpa_offset;
54750f2c
MT		 2129 struct kvm_arch *ka = &vcpu->kvm->arch;
2130
12f9a48f 2131 kvmclock_reset(vcpu);
18068523 2132
54750f2c
MT		 2133 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2134 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2135
2136 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2137 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2138 &vcpu->requests);
2139
2140 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2141
2142 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2143 }
2144
18068523 2145 vcpu->arch.time = data;
0061d53d 2146 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2147
2148 /* we verify if the enable bit is set... */
2149 if (!(data & 1))
2150 break;
2151
0b79459b 2152 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2153
0b79459b 2154 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2155 &vcpu->arch.pv_time, data & ~1ULL,
2156 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2157 vcpu->arch.pv_time_enabled = false;
2158 else
2159 vcpu->arch.pv_time_enabled = true;
32cad84f 2160
18068523
GOC		 2161 break;
2162 }
344d9588
GN		 2163 case MSR_KVM_ASYNC_PF_EN:
2164 if (kvm_pv_enable_async_pf(vcpu, data))
2165 return 1;
2166 break;
c9aaa895
GC		 2167 case MSR_KVM_STEAL_TIME:
2168
2169 if (unlikely(!sched_info_on()))
2170 return 1;
2171
2172 if (data & KVM_STEAL_RESERVED_MASK)
2173 return 1;
2174
2175 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2176 data & KVM_STEAL_VALID_BITS,
2177 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2178 return 1;
2179
2180 vcpu->arch.st.msr_val = data;
2181
2182 if (!(data & KVM_MSR_ENABLED))
2183 break;
2184
2185 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2186
2187 preempt_disable();
2188 accumulate_steal_time(vcpu);
2189 preempt_enable();
2190
2191 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2192
2193 break;
ae7a2a3f
MT		 2194 case MSR_KVM_PV_EOI_EN:
2195 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2196 return 1;
2197 break;
c9aaa895 2198
890ca9ae
HY		 2199 case MSR_IA32_MCG_CTL:
2200 case MSR_IA32_MCG_STATUS:
81760dcc 2201 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2202 return set_msr_mce(vcpu, msr, data);
71db6023 2203
6912ac32
WH		 2204 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2205 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2206 pr = true; /* fall through */
2207 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2208 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2209 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2210 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2211
2212 if (pr || data != 0)
a737f256
CD		 2213 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2214 "0x%x data 0x%llx\n", msr, data);
5753785f 2215 break;
84e0cefa
JS		 2216 case MSR_K7_CLK_CTL:
2217 /*
2218 * Ignore all writes to this no longer documented MSR.
2219 * Writes are only relevant for old K7 processors,
2220 * all pre-dating SVM, but a recommended workaround from
4a969980 2221 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2222 * affected processor models on the command line, hence
2223 * the need to ignore the workaround.
2224 */
2225 break;
55cd8e5a
GN		 2226 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2227 if (kvm_hv_msr_partition_wide(msr)) {
2228 int r;
2229 mutex_lock(&vcpu->kvm->lock);
2230 r = set_msr_hyperv_pw(vcpu, msr, data);
2231 mutex_unlock(&vcpu->kvm->lock);
2232 return r;
2233 } else
2234 return set_msr_hyperv(vcpu, msr, data);
2235 break;
91c9c3ed 2236 case MSR_IA32_BBL_CR_CTL3:
2237 /* Drop writes to this legacy MSR -- see rdmsr
2238 * counterpart for further detail.
2239 */
a737f256 2240 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2241 break;
2b036c6b
BO		 2242 case MSR_AMD64_OSVW_ID_LENGTH:
2243 if (!guest_cpuid_has_osvw(vcpu))
2244 return 1;
2245 vcpu->arch.osvw.length = data;
2246 break;
2247 case MSR_AMD64_OSVW_STATUS:
2248 if (!guest_cpuid_has_osvw(vcpu))
2249 return 1;
2250 vcpu->arch.osvw.status = data;
2251 break;
15c4a640 2252 default:
ffde22ac
ES		 2253 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2254 return xen_hvm_config(vcpu, data);
c6702c9d 2255 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2256 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2257 if (!ignore_msrs) {
a737f256
CD		 2258 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2259 msr, data);
ed85c068
AP		 2260 return 1;
2261 } else {
a737f256
CD		 2262 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2263 msr, data);
ed85c068
AP		 2264 break;
2265 }
15c4a640
CO		 2266 }
2267 return 0;
2268}
2269EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2270
2271
2272/*
2273 * Reads an msr value (of 'msr_index') into 'pdata'.
2274 * Returns 0 on success, non-0 otherwise.
2275 * Assumes vcpu_load() was already called.
2276 */
609e36d3 2277int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2278{
609e36d3 2279 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2280}
ff651cb6 2281EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2282
890ca9ae 2283static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2284{
2285 u64 data;
890ca9ae
HY		 2286 u64 mcg_cap = vcpu->arch.mcg_cap;
2287 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2288
2289 switch (msr) {
15c4a640
CO		 2290 case MSR_IA32_P5_MC_ADDR:
2291 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2292 data = 0;
2293 break;
15c4a640 2294 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2295 data = vcpu->arch.mcg_cap;
2296 break;
c7ac679c 2297 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2298 if (!(mcg_cap & MCG_CTL_P))
2299 return 1;
2300 data = vcpu->arch.mcg_ctl;
2301 break;
2302 case MSR_IA32_MCG_STATUS:
2303 data = vcpu->arch.mcg_status;
2304 break;
2305 default:
2306 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2307 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2308 u32 offset = msr - MSR_IA32_MC0_CTL;
2309 data = vcpu->arch.mce_banks[offset];
2310 break;
2311 }
2312 return 1;
2313 }
2314 *pdata = data;
2315 return 0;
2316}
2317
55cd8e5a
GN		 2318static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2319{
2320 u64 data = 0;
2321 struct kvm *kvm = vcpu->kvm;
2322
2323 switch (msr) {
2324 case HV_X64_MSR_GUEST_OS_ID:
2325 data = kvm->arch.hv_guest_os_id;
2326 break;
2327 case HV_X64_MSR_HYPERCALL:
2328 data = kvm->arch.hv_hypercall;
2329 break;
e984097b
VR		 2330 case HV_X64_MSR_TIME_REF_COUNT: {
2331 data =
2332 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2333 break;
2334 }
2335 case HV_X64_MSR_REFERENCE_TSC:
2336 data = kvm->arch.hv_tsc_page;
2337 break;
55cd8e5a 2338 default:
a737f256 2339 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2340 return 1;
2341 }
2342
2343 *pdata = data;
2344 return 0;
2345}
2346
2347static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2348{
2349 u64 data = 0;
2350
2351 switch (msr) {
2352 case HV_X64_MSR_VP_INDEX: {
2353 int r;
2354 struct kvm_vcpu *v;
684851a1
TY		 2355 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2356 if (v == vcpu) {
55cd8e5a 2357 data = r;
684851a1
TY		 2358 break;
2359 }
2360 }
55cd8e5a
GN		 2361 break;
2362 }
10388a07
GN		 2363 case HV_X64_MSR_EOI:
2364 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2365 case HV_X64_MSR_ICR:
2366 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2367 case HV_X64_MSR_TPR:
2368 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2369 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2370 data = vcpu->arch.hv_vapic;
2371 break;
55cd8e5a 2372 default:
a737f256 2373 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2374 return 1;
2375 }
2376 *pdata = data;
2377 return 0;
2378}
2379
609e36d3 2380int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2381{
609e36d3 2382 switch (msr_info->index) {
890ca9ae 2383 case MSR_IA32_PLATFORM_ID:
15c4a640 2384 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2385 case MSR_IA32_DEBUGCTLMSR:
2386 case MSR_IA32_LASTBRANCHFROMIP:
2387 case MSR_IA32_LASTBRANCHTOIP:
2388 case MSR_IA32_LASTINTFROMIP:
2389 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2390 case MSR_K8_SYSCFG:
2391 case MSR_K7_HWCR:
61a6bd67 2392 case MSR_VM_HSAVE_PA:
1fdbd48c 2393 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2394 case MSR_AMD64_NB_CFG:
f7c6d140 2395 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2396 case MSR_AMD64_BU_CFG2:
609e36d3 2397 msr_info->data = 0;
15c4a640 2398 break;
6912ac32
WH		 2399 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2400 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2401 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2402 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2403 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2404 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2405 msr_info->data = 0;
5753785f 2406 break;
742bc670 2407 case MSR_IA32_UCODE_REV:
609e36d3 2408 msr_info->data = 0x100000000ULL;
742bc670 2409 break;
9ba075a6 2410 case MSR_MTRRcap:
9ba075a6 2411 case 0x200 ... 0x2ff:
ff53604b 2412 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2413 case 0xcd: /* fsb frequency */
609e36d3 2414 msr_info->data = 3;
15c4a640 2415 break;
7b914098
JS		 2416 /*
2417 * MSR_EBC_FREQUENCY_ID
2418 * Conservative value valid for even the basic CPU models.
2419 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2420 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2421 * and 266MHz for model 3, or 4. Set Core Clock
2422 * Frequency to System Bus Frequency Ratio to 1 (bits
2423 * 31:24) even though these are only valid for CPU
2424 * models > 2, however guests may end up dividing or
2425 * multiplying by zero otherwise.
2426 */
2427 case MSR_EBC_FREQUENCY_ID:
609e36d3 2428 msr_info->data = 1 << 24;
7b914098 2429 break;
15c4a640 2430 case MSR_IA32_APICBASE:
609e36d3 2431 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2432 break;
0105d1a5 2433 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2434 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2435 break;
a3e06bbe 2436 case MSR_IA32_TSCDEADLINE:
609e36d3 2437 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2438 break;
ba904635 2439 case MSR_IA32_TSC_ADJUST:
609e36d3 2440 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2441 break;
15c4a640 2442 case MSR_IA32_MISC_ENABLE:
609e36d3 2443 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2444 break;
64d60670
PB		 2445 case MSR_IA32_SMBASE:
2446 if (!msr_info->host_initiated)
2447 return 1;
2448 msr_info->data = vcpu->arch.smbase;
15c4a640 2449 break;
847f0ad8
AG		 2450 case MSR_IA32_PERF_STATUS:
2451 /* TSC increment by tick */
609e36d3 2452 msr_info->data = 1000ULL;
847f0ad8 2453 /* CPU multiplier */
b0996ae4 2454 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2455 break;
15c4a640 2456 case MSR_EFER:
609e36d3 2457 msr_info->data = vcpu->arch.efer;
15c4a640 2458 break;
18068523 2459 case MSR_KVM_WALL_CLOCK:
11c6bffa 2460 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2461 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2462 break;
2463 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2464 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2465 msr_info->data = vcpu->arch.time;
18068523 2466 break;
344d9588 2467 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2468 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2469 break;
c9aaa895 2470 case MSR_KVM_STEAL_TIME:
609e36d3 2471 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2472 break;
1d92128f 2473 case MSR_KVM_PV_EOI_EN:
609e36d3 2474 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2475 break;
890ca9ae
HY		 2476 case MSR_IA32_P5_MC_ADDR:
2477 case MSR_IA32_P5_MC_TYPE:
2478 case MSR_IA32_MCG_CAP:
2479 case MSR_IA32_MCG_CTL:
2480 case MSR_IA32_MCG_STATUS:
81760dcc 2481 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2482 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2483 case MSR_K7_CLK_CTL:
2484 /*
2485 * Provide expected ramp-up count for K7. All other
2486 * are set to zero, indicating minimum divisors for
2487 * every field.
2488 *
2489 * This prevents guest kernels on AMD host with CPU
2490 * type 6, model 8 and higher from exploding due to
2491 * the rdmsr failing.
2492 */
609e36d3 2493 msr_info->data = 0x20000000;
84e0cefa 2494 break;
55cd8e5a 2495 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
609e36d3 2496 if (kvm_hv_msr_partition_wide(msr_info->index)) {
55cd8e5a
GN		 2497 int r;
2498 mutex_lock(&vcpu->kvm->lock);
609e36d3 2499 r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data);
55cd8e5a
GN		 2500 mutex_unlock(&vcpu->kvm->lock);
2501 return r;
2502 } else
609e36d3 2503 return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data);
55cd8e5a 2504 break;
91c9c3ed 2505 case MSR_IA32_BBL_CR_CTL3:
2506 /* This legacy MSR exists but isn't fully documented in current
2507 * silicon. It is however accessed by winxp in very narrow
2508 * scenarios where it sets bit #19, itself documented as
2509 * a "reserved" bit. Best effort attempt to source coherent
2510 * read data here should the balance of the register be
2511 * interpreted by the guest:
2512 *
2513 * L2 cache control register 3: 64GB range, 256KB size,
2514 * enabled, latency 0x1, configured
2515 */
609e36d3 2516 msr_info->data = 0xbe702111;
91c9c3ed 2517 break;
2b036c6b
BO		 2518 case MSR_AMD64_OSVW_ID_LENGTH:
2519 if (!guest_cpuid_has_osvw(vcpu))
2520 return 1;
609e36d3 2521 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2522 break;
2523 case MSR_AMD64_OSVW_STATUS:
2524 if (!guest_cpuid_has_osvw(vcpu))
2525 return 1;
609e36d3 2526 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2527 break;
15c4a640 2528 default:
c6702c9d 2529 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2530 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2531 if (!ignore_msrs) {
609e36d3 2532 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2533 return 1;
2534 } else {
609e36d3
PB		 2535 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2536 msr_info->data = 0;
ed85c068
AP		 2537 }
2538 break;
15c4a640 2539 }
15c4a640
CO		 2540 return 0;
2541}
2542EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2543
313a3dc7
CO		 2544/*
2545 * Read or write a bunch of msrs. All parameters are kernel addresses.
2546 *
2547 * @return number of msrs set successfully.
2548 */
2549static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2550 struct kvm_msr_entry *entries,
2551 int (*do_msr)(struct kvm_vcpu *vcpu,
2552 unsigned index, u64 *data))
2553{
f656ce01 2554 int i, idx;
313a3dc7 2555
f656ce01 2556 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2557 for (i = 0; i < msrs->nmsrs; ++i)
2558 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2559 break;
f656ce01 2560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2561
313a3dc7
CO		 2562 return i;
2563}
2564
2565/*
2566 * Read or write a bunch of msrs. Parameters are user addresses.
2567 *
2568 * @return number of msrs set successfully.
2569 */
2570static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2571 int (*do_msr)(struct kvm_vcpu *vcpu,
2572 unsigned index, u64 *data),
2573 int writeback)
2574{
2575 struct kvm_msrs msrs;
2576 struct kvm_msr_entry *entries;
2577 int r, n;
2578 unsigned size;
2579
2580 r = -EFAULT;
2581 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2582 goto out;
2583
2584 r = -E2BIG;
2585 if (msrs.nmsrs >= MAX_IO_MSRS)
2586 goto out;
2587
313a3dc7 2588 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2589 entries = memdup_user(user_msrs->entries, size);
2590 if (IS_ERR(entries)) {
2591 r = PTR_ERR(entries);
313a3dc7 2592 goto out;
ff5c2c03 2593 }
313a3dc7
CO		 2594
2595 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2596 if (r < 0)
2597 goto out_free;
2598
2599 r = -EFAULT;
2600 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2601 goto out_free;
2602
2603 r = n;
2604
2605out_free:
7a73c028 2606 kfree(entries);
313a3dc7
CO		 2607out:
2608 return r;
2609}
2610
784aa3d7 2611int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2612{
2613 int r;
2614
2615 switch (ext) {
2616 case KVM_CAP_IRQCHIP:
2617 case KVM_CAP_HLT:
2618 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2619 case KVM_CAP_SET_TSS_ADDR:
07716717 2620 case KVM_CAP_EXT_CPUID:
9c15bb1d 2621 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2622 case KVM_CAP_CLOCKSOURCE:
7837699f 2623 case KVM_CAP_PIT:
a28e4f5a 2624 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2625 case KVM_CAP_MP_STATE:
ed848624 2626 case KVM_CAP_SYNC_MMU:
a355c85c 2627 case KVM_CAP_USER_NMI:
52d939a0 2628 case KVM_CAP_REINJECT_CONTROL:
4925663a 2629 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2630 case KVM_CAP_IOEVENTFD:
f848a5a8 2631 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2632 case KVM_CAP_PIT2:
e9f42757 2633 case KVM_CAP_PIT_STATE2:
b927a3ce 2634 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2635 case KVM_CAP_XEN_HVM:
afbcf7ab 2636 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2637 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2638 case KVM_CAP_HYPERV:
10388a07 2639 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2640 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2641 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2642 case KVM_CAP_DEBUGREGS:
d2be1651 2643 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2644 case KVM_CAP_XSAVE:
344d9588 2645 case KVM_CAP_ASYNC_PF:
92a1f12d 2646 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2647 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2648 case KVM_CAP_READONLY_MEM:
5f66b620 2649 case KVM_CAP_HYPERV_TIME:
100943c5 2650 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2651 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2652 case KVM_CAP_ENABLE_CAP_VM:
2653 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2654#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2655 case KVM_CAP_ASSIGN_DEV_IRQ:
2656 case KVM_CAP_PCI_2_3:
2657#endif
018d00d2
ZX		 2658 r = 1;
2659 break;
6d396b55
PB		 2660 case KVM_CAP_X86_SMM:
2661 /* SMBASE is usually relocated above 1M on modern chipsets,
2662 * and SMM handlers might indeed rely on 4G segment limits,
2663 * so do not report SMM to be available if real mode is
2664 * emulated via vm86 mode. Still, do not go to great lengths
2665 * to avoid userspace's usage of the feature, because it is a
2666 * fringe case that is not enabled except via specific settings
2667 * of the module parameters.
2668 */
2669 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2670 break;
542472b5
LV		 2671 case KVM_CAP_COALESCED_MMIO:
2672 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2673 break;
774ead3a
AK		 2674 case KVM_CAP_VAPIC:
2675 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2676 break;
f725230a 2677 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2678 r = KVM_SOFT_MAX_VCPUS;
2679 break;
2680 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2681 r = KVM_MAX_VCPUS;
2682 break;
a988b910 2683 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2684 r = KVM_USER_MEM_SLOTS;
a988b910 2685 break;
a68a6a72
MT		 2686 case KVM_CAP_PV_MMU: /* obsolete */
2687 r = 0;
2f333bcb 2688 break;
4cee4b72 2689#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2690 case KVM_CAP_IOMMU:
a1b60c1c 2691 r = iommu_present(&pci_bus_type);
62c476c7 2692 break;
4cee4b72 2693#endif
890ca9ae
HY		 2694 case KVM_CAP_MCE:
2695 r = KVM_MAX_MCE_BANKS;
2696 break;
2d5b5a66
SY		 2697 case KVM_CAP_XCRS:
2698 r = cpu_has_xsave;
2699 break;
92a1f12d
JR		 2700 case KVM_CAP_TSC_CONTROL:
2701 r = kvm_has_tsc_control;
2702 break;
018d00d2
ZX		 2703 default:
2704 r = 0;
2705 break;
2706 }
2707 return r;
2708
2709}
2710
043405e1
CO		 2711long kvm_arch_dev_ioctl(struct file *filp,
2712 unsigned int ioctl, unsigned long arg)
2713{
2714 void __user *argp = (void __user *)arg;
2715 long r;
2716
2717 switch (ioctl) {
2718 case KVM_GET_MSR_INDEX_LIST: {
2719 struct kvm_msr_list __user *user_msr_list = argp;
2720 struct kvm_msr_list msr_list;
2721 unsigned n;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2725 goto out;
2726 n = msr_list.nmsrs;
62ef68bb 2727 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2728 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2729 goto out;
2730 r = -E2BIG;
e125e7b6 2731 if (n < msr_list.nmsrs)
043405e1
CO		 2732 goto out;
2733 r = -EFAULT;
2734 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2735 num_msrs_to_save * sizeof(u32)))
2736 goto out;
e125e7b6 2737 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2738 &emulated_msrs,
62ef68bb 2739 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2740 goto out;
2741 r = 0;
2742 break;
2743 }
9c15bb1d
BP		 2744 case KVM_GET_SUPPORTED_CPUID:
2745 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2746 struct kvm_cpuid2 __user *cpuid_arg = argp;
2747 struct kvm_cpuid2 cpuid;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2751 goto out;
9c15bb1d
BP		 2752
2753 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2754 ioctl);
674eea0f
AK		 2755 if (r)
2756 goto out;
2757
2758 r = -EFAULT;
2759 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2760 goto out;
2761 r = 0;
2762 break;
2763 }
890ca9ae
HY		 2764 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2765 u64 mce_cap;
2766
2767 mce_cap = KVM_MCE_CAP_SUPPORTED;
2768 r = -EFAULT;
2769 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2770 goto out;
2771 r = 0;
2772 break;
2773 }
043405e1
CO		 2774 default:
2775 r = -EINVAL;
2776 }
2777out:
2778 return r;
2779}
2780
f5f48ee1
SY		 2781static void wbinvd_ipi(void *garbage)
2782{
2783 wbinvd();
2784}
2785
2786static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2787{
e0f0bbc5 2788 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2789}
2790
313a3dc7
CO		 2791void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2792{
f5f48ee1
SY		 2793 /* Address WBINVD may be executed by guest */
2794 if (need_emulate_wbinvd(vcpu)) {
2795 if (kvm_x86_ops->has_wbinvd_exit())
2796 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2797 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2798 smp_call_function_single(vcpu->cpu,
2799 wbinvd_ipi, NULL, 1);
2800 }
2801
313a3dc7 2802 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2803
0dd6a6ed
ZA		 2804 /* Apply any externally detected TSC adjustments (due to suspend) */
2805 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2806 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2807 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2808 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2809 }
8f6055cb 2810
48434c20 2811 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2812 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2813 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2814 if (tsc_delta < 0)
2815 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2816 if (check_tsc_unstable()) {
b183aa58
ZA		 2817 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2818 vcpu->arch.last_guest_tsc);
2819 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2820 vcpu->arch.tsc_catchup = 1;
c285545f 2821 }
d98d07ca
MT		 2822 /*
2823 * On a host with synchronized TSC, there is no need to update
2824 * kvmclock on vcpu->cpu migration
2825 */
2826 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2827 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2828 if (vcpu->cpu != cpu)
2829 kvm_migrate_timers(vcpu);
e48672fa 2830 vcpu->cpu = cpu;
6b7d7e76 2831 }
c9aaa895
GC		 2832
2833 accumulate_steal_time(vcpu);
2834 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2835}
2836
2837void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2838{
02daab21 2839 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2840 kvm_put_guest_fpu(vcpu);
6f526ec5 2841 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2842}
2843
313a3dc7
CO		 2844static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2845 struct kvm_lapic_state *s)
2846{
5a71785d 2847 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2848 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2849
2850 return 0;
2851}
2852
2853static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2854 struct kvm_lapic_state *s)
2855{
64eb0620 2856 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2857 update_cr8_intercept(vcpu);
313a3dc7
CO		 2858
2859 return 0;
2860}
2861
f77bc6a4
ZX		 2862static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2863 struct kvm_interrupt *irq)
2864{
02cdb50f 2865 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2866 return -EINVAL;
2867 if (irqchip_in_kernel(vcpu->kvm))
2868 return -ENXIO;
f77bc6a4 2869
66fd3f7f 2870 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2871 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2872
f77bc6a4
ZX		 2873 return 0;
2874}
2875
c4abb7c9
JK		 2876static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2877{
c4abb7c9 2878 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2879
2880 return 0;
2881}
2882
f077825a
PB		 2883static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2884{
64d60670
PB		 2885 kvm_make_request(KVM_REQ_SMI, vcpu);
2886
f077825a
PB		 2887 return 0;
2888}
2889
b209749f
AK		 2890static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2891 struct kvm_tpr_access_ctl *tac)
2892{
2893 if (tac->flags)
2894 return -EINVAL;
2895 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2896 return 0;
2897}
2898
890ca9ae
HY		 2899static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2900 u64 mcg_cap)
2901{
2902 int r;
2903 unsigned bank_num = mcg_cap & 0xff, bank;
2904
2905 r = -EINVAL;
a9e38c3e 2906 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2907 goto out;
2908 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2909 goto out;
2910 r = 0;
2911 vcpu->arch.mcg_cap = mcg_cap;
2912 /* Init IA32_MCG_CTL to all 1s */
2913 if (mcg_cap & MCG_CTL_P)
2914 vcpu->arch.mcg_ctl = ~(u64)0;
2915 /* Init IA32_MCi_CTL to all 1s */
2916 for (bank = 0; bank < bank_num; bank++)
2917 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2918out:
2919 return r;
2920}
2921
2922static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2923 struct kvm_x86_mce *mce)
2924{
2925 u64 mcg_cap = vcpu->arch.mcg_cap;
2926 unsigned bank_num = mcg_cap & 0xff;
2927 u64 *banks = vcpu->arch.mce_banks;
2928
2929 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2930 return -EINVAL;
2931 /*
2932 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2933 * reporting is disabled
2934 */
2935 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2936 vcpu->arch.mcg_ctl != ~(u64)0)
2937 return 0;
2938 banks += 4 * mce->bank;
2939 /*
2940 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2941 * reporting is disabled for the bank
2942 */
2943 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2944 return 0;
2945 if (mce->status & MCI_STATUS_UC) {
2946 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2947 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2948 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2949 return 0;
2950 }
2951 if (banks[1] & MCI_STATUS_VAL)
2952 mce->status |= MCI_STATUS_OVER;
2953 banks[2] = mce->addr;
2954 banks[3] = mce->misc;
2955 vcpu->arch.mcg_status = mce->mcg_status;
2956 banks[1] = mce->status;
2957 kvm_queue_exception(vcpu, MC_VECTOR);
2958 } else if (!(banks[1] & MCI_STATUS_VAL)
2959 || !(banks[1] & MCI_STATUS_UC)) {
2960 if (banks[1] & MCI_STATUS_VAL)
2961 mce->status |= MCI_STATUS_OVER;
2962 banks[2] = mce->addr;
2963 banks[3] = mce->misc;
2964 banks[1] = mce->status;
2965 } else
2966 banks[1] |= MCI_STATUS_OVER;
2967 return 0;
2968}
2969
3cfc3092
JK		 2970static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2971 struct kvm_vcpu_events *events)
2972{
7460fb4a 2973 process_nmi(vcpu);
03b82a30
JK		 2974 events->exception.injected =
2975 vcpu->arch.exception.pending &&
2976 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2977 events->exception.nr = vcpu->arch.exception.nr;
2978 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2979 events->exception.pad = 0;
3cfc3092
JK		 2980 events->exception.error_code = vcpu->arch.exception.error_code;
2981
03b82a30
JK		 2982 events->interrupt.injected =
2983 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2984 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2985 events->interrupt.soft = 0;
37ccdcbe 2986 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2987
2988 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2989 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2990 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2991 events->nmi.pad = 0;
3cfc3092 2992
66450a21 2993 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2994
f077825a
PB		 2995 events->smi.smm = is_smm(vcpu);
2996 events->smi.pending = vcpu->arch.smi_pending;
2997 events->smi.smm_inside_nmi =
2998 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2999 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3000
dab4b911 3001 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3002 | KVM_VCPUEVENT_VALID_SHADOW
3003 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3004 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3005}
3006
3007static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3008 struct kvm_vcpu_events *events)
3009{
dab4b911 3010 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3011 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3012 | KVM_VCPUEVENT_VALID_SHADOW
3013 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3014 return -EINVAL;
3015
7460fb4a 3016 process_nmi(vcpu);
3cfc3092
JK		 3017 vcpu->arch.exception.pending = events->exception.injected;
3018 vcpu->arch.exception.nr = events->exception.nr;
3019 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3020 vcpu->arch.exception.error_code = events->exception.error_code;
3021
3022 vcpu->arch.interrupt.pending = events->interrupt.injected;
3023 vcpu->arch.interrupt.nr = events->interrupt.nr;
3024 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3025 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3026 kvm_x86_ops->set_interrupt_shadow(vcpu,
3027 events->interrupt.shadow);
3cfc3092
JK		 3028
3029 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3030 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3031 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3032 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3033
66450a21
JK		 3034 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3035 kvm_vcpu_has_lapic(vcpu))
3036 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3037
f077825a
PB		 3038 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3039 if (events->smi.smm)
3040 vcpu->arch.hflags |= HF_SMM_MASK;
3041 else
3042 vcpu->arch.hflags &= ~HF_SMM_MASK;
3043 vcpu->arch.smi_pending = events->smi.pending;
3044 if (events->smi.smm_inside_nmi)
3045 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3046 else
3047 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3048 if (kvm_vcpu_has_lapic(vcpu)) {
3049 if (events->smi.latched_init)
3050 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3051 else
3052 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3053 }
3054 }
3055
3842d135
AK		 3056 kvm_make_request(KVM_REQ_EVENT, vcpu);
3057
3cfc3092
JK		 3058 return 0;
3059}
3060
a1efbe77
JK		 3061static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3062 struct kvm_debugregs *dbgregs)
3063{
73aaf249
JK		 3064 unsigned long val;
3065
a1efbe77 3066 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3067 kvm_get_dr(vcpu, 6, &val);
73aaf249 3068 dbgregs->dr6 = val;
a1efbe77
JK		 3069 dbgregs->dr7 = vcpu->arch.dr7;
3070 dbgregs->flags = 0;
97e69aa6 3071 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3072}
3073
3074static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3075 struct kvm_debugregs *dbgregs)
3076{
3077 if (dbgregs->flags)
3078 return -EINVAL;
3079
a1efbe77 3080 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3081 kvm_update_dr0123(vcpu);
a1efbe77 3082 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3083 kvm_update_dr6(vcpu);
a1efbe77 3084 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3085 kvm_update_dr7(vcpu);
a1efbe77 3086
a1efbe77
JK		 3087 return 0;
3088}
3089
df1daba7
PB		 3090#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3091
3092static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3093{
c47ada30 3094 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3095 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3096 u64 valid;
3097
3098 /*
3099 * Copy legacy XSAVE area, to avoid complications with CPUID
3100 * leaves 0 and 1 in the loop below.
3101 */
3102 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3103
3104 /* Set XSTATE_BV */
3105 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3106
3107 /*
3108 * Copy each region from the possibly compacted offset to the
3109 * non-compacted offset.
3110 */
3111 valid = xstate_bv & ~XSTATE_FPSSE;
3112 while (valid) {
3113 u64 feature = valid & -valid;
3114 int index = fls64(feature) - 1;
3115 void *src = get_xsave_addr(xsave, feature);
3116
3117 if (src) {
3118 u32 size, offset, ecx, edx;
3119 cpuid_count(XSTATE_CPUID, index,
3120 &size, &offset, &ecx, &edx);
3121 memcpy(dest + offset, src, size);
3122 }
3123
3124 valid -= feature;
3125 }
3126}
3127
3128static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3129{
c47ada30 3130 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3131 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3132 u64 valid;
3133
3134 /*
3135 * Copy legacy XSAVE area, to avoid complications with CPUID
3136 * leaves 0 and 1 in the loop below.
3137 */
3138 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3139
3140 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3141 xsave->header.xfeatures = xstate_bv;
df1daba7 3142 if (cpu_has_xsaves)
3a54450b 3143 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3144
3145 /*
3146 * Copy each region from the non-compacted offset to the
3147 * possibly compacted offset.
3148 */
3149 valid = xstate_bv & ~XSTATE_FPSSE;
3150 while (valid) {
3151 u64 feature = valid & -valid;
3152 int index = fls64(feature) - 1;
3153 void *dest = get_xsave_addr(xsave, feature);
3154
3155 if (dest) {
3156 u32 size, offset, ecx, edx;
3157 cpuid_count(XSTATE_CPUID, index,
3158 &size, &offset, &ecx, &edx);
3159 memcpy(dest, src + offset, size);
3160 } else
3161 WARN_ON_ONCE(1);
3162
3163 valid -= feature;
3164 }
3165}
3166
2d5b5a66
SY		 3167static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3168 struct kvm_xsave *guest_xsave)
3169{
4344ee98 3170 if (cpu_has_xsave) {
df1daba7
PB		 3171 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3172 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3173 } else {
2d5b5a66 3174 memcpy(guest_xsave->region,
7366ed77 3175 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3176 sizeof(struct fxregs_state));
2d5b5a66
SY		 3177 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3178 XSTATE_FPSSE;
3179 }
3180}
3181
3182static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3183 struct kvm_xsave *guest_xsave)
3184{
3185 u64 xstate_bv =
3186 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3187
d7876f1b
PB		 3188 if (cpu_has_xsave) {
3189 /*
3190 * Here we allow setting states that are not present in
3191 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3192 * with old userspace.
3193 */
4ff41732 3194 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3195 return -EINVAL;
df1daba7 3196 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3197 } else {
2d5b5a66
SY		 3198 if (xstate_bv & ~XSTATE_FPSSE)
3199 return -EINVAL;
7366ed77 3200 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3201 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3202 }
3203 return 0;
3204}
3205
3206static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3207 struct kvm_xcrs *guest_xcrs)
3208{
3209 if (!cpu_has_xsave) {
3210 guest_xcrs->nr_xcrs = 0;
3211 return;
3212 }
3213
3214 guest_xcrs->nr_xcrs = 1;
3215 guest_xcrs->flags = 0;
3216 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3217 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3218}
3219
3220static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3221 struct kvm_xcrs *guest_xcrs)
3222{
3223 int i, r = 0;
3224
3225 if (!cpu_has_xsave)
3226 return -EINVAL;
3227
3228 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3229 return -EINVAL;
3230
3231 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3232 /* Only support XCR0 currently */
c67a04cb 3233 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3234 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3235 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3236 break;
3237 }
3238 if (r)
3239 r = -EINVAL;
3240 return r;
3241}
3242
1c0b28c2
EM		 3243/*
3244 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3245 * stopped by the hypervisor. This function will be called from the host only.
3246 * EINVAL is returned when the host attempts to set the flag for a guest that
3247 * does not support pv clocks.
3248 */
3249static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3250{
0b79459b 3251 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3252 return -EINVAL;
51d59c6b 3253 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3254 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3255 return 0;
3256}
3257
313a3dc7
CO		 3258long kvm_arch_vcpu_ioctl(struct file *filp,
3259 unsigned int ioctl, unsigned long arg)
3260{
3261 struct kvm_vcpu *vcpu = filp->private_data;
3262 void __user *argp = (void __user *)arg;
3263 int r;
d1ac91d8
AK		 3264 union {
3265 struct kvm_lapic_state *lapic;
3266 struct kvm_xsave *xsave;
3267 struct kvm_xcrs *xcrs;
3268 void *buffer;
3269 } u;
3270
3271 u.buffer = NULL;
313a3dc7
CO		 3272 switch (ioctl) {
3273 case KVM_GET_LAPIC: {
2204ae3c
MT		 3274 r = -EINVAL;
3275 if (!vcpu->arch.apic)
3276 goto out;
d1ac91d8 3277 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3278
b772ff36 3279 r = -ENOMEM;
d1ac91d8 3280 if (!u.lapic)
b772ff36 3281 goto out;
d1ac91d8 3282 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3283 if (r)
3284 goto out;
3285 r = -EFAULT;
d1ac91d8 3286 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3287 goto out;
3288 r = 0;
3289 break;
3290 }
3291 case KVM_SET_LAPIC: {
2204ae3c
MT		 3292 r = -EINVAL;
3293 if (!vcpu->arch.apic)
3294 goto out;
ff5c2c03 3295 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3296 if (IS_ERR(u.lapic))
3297 return PTR_ERR(u.lapic);
ff5c2c03 3298
d1ac91d8 3299 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3300 break;
3301 }
f77bc6a4
ZX		 3302 case KVM_INTERRUPT: {
3303 struct kvm_interrupt irq;
3304
3305 r = -EFAULT;
3306 if (copy_from_user(&irq, argp, sizeof irq))
3307 goto out;
3308 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3309 break;
3310 }
c4abb7c9
JK		 3311 case KVM_NMI: {
3312 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3313 break;
3314 }
f077825a
PB		 3315 case KVM_SMI: {
3316 r = kvm_vcpu_ioctl_smi(vcpu);
3317 break;
3318 }
313a3dc7
CO		 3319 case KVM_SET_CPUID: {
3320 struct kvm_cpuid __user *cpuid_arg = argp;
3321 struct kvm_cpuid cpuid;
3322
3323 r = -EFAULT;
3324 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3325 goto out;
3326 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3327 break;
3328 }
07716717
DK		 3329 case KVM_SET_CPUID2: {
3330 struct kvm_cpuid2 __user *cpuid_arg = argp;
3331 struct kvm_cpuid2 cpuid;
3332
3333 r = -EFAULT;
3334 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3335 goto out;
3336 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3337 cpuid_arg->entries);
07716717
DK		 3338 break;
3339 }
3340 case KVM_GET_CPUID2: {
3341 struct kvm_cpuid2 __user *cpuid_arg = argp;
3342 struct kvm_cpuid2 cpuid;
3343
3344 r = -EFAULT;
3345 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3346 goto out;
3347 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3348 cpuid_arg->entries);
07716717
DK		 3349 if (r)
3350 goto out;
3351 r = -EFAULT;
3352 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3353 goto out;
3354 r = 0;
3355 break;
3356 }
313a3dc7 3357 case KVM_GET_MSRS:
609e36d3 3358 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3359 break;
3360 case KVM_SET_MSRS:
3361 r = msr_io(vcpu, argp, do_set_msr, 0);
3362 break;
b209749f
AK		 3363 case KVM_TPR_ACCESS_REPORTING: {
3364 struct kvm_tpr_access_ctl tac;
3365
3366 r = -EFAULT;
3367 if (copy_from_user(&tac, argp, sizeof tac))
3368 goto out;
3369 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3370 if (r)
3371 goto out;
3372 r = -EFAULT;
3373 if (copy_to_user(argp, &tac, sizeof tac))
3374 goto out;
3375 r = 0;
3376 break;
3377 };
b93463aa
AK		 3378 case KVM_SET_VAPIC_ADDR: {
3379 struct kvm_vapic_addr va;
3380
3381 r = -EINVAL;
3382 if (!irqchip_in_kernel(vcpu->kvm))
3383 goto out;
3384 r = -EFAULT;
3385 if (copy_from_user(&va, argp, sizeof va))
3386 goto out;
fda4e2e8 3387 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3388 break;
3389 }
890ca9ae
HY		 3390 case KVM_X86_SETUP_MCE: {
3391 u64 mcg_cap;
3392
3393 r = -EFAULT;
3394 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3395 goto out;
3396 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3397 break;
3398 }
3399 case KVM_X86_SET_MCE: {
3400 struct kvm_x86_mce mce;
3401
3402 r = -EFAULT;
3403 if (copy_from_user(&mce, argp, sizeof mce))
3404 goto out;
3405 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3406 break;
3407 }
3cfc3092
JK		 3408 case KVM_GET_VCPU_EVENTS: {
3409 struct kvm_vcpu_events events;
3410
3411 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3412
3413 r = -EFAULT;
3414 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3415 break;
3416 r = 0;
3417 break;
3418 }
3419 case KVM_SET_VCPU_EVENTS: {
3420 struct kvm_vcpu_events events;
3421
3422 r = -EFAULT;
3423 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3424 break;
3425
3426 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3427 break;
3428 }
a1efbe77
JK		 3429 case KVM_GET_DEBUGREGS: {
3430 struct kvm_debugregs dbgregs;
3431
3432 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3433
3434 r = -EFAULT;
3435 if (copy_to_user(argp, &dbgregs,
3436 sizeof(struct kvm_debugregs)))
3437 break;
3438 r = 0;
3439 break;
3440 }
3441 case KVM_SET_DEBUGREGS: {
3442 struct kvm_debugregs dbgregs;
3443
3444 r = -EFAULT;
3445 if (copy_from_user(&dbgregs, argp,
3446 sizeof(struct kvm_debugregs)))
3447 break;
3448
3449 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3450 break;
3451 }
2d5b5a66 3452 case KVM_GET_XSAVE: {
d1ac91d8 3453 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3454 r = -ENOMEM;
d1ac91d8 3455 if (!u.xsave)
2d5b5a66
SY		 3456 break;
3457
d1ac91d8 3458 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3459
3460 r = -EFAULT;
d1ac91d8 3461 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3462 break;
3463 r = 0;
3464 break;
3465 }
3466 case KVM_SET_XSAVE: {
ff5c2c03 3467 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3468 if (IS_ERR(u.xsave))
3469 return PTR_ERR(u.xsave);
2d5b5a66 3470
d1ac91d8 3471 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3472 break;
3473 }
3474 case KVM_GET_XCRS: {
d1ac91d8 3475 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3476 r = -ENOMEM;
d1ac91d8 3477 if (!u.xcrs)
2d5b5a66
SY		 3478 break;
3479
d1ac91d8 3480 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3481
3482 r = -EFAULT;
d1ac91d8 3483 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3484 sizeof(struct kvm_xcrs)))
3485 break;
3486 r = 0;
3487 break;
3488 }
3489 case KVM_SET_XCRS: {
ff5c2c03 3490 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3491 if (IS_ERR(u.xcrs))
3492 return PTR_ERR(u.xcrs);
2d5b5a66 3493
d1ac91d8 3494 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3495 break;
3496 }
92a1f12d
JR		 3497 case KVM_SET_TSC_KHZ: {
3498 u32 user_tsc_khz;
3499
3500 r = -EINVAL;
92a1f12d
JR		 3501 user_tsc_khz = (u32)arg;
3502
3503 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3504 goto out;
3505
cc578287
ZA		 3506 if (user_tsc_khz == 0)
3507 user_tsc_khz = tsc_khz;
3508
3509 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3510
3511 r = 0;
3512 goto out;
3513 }
3514 case KVM_GET_TSC_KHZ: {
cc578287 3515 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3516 goto out;
3517 }
1c0b28c2
EM		 3518 case KVM_KVMCLOCK_CTRL: {
3519 r = kvm_set_guest_paused(vcpu);
3520 goto out;
3521 }
313a3dc7
CO		 3522 default:
3523 r = -EINVAL;
3524 }
3525out:
d1ac91d8 3526 kfree(u.buffer);
313a3dc7
CO		 3527 return r;
3528}
3529
5b1c1493
CO		 3530int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3531{
3532 return VM_FAULT_SIGBUS;
3533}
3534
1fe779f8
CO		 3535static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3536{
3537 int ret;
3538
3539 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3540 return -EINVAL;
1fe779f8
CO		 3541 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3542 return ret;
3543}
3544
b927a3ce
SY		 3545static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3546 u64 ident_addr)
3547{
3548 kvm->arch.ept_identity_map_addr = ident_addr;
3549 return 0;
3550}
3551
1fe779f8
CO		 3552static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3553 u32 kvm_nr_mmu_pages)
3554{
3555 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3556 return -EINVAL;
3557
79fac95e 3558 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3559
3560 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3561 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3562
79fac95e 3563 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3564 return 0;
3565}
3566
3567static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3568{
39de71ec 3569 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3570}
3571
1fe779f8
CO		 3572static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3573{
3574 int r;
3575
3576 r = 0;
3577 switch (chip->chip_id) {
3578 case KVM_IRQCHIP_PIC_MASTER:
3579 memcpy(&chip->chip.pic,
3580 &pic_irqchip(kvm)->pics[0],
3581 sizeof(struct kvm_pic_state));
3582 break;
3583 case KVM_IRQCHIP_PIC_SLAVE:
3584 memcpy(&chip->chip.pic,
3585 &pic_irqchip(kvm)->pics[1],
3586 sizeof(struct kvm_pic_state));
3587 break;
3588 case KVM_IRQCHIP_IOAPIC:
eba0226b 3589 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3590 break;
3591 default:
3592 r = -EINVAL;
3593 break;
3594 }
3595 return r;
3596}
3597
3598static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3599{
3600 int r;
3601
3602 r = 0;
3603 switch (chip->chip_id) {
3604 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3605 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3606 memcpy(&pic_irqchip(kvm)->pics[0],
3607 &chip->chip.pic,
3608 sizeof(struct kvm_pic_state));
f4f51050 3609 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3610 break;
3611 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3612 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3613 memcpy(&pic_irqchip(kvm)->pics[1],
3614 &chip->chip.pic,
3615 sizeof(struct kvm_pic_state));
f4f51050 3616 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3617 break;
3618 case KVM_IRQCHIP_IOAPIC:
eba0226b 3619 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3620 break;
3621 default:
3622 r = -EINVAL;
3623 break;
3624 }
3625 kvm_pic_update_irq(pic_irqchip(kvm));
3626 return r;
3627}
3628
e0f63cb9
SY		 3629static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3630{
3631 int r = 0;
3632
894a9c55 3633 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3634 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3635 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3636 return r;
3637}
3638
3639static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3640{
3641 int r = 0;
3642
894a9c55 3643 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3644 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3645 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3646 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3647 return r;
3648}
3649
3650static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3651{
3652 int r = 0;
3653
3654 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3655 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3656 sizeof(ps->channels));
3657 ps->flags = kvm->arch.vpit->pit_state.flags;
3658 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3659 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3660 return r;
3661}
3662
3663static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3664{
3665 int r = 0, start = 0;
3666 u32 prev_legacy, cur_legacy;
3667 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3668 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3669 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3670 if (!prev_legacy && cur_legacy)
3671 start = 1;
3672 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3673 sizeof(kvm->arch.vpit->pit_state.channels));
3674 kvm->arch.vpit->pit_state.flags = ps->flags;
3675 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3676 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3677 return r;
3678}
3679
52d939a0
MT		 3680static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3681 struct kvm_reinject_control *control)
3682{
3683 if (!kvm->arch.vpit)
3684 return -ENXIO;
894a9c55 3685 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3686 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3687 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3688 return 0;
3689}
3690
95d4c16c 3691/**
60c34612
TY		 3692 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3693 * @kvm: kvm instance
3694 * @log: slot id and address to which we copy the log
95d4c16c 3695 *
e108ff2f
PB		 3696 * Steps 1-4 below provide general overview of dirty page logging. See
3697 * kvm_get_dirty_log_protect() function description for additional details.
3698 *
3699 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3700 * always flush the TLB (step 4) even if previous step failed and the dirty
3701 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3702 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3703 * writes will be marked dirty for next log read.
95d4c16c 3704 *
60c34612
TY		 3705 * 1. Take a snapshot of the bit and clear it if needed.
3706 * 2. Write protect the corresponding page.
e108ff2f
PB		 3707 * 3. Copy the snapshot to the userspace.
3708 * 4. Flush TLB's if needed.
5bb064dc 3709 */
60c34612 3710int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3711{
60c34612 3712 bool is_dirty = false;
e108ff2f 3713 int r;
5bb064dc 3714
79fac95e 3715 mutex_lock(&kvm->slots_lock);
5bb064dc 3716
88178fd4
KH		 3717 /*
3718 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3719 */
3720 if (kvm_x86_ops->flush_log_dirty)
3721 kvm_x86_ops->flush_log_dirty(kvm);
3722
e108ff2f 3723 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3724
3725 /*
3726 * All the TLBs can be flushed out of mmu lock, see the comments in
3727 * kvm_mmu_slot_remove_write_access().
3728 */
e108ff2f 3729 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3730 if (is_dirty)
3731 kvm_flush_remote_tlbs(kvm);
3732
79fac95e 3733 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3734 return r;
3735}
3736
aa2fbe6d
YZ		 3737int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3738 bool line_status)
23d43cf9
CD		 3739{
3740 if (!irqchip_in_kernel(kvm))
3741 return -ENXIO;
3742
3743 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3744 irq_event->irq, irq_event->level,
3745 line_status);
23d43cf9
CD		 3746 return 0;
3747}
3748
90de4a18
NA		 3749static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3750 struct kvm_enable_cap *cap)
3751{
3752 int r;
3753
3754 if (cap->flags)
3755 return -EINVAL;
3756
3757 switch (cap->cap) {
3758 case KVM_CAP_DISABLE_QUIRKS:
3759 kvm->arch.disabled_quirks = cap->args[0];
3760 r = 0;
3761 break;
3762 default:
3763 r = -EINVAL;
3764 break;
3765 }
3766 return r;
3767}
3768
1fe779f8
CO		 3769long kvm_arch_vm_ioctl(struct file *filp,
3770 unsigned int ioctl, unsigned long arg)
3771{
3772 struct kvm *kvm = filp->private_data;
3773 void __user *argp = (void __user *)arg;
367e1319 3774 int r = -ENOTTY;
f0d66275
DH		 3775 /*
3776 * This union makes it completely explicit to gcc-3.x
3777 * that these two variables' stack usage should be
3778 * combined, not added together.
3779 */
3780 union {
3781 struct kvm_pit_state ps;
e9f42757 3782 struct kvm_pit_state2 ps2;
c5ff41ce 3783 struct kvm_pit_config pit_config;
f0d66275 3784 } u;
1fe779f8
CO		 3785
3786 switch (ioctl) {
3787 case KVM_SET_TSS_ADDR:
3788 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3789 break;
b927a3ce
SY		 3790 case KVM_SET_IDENTITY_MAP_ADDR: {
3791 u64 ident_addr;
3792
3793 r = -EFAULT;
3794 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3795 goto out;
3796 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3797 break;
3798 }
1fe779f8
CO		 3799 case KVM_SET_NR_MMU_PAGES:
3800 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3801 break;
3802 case KVM_GET_NR_MMU_PAGES:
3803 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3804 break;
3ddea128
MT		 3805 case KVM_CREATE_IRQCHIP: {
3806 struct kvm_pic *vpic;
3807
3808 mutex_lock(&kvm->lock);
3809 r = -EEXIST;
3810 if (kvm->arch.vpic)
3811 goto create_irqchip_unlock;
3e515705
AK		 3812 r = -EINVAL;
3813 if (atomic_read(&kvm->online_vcpus))
3814 goto create_irqchip_unlock;
1fe779f8 3815 r = -ENOMEM;
3ddea128
MT		 3816 vpic = kvm_create_pic(kvm);
3817 if (vpic) {
1fe779f8
CO		 3818 r = kvm_ioapic_init(kvm);
3819 if (r) {
175504cd 3820 mutex_lock(&kvm->slots_lock);
72bb2fcd 3821 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3822 &vpic->dev_master);
3823 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3824 &vpic->dev_slave);
3825 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3826 &vpic->dev_eclr);
175504cd 3827 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3828 kfree(vpic);
3829 goto create_irqchip_unlock;
1fe779f8
CO		 3830 }
3831 } else
3ddea128
MT		 3832 goto create_irqchip_unlock;
3833 smp_wmb();
3834 kvm->arch.vpic = vpic;
3835 smp_wmb();
399ec807
AK		 3836 r = kvm_setup_default_irq_routing(kvm);
3837 if (r) {
175504cd 3838 mutex_lock(&kvm->slots_lock);
3ddea128 3839 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3840 kvm_ioapic_destroy(kvm);
3841 kvm_destroy_pic(kvm);
3ddea128 3842 mutex_unlock(&kvm->irq_lock);
175504cd 3843 mutex_unlock(&kvm->slots_lock);
399ec807 3844 }
3ddea128
MT		 3845 create_irqchip_unlock:
3846 mutex_unlock(&kvm->lock);
1fe779f8 3847 break;
3ddea128 3848 }
7837699f 3849 case KVM_CREATE_PIT:
c5ff41ce
JK		 3850 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3851 goto create_pit;
3852 case KVM_CREATE_PIT2:
3853 r = -EFAULT;
3854 if (copy_from_user(&u.pit_config, argp,
3855 sizeof(struct kvm_pit_config)))
3856 goto out;
3857 create_pit:
79fac95e 3858 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3859 r = -EEXIST;
3860 if (kvm->arch.vpit)
3861 goto create_pit_unlock;
7837699f 3862 r = -ENOMEM;
c5ff41ce 3863 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3864 if (kvm->arch.vpit)
3865 r = 0;
269e05e4 3866 create_pit_unlock:
79fac95e 3867 mutex_unlock(&kvm->slots_lock);
7837699f 3868 break;
1fe779f8
CO		 3869 case KVM_GET_IRQCHIP: {
3870 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3871 struct kvm_irqchip *chip;
1fe779f8 3872
ff5c2c03
SL		 3873 chip = memdup_user(argp, sizeof(*chip));
3874 if (IS_ERR(chip)) {
3875 r = PTR_ERR(chip);
1fe779f8 3876 goto out;
ff5c2c03
SL		 3877 }
3878
1fe779f8
CO		 3879 r = -ENXIO;
3880 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3881 goto get_irqchip_out;
3882 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3883 if (r)
f0d66275 3884 goto get_irqchip_out;
1fe779f8 3885 r = -EFAULT;
f0d66275
DH		 3886 if (copy_to_user(argp, chip, sizeof *chip))
3887 goto get_irqchip_out;
1fe779f8 3888 r = 0;
f0d66275
DH		 3889 get_irqchip_out:
3890 kfree(chip);
1fe779f8
CO		 3891 break;
3892 }
3893 case KVM_SET_IRQCHIP: {
3894 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3895 struct kvm_irqchip *chip;
1fe779f8 3896
ff5c2c03
SL		 3897 chip = memdup_user(argp, sizeof(*chip));
3898 if (IS_ERR(chip)) {
3899 r = PTR_ERR(chip);
1fe779f8 3900 goto out;
ff5c2c03
SL		 3901 }
3902
1fe779f8
CO		 3903 r = -ENXIO;
3904 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3905 goto set_irqchip_out;
3906 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3907 if (r)
f0d66275 3908 goto set_irqchip_out;
1fe779f8 3909 r = 0;
f0d66275
DH		 3910 set_irqchip_out:
3911 kfree(chip);
1fe779f8
CO		 3912 break;
3913 }
e0f63cb9 3914 case KVM_GET_PIT: {
e0f63cb9 3915 r = -EFAULT;
f0d66275 3916 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3917 goto out;
3918 r = -ENXIO;
3919 if (!kvm->arch.vpit)
3920 goto out;
f0d66275 3921 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3922 if (r)
3923 goto out;
3924 r = -EFAULT;
f0d66275 3925 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3926 goto out;
3927 r = 0;
3928 break;
3929 }
3930 case KVM_SET_PIT: {
e0f63cb9 3931 r = -EFAULT;
f0d66275 3932 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3933 goto out;
3934 r = -ENXIO;
3935 if (!kvm->arch.vpit)
3936 goto out;
f0d66275 3937 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3938 break;
3939 }
e9f42757
BK		 3940 case KVM_GET_PIT2: {
3941 r = -ENXIO;
3942 if (!kvm->arch.vpit)
3943 goto out;
3944 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3945 if (r)
3946 goto out;
3947 r = -EFAULT;
3948 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3949 goto out;
3950 r = 0;
3951 break;
3952 }
3953 case KVM_SET_PIT2: {
3954 r = -EFAULT;
3955 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3956 goto out;
3957 r = -ENXIO;
3958 if (!kvm->arch.vpit)
3959 goto out;
3960 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3961 break;
3962 }
52d939a0
MT		 3963 case KVM_REINJECT_CONTROL: {
3964 struct kvm_reinject_control control;
3965 r = -EFAULT;
3966 if (copy_from_user(&control, argp, sizeof(control)))
3967 goto out;
3968 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3969 break;
3970 }
ffde22ac
ES		 3971 case KVM_XEN_HVM_CONFIG: {
3972 r = -EFAULT;
3973 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3974 sizeof(struct kvm_xen_hvm_config)))
3975 goto out;
3976 r = -EINVAL;
3977 if (kvm->arch.xen_hvm_config.flags)
3978 goto out;
3979 r = 0;
3980 break;
3981 }
afbcf7ab 3982 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3983 struct kvm_clock_data user_ns;
3984 u64 now_ns;
3985 s64 delta;
3986
3987 r = -EFAULT;
3988 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3989 goto out;
3990
3991 r = -EINVAL;
3992 if (user_ns.flags)
3993 goto out;
3994
3995 r = 0;
395c6b0a 3996 local_irq_disable();
759379dd 3997 now_ns = get_kernel_ns();
afbcf7ab 3998 delta = user_ns.clock - now_ns;
395c6b0a 3999 local_irq_enable();
afbcf7ab 4000 kvm->arch.kvmclock_offset = delta;
2e762ff7 4001 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4002 break;
4003 }
4004 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4005 struct kvm_clock_data user_ns;
4006 u64 now_ns;
4007
395c6b0a 4008 local_irq_disable();
759379dd 4009 now_ns = get_kernel_ns();
afbcf7ab 4010 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4011 local_irq_enable();
afbcf7ab 4012 user_ns.flags = 0;
97e69aa6 4013 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4014
4015 r = -EFAULT;
4016 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4017 goto out;
4018 r = 0;
4019 break;
4020 }
90de4a18
NA		 4021 case KVM_ENABLE_CAP: {
4022 struct kvm_enable_cap cap;
afbcf7ab 4023
90de4a18
NA		 4024 r = -EFAULT;
4025 if (copy_from_user(&cap, argp, sizeof(cap)))
4026 goto out;
4027 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4028 break;
4029 }
1fe779f8 4030 default:
c274e03a 4031 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4032 }
4033out:
4034 return r;
4035}
4036
a16b043c 4037static void kvm_init_msr_list(void)
043405e1
CO		 4038{
4039 u32 dummy[2];
4040 unsigned i, j;
4041
62ef68bb 4042 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4043 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4044 continue;
93c4adc7
PB		 4045
4046 /*
4047 * Even MSRs that are valid in the host may not be exposed
4048 * to the guests in some cases. We could work around this
4049 * in VMX with the generic MSR save/load machinery, but it
4050 * is not really worthwhile since it will really only
4051 * happen with nested virtualization.
4052 */
4053 switch (msrs_to_save[i]) {
4054 case MSR_IA32_BNDCFGS:
4055 if (!kvm_x86_ops->mpx_supported())
4056 continue;
4057 break;
4058 default:
4059 break;
4060 }
4061
043405e1
CO		 4062 if (j < i)
4063 msrs_to_save[j] = msrs_to_save[i];
4064 j++;
4065 }
4066 num_msrs_to_save = j;
62ef68bb
PB		 4067
4068 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4069 switch (emulated_msrs[i]) {
6d396b55
PB		 4070 case MSR_IA32_SMBASE:
4071 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4072 continue;
4073 break;
62ef68bb
PB		 4074 default:
4075 break;
4076 }
4077
4078 if (j < i)
4079 emulated_msrs[j] = emulated_msrs[i];
4080 j++;
4081 }
4082 num_emulated_msrs = j;
043405e1
CO		 4083}
4084
bda9020e
MT		 4085static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4086 const void *v)
bbd9b64e 4087{
70252a10
AK		 4088 int handled = 0;
4089 int n;
4090
4091 do {
4092 n = min(len, 8);
4093 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4094 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4095 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4096 break;
4097 handled += n;
4098 addr += n;
4099 len -= n;
4100 v += n;
4101 } while (len);
bbd9b64e 4102
70252a10 4103 return handled;
bbd9b64e
CO		 4104}
4105
bda9020e 4106static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4107{
70252a10
AK		 4108 int handled = 0;
4109 int n;
4110
4111 do {
4112 n = min(len, 8);
4113 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4114 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4115 addr, n, v))
4116 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4117 break;
4118 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4119 handled += n;
4120 addr += n;
4121 len -= n;
4122 v += n;
4123 } while (len);
bbd9b64e 4124
70252a10 4125 return handled;
bbd9b64e
CO		 4126}
4127
2dafc6c2
GN		 4128static void kvm_set_segment(struct kvm_vcpu *vcpu,
4129 struct kvm_segment *var, int seg)
4130{
4131 kvm_x86_ops->set_segment(vcpu, var, seg);
4132}
4133
4134void kvm_get_segment(struct kvm_vcpu *vcpu,
4135 struct kvm_segment *var, int seg)
4136{
4137 kvm_x86_ops->get_segment(vcpu, var, seg);
4138}
4139
54987b7a
PB		 4140gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4141 struct x86_exception *exception)
02f59dc9
JR		 4142{
4143 gpa_t t_gpa;
02f59dc9
JR		 4144
4145 BUG_ON(!mmu_is_nested(vcpu));
4146
4147 /* NPT walks are always user-walks */
4148 access |= PFERR_USER_MASK;
54987b7a 4149 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4150
4151 return t_gpa;
4152}
4153
ab9ae313
AK		 4154gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4155 struct x86_exception *exception)
1871c602
GN		 4156{
4157 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4158 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4159}
4160
ab9ae313
AK		 4161 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4162 struct x86_exception *exception)
1871c602
GN		 4163{
4164 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4165 access |= PFERR_FETCH_MASK;
ab9ae313 4166 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4167}
4168
ab9ae313
AK		 4169gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4170 struct x86_exception *exception)
1871c602
GN		 4171{
4172 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4173 access |= PFERR_WRITE_MASK;
ab9ae313 4174 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4175}
4176
4177/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4178gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4179 struct x86_exception *exception)
1871c602 4180{
ab9ae313 4181 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4182}
4183
4184static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4185 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4186 struct x86_exception *exception)
bbd9b64e
CO		 4187{
4188 void *data = val;
10589a46 4189 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4190
4191 while (bytes) {
14dfe855 4192 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4193 exception);
bbd9b64e 4194 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4195 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4196 int ret;
4197
bcc55cba 4198 if (gpa == UNMAPPED_GVA)
ab9ae313 4199 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4200 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4201 offset, toread);
10589a46 4202 if (ret < 0) {
c3cd7ffa 4203 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4204 goto out;
4205 }
bbd9b64e 4206
77c2002e
IE		 4207 bytes -= toread;
4208 data += toread;
4209 addr += toread;
bbd9b64e 4210 }
10589a46 4211out:
10589a46 4212 return r;
bbd9b64e 4213}
77c2002e 4214
1871c602 4215/* used for instruction fetching */
0f65dd70
AK		 4216static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4217 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4218 struct x86_exception *exception)
1871c602 4219{
0f65dd70 4220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4222 unsigned offset;
4223 int ret;
0f65dd70 4224
44583cba
PB		 4225 /* Inline kvm_read_guest_virt_helper for speed. */
4226 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4227 exception);
4228 if (unlikely(gpa == UNMAPPED_GVA))
4229 return X86EMUL_PROPAGATE_FAULT;
4230
4231 offset = addr & (PAGE_SIZE-1);
4232 if (WARN_ON(offset + bytes > PAGE_SIZE))
4233 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4234 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4235 offset, bytes);
44583cba
PB		 4236 if (unlikely(ret < 0))
4237 return X86EMUL_IO_NEEDED;
4238
4239 return X86EMUL_CONTINUE;
1871c602
GN		 4240}
4241
064aea77 4242int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4243 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4244 struct x86_exception *exception)
1871c602 4245{
0f65dd70 4246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4247 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4248
1871c602 4249 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4250 exception);
1871c602 4251}
064aea77 4252EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4253
0f65dd70
AK		 4254static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4255 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4256 struct x86_exception *exception)
1871c602 4257{
0f65dd70 4258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4259 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4260}
4261
6a4d7550 4262int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4263 gva_t addr, void *val,
2dafc6c2 4264 unsigned int bytes,
bcc55cba 4265 struct x86_exception *exception)
77c2002e 4266{
0f65dd70 4267 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4268 void *data = val;
4269 int r = X86EMUL_CONTINUE;
4270
4271 while (bytes) {
14dfe855
JR		 4272 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4273 PFERR_WRITE_MASK,
ab9ae313 4274 exception);
77c2002e
IE		 4275 unsigned offset = addr & (PAGE_SIZE-1);
4276 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4277 int ret;
4278
bcc55cba 4279 if (gpa == UNMAPPED_GVA)
ab9ae313 4280 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4281 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4282 if (ret < 0) {
c3cd7ffa 4283 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4284 goto out;
4285 }
4286
4287 bytes -= towrite;
4288 data += towrite;
4289 addr += towrite;
4290 }
4291out:
4292 return r;
4293}
6a4d7550 4294EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4295
af7cc7d1
XG		 4296static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4297 gpa_t *gpa, struct x86_exception *exception,
4298 bool write)
4299{
97d64b78
AK		 4300 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4301 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4302
97d64b78 4303 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4304 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4305 vcpu->arch.access, access)) {
bebb106a
XG		 4306 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4307 (gva & (PAGE_SIZE - 1));
4f022648 4308 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4309 return 1;
4310 }
4311
af7cc7d1
XG		 4312 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4313
4314 if (*gpa == UNMAPPED_GVA)
4315 return -1;
4316
4317 /* For APIC access vmexit */
4318 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4319 return 1;
4320
4f022648
XG		 4321 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4322 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4323 return 1;
4f022648 4324 }
bebb106a 4325
af7cc7d1
XG		 4326 return 0;
4327}
4328
3200f405 4329int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4330 const void *val, int bytes)
bbd9b64e
CO		 4331{
4332 int ret;
4333
54bf36aa 4334 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4335 if (ret < 0)
bbd9b64e 4336 return 0;
f57f2ef5 4337 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4338 return 1;
4339}
4340
77d197b2
XG		 4341struct read_write_emulator_ops {
4342 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4343 int bytes);
4344 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4345 void *val, int bytes);
4346 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4347 int bytes, void *val);
4348 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4349 void *val, int bytes);
4350 bool write;
4351};
4352
4353static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4354{
4355 if (vcpu->mmio_read_completed) {
77d197b2 4356 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4357 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4358 vcpu->mmio_read_completed = 0;
4359 return 1;
4360 }
4361
4362 return 0;
4363}
4364
4365static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4366 void *val, int bytes)
4367{
54bf36aa 4368 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4369}
4370
4371static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4372 void *val, int bytes)
4373{
4374 return emulator_write_phys(vcpu, gpa, val, bytes);
4375}
4376
4377static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4378{
4379 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4380 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4381}
4382
4383static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 void *val, int bytes)
4385{
4386 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4387 return X86EMUL_IO_NEEDED;
4388}
4389
4390static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4391 void *val, int bytes)
4392{
f78146b0
AK		 4393 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4394
87da7e66 4395 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4396 return X86EMUL_CONTINUE;
4397}
4398
0fbe9b0b 4399static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4400 .read_write_prepare = read_prepare,
4401 .read_write_emulate = read_emulate,
4402 .read_write_mmio = vcpu_mmio_read,
4403 .read_write_exit_mmio = read_exit_mmio,
4404};
4405
0fbe9b0b 4406static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4407 .read_write_emulate = write_emulate,
4408 .read_write_mmio = write_mmio,
4409 .read_write_exit_mmio = write_exit_mmio,
4410 .write = true,
4411};
4412
22388a3c
XG		 4413static int emulator_read_write_onepage(unsigned long addr, void *val,
4414 unsigned int bytes,
4415 struct x86_exception *exception,
4416 struct kvm_vcpu *vcpu,
0fbe9b0b 4417 const struct read_write_emulator_ops *ops)
bbd9b64e 4418{
af7cc7d1
XG		 4419 gpa_t gpa;
4420 int handled, ret;
22388a3c 4421 bool write = ops->write;
f78146b0 4422 struct kvm_mmio_fragment *frag;
10589a46 4423
22388a3c 4424 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4425
af7cc7d1 4426 if (ret < 0)
bbd9b64e 4427 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4428
4429 /* For APIC access vmexit */
af7cc7d1 4430 if (ret)
bbd9b64e
CO		 4431 goto mmio;
4432
22388a3c 4433 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4434 return X86EMUL_CONTINUE;
4435
4436mmio:
4437 /*
4438 * Is this MMIO handled locally?
4439 */
22388a3c 4440 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4441 if (handled == bytes)
bbd9b64e 4442 return X86EMUL_CONTINUE;
bbd9b64e 4443
70252a10
AK		 4444 gpa += handled;
4445 bytes -= handled;
4446 val += handled;
4447
87da7e66
XG		 4448 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4449 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4450 frag->gpa = gpa;
4451 frag->data = val;
4452 frag->len = bytes;
f78146b0 4453 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4454}
4455
52eb5a6d
XL		 4456static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4457 unsigned long addr,
22388a3c
XG		 4458 void *val, unsigned int bytes,
4459 struct x86_exception *exception,
0fbe9b0b 4460 const struct read_write_emulator_ops *ops)
bbd9b64e 4461{
0f65dd70 4462 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4463 gpa_t gpa;
4464 int rc;
4465
4466 if (ops->read_write_prepare &&
4467 ops->read_write_prepare(vcpu, val, bytes))
4468 return X86EMUL_CONTINUE;
4469
4470 vcpu->mmio_nr_fragments = 0;
0f65dd70 4471
bbd9b64e
CO		 4472 /* Crossing a page boundary? */
4473 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4474 int now;
bbd9b64e
CO		 4475
4476 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4477 rc = emulator_read_write_onepage(addr, val, now, exception,
4478 vcpu, ops);
4479
bbd9b64e
CO		 4480 if (rc != X86EMUL_CONTINUE)
4481 return rc;
4482 addr += now;
bac15531
NA		 4483 if (ctxt->mode != X86EMUL_MODE_PROT64)
4484 addr = (u32)addr;
bbd9b64e
CO		 4485 val += now;
4486 bytes -= now;
4487 }
22388a3c 4488
f78146b0
AK		 4489 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4490 vcpu, ops);
4491 if (rc != X86EMUL_CONTINUE)
4492 return rc;
4493
4494 if (!vcpu->mmio_nr_fragments)
4495 return rc;
4496
4497 gpa = vcpu->mmio_fragments[0].gpa;
4498
4499 vcpu->mmio_needed = 1;
4500 vcpu->mmio_cur_fragment = 0;
4501
87da7e66 4502 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4503 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4504 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4505 vcpu->run->mmio.phys_addr = gpa;
4506
4507 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4508}
4509
4510static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4511 unsigned long addr,
4512 void *val,
4513 unsigned int bytes,
4514 struct x86_exception *exception)
4515{
4516 return emulator_read_write(ctxt, addr, val, bytes,
4517 exception, &read_emultor);
4518}
4519
52eb5a6d 4520static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4521 unsigned long addr,
4522 const void *val,
4523 unsigned int bytes,
4524 struct x86_exception *exception)
4525{
4526 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4527 exception, &write_emultor);
bbd9b64e 4528}
bbd9b64e 4529
daea3e73
AK		 4530#define CMPXCHG_TYPE(t, ptr, old, new) \
4531 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4532
4533#ifdef CONFIG_X86_64
4534# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4535#else
4536# define CMPXCHG64(ptr, old, new) \
9749a6c0 4537 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4538#endif
4539
0f65dd70
AK		 4540static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4541 unsigned long addr,
bbd9b64e
CO		 4542 const void *old,
4543 const void *new,
4544 unsigned int bytes,
0f65dd70 4545 struct x86_exception *exception)
bbd9b64e 4546{
0f65dd70 4547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4548 gpa_t gpa;
4549 struct page *page;
4550 char *kaddr;
4551 bool exchanged;
2bacc55c 4552
daea3e73
AK		 4553 /* guests cmpxchg8b have to be emulated atomically */
4554 if (bytes > 8 || (bytes & (bytes - 1)))
4555 goto emul_write;
10589a46 4556
daea3e73 4557 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4558
daea3e73
AK		 4559 if (gpa == UNMAPPED_GVA ||
4560 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4561 goto emul_write;
2bacc55c 4562
daea3e73
AK		 4563 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4564 goto emul_write;
72dc67a6 4565
54bf36aa 4566 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4567 if (is_error_page(page))
c19b8bd6 4568 goto emul_write;
72dc67a6 4569
8fd75e12 4570 kaddr = kmap_atomic(page);
daea3e73
AK		 4571 kaddr += offset_in_page(gpa);
4572 switch (bytes) {
4573 case 1:
4574 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4575 break;
4576 case 2:
4577 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4578 break;
4579 case 4:
4580 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4581 break;
4582 case 8:
4583 exchanged = CMPXCHG64(kaddr, old, new);
4584 break;
4585 default:
4586 BUG();
2bacc55c 4587 }
8fd75e12 4588 kunmap_atomic(kaddr);
daea3e73
AK		 4589 kvm_release_page_dirty(page);
4590
4591 if (!exchanged)
4592 return X86EMUL_CMPXCHG_FAILED;
4593
54bf36aa 4594 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4595 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4596
4597 return X86EMUL_CONTINUE;
4a5f48f6 4598
3200f405 4599emul_write:
daea3e73 4600 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4601
0f65dd70 4602 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4603}
4604
cf8f70bf
GN		 4605static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4606{
4607 /* TODO: String I/O for in kernel device */
4608 int r;
4609
4610 if (vcpu->arch.pio.in)
e32edf4f 4611 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4612 vcpu->arch.pio.size, pd);
4613 else
e32edf4f 4614 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4615 vcpu->arch.pio.port, vcpu->arch.pio.size,
4616 pd);
4617 return r;
4618}
4619
6f6fbe98
XG		 4620static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4621 unsigned short port, void *val,
4622 unsigned int count, bool in)
cf8f70bf 4623{
cf8f70bf 4624 vcpu->arch.pio.port = port;
6f6fbe98 4625 vcpu->arch.pio.in = in;
7972995b 4626 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4627 vcpu->arch.pio.size = size;
4628
4629 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4630 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4631 return 1;
4632 }
4633
4634 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4635 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4636 vcpu->run->io.size = size;
4637 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4638 vcpu->run->io.count = count;
4639 vcpu->run->io.port = port;
4640
4641 return 0;
4642}
4643
6f6fbe98
XG		 4644static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4645 int size, unsigned short port, void *val,
4646 unsigned int count)
cf8f70bf 4647{
ca1d4a9e 4648 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4649 int ret;
ca1d4a9e 4650
6f6fbe98
XG		 4651 if (vcpu->arch.pio.count)
4652 goto data_avail;
cf8f70bf 4653
6f6fbe98
XG		 4654 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4655 if (ret) {
4656data_avail:
4657 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4658 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4659 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4660 return 1;
4661 }
4662
cf8f70bf
GN		 4663 return 0;
4664}
4665
6f6fbe98
XG		 4666static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4667 int size, unsigned short port,
4668 const void *val, unsigned int count)
4669{
4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4671
4672 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4673 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4674 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4675}
4676
bbd9b64e
CO		 4677static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4678{
4679 return kvm_x86_ops->get_segment_base(vcpu, seg);
4680}
4681
3cb16fe7 4682static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4683{
3cb16fe7 4684 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4685}
4686
5cb56059 4687int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4688{
4689 if (!need_emulate_wbinvd(vcpu))
4690 return X86EMUL_CONTINUE;
4691
4692 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4693 int cpu = get_cpu();
4694
4695 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4696 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4697 wbinvd_ipi, NULL, 1);
2eec7343 4698 put_cpu();
f5f48ee1 4699 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4700 } else
4701 wbinvd();
f5f48ee1
SY		 4702 return X86EMUL_CONTINUE;
4703}
5cb56059
JS		 4704
4705int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4706{
4707 kvm_x86_ops->skip_emulated_instruction(vcpu);
4708 return kvm_emulate_wbinvd_noskip(vcpu);
4709}
f5f48ee1
SY		 4710EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4711
5cb56059
JS		 4712
4713
bcaf5cc5
AK		 4714static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4715{
5cb56059 4716 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4717}
4718
52eb5a6d
XL		 4719static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4720 unsigned long *dest)
bbd9b64e 4721{
16f8a6f9 4722 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4723}
4724
52eb5a6d
XL		 4725static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4726 unsigned long value)
bbd9b64e 4727{
338dbc97 4728
717746e3 4729 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4730}
4731
52a46617 4732static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4733{
52a46617 4734 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4735}
4736
717746e3 4737static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4738{
717746e3 4739 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4740 unsigned long value;
4741
4742 switch (cr) {
4743 case 0:
4744 value = kvm_read_cr0(vcpu);
4745 break;
4746 case 2:
4747 value = vcpu->arch.cr2;
4748 break;
4749 case 3:
9f8fe504 4750 value = kvm_read_cr3(vcpu);
52a46617
GN		 4751 break;
4752 case 4:
4753 value = kvm_read_cr4(vcpu);
4754 break;
4755 case 8:
4756 value = kvm_get_cr8(vcpu);
4757 break;
4758 default:
a737f256 4759 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4760 return 0;
4761 }
4762
4763 return value;
4764}
4765
717746e3 4766static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4767{
717746e3 4768 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4769 int res = 0;
4770
52a46617
GN		 4771 switch (cr) {
4772 case 0:
49a9b07e 4773 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4774 break;
4775 case 2:
4776 vcpu->arch.cr2 = val;
4777 break;
4778 case 3:
2390218b 4779 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4780 break;
4781 case 4:
a83b29c6 4782 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4783 break;
4784 case 8:
eea1cff9 4785 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4786 break;
4787 default:
a737f256 4788 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4789 res = -1;
52a46617 4790 }
0f12244f
GN		 4791
4792 return res;
52a46617
GN		 4793}
4794
717746e3 4795static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4796{
717746e3 4797 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4798}
4799
4bff1e86 4800static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4801{
4bff1e86 4802 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4803}
4804
4bff1e86 4805static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4806{
4bff1e86 4807 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4808}
4809
1ac9d0cf
AK		 4810static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4811{
4812 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4813}
4814
4815static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4816{
4817 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4818}
4819
4bff1e86
AK		 4820static unsigned long emulator_get_cached_segment_base(
4821 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4822{
4bff1e86 4823 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4824}
4825
1aa36616
AK		 4826static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4827 struct desc_struct *desc, u32 *base3,
4828 int seg)
2dafc6c2
GN		 4829{
4830 struct kvm_segment var;
4831
4bff1e86 4832 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4833 *selector = var.selector;
2dafc6c2 4834
378a8b09
GN		 4835 if (var.unusable) {
4836 memset(desc, 0, sizeof(*desc));
2dafc6c2 4837 return false;
378a8b09 4838 }
2dafc6c2
GN		 4839
4840 if (var.g)
4841 var.limit >>= 12;
4842 set_desc_limit(desc, var.limit);
4843 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4844#ifdef CONFIG_X86_64
4845 if (base3)
4846 *base3 = var.base >> 32;
4847#endif
2dafc6c2
GN		 4848 desc->type = var.type;
4849 desc->s = var.s;
4850 desc->dpl = var.dpl;
4851 desc->p = var.present;
4852 desc->avl = var.avl;
4853 desc->l = var.l;
4854 desc->d = var.db;
4855 desc->g = var.g;
4856
4857 return true;
4858}
4859
1aa36616
AK		 4860static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4861 struct desc_struct *desc, u32 base3,
4862 int seg)
2dafc6c2 4863{
4bff1e86 4864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4865 struct kvm_segment var;
4866
1aa36616 4867 var.selector = selector;
2dafc6c2 4868 var.base = get_desc_base(desc);
5601d05b
GN		 4869#ifdef CONFIG_X86_64
4870 var.base |= ((u64)base3) << 32;
4871#endif
2dafc6c2
GN		 4872 var.limit = get_desc_limit(desc);
4873 if (desc->g)
4874 var.limit = (var.limit << 12) | 0xfff;
4875 var.type = desc->type;
2dafc6c2
GN		 4876 var.dpl = desc->dpl;
4877 var.db = desc->d;
4878 var.s = desc->s;
4879 var.l = desc->l;
4880 var.g = desc->g;
4881 var.avl = desc->avl;
4882 var.present = desc->p;
4883 var.unusable = !var.present;
4884 var.padding = 0;
4885
4886 kvm_set_segment(vcpu, &var, seg);
4887 return;
4888}
4889
717746e3
AK		 4890static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4891 u32 msr_index, u64 *pdata)
4892{
609e36d3
PB		 4893 struct msr_data msr;
4894 int r;
4895
4896 msr.index = msr_index;
4897 msr.host_initiated = false;
4898 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4899 if (r)
4900 return r;
4901
4902 *pdata = msr.data;
4903 return 0;
717746e3
AK		 4904}
4905
4906static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4907 u32 msr_index, u64 data)
4908{
8fe8ab46
WA		 4909 struct msr_data msr;
4910
4911 msr.data = data;
4912 msr.index = msr_index;
4913 msr.host_initiated = false;
4914 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4915}
4916
64d60670
PB		 4917static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4918{
4919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4920
4921 return vcpu->arch.smbase;
4922}
4923
4924static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4925{
4926 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4927
4928 vcpu->arch.smbase = smbase;
4929}
4930
67f4d428
NA		 4931static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4932 u32 pmc)
4933{
c6702c9d 4934 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4935}
4936
222d21aa
AK		 4937static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4938 u32 pmc, u64 *pdata)
4939{
c6702c9d 4940 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4941}
4942
6c3287f7
AK		 4943static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4944{
4945 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4946}
4947
5037f6f3
AK		 4948static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4949{
4950 preempt_disable();
5197b808 4951 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4952 /*
4953 * CR0.TS may reference the host fpu state, not the guest fpu state,
4954 * so it may be clear at this point.
4955 */
4956 clts();
4957}
4958
4959static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4960{
4961 preempt_enable();
4962}
4963
2953538e 4964static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4965 struct x86_instruction_info *info,
c4f035c6
AK		 4966 enum x86_intercept_stage stage)
4967{
2953538e 4968 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4969}
4970
0017f93a 4971static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4972 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4973{
0017f93a 4974 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4975}
4976
dd856efa
AK		 4977static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4978{
4979 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4980}
4981
4982static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4983{
4984 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4985}
4986
801806d9
NA		 4987static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4988{
4989 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4990}
4991
0225fb50 4992static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4993 .read_gpr = emulator_read_gpr,
4994 .write_gpr = emulator_write_gpr,
1871c602 4995 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4996 .write_std = kvm_write_guest_virt_system,
1871c602 4997 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4998 .read_emulated = emulator_read_emulated,
4999 .write_emulated = emulator_write_emulated,
5000 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5001 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5002 .pio_in_emulated = emulator_pio_in_emulated,
5003 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5004 .get_segment = emulator_get_segment,
5005 .set_segment = emulator_set_segment,
5951c442 5006 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5007 .get_gdt = emulator_get_gdt,
160ce1f1 5008 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5009 .set_gdt = emulator_set_gdt,
5010 .set_idt = emulator_set_idt,
52a46617
GN		 5011 .get_cr = emulator_get_cr,
5012 .set_cr = emulator_set_cr,
9c537244 5013 .cpl = emulator_get_cpl,
35aa5375
GN		 5014 .get_dr = emulator_get_dr,
5015 .set_dr = emulator_set_dr,
64d60670
PB		 5016 .get_smbase = emulator_get_smbase,
5017 .set_smbase = emulator_set_smbase,
717746e3
AK		 5018 .set_msr = emulator_set_msr,
5019 .get_msr = emulator_get_msr,
67f4d428 5020 .check_pmc = emulator_check_pmc,
222d21aa 5021 .read_pmc = emulator_read_pmc,
6c3287f7 5022 .halt = emulator_halt,
bcaf5cc5 5023 .wbinvd = emulator_wbinvd,
d6aa1000 5024 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5025 .get_fpu = emulator_get_fpu,
5026 .put_fpu = emulator_put_fpu,
c4f035c6 5027 .intercept = emulator_intercept,
bdb42f5a 5028 .get_cpuid = emulator_get_cpuid,
801806d9 5029 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5030};
5031
95cb2295
GN		 5032static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5033{
37ccdcbe 5034 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5035 /*
5036 * an sti; sti; sequence only disable interrupts for the first
5037 * instruction. So, if the last instruction, be it emulated or
5038 * not, left the system with the INT_STI flag enabled, it
5039 * means that the last instruction is an sti. We should not
5040 * leave the flag on in this case. The same goes for mov ss
5041 */
37ccdcbe
PB		 5042 if (int_shadow & mask)
5043 mask = 0;
6addfc42 5044 if (unlikely(int_shadow || mask)) {
95cb2295 5045 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5046 if (!mask)
5047 kvm_make_request(KVM_REQ_EVENT, vcpu);
5048 }
95cb2295
GN		 5049}
5050
ef54bcfe 5051static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5052{
5053 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5054 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5055 return kvm_propagate_fault(vcpu, &ctxt->exception);
5056
5057 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5058 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5059 ctxt->exception.error_code);
54b8486f 5060 else
da9cb575 5061 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5062 return false;
54b8486f
GN		 5063}
5064
8ec4722d
MG		 5065static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5066{
adf52235 5067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5068 int cs_db, cs_l;
5069
8ec4722d
MG		 5070 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5071
adf52235
TY		 5072 ctxt->eflags = kvm_get_rflags(vcpu);
5073 ctxt->eip = kvm_rip_read(vcpu);
5074 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5075 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5076 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5077 cs_db ? X86EMUL_MODE_PROT32 :
5078 X86EMUL_MODE_PROT16;
a584539b 5079 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5080 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5081 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5082 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5083
dd856efa 5084 init_decode_cache(ctxt);
7ae441ea 5085 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5086}
5087
71f9833b 5088int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5089{
9d74191a 5090 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5091 int ret;
5092
5093 init_emulate_ctxt(vcpu);
5094
9dac77fa
AK		 5095 ctxt->op_bytes = 2;
5096 ctxt->ad_bytes = 2;
5097 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5098 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5099
5100 if (ret != X86EMUL_CONTINUE)
5101 return EMULATE_FAIL;
5102
9dac77fa 5103 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5104 kvm_rip_write(vcpu, ctxt->eip);
5105 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5106
5107 if (irq == NMI_VECTOR)
7460fb4a 5108 vcpu->arch.nmi_pending = 0;
63995653
MG		 5109 else
5110 vcpu->arch.interrupt.pending = false;
5111
5112 return EMULATE_DONE;
5113}
5114EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5115
6d77dbfc
GN		 5116static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5117{
fc3a9157
JR		 5118 int r = EMULATE_DONE;
5119
6d77dbfc
GN		 5120 ++vcpu->stat.insn_emulation_fail;
5121 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5122 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5123 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5124 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5125 vcpu->run->internal.ndata = 0;
5126 r = EMULATE_FAIL;
5127 }
6d77dbfc 5128 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5129
5130 return r;
6d77dbfc
GN		 5131}
5132
93c05d3e 5133static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5134 bool write_fault_to_shadow_pgtable,
5135 int emulation_type)
a6f177ef 5136{
95b3cf69 5137 gpa_t gpa = cr2;
8e3d9d06 5138 pfn_t pfn;
a6f177ef 5139
991eebf9
GN		 5140 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5141 return false;
5142
95b3cf69
XG		 5143 if (!vcpu->arch.mmu.direct_map) {
5144 /*
5145 * Write permission should be allowed since only
5146 * write access need to be emulated.
5147 */
5148 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5149
95b3cf69
XG		 5150 /*
5151 * If the mapping is invalid in guest, let cpu retry
5152 * it to generate fault.
5153 */
5154 if (gpa == UNMAPPED_GVA)
5155 return true;
5156 }
a6f177ef 5157
8e3d9d06
XG		 5158 /*
5159 * Do not retry the unhandleable instruction if it faults on the
5160 * readonly host memory, otherwise it will goto a infinite loop:
5161 * retry instruction -> write #PF -> emulation fail -> retry
5162 * instruction -> ...
5163 */
5164 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5165
5166 /*
5167 * If the instruction failed on the error pfn, it can not be fixed,
5168 * report the error to userspace.
5169 */
5170 if (is_error_noslot_pfn(pfn))
5171 return false;
5172
5173 kvm_release_pfn_clean(pfn);
5174
5175 /* The instructions are well-emulated on direct mmu. */
5176 if (vcpu->arch.mmu.direct_map) {
5177 unsigned int indirect_shadow_pages;
5178
5179 spin_lock(&vcpu->kvm->mmu_lock);
5180 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5181 spin_unlock(&vcpu->kvm->mmu_lock);
5182
5183 if (indirect_shadow_pages)
5184 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5185
a6f177ef 5186 return true;
8e3d9d06 5187 }
a6f177ef 5188
95b3cf69
XG		 5189 /*
5190 * if emulation was due to access to shadowed page table
5191 * and it failed try to unshadow page and re-enter the
5192 * guest to let CPU execute the instruction.
5193 */
5194 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5195
5196 /*
5197 * If the access faults on its page table, it can not
5198 * be fixed by unprotecting shadow page and it should
5199 * be reported to userspace.
5200 */
5201 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5202}
5203
1cb3f3ae
XG		 5204static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5205 unsigned long cr2, int emulation_type)
5206{
5207 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5208 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5209
5210 last_retry_eip = vcpu->arch.last_retry_eip;
5211 last_retry_addr = vcpu->arch.last_retry_addr;
5212
5213 /*
5214 * If the emulation is caused by #PF and it is non-page_table
5215 * writing instruction, it means the VM-EXIT is caused by shadow
5216 * page protected, we can zap the shadow page and retry this
5217 * instruction directly.
5218 *
5219 * Note: if the guest uses a non-page-table modifying instruction
5220 * on the PDE that points to the instruction, then we will unmap
5221 * the instruction and go to an infinite loop. So, we cache the
5222 * last retried eip and the last fault address, if we meet the eip
5223 * and the address again, we can break out of the potential infinite
5224 * loop.
5225 */
5226 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5227
5228 if (!(emulation_type & EMULTYPE_RETRY))
5229 return false;
5230
5231 if (x86_page_table_writing_insn(ctxt))
5232 return false;
5233
5234 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5235 return false;
5236
5237 vcpu->arch.last_retry_eip = ctxt->eip;
5238 vcpu->arch.last_retry_addr = cr2;
5239
5240 if (!vcpu->arch.mmu.direct_map)
5241 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5242
22368028 5243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5244
5245 return true;
5246}
5247
716d51ab
GN		 5248static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5249static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5250
64d60670 5251static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5252{
64d60670 5253 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5254 /* This is a good place to trace that we are exiting SMM. */
5255 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5256
64d60670
PB		 5257 if (unlikely(vcpu->arch.smi_pending)) {
5258 kvm_make_request(KVM_REQ_SMI, vcpu);
5259 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5260 } else {
5261 /* Process a latched INIT, if any. */
5262 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5263 }
5264 }
699023e2
PB		 5265
5266 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5267}
5268
5269static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5270{
5271 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5272
a584539b 5273 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5274
5275 if (changed & HF_SMM_MASK)
5276 kvm_smm_changed(vcpu);
a584539b
PB		 5277}
5278
4a1e10d5
PB		 5279static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5280 unsigned long *db)
5281{
5282 u32 dr6 = 0;
5283 int i;
5284 u32 enable, rwlen;
5285
5286 enable = dr7;
5287 rwlen = dr7 >> 16;
5288 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5289 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5290 dr6 |= (1 << i);
5291 return dr6;
5292}
5293
6addfc42 5294static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5295{
5296 struct kvm_run *kvm_run = vcpu->run;
5297
5298 /*
6addfc42
PB		 5299 * rflags is the old, "raw" value of the flags. The new value has
5300 * not been saved yet.
663f4c61
PB		 5301 *
5302 * This is correct even for TF set by the guest, because "the
5303 * processor will not generate this exception after the instruction
5304 * that sets the TF flag".
5305 */
663f4c61
PB		 5306 if (unlikely(rflags & X86_EFLAGS_TF)) {
5307 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5308 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5309 DR6_RTM;
663f4c61
PB		 5310 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5311 kvm_run->debug.arch.exception = DB_VECTOR;
5312 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5313 *r = EMULATE_USER_EXIT;
5314 } else {
5315 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5316 /*
5317 * "Certain debug exceptions may clear bit 0-3. The
5318 * remaining contents of the DR6 register are never
5319 * cleared by the processor".
5320 */
5321 vcpu->arch.dr6 &= ~15;
6f43ed01 5322 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5323 kvm_queue_exception(vcpu, DB_VECTOR);
5324 }
5325 }
5326}
5327
4a1e10d5
PB		 5328static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5329{
4a1e10d5
PB		 5330 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5331 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5332 struct kvm_run *kvm_run = vcpu->run;
5333 unsigned long eip = kvm_get_linear_rip(vcpu);
5334 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5335 vcpu->arch.guest_debug_dr7,
5336 vcpu->arch.eff_db);
5337
5338 if (dr6 != 0) {
6f43ed01 5339 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5340 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5341 kvm_run->debug.arch.exception = DB_VECTOR;
5342 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5343 *r = EMULATE_USER_EXIT;
5344 return true;
5345 }
5346 }
5347
4161a569
NA		 5348 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5349 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5350 unsigned long eip = kvm_get_linear_rip(vcpu);
5351 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5352 vcpu->arch.dr7,
5353 vcpu->arch.db);
5354
5355 if (dr6 != 0) {
5356 vcpu->arch.dr6 &= ~15;
6f43ed01 5357 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5358 kvm_queue_exception(vcpu, DB_VECTOR);
5359 *r = EMULATE_DONE;
5360 return true;
5361 }
5362 }
5363
5364 return false;
5365}
5366
51d8b661
AP		 5367int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5368 unsigned long cr2,
dc25e89e
AP		 5369 int emulation_type,
5370 void *insn,
5371 int insn_len)
bbd9b64e 5372{
95cb2295 5373 int r;
9d74191a 5374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5375 bool writeback = true;
93c05d3e 5376 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5377
93c05d3e
XG		 5378 /*
5379 * Clear write_fault_to_shadow_pgtable here to ensure it is
5380 * never reused.
5381 */
5382 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5383 kvm_clear_exception_queue(vcpu);
8d7d8102 5384
571008da 5385 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5386 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5387
5388 /*
5389 * We will reenter on the same instruction since
5390 * we do not set complete_userspace_io. This does not
5391 * handle watchpoints yet, those would be handled in
5392 * the emulate_ops.
5393 */
5394 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5395 return r;
5396
9d74191a
TY		 5397 ctxt->interruptibility = 0;
5398 ctxt->have_exception = false;
e0ad0b47 5399 ctxt->exception.vector = -1;
9d74191a 5400 ctxt->perm_ok = false;
bbd9b64e 5401
b51e974f 5402 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5403
9d74191a 5404 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5405
e46479f8 5406 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5407 ++vcpu->stat.insn_emulation;
1d2887e2 5408 if (r != EMULATION_OK) {
4005996e
AK		 5409 if (emulation_type & EMULTYPE_TRAP_UD)
5410 return EMULATE_FAIL;
991eebf9
GN		 5411 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5412 emulation_type))
bbd9b64e 5413 return EMULATE_DONE;
6d77dbfc
GN		 5414 if (emulation_type & EMULTYPE_SKIP)
5415 return EMULATE_FAIL;
5416 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5417 }
5418 }
5419
ba8afb6b 5420 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5421 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5422 if (ctxt->eflags & X86_EFLAGS_RF)
5423 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5424 return EMULATE_DONE;
5425 }
5426
1cb3f3ae
XG		 5427 if (retry_instruction(ctxt, cr2, emulation_type))
5428 return EMULATE_DONE;
5429
7ae441ea 5430 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5431 changes registers values during IO operation */
7ae441ea
GN		 5432 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5433 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5434 emulator_invalidate_register_cache(ctxt);
7ae441ea 5435 }
4d2179e1 5436
5cd21917 5437restart:
9d74191a 5438 r = x86_emulate_insn(ctxt);
bbd9b64e 5439
775fde86
JR		 5440 if (r == EMULATION_INTERCEPTED)
5441 return EMULATE_DONE;
5442
d2ddd1c4 5443 if (r == EMULATION_FAILED) {
991eebf9
GN		 5444 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5445 emulation_type))
c3cd7ffa
GN		 5446 return EMULATE_DONE;
5447
6d77dbfc 5448 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5449 }
5450
9d74191a 5451 if (ctxt->have_exception) {
d2ddd1c4 5452 r = EMULATE_DONE;
ef54bcfe
PB		 5453 if (inject_emulated_exception(vcpu))
5454 return r;
d2ddd1c4 5455 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5456 if (!vcpu->arch.pio.in) {
5457 /* FIXME: return into emulator if single-stepping. */
3457e419 5458 vcpu->arch.pio.count = 0;
0912c977 5459 } else {
7ae441ea 5460 writeback = false;
716d51ab
GN		 5461 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5462 }
ac0a48c3 5463 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5464 } else if (vcpu->mmio_needed) {
5465 if (!vcpu->mmio_is_write)
5466 writeback = false;
ac0a48c3 5467 r = EMULATE_USER_EXIT;
716d51ab 5468 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5469 } else if (r == EMULATION_RESTART)
5cd21917 5470 goto restart;
d2ddd1c4
GN		 5471 else
5472 r = EMULATE_DONE;
f850e2e6 5473
7ae441ea 5474 if (writeback) {
6addfc42 5475 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5476 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5477 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5478 if (vcpu->arch.hflags != ctxt->emul_flags)
5479 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5480 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5481 if (r == EMULATE_DONE)
6addfc42 5482 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5483 if (!ctxt->have_exception ||
5484 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5485 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5486
5487 /*
5488 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5489 * do nothing, and it will be requested again as soon as
5490 * the shadow expires. But we still need to check here,
5491 * because POPF has no interrupt shadow.
5492 */
5493 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5494 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5495 } else
5496 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5497
5498 return r;
de7d789a 5499}
51d8b661 5500EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5501
cf8f70bf 5502int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5503{
cf8f70bf 5504 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5505 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5506 size, port, &val, 1);
cf8f70bf 5507 /* do not return to emulator after return from userspace */
7972995b 5508 vcpu->arch.pio.count = 0;
de7d789a
CO		 5509 return ret;
5510}
cf8f70bf 5511EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5512
8cfdc000
ZA		 5513static void tsc_bad(void *info)
5514{
0a3aee0d 5515 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5516}
5517
5518static void tsc_khz_changed(void *data)
c8076604 5519{
8cfdc000
ZA		 5520 struct cpufreq_freqs *freq = data;
5521 unsigned long khz = 0;
5522
5523 if (data)
5524 khz = freq->new;
5525 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5526 khz = cpufreq_quick_get(raw_smp_processor_id());
5527 if (!khz)
5528 khz = tsc_khz;
0a3aee0d 5529 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5530}
5531
c8076604
GH		 5532static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5533 void *data)
5534{
5535 struct cpufreq_freqs *freq = data;
5536 struct kvm *kvm;
5537 struct kvm_vcpu *vcpu;
5538 int i, send_ipi = 0;
5539
8cfdc000
ZA		 5540 /*
5541 * We allow guests to temporarily run on slowing clocks,
5542 * provided we notify them after, or to run on accelerating
5543 * clocks, provided we notify them before. Thus time never
5544 * goes backwards.
5545 *
5546 * However, we have a problem. We can't atomically update
5547 * the frequency of a given CPU from this function; it is
5548 * merely a notifier, which can be called from any CPU.
5549 * Changing the TSC frequency at arbitrary points in time
5550 * requires a recomputation of local variables related to
5551 * the TSC for each VCPU. We must flag these local variables
5552 * to be updated and be sure the update takes place with the
5553 * new frequency before any guests proceed.
5554 *
5555 * Unfortunately, the combination of hotplug CPU and frequency
5556 * change creates an intractable locking scenario; the order
5557 * of when these callouts happen is undefined with respect to
5558 * CPU hotplug, and they can race with each other. As such,
5559 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5560 * undefined; you can actually have a CPU frequency change take
5561 * place in between the computation of X and the setting of the
5562 * variable. To protect against this problem, all updates of
5563 * the per_cpu tsc_khz variable are done in an interrupt
5564 * protected IPI, and all callers wishing to update the value
5565 * must wait for a synchronous IPI to complete (which is trivial
5566 * if the caller is on the CPU already). This establishes the
5567 * necessary total order on variable updates.
5568 *
5569 * Note that because a guest time update may take place
5570 * anytime after the setting of the VCPU's request bit, the
5571 * correct TSC value must be set before the request. However,
5572 * to ensure the update actually makes it to any guest which
5573 * starts running in hardware virtualization between the set
5574 * and the acquisition of the spinlock, we must also ping the
5575 * CPU after setting the request bit.
5576 *
5577 */
5578
c8076604
GH		 5579 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5580 return 0;
5581 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5582 return 0;
8cfdc000
ZA		 5583
5584 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5585
2f303b74 5586 spin_lock(&kvm_lock);
c8076604 5587 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5588 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5589 if (vcpu->cpu != freq->cpu)
5590 continue;
c285545f 5591 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5592 if (vcpu->cpu != smp_processor_id())
8cfdc000 5593 send_ipi = 1;
c8076604
GH		 5594 }
5595 }
2f303b74 5596 spin_unlock(&kvm_lock);
c8076604
GH		 5597
5598 if (freq->old < freq->new && send_ipi) {
5599 /*
5600 * We upscale the frequency. Must make the guest
5601 * doesn't see old kvmclock values while running with
5602 * the new frequency, otherwise we risk the guest sees
5603 * time go backwards.
5604 *
5605 * In case we update the frequency for another cpu
5606 * (which might be in guest context) send an interrupt
5607 * to kick the cpu out of guest context. Next time
5608 * guest context is entered kvmclock will be updated,
5609 * so the guest will not see stale values.
5610 */
8cfdc000 5611 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5612 }
5613 return 0;
5614}
5615
5616static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5617 .notifier_call = kvmclock_cpufreq_notifier
5618};
5619
5620static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5621 unsigned long action, void *hcpu)
5622{
5623 unsigned int cpu = (unsigned long)hcpu;
5624
5625 switch (action) {
5626 case CPU_ONLINE:
5627 case CPU_DOWN_FAILED:
5628 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5629 break;
5630 case CPU_DOWN_PREPARE:
5631 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5632 break;
5633 }
5634 return NOTIFY_OK;
5635}
5636
5637static struct notifier_block kvmclock_cpu_notifier_block = {
5638 .notifier_call = kvmclock_cpu_notifier,
5639 .priority = -INT_MAX
c8076604
GH		 5640};
5641
b820cc0c
ZA		 5642static void kvm_timer_init(void)
5643{
5644 int cpu;
5645
c285545f 5646 max_tsc_khz = tsc_khz;
460dd42e
SB		 5647
5648 cpu_notifier_register_begin();
b820cc0c 5649 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5650#ifdef CONFIG_CPU_FREQ
5651 struct cpufreq_policy policy;
5652 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5653 cpu = get_cpu();
5654 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5655 if (policy.cpuinfo.max_freq)
5656 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5657 put_cpu();
c285545f 5658#endif
b820cc0c
ZA		 5659 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5660 CPUFREQ_TRANSITION_NOTIFIER);
5661 }
c285545f 5662 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5663 for_each_online_cpu(cpu)
5664 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5665
5666 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5667 cpu_notifier_register_done();
5668
b820cc0c
ZA		 5669}
5670
ff9d07a0
ZY		 5671static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5672
f5132b01 5673int kvm_is_in_guest(void)
ff9d07a0 5674{
086c9855 5675 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5676}
5677
5678static int kvm_is_user_mode(void)
5679{
5680 int user_mode = 3;
dcf46b94 5681
086c9855
AS		 5682 if (__this_cpu_read(current_vcpu))
5683 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5684
ff9d07a0
ZY		 5685 return user_mode != 0;
5686}
5687
5688static unsigned long kvm_get_guest_ip(void)
5689{
5690 unsigned long ip = 0;
dcf46b94 5691
086c9855
AS		 5692 if (__this_cpu_read(current_vcpu))
5693 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5694
ff9d07a0
ZY		 5695 return ip;
5696}
5697
5698static struct perf_guest_info_callbacks kvm_guest_cbs = {
5699 .is_in_guest = kvm_is_in_guest,
5700 .is_user_mode = kvm_is_user_mode,
5701 .get_guest_ip = kvm_get_guest_ip,
5702};
5703
5704void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5705{
086c9855 5706 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5707}
5708EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5709
5710void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5711{
086c9855 5712 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5713}
5714EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5715
ce88decf
XG		 5716static void kvm_set_mmio_spte_mask(void)
5717{
5718 u64 mask;
5719 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5720
5721 /*
5722 * Set the reserved bits and the present bit of an paging-structure
5723 * entry to generate page fault with PFER.RSV = 1.
5724 */
885032b9 5725 /* Mask the reserved physical address bits. */
d1431483 5726 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5727
5728 /* Bit 62 is always reserved for 32bit host. */
5729 mask |= 0x3ull << 62;
5730
5731 /* Set the present bit. */
ce88decf
XG		 5732 mask |= 1ull;
5733
5734#ifdef CONFIG_X86_64
5735 /*
5736 * If reserved bit is not supported, clear the present bit to disable
5737 * mmio page fault.
5738 */
5739 if (maxphyaddr == 52)
5740 mask &= ~1ull;
5741#endif
5742
5743 kvm_mmu_set_mmio_spte_mask(mask);
5744}
5745
16e8d74d
MT		 5746#ifdef CONFIG_X86_64
5747static void pvclock_gtod_update_fn(struct work_struct *work)
5748{
d828199e
MT		 5749 struct kvm *kvm;
5750
5751 struct kvm_vcpu *vcpu;
5752 int i;
5753
2f303b74 5754 spin_lock(&kvm_lock);
d828199e
MT		 5755 list_for_each_entry(kvm, &vm_list, vm_list)
5756 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5757 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5758 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5759 spin_unlock(&kvm_lock);
16e8d74d
MT		 5760}
5761
5762static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5763
5764/*
5765 * Notification about pvclock gtod data update.
5766 */
5767static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5768 void *priv)
5769{
5770 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5771 struct timekeeper *tk = priv;
5772
5773 update_pvclock_gtod(tk);
5774
5775 /* disable master clock if host does not trust, or does not
5776 * use, TSC clocksource
5777 */
5778 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5779 atomic_read(&kvm_guest_has_master_clock) != 0)
5780 queue_work(system_long_wq, &pvclock_gtod_work);
5781
5782 return 0;
5783}
5784
5785static struct notifier_block pvclock_gtod_notifier = {
5786 .notifier_call = pvclock_gtod_notify,
5787};
5788#endif
5789
f8c16bba 5790int kvm_arch_init(void *opaque)
043405e1 5791{
b820cc0c 5792 int r;
6b61edf7 5793 struct kvm_x86_ops *ops = opaque;
f8c16bba 5794
f8c16bba
ZX		 5795 if (kvm_x86_ops) {
5796 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5797 r = -EEXIST;
5798 goto out;
f8c16bba
ZX		 5799 }
5800
5801 if (!ops->cpu_has_kvm_support()) {
5802 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5803 r = -EOPNOTSUPP;
5804 goto out;
f8c16bba
ZX		 5805 }
5806 if (ops->disabled_by_bios()) {
5807 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5808 r = -EOPNOTSUPP;
5809 goto out;
f8c16bba
ZX		 5810 }
5811
013f6a5d
MT		 5812 r = -ENOMEM;
5813 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5814 if (!shared_msrs) {
5815 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5816 goto out;
5817 }
5818
97db56ce
AK		 5819 r = kvm_mmu_module_init();
5820 if (r)
013f6a5d 5821 goto out_free_percpu;
97db56ce 5822
ce88decf 5823 kvm_set_mmio_spte_mask();
97db56ce 5824
f8c16bba 5825 kvm_x86_ops = ops;
920c8377 5826
7b52345e 5827 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5828 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5829
b820cc0c 5830 kvm_timer_init();
c8076604 5831
ff9d07a0
ZY		 5832 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5833
2acf923e
DC		 5834 if (cpu_has_xsave)
5835 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5836
c5cc421b 5837 kvm_lapic_init();
16e8d74d
MT		 5838#ifdef CONFIG_X86_64
5839 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5840#endif
5841
f8c16bba 5842 return 0;
56c6d28a 5843
013f6a5d
MT		 5844out_free_percpu:
5845 free_percpu(shared_msrs);
56c6d28a 5846out:
56c6d28a 5847 return r;
043405e1 5848}
8776e519 5849
f8c16bba
ZX		 5850void kvm_arch_exit(void)
5851{
ff9d07a0
ZY		 5852 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5853
888d256e
JK		 5854 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5855 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5856 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5857 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5858#ifdef CONFIG_X86_64
5859 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5860#endif
f8c16bba 5861 kvm_x86_ops = NULL;
56c6d28a 5862 kvm_mmu_module_exit();
013f6a5d 5863 free_percpu(shared_msrs);
56c6d28a 5864}
f8c16bba 5865
5cb56059 5866int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5867{
5868 ++vcpu->stat.halt_exits;
5869 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5870 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5871 return 1;
5872 } else {
5873 vcpu->run->exit_reason = KVM_EXIT_HLT;
5874 return 0;
5875 }
5876}
5cb56059
JS		 5877EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5878
5879int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5880{
5881 kvm_x86_ops->skip_emulated_instruction(vcpu);
5882 return kvm_vcpu_halt(vcpu);
5883}
8776e519
HB		 5884EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5885
55cd8e5a
GN		 5886int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5887{
5888 u64 param, ingpa, outgpa, ret;
5889 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5890 bool fast, longmode;
55cd8e5a
GN		 5891
5892 /*
5893 * hypercall generates UD from non zero cpl and real mode
5894 * per HYPER-V spec
5895 */
3eeb3288 5896 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5897 kvm_queue_exception(vcpu, UD_VECTOR);
5898 return 0;
5899 }
5900
a449c7aa 5901 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5902
5903 if (!longmode) {
ccd46936
GN		 5904 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5905 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5906 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5907 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5908 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5909 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5910 }
5911#ifdef CONFIG_X86_64
5912 else {
5913 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5914 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5915 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5916 }
5917#endif
5918
5919 code = param & 0xffff;
5920 fast = (param >> 16) & 0x1;
5921 rep_cnt = (param >> 32) & 0xfff;
5922 rep_idx = (param >> 48) & 0xfff;
5923
5924 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5925
c25bc163
GN		 5926 switch (code) {
5927 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5928 kvm_vcpu_on_spin(vcpu);
5929 break;
5930 default:
5931 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5932 break;
5933 }
55cd8e5a
GN		 5934
5935 ret = res | (((u64)rep_done & 0xfff) << 32);
5936 if (longmode) {
5937 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5938 } else {
5939 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5940 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5941 }
5942
5943 return 1;
5944}
5945
6aef266c
SV		 5946/*
5947 * kvm_pv_kick_cpu_op: Kick a vcpu.
5948 *
5949 * @apicid - apicid of vcpu to be kicked.
5950 */
5951static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5952{
24d2166b 5953 struct kvm_lapic_irq lapic_irq;
6aef266c 5954
24d2166b
R		 5955 lapic_irq.shorthand = 0;
5956 lapic_irq.dest_mode = 0;
5957 lapic_irq.dest_id = apicid;
93bbf0b8 5958 lapic_irq.msi_redir_hint = false;
6aef266c 5959
24d2166b 5960 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5961 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5962}
5963
8776e519
HB		 5964int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5965{
5966 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5967 int op_64_bit, r = 1;
8776e519 5968
5cb56059
JS		 5969 kvm_x86_ops->skip_emulated_instruction(vcpu);
5970
55cd8e5a
GN		 5971 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5972 return kvm_hv_hypercall(vcpu);
5973
5fdbf976
MT		 5974 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5975 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5976 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5977 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5978 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5979
229456fc 5980 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5981
a449c7aa
NA		 5982 op_64_bit = is_64_bit_mode(vcpu);
5983 if (!op_64_bit) {
8776e519
HB		 5984 nr &= 0xFFFFFFFF;
5985 a0 &= 0xFFFFFFFF;
5986 a1 &= 0xFFFFFFFF;
5987 a2 &= 0xFFFFFFFF;
5988 a3 &= 0xFFFFFFFF;
5989 }
5990
07708c4a
JK		 5991 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5992 ret = -KVM_EPERM;
5993 goto out;
5994 }
5995
8776e519 5996 switch (nr) {
b93463aa
AK		 5997 case KVM_HC_VAPIC_POLL_IRQ:
5998 ret = 0;
5999 break;
6aef266c
SV		 6000 case KVM_HC_KICK_CPU:
6001 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6002 ret = 0;
6003 break;
8776e519
HB		 6004 default:
6005 ret = -KVM_ENOSYS;
6006 break;
6007 }
07708c4a 6008out:
a449c7aa
NA		 6009 if (!op_64_bit)
6010 ret = (u32)ret;
5fdbf976 6011 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6012 ++vcpu->stat.hypercalls;
2f333bcb 6013 return r;
8776e519
HB		 6014}
6015EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6016
b6785def 6017static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6018{
d6aa1000 6019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6020 char instruction[3];
5fdbf976 6021 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6022
8776e519 6023 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6024
9d74191a 6025 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6026}
6027
b6c7a5dc
HB		 6028/*
6029 * Check if userspace requested an interrupt window, and that the
6030 * interrupt window is open.
6031 *
6032 * No need to exit to userspace if we already have an interrupt queued.
6033 */
851ba692 6034static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6035{
8061823a 6036 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6037 vcpu->run->request_interrupt_window &&
5df56646 6038 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6039}
6040
851ba692 6041static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6042{
851ba692
AK		 6043 struct kvm_run *kvm_run = vcpu->run;
6044
91586a3b 6045 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6046 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6047 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6048 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6049 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6050 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6051 else
b6c7a5dc 6052 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6053 kvm_arch_interrupt_allowed(vcpu) &&
6054 !kvm_cpu_has_interrupt(vcpu) &&
6055 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6056}
6057
95ba8273
GN		 6058static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6059{
6060 int max_irr, tpr;
6061
6062 if (!kvm_x86_ops->update_cr8_intercept)
6063 return;
6064
88c808fd
AK		 6065 if (!vcpu->arch.apic)
6066 return;
6067
8db3baa2
GN		 6068 if (!vcpu->arch.apic->vapic_addr)
6069 max_irr = kvm_lapic_find_highest_irr(vcpu);
6070 else
6071 max_irr = -1;
95ba8273
GN		 6072
6073 if (max_irr != -1)
6074 max_irr >>= 4;
6075
6076 tpr = kvm_lapic_get_cr8(vcpu);
6077
6078 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6079}
6080
b6b8a145 6081static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6082{
b6b8a145
JK		 6083 int r;
6084
95ba8273 6085 /* try to reinject previous events if any */
b59bb7bd 6086 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6087 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6088 vcpu->arch.exception.has_error_code,
6089 vcpu->arch.exception.error_code);
d6e8c854
NA		 6090
6091 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6092 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6093 X86_EFLAGS_RF);
6094
6bdf0662
NA		 6095 if (vcpu->arch.exception.nr == DB_VECTOR &&
6096 (vcpu->arch.dr7 & DR7_GD)) {
6097 vcpu->arch.dr7 &= ~DR7_GD;
6098 kvm_update_dr7(vcpu);
6099 }
6100
b59bb7bd
GN		 6101 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6102 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6103 vcpu->arch.exception.error_code,
6104 vcpu->arch.exception.reinject);
b6b8a145 6105 return 0;
b59bb7bd
GN		 6106 }
6107
95ba8273
GN		 6108 if (vcpu->arch.nmi_injected) {
6109 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6110 return 0;
95ba8273
GN		 6111 }
6112
6113 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6114 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6115 return 0;
6116 }
6117
6118 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6119 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6120 if (r != 0)
6121 return r;
95ba8273
GN		 6122 }
6123
6124 /* try to inject new event if pending */
6125 if (vcpu->arch.nmi_pending) {
6126 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6127 --vcpu->arch.nmi_pending;
95ba8273
GN		 6128 vcpu->arch.nmi_injected = true;
6129 kvm_x86_ops->set_nmi(vcpu);
6130 }
c7c9c56c 6131 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6132 /*
6133 * Because interrupts can be injected asynchronously, we are
6134 * calling check_nested_events again here to avoid a race condition.
6135 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6136 * proposal and current concerns. Perhaps we should be setting
6137 * KVM_REQ_EVENT only on certain events and not unconditionally?
6138 */
6139 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6140 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6141 if (r != 0)
6142 return r;
6143 }
95ba8273 6144 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6145 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6146 false);
6147 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6148 }
6149 }
b6b8a145 6150 return 0;
95ba8273
GN		 6151}
6152
7460fb4a
AK		 6153static void process_nmi(struct kvm_vcpu *vcpu)
6154{
6155 unsigned limit = 2;
6156
6157 /*
6158 * x86 is limited to one NMI running, and one NMI pending after it.
6159 * If an NMI is already in progress, limit further NMIs to just one.
6160 * Otherwise, allow two (and we'll inject the first one immediately).
6161 */
6162 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6163 limit = 1;
6164
6165 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6166 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6167 kvm_make_request(KVM_REQ_EVENT, vcpu);
6168}
6169
660a5d51
PB		 6170#define put_smstate(type, buf, offset, val) \
6171 *(type *)((buf) + (offset) - 0x7e00) = val
6172
6173static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6174{
6175 u32 flags = 0;
6176 flags |= seg->g << 23;
6177 flags |= seg->db << 22;
6178 flags |= seg->l << 21;
6179 flags |= seg->avl << 20;
6180 flags |= seg->present << 15;
6181 flags |= seg->dpl << 13;
6182 flags |= seg->s << 12;
6183 flags |= seg->type << 8;
6184 return flags;
6185}
6186
6187static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6188{
6189 struct kvm_segment seg;
6190 int offset;
6191
6192 kvm_get_segment(vcpu, &seg, n);
6193 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6194
6195 if (n < 3)
6196 offset = 0x7f84 + n * 12;
6197 else
6198 offset = 0x7f2c + (n - 3) * 12;
6199
6200 put_smstate(u32, buf, offset + 8, seg.base);
6201 put_smstate(u32, buf, offset + 4, seg.limit);
6202 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6203}
6204
6205static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6206{
6207 struct kvm_segment seg;
6208 int offset;
6209 u16 flags;
6210
6211 kvm_get_segment(vcpu, &seg, n);
6212 offset = 0x7e00 + n * 16;
6213
6214 flags = process_smi_get_segment_flags(&seg) >> 8;
6215 put_smstate(u16, buf, offset, seg.selector);
6216 put_smstate(u16, buf, offset + 2, flags);
6217 put_smstate(u32, buf, offset + 4, seg.limit);
6218 put_smstate(u64, buf, offset + 8, seg.base);
6219}
6220
6221static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6222{
6223 struct desc_ptr dt;
6224 struct kvm_segment seg;
6225 unsigned long val;
6226 int i;
6227
6228 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6229 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6230 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6231 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6232
6233 for (i = 0; i < 8; i++)
6234 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6235
6236 kvm_get_dr(vcpu, 6, &val);
6237 put_smstate(u32, buf, 0x7fcc, (u32)val);
6238 kvm_get_dr(vcpu, 7, &val);
6239 put_smstate(u32, buf, 0x7fc8, (u32)val);
6240
6241 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6242 put_smstate(u32, buf, 0x7fc4, seg.selector);
6243 put_smstate(u32, buf, 0x7f64, seg.base);
6244 put_smstate(u32, buf, 0x7f60, seg.limit);
6245 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6246
6247 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6248 put_smstate(u32, buf, 0x7fc0, seg.selector);
6249 put_smstate(u32, buf, 0x7f80, seg.base);
6250 put_smstate(u32, buf, 0x7f7c, seg.limit);
6251 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6252
6253 kvm_x86_ops->get_gdt(vcpu, &dt);
6254 put_smstate(u32, buf, 0x7f74, dt.address);
6255 put_smstate(u32, buf, 0x7f70, dt.size);
6256
6257 kvm_x86_ops->get_idt(vcpu, &dt);
6258 put_smstate(u32, buf, 0x7f58, dt.address);
6259 put_smstate(u32, buf, 0x7f54, dt.size);
6260
6261 for (i = 0; i < 6; i++)
6262 process_smi_save_seg_32(vcpu, buf, i);
6263
6264 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6265
6266 /* revision id */
6267 put_smstate(u32, buf, 0x7efc, 0x00020000);
6268 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6269}
6270
6271static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6272{
6273#ifdef CONFIG_X86_64
6274 struct desc_ptr dt;
6275 struct kvm_segment seg;
6276 unsigned long val;
6277 int i;
6278
6279 for (i = 0; i < 16; i++)
6280 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6281
6282 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6283 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6284
6285 kvm_get_dr(vcpu, 6, &val);
6286 put_smstate(u64, buf, 0x7f68, val);
6287 kvm_get_dr(vcpu, 7, &val);
6288 put_smstate(u64, buf, 0x7f60, val);
6289
6290 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6291 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6292 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6293
6294 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6295
6296 /* revision id */
6297 put_smstate(u32, buf, 0x7efc, 0x00020064);
6298
6299 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6300
6301 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6302 put_smstate(u16, buf, 0x7e90, seg.selector);
6303 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6304 put_smstate(u32, buf, 0x7e94, seg.limit);
6305 put_smstate(u64, buf, 0x7e98, seg.base);
6306
6307 kvm_x86_ops->get_idt(vcpu, &dt);
6308 put_smstate(u32, buf, 0x7e84, dt.size);
6309 put_smstate(u64, buf, 0x7e88, dt.address);
6310
6311 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6312 put_smstate(u16, buf, 0x7e70, seg.selector);
6313 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6314 put_smstate(u32, buf, 0x7e74, seg.limit);
6315 put_smstate(u64, buf, 0x7e78, seg.base);
6316
6317 kvm_x86_ops->get_gdt(vcpu, &dt);
6318 put_smstate(u32, buf, 0x7e64, dt.size);
6319 put_smstate(u64, buf, 0x7e68, dt.address);
6320
6321 for (i = 0; i < 6; i++)
6322 process_smi_save_seg_64(vcpu, buf, i);
6323#else
6324 WARN_ON_ONCE(1);
6325#endif
6326}
6327
64d60670
PB		 6328static void process_smi(struct kvm_vcpu *vcpu)
6329{
660a5d51
PB		 6330 struct kvm_segment cs, ds;
6331 char buf[512];
6332 u32 cr0;
6333
64d60670
PB		 6334 if (is_smm(vcpu)) {
6335 vcpu->arch.smi_pending = true;
6336 return;
6337 }
6338
660a5d51
PB		 6339 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6340 vcpu->arch.hflags |= HF_SMM_MASK;
6341 memset(buf, 0, 512);
6342 if (guest_cpuid_has_longmode(vcpu))
6343 process_smi_save_state_64(vcpu, buf);
6344 else
6345 process_smi_save_state_32(vcpu, buf);
6346
54bf36aa 6347 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6348
6349 if (kvm_x86_ops->get_nmi_mask(vcpu))
6350 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6351 else
6352 kvm_x86_ops->set_nmi_mask(vcpu, true);
6353
6354 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6355 kvm_rip_write(vcpu, 0x8000);
6356
6357 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6358 kvm_x86_ops->set_cr0(vcpu, cr0);
6359 vcpu->arch.cr0 = cr0;
6360
6361 kvm_x86_ops->set_cr4(vcpu, 0);
6362
6363 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6364
6365 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6366 cs.base = vcpu->arch.smbase;
6367
6368 ds.selector = 0;
6369 ds.base = 0;
6370
6371 cs.limit = ds.limit = 0xffffffff;
6372 cs.type = ds.type = 0x3;
6373 cs.dpl = ds.dpl = 0;
6374 cs.db = ds.db = 0;
6375 cs.s = ds.s = 1;
6376 cs.l = ds.l = 0;
6377 cs.g = ds.g = 1;
6378 cs.avl = ds.avl = 0;
6379 cs.present = ds.present = 1;
6380 cs.unusable = ds.unusable = 0;
6381 cs.padding = ds.padding = 0;
6382
6383 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6384 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6385 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6386 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6387 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6388 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6389
6390 if (guest_cpuid_has_longmode(vcpu))
6391 kvm_x86_ops->set_efer(vcpu, 0);
6392
6393 kvm_update_cpuid(vcpu);
6394 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6395}
6396
3d81bc7e 6397static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6398{
6399 u64 eoi_exit_bitmap[4];
cf9e65b7 6400 u32 tmr[8];
c7c9c56c 6401
3d81bc7e
YZ		 6402 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6403 return;
c7c9c56c
YZ		 6404
6405 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6406 memset(tmr, 0, 32);
c7c9c56c 6407
cf9e65b7 6408 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6409 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6410 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6411}
6412
a70656b6
RK		 6413static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6414{
6415 ++vcpu->stat.tlb_flush;
6416 kvm_x86_ops->tlb_flush(vcpu);
6417}
6418
4256f43f
TC		 6419void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6420{
c24ae0dc
TC		 6421 struct page *page = NULL;
6422
f439ed27
PB		 6423 if (!irqchip_in_kernel(vcpu->kvm))
6424 return;
6425
4256f43f
TC		 6426 if (!kvm_x86_ops->set_apic_access_page_addr)
6427 return;
6428
c24ae0dc 6429 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6430 if (is_error_page(page))
6431 return;
c24ae0dc
TC		 6432 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6433
6434 /*
6435 * Do not pin apic access page in memory, the MMU notifier
6436 * will call us again if it is migrated or swapped out.
6437 */
6438 put_page(page);
4256f43f
TC		 6439}
6440EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6441
fe71557a
TC		 6442void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6443 unsigned long address)
6444{
c24ae0dc
TC		 6445 /*
6446 * The physical address of apic access page is stored in the VMCS.
6447 * Update it when it becomes invalid.
6448 */
6449 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6450 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6451}
6452
9357d939 6453/*
362c698f 6454 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6455 * exiting to the userspace. Otherwise, the value will be returned to the
6456 * userspace.
6457 */
851ba692 6458static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6459{
6460 int r;
6a8b1d13 6461 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6462 vcpu->run->request_interrupt_window;
730dca42 6463 bool req_immediate_exit = false;
b6c7a5dc 6464
3e007509 6465 if (vcpu->requests) {
a8eeb04a 6466 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6467 kvm_mmu_unload(vcpu);
a8eeb04a 6468 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6469 __kvm_migrate_timers(vcpu);
d828199e
MT		 6470 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6471 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6472 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6473 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6474 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6475 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6476 if (unlikely(r))
6477 goto out;
6478 }
a8eeb04a 6479 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6480 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6481 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6482 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6483 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6484 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6485 r = 0;
6486 goto out;
6487 }
a8eeb04a 6488 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6489 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6490 r = 0;
6491 goto out;
6492 }
a8eeb04a 6493 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6494 vcpu->fpu_active = 0;
6495 kvm_x86_ops->fpu_deactivate(vcpu);
6496 }
af585b92
GN		 6497 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6498 /* Page is swapped out. Do synthetic halt */
6499 vcpu->arch.apf.halted = true;
6500 r = 1;
6501 goto out;
6502 }
c9aaa895
GC		 6503 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6504 record_steal_time(vcpu);
64d60670
PB		 6505 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6506 process_smi(vcpu);
7460fb4a
AK		 6507 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6508 process_nmi(vcpu);
f5132b01 6509 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6510 kvm_pmu_handle_event(vcpu);
f5132b01 6511 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6512 kvm_pmu_deliver_pmi(vcpu);
3d81bc7e
YZ		 6513 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6514 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6515 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6516 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6517 }
b93463aa 6518
b463a6f7 6519 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6520 kvm_apic_accept_events(vcpu);
6521 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6522 r = 1;
6523 goto out;
6524 }
6525
b6b8a145
JK		 6526 if (inject_pending_event(vcpu, req_int_win) != 0)
6527 req_immediate_exit = true;
b463a6f7 6528 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6529 else if (vcpu->arch.nmi_pending)
c9a7953f 6530 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6531 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6532 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6533
6534 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6535 /*
6536 * Update architecture specific hints for APIC
6537 * virtual interrupt delivery.
6538 */
6539 if (kvm_x86_ops->hwapic_irr_update)
6540 kvm_x86_ops->hwapic_irr_update(vcpu,
6541 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6542 update_cr8_intercept(vcpu);
6543 kvm_lapic_sync_to_vapic(vcpu);
6544 }
6545 }
6546
d8368af8
AK		 6547 r = kvm_mmu_reload(vcpu);
6548 if (unlikely(r)) {
d905c069 6549 goto cancel_injection;
d8368af8
AK		 6550 }
6551
b6c7a5dc
HB		 6552 preempt_disable();
6553
6554 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6555 if (vcpu->fpu_active)
6556 kvm_load_guest_fpu(vcpu);
2acf923e 6557 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6558
6b7e2d09
XG		 6559 vcpu->mode = IN_GUEST_MODE;
6560
01b71917
MT		 6561 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6562
6b7e2d09
XG		 6563 /* We should set ->mode before check ->requests,
6564 * see the comment in make_all_cpus_request.
6565 */
01b71917 6566 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6567
d94e1dc9 6568 local_irq_disable();
32f88400 6569
6b7e2d09 6570 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6571 || need_resched() || signal_pending(current)) {
6b7e2d09 6572 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6573 smp_wmb();
6c142801
AK		 6574 local_irq_enable();
6575 preempt_enable();
01b71917 6576 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6577 r = 1;
d905c069 6578 goto cancel_injection;
6c142801
AK		 6579 }
6580
d6185f20
NHE		 6581 if (req_immediate_exit)
6582 smp_send_reschedule(vcpu->cpu);
6583
ccf73aaf 6584 __kvm_guest_enter();
b6c7a5dc 6585
42dbaa5a 6586 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6587 set_debugreg(0, 7);
6588 set_debugreg(vcpu->arch.eff_db[0], 0);
6589 set_debugreg(vcpu->arch.eff_db[1], 1);
6590 set_debugreg(vcpu->arch.eff_db[2], 2);
6591 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6592 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6593 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6594 }
b6c7a5dc 6595
229456fc 6596 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6597 wait_lapic_expire(vcpu);
851ba692 6598 kvm_x86_ops->run(vcpu);
b6c7a5dc 6599
c77fb5fe
PB		 6600 /*
6601 * Do this here before restoring debug registers on the host. And
6602 * since we do this before handling the vmexit, a DR access vmexit
6603 * can (a) read the correct value of the debug registers, (b) set
6604 * KVM_DEBUGREG_WONT_EXIT again.
6605 */
6606 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6607 int i;
6608
6609 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6610 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6611 for (i = 0; i < KVM_NR_DB_REGS; i++)
6612 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6613 }
6614
24f1e32c
FW		 6615 /*
6616 * If the guest has used debug registers, at least dr7
6617 * will be disabled while returning to the host.
6618 * If we don't have active breakpoints in the host, we don't
6619 * care about the messed up debug address registers. But if
6620 * we have some of them active, restore the old state.
6621 */
59d8eb53 6622 if (hw_breakpoint_active())
24f1e32c 6623 hw_breakpoint_restore();
42dbaa5a 6624
886b470c
MT		 6625 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6626 native_read_tsc());
1d5f066e 6627
6b7e2d09 6628 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6629 smp_wmb();
a547c6db
YZ		 6630
6631 /* Interrupt is enabled by handle_external_intr() */
6632 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6633
6634 ++vcpu->stat.exits;
6635
6636 /*
6637 * We must have an instruction between local_irq_enable() and
6638 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6639 * the interrupt shadow. The stat.exits increment will do nicely.
6640 * But we need to prevent reordering, hence this barrier():
6641 */
6642 barrier();
6643
6644 kvm_guest_exit();
6645
6646 preempt_enable();
6647
f656ce01 6648 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6649
b6c7a5dc
HB		 6650 /*
6651 * Profile KVM exit RIPs:
6652 */
6653 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6654 unsigned long rip = kvm_rip_read(vcpu);
6655 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6656 }
6657
cc578287
ZA		 6658 if (unlikely(vcpu->arch.tsc_always_catchup))
6659 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6660
5cfb1d5a
MT		 6661 if (vcpu->arch.apic_attention)
6662 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6663
851ba692 6664 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6665 return r;
6666
6667cancel_injection:
6668 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6669 if (unlikely(vcpu->arch.apic_attention))
6670 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6671out:
6672 return r;
6673}
b6c7a5dc 6674
362c698f
PB		 6675static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6676{
9c8fd1ba
PB		 6677 if (!kvm_arch_vcpu_runnable(vcpu)) {
6678 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6679 kvm_vcpu_block(vcpu);
6680 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6681 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6682 return 1;
6683 }
362c698f
PB		 6684
6685 kvm_apic_accept_events(vcpu);
6686 switch(vcpu->arch.mp_state) {
6687 case KVM_MP_STATE_HALTED:
6688 vcpu->arch.pv.pv_unhalted = false;
6689 vcpu->arch.mp_state =
6690 KVM_MP_STATE_RUNNABLE;
6691 case KVM_MP_STATE_RUNNABLE:
6692 vcpu->arch.apf.halted = false;
6693 break;
6694 case KVM_MP_STATE_INIT_RECEIVED:
6695 break;
6696 default:
6697 return -EINTR;
6698 break;
6699 }
6700 return 1;
6701}
09cec754 6702
362c698f 6703static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6704{
6705 int r;
f656ce01 6706 struct kvm *kvm = vcpu->kvm;
d7690175 6707
f656ce01 6708 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6709
362c698f 6710 for (;;) {
af585b92
GN		 6711 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6712 !vcpu->arch.apf.halted)
851ba692 6713 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6714 else
6715 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6716 if (r <= 0)
6717 break;
6718
6719 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6720 if (kvm_cpu_has_pending_timer(vcpu))
6721 kvm_inject_pending_timer_irqs(vcpu);
6722
851ba692 6723 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6724 r = -EINTR;
851ba692 6725 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6726 ++vcpu->stat.request_irq_exits;
362c698f 6727 break;
09cec754 6728 }
af585b92
GN		 6729
6730 kvm_check_async_pf_completion(vcpu);
6731
09cec754
GN		 6732 if (signal_pending(current)) {
6733 r = -EINTR;
851ba692 6734 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6735 ++vcpu->stat.signal_exits;
362c698f 6736 break;
09cec754
GN		 6737 }
6738 if (need_resched()) {
f656ce01 6739 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6740 cond_resched();
f656ce01 6741 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6742 }
b6c7a5dc
HB		 6743 }
6744
f656ce01 6745 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6746
6747 return r;
6748}
6749
716d51ab
GN		 6750static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6751{
6752 int r;
6753 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6754 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6755 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6756 if (r != EMULATE_DONE)
6757 return 0;
6758 return 1;
6759}
6760
6761static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6762{
6763 BUG_ON(!vcpu->arch.pio.count);
6764
6765 return complete_emulated_io(vcpu);
6766}
6767
f78146b0
AK		 6768/*
6769 * Implements the following, as a state machine:
6770 *
6771 * read:
6772 * for each fragment
87da7e66
XG		 6773 * for each mmio piece in the fragment
6774 * write gpa, len
6775 * exit
6776 * copy data
f78146b0
AK		 6777 * execute insn
6778 *
6779 * write:
6780 * for each fragment
87da7e66
XG		 6781 * for each mmio piece in the fragment
6782 * write gpa, len
6783 * copy data
6784 * exit
f78146b0 6785 */
716d51ab 6786static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6787{
6788 struct kvm_run *run = vcpu->run;
f78146b0 6789 struct kvm_mmio_fragment *frag;
87da7e66 6790 unsigned len;
5287f194 6791
716d51ab 6792 BUG_ON(!vcpu->mmio_needed);
5287f194 6793
716d51ab 6794 /* Complete previous fragment */
87da7e66
XG		 6795 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6796 len = min(8u, frag->len);
716d51ab 6797 if (!vcpu->mmio_is_write)
87da7e66
XG		 6798 memcpy(frag->data, run->mmio.data, len);
6799
6800 if (frag->len <= 8) {
6801 /* Switch to the next fragment. */
6802 frag++;
6803 vcpu->mmio_cur_fragment++;
6804 } else {
6805 /* Go forward to the next mmio piece. */
6806 frag->data += len;
6807 frag->gpa += len;
6808 frag->len -= len;
6809 }
6810
a08d3b3b 6811 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6812 vcpu->mmio_needed = 0;
0912c977
PB		 6813
6814 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6815 if (vcpu->mmio_is_write)
716d51ab
GN		 6816 return 1;
6817 vcpu->mmio_read_completed = 1;
6818 return complete_emulated_io(vcpu);
6819 }
87da7e66 6820
716d51ab
GN		 6821 run->exit_reason = KVM_EXIT_MMIO;
6822 run->mmio.phys_addr = frag->gpa;
6823 if (vcpu->mmio_is_write)
87da7e66
XG		 6824 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6825 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6826 run->mmio.is_write = vcpu->mmio_is_write;
6827 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6828 return 0;
5287f194
AK		 6829}
6830
716d51ab 6831
b6c7a5dc
HB		 6832int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6833{
c5bedc68 6834 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6835 int r;
6836 sigset_t sigsaved;
6837
c4d72e2d 6838 fpu__activate_curr(fpu);
e5c30142 6839
ac9f6dc0
AK		 6840 if (vcpu->sigset_active)
6841 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6842
a4535290 6843 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6844 kvm_vcpu_block(vcpu);
66450a21 6845 kvm_apic_accept_events(vcpu);
d7690175 6846 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6847 r = -EAGAIN;
6848 goto out;
b6c7a5dc
HB		 6849 }
6850
b6c7a5dc 6851 /* re-sync apic's tpr */
eea1cff9
AP		 6852 if (!irqchip_in_kernel(vcpu->kvm)) {
6853 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6854 r = -EINVAL;
6855 goto out;
6856 }
6857 }
b6c7a5dc 6858
716d51ab
GN		 6859 if (unlikely(vcpu->arch.complete_userspace_io)) {
6860 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6861 vcpu->arch.complete_userspace_io = NULL;
6862 r = cui(vcpu);
6863 if (r <= 0)
6864 goto out;
6865 } else
6866 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6867
362c698f 6868 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6869
6870out:
f1d86e46 6871 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6872 if (vcpu->sigset_active)
6873 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6874
b6c7a5dc
HB		 6875 return r;
6876}
6877
6878int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6879{
7ae441ea
GN		 6880 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6881 /*
6882 * We are here if userspace calls get_regs() in the middle of
6883 * instruction emulation. Registers state needs to be copied
4a969980 6884 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6885 * that usually, but some bad designed PV devices (vmware
6886 * backdoor interface) need this to work
6887 */
dd856efa 6888 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6889 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6890 }
5fdbf976
MT		 6891 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6892 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6893 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6894 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6895 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6896 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6897 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6898 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6899#ifdef CONFIG_X86_64
5fdbf976
MT		 6900 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6901 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6902 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6903 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6904 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6905 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6906 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6907 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6908#endif
6909
5fdbf976 6910 regs->rip = kvm_rip_read(vcpu);
91586a3b 6911 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6912
b6c7a5dc
HB		 6913 return 0;
6914}
6915
6916int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6917{
7ae441ea
GN		 6918 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6919 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6920
5fdbf976
MT		 6921 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6922 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6923 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6924 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6925 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6926 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6927 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6928 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6929#ifdef CONFIG_X86_64
5fdbf976
MT		 6930 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6931 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6932 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6933 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6934 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6935 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6936 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6937 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6938#endif
6939
5fdbf976 6940 kvm_rip_write(vcpu, regs->rip);
91586a3b 6941 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6942
b4f14abd
JK		 6943 vcpu->arch.exception.pending = false;
6944
3842d135
AK		 6945 kvm_make_request(KVM_REQ_EVENT, vcpu);
6946
b6c7a5dc
HB		 6947 return 0;
6948}
6949
b6c7a5dc
HB		 6950void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6951{
6952 struct kvm_segment cs;
6953
3e6e0aab 6954 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6955 *db = cs.db;
6956 *l = cs.l;
6957}
6958EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6959
6960int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6961 struct kvm_sregs *sregs)
6962{
89a27f4d 6963 struct desc_ptr dt;
b6c7a5dc 6964
3e6e0aab
GT		 6965 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6966 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6967 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6968 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6969 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6970 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6971
3e6e0aab
GT		 6972 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6973 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6974
6975 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6976 sregs->idt.limit = dt.size;
6977 sregs->idt.base = dt.address;
b6c7a5dc 6978 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6979 sregs->gdt.limit = dt.size;
6980 sregs->gdt.base = dt.address;
b6c7a5dc 6981
4d4ec087 6982 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6983 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6984 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6985 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6986 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6987 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6988 sregs->apic_base = kvm_get_apic_base(vcpu);
6989
923c61bb 6990 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6991
36752c9b 6992 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6993 set_bit(vcpu->arch.interrupt.nr,
6994 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6995
b6c7a5dc
HB		 6996 return 0;
6997}
6998
62d9f0db
MT		 6999int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7000 struct kvm_mp_state *mp_state)
7001{
66450a21 7002 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7003 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7004 vcpu->arch.pv.pv_unhalted)
7005 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7006 else
7007 mp_state->mp_state = vcpu->arch.mp_state;
7008
62d9f0db
MT		 7009 return 0;
7010}
7011
7012int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7013 struct kvm_mp_state *mp_state)
7014{
66450a21
JK		 7015 if (!kvm_vcpu_has_lapic(vcpu) &&
7016 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7017 return -EINVAL;
7018
7019 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7020 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7021 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7022 } else
7023 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7024 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7025 return 0;
7026}
7027
7f3d35fd
KW		 7028int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7029 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7030{
9d74191a 7031 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7032 int ret;
e01c2426 7033
8ec4722d 7034 init_emulate_ctxt(vcpu);
c697518a 7035
7f3d35fd 7036 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7037 has_error_code, error_code);
c697518a 7038
c697518a 7039 if (ret)
19d04437 7040 return EMULATE_FAIL;
37817f29 7041
9d74191a
TY		 7042 kvm_rip_write(vcpu, ctxt->eip);
7043 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7044 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7045 return EMULATE_DONE;
37817f29
IE		 7046}
7047EXPORT_SYMBOL_GPL(kvm_task_switch);
7048
b6c7a5dc
HB		 7049int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7050 struct kvm_sregs *sregs)
7051{
58cb628d 7052 struct msr_data apic_base_msr;
b6c7a5dc 7053 int mmu_reset_needed = 0;
63f42e02 7054 int pending_vec, max_bits, idx;
89a27f4d 7055 struct desc_ptr dt;
b6c7a5dc 7056
6d1068b3
PM		 7057 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7058 return -EINVAL;
7059
89a27f4d
GN		 7060 dt.size = sregs->idt.limit;
7061 dt.address = sregs->idt.base;
b6c7a5dc 7062 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7063 dt.size = sregs->gdt.limit;
7064 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7065 kvm_x86_ops->set_gdt(vcpu, &dt);
7066
ad312c7c 7067 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7068 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7069 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7070 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7071
2d3ad1f4 7072 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7073
f6801dff 7074 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7075 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7076 apic_base_msr.data = sregs->apic_base;
7077 apic_base_msr.host_initiated = true;
7078 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7079
4d4ec087 7080 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7081 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7082 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7083
fc78f519 7084 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7085 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7086 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7087 kvm_update_cpuid(vcpu);
63f42e02
XG		 7088
7089 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7090 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7091 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7092 mmu_reset_needed = 1;
7093 }
63f42e02 7094 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7095
7096 if (mmu_reset_needed)
7097 kvm_mmu_reset_context(vcpu);
7098
a50abc3b 7099 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7100 pending_vec = find_first_bit(
7101 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7102 if (pending_vec < max_bits) {
66fd3f7f 7103 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7104 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7105 }
7106
3e6e0aab
GT		 7107 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7108 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7109 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7110 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7111 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7112 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7113
3e6e0aab
GT		 7114 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7115 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7116
5f0269f5
ME		 7117 update_cr8_intercept(vcpu);
7118
9c3e4aab 7119 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7120 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7121 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7122 !is_protmode(vcpu))
9c3e4aab
MT		 7123 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7124
3842d135
AK		 7125 kvm_make_request(KVM_REQ_EVENT, vcpu);
7126
b6c7a5dc
HB		 7127 return 0;
7128}
7129
d0bfb940
JK		 7130int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7131 struct kvm_guest_debug *dbg)
b6c7a5dc 7132{
355be0b9 7133 unsigned long rflags;
ae675ef0 7134 int i, r;
b6c7a5dc 7135
4f926bf2
JK		 7136 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7137 r = -EBUSY;
7138 if (vcpu->arch.exception.pending)
2122ff5e 7139 goto out;
4f926bf2
JK		 7140 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7141 kvm_queue_exception(vcpu, DB_VECTOR);
7142 else
7143 kvm_queue_exception(vcpu, BP_VECTOR);
7144 }
7145
91586a3b
JK		 7146 /*
7147 * Read rflags as long as potentially injected trace flags are still
7148 * filtered out.
7149 */
7150 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7151
7152 vcpu->guest_debug = dbg->control;
7153 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7154 vcpu->guest_debug = 0;
7155
7156 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7157 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7158 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7159 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7160 } else {
7161 for (i = 0; i < KVM_NR_DB_REGS; i++)
7162 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7163 }
c8639010 7164 kvm_update_dr7(vcpu);
ae675ef0 7165
f92653ee
JK		 7166 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7167 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7168 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7169
91586a3b
JK		 7170 /*
7171 * Trigger an rflags update that will inject or remove the trace
7172 * flags.
7173 */
7174 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7175
c8639010 7176 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7177
4f926bf2 7178 r = 0;
d0bfb940 7179
2122ff5e 7180out:
b6c7a5dc
HB		 7181
7182 return r;
7183}
7184
8b006791
ZX		 7185/*
7186 * Translate a guest virtual address to a guest physical address.
7187 */
7188int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7189 struct kvm_translation *tr)
7190{
7191 unsigned long vaddr = tr->linear_address;
7192 gpa_t gpa;
f656ce01 7193 int idx;
8b006791 7194
f656ce01 7195 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7196 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7197 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7198 tr->physical_address = gpa;
7199 tr->valid = gpa != UNMAPPED_GVA;
7200 tr->writeable = 1;
7201 tr->usermode = 0;
8b006791
ZX		 7202
7203 return 0;
7204}
7205
d0752060
HB		 7206int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7207{
c47ada30 7208 struct fxregs_state *fxsave =
7366ed77 7209 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7210
d0752060
HB		 7211 memcpy(fpu->fpr, fxsave->st_space, 128);
7212 fpu->fcw = fxsave->cwd;
7213 fpu->fsw = fxsave->swd;
7214 fpu->ftwx = fxsave->twd;
7215 fpu->last_opcode = fxsave->fop;
7216 fpu->last_ip = fxsave->rip;
7217 fpu->last_dp = fxsave->rdp;
7218 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7219
d0752060
HB		 7220 return 0;
7221}
7222
7223int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7224{
c47ada30 7225 struct fxregs_state *fxsave =
7366ed77 7226 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7227
d0752060
HB		 7228 memcpy(fxsave->st_space, fpu->fpr, 128);
7229 fxsave->cwd = fpu->fcw;
7230 fxsave->swd = fpu->fsw;
7231 fxsave->twd = fpu->ftwx;
7232 fxsave->fop = fpu->last_opcode;
7233 fxsave->rip = fpu->last_ip;
7234 fxsave->rdp = fpu->last_dp;
7235 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7236
d0752060
HB		 7237 return 0;
7238}
7239
0ee6a517 7240static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7241{
bf935b0b 7242 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7243 if (cpu_has_xsaves)
7366ed77 7244 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7245 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7246
2acf923e
DC		 7247 /*
7248 * Ensure guest xcr0 is valid for loading
7249 */
7250 vcpu->arch.xcr0 = XSTATE_FP;
7251
ad312c7c 7252 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7253}
d0752060
HB		 7254
7255void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7256{
2608d7a1 7257 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7258 return;
7259
2acf923e
DC		 7260 /*
7261 * Restore all possible states in the guest,
7262 * and assume host would use all available bits.
7263 * Guest xcr0 would be loaded later.
7264 */
7265 kvm_put_guest_xcr0(vcpu);
d0752060 7266 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7267 __kernel_fpu_begin();
003e2e8b 7268 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7269 trace_kvm_fpu(1);
d0752060 7270}
d0752060
HB		 7271
7272void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7273{
2acf923e
DC		 7274 kvm_put_guest_xcr0(vcpu);
7275
653f52c3
RR		 7276 if (!vcpu->guest_fpu_loaded) {
7277 vcpu->fpu_counter = 0;
d0752060 7278 return;
653f52c3 7279 }
d0752060
HB		 7280
7281 vcpu->guest_fpu_loaded = 0;
4f836347 7282 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7283 __kernel_fpu_end();
f096ed85 7284 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7285 /*
7286 * If using eager FPU mode, or if the guest is a frequent user
7287 * of the FPU, just leave the FPU active for next time.
7288 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7289 * the FPU in bursts will revert to loading it on demand.
7290 */
a9b4fb7e 7291 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7292 if (++vcpu->fpu_counter < 5)
7293 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7294 }
0c04851c 7295 trace_kvm_fpu(0);
d0752060 7296}
e9b11c17
ZX		 7297
7298void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7299{
12f9a48f 7300 kvmclock_reset(vcpu);
7f1ea208 7301
f5f48ee1 7302 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7303 kvm_x86_ops->vcpu_free(vcpu);
7304}
7305
7306struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7307 unsigned int id)
7308{
c447e76b
LL		 7309 struct kvm_vcpu *vcpu;
7310
6755bae8
ZA		 7311 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7312 printk_once(KERN_WARNING
7313 "kvm: SMP vm created on host with unstable TSC; "
7314 "guest TSC will not be reliable\n");
c447e76b
LL		 7315
7316 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7317
7318 /*
7319 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7320 * deactivated soon if it doesn't.
7321 */
7322 kvm_x86_ops->fpu_activate(vcpu);
7323 return vcpu;
26e5215f 7324}
e9b11c17 7325
26e5215f
AK		 7326int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7327{
7328 int r;
e9b11c17 7329
19efffa2 7330 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7331 r = vcpu_load(vcpu);
7332 if (r)
7333 return r;
d28bc9dd 7334 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7335 kvm_mmu_setup(vcpu);
e9b11c17 7336 vcpu_put(vcpu);
26e5215f 7337 return r;
e9b11c17
ZX		 7338}
7339
31928aa5 7340void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7341{
8fe8ab46 7342 struct msr_data msr;
332967a3 7343 struct kvm *kvm = vcpu->kvm;
42897d86 7344
31928aa5
DD		 7345 if (vcpu_load(vcpu))
7346 return;
8fe8ab46
WA		 7347 msr.data = 0x0;
7348 msr.index = MSR_IA32_TSC;
7349 msr.host_initiated = true;
7350 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7351 vcpu_put(vcpu);
7352
630994b3
MT		 7353 if (!kvmclock_periodic_sync)
7354 return;
7355
332967a3
AJ		 7356 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7357 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7358}
7359
d40ccc62 7360void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7361{
9fc77441 7362 int r;
344d9588
GN		 7363 vcpu->arch.apf.msr_val = 0;
7364
9fc77441
MT		 7365 r = vcpu_load(vcpu);
7366 BUG_ON(r);
e9b11c17
ZX		 7367 kvm_mmu_unload(vcpu);
7368 vcpu_put(vcpu);
7369
7370 kvm_x86_ops->vcpu_free(vcpu);
7371}
7372
d28bc9dd 7373void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7374{
e69fab5d
PB		 7375 vcpu->arch.hflags = 0;
7376
7460fb4a
AK		 7377 atomic_set(&vcpu->arch.nmi_queued, 0);
7378 vcpu->arch.nmi_pending = 0;
448fa4a9 7379 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7380 kvm_clear_interrupt_queue(vcpu);
7381 kvm_clear_exception_queue(vcpu);
448fa4a9 7382
42dbaa5a 7383 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7384 kvm_update_dr0123(vcpu);
6f43ed01 7385 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7386 kvm_update_dr6(vcpu);
42dbaa5a 7387 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7388 kvm_update_dr7(vcpu);
42dbaa5a 7389
1119022c
NA		 7390 vcpu->arch.cr2 = 0;
7391
3842d135 7392 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7393 vcpu->arch.apf.msr_val = 0;
c9aaa895 7394 vcpu->arch.st.msr_val = 0;
3842d135 7395
12f9a48f
GC		 7396 kvmclock_reset(vcpu);
7397
af585b92
GN		 7398 kvm_clear_async_pf_completion_queue(vcpu);
7399 kvm_async_pf_hash_reset(vcpu);
7400 vcpu->arch.apf.halted = false;
3842d135 7401
64d60670 7402 if (!init_event) {
d28bc9dd 7403 kvm_pmu_reset(vcpu);
64d60670
PB		 7404 vcpu->arch.smbase = 0x30000;
7405 }
f5132b01 7406
66f7b72e
JS		 7407 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7408 vcpu->arch.regs_avail = ~0;
7409 vcpu->arch.regs_dirty = ~0;
7410
d28bc9dd 7411 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7412}
7413
2b4a273b 7414void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7415{
7416 struct kvm_segment cs;
7417
7418 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7419 cs.selector = vector << 8;
7420 cs.base = vector << 12;
7421 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7422 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7423}
7424
13a34e06 7425int kvm_arch_hardware_enable(void)
e9b11c17 7426{
ca84d1a2
ZA		 7427 struct kvm *kvm;
7428 struct kvm_vcpu *vcpu;
7429 int i;
0dd6a6ed
ZA		 7430 int ret;
7431 u64 local_tsc;
7432 u64 max_tsc = 0;
7433 bool stable, backwards_tsc = false;
18863bdd
AK		 7434
7435 kvm_shared_msr_cpu_online();
13a34e06 7436 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7437 if (ret != 0)
7438 return ret;
7439
7440 local_tsc = native_read_tsc();
7441 stable = !check_tsc_unstable();
7442 list_for_each_entry(kvm, &vm_list, vm_list) {
7443 kvm_for_each_vcpu(i, vcpu, kvm) {
7444 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7445 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7446 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7447 backwards_tsc = true;
7448 if (vcpu->arch.last_host_tsc > max_tsc)
7449 max_tsc = vcpu->arch.last_host_tsc;
7450 }
7451 }
7452 }
7453
7454 /*
7455 * Sometimes, even reliable TSCs go backwards. This happens on
7456 * platforms that reset TSC during suspend or hibernate actions, but
7457 * maintain synchronization. We must compensate. Fortunately, we can
7458 * detect that condition here, which happens early in CPU bringup,
7459 * before any KVM threads can be running. Unfortunately, we can't
7460 * bring the TSCs fully up to date with real time, as we aren't yet far
7461 * enough into CPU bringup that we know how much real time has actually
7462 * elapsed; our helper function, get_kernel_ns() will be using boot
7463 * variables that haven't been updated yet.
7464 *
7465 * So we simply find the maximum observed TSC above, then record the
7466 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7467 * the adjustment will be applied. Note that we accumulate
7468 * adjustments, in case multiple suspend cycles happen before some VCPU
7469 * gets a chance to run again. In the event that no KVM threads get a
7470 * chance to run, we will miss the entire elapsed period, as we'll have
7471 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7472 * loose cycle time. This isn't too big a deal, since the loss will be
7473 * uniform across all VCPUs (not to mention the scenario is extremely
7474 * unlikely). It is possible that a second hibernate recovery happens
7475 * much faster than a first, causing the observed TSC here to be
7476 * smaller; this would require additional padding adjustment, which is
7477 * why we set last_host_tsc to the local tsc observed here.
7478 *
7479 * N.B. - this code below runs only on platforms with reliable TSC,
7480 * as that is the only way backwards_tsc is set above. Also note
7481 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7482 * have the same delta_cyc adjustment applied if backwards_tsc
7483 * is detected. Note further, this adjustment is only done once,
7484 * as we reset last_host_tsc on all VCPUs to stop this from being
7485 * called multiple times (one for each physical CPU bringup).
7486 *
4a969980 7487 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7488 * will be compensated by the logic in vcpu_load, which sets the TSC to
7489 * catchup mode. This will catchup all VCPUs to real time, but cannot
7490 * guarantee that they stay in perfect synchronization.
7491 */
7492 if (backwards_tsc) {
7493 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7494 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7495 list_for_each_entry(kvm, &vm_list, vm_list) {
7496 kvm_for_each_vcpu(i, vcpu, kvm) {
7497 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7498 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7499 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7500 }
7501
7502 /*
7503 * We have to disable TSC offset matching.. if you were
7504 * booting a VM while issuing an S4 host suspend....
7505 * you may have some problem. Solving this issue is
7506 * left as an exercise to the reader.
7507 */
7508 kvm->arch.last_tsc_nsec = 0;
7509 kvm->arch.last_tsc_write = 0;
7510 }
7511
7512 }
7513 return 0;
e9b11c17
ZX		 7514}
7515
13a34e06 7516void kvm_arch_hardware_disable(void)
e9b11c17 7517{
13a34e06
RK		 7518 kvm_x86_ops->hardware_disable();
7519 drop_user_return_notifiers();
e9b11c17
ZX		 7520}
7521
7522int kvm_arch_hardware_setup(void)
7523{
9e9c3fe4
NA		 7524 int r;
7525
7526 r = kvm_x86_ops->hardware_setup();
7527 if (r != 0)
7528 return r;
7529
7530 kvm_init_msr_list();
7531 return 0;
e9b11c17
ZX		 7532}
7533
7534void kvm_arch_hardware_unsetup(void)
7535{
7536 kvm_x86_ops->hardware_unsetup();
7537}
7538
7539void kvm_arch_check_processor_compat(void *rtn)
7540{
7541 kvm_x86_ops->check_processor_compatibility(rtn);
7542}
7543
3e515705
AK		 7544bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7545{
7546 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7547}
7548
54e9818f
GN		 7549struct static_key kvm_no_apic_vcpu __read_mostly;
7550
e9b11c17
ZX		 7551int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7552{
7553 struct page *page;
7554 struct kvm *kvm;
7555 int r;
7556
7557 BUG_ON(vcpu->kvm == NULL);
7558 kvm = vcpu->kvm;
7559
6aef266c 7560 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7561 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7562 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7563 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7564 else
a4535290 7565 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7566
7567 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7568 if (!page) {
7569 r = -ENOMEM;
7570 goto fail;
7571 }
ad312c7c 7572 vcpu->arch.pio_data = page_address(page);
e9b11c17 7573
cc578287 7574 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7575
e9b11c17
ZX		 7576 r = kvm_mmu_create(vcpu);
7577 if (r < 0)
7578 goto fail_free_pio_data;
7579
7580 if (irqchip_in_kernel(kvm)) {
7581 r = kvm_create_lapic(vcpu);
7582 if (r < 0)
7583 goto fail_mmu_destroy;
54e9818f
GN		 7584 } else
7585 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7586
890ca9ae
HY		 7587 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7588 GFP_KERNEL);
7589 if (!vcpu->arch.mce_banks) {
7590 r = -ENOMEM;
443c39bc 7591 goto fail_free_lapic;
890ca9ae
HY		 7592 }
7593 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7594
f1797359
WY		 7595 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7596 r = -ENOMEM;
f5f48ee1 7597 goto fail_free_mce_banks;
f1797359 7598 }
f5f48ee1 7599
0ee6a517 7600 fx_init(vcpu);
66f7b72e 7601
ba904635 7602 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7603 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7604
7605 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7606 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7607
5a4f55cd
EK		 7608 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7609
74545705
RK		 7610 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7611
af585b92 7612 kvm_async_pf_hash_reset(vcpu);
f5132b01 7613 kvm_pmu_init(vcpu);
af585b92 7614
e9b11c17 7615 return 0;
0ee6a517 7616
f5f48ee1
SY		 7617fail_free_mce_banks:
7618 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7619fail_free_lapic:
7620 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7621fail_mmu_destroy:
7622 kvm_mmu_destroy(vcpu);
7623fail_free_pio_data:
ad312c7c 7624 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7625fail:
7626 return r;
7627}
7628
7629void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7630{
f656ce01
MT		 7631 int idx;
7632
f5132b01 7633 kvm_pmu_destroy(vcpu);
36cb93fd 7634 kfree(vcpu->arch.mce_banks);
e9b11c17 7635 kvm_free_lapic(vcpu);
f656ce01 7636 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7637 kvm_mmu_destroy(vcpu);
f656ce01 7638 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7639 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7640 if (!irqchip_in_kernel(vcpu->kvm))
7641 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7642}
d19a9cd2 7643
e790d9ef
RK		 7644void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7645{
ae97a3b8 7646 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7647}
7648
e08b9637 7649int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7650{
e08b9637
CO		 7651 if (type)
7652 return -EINVAL;
7653
6ef768fa 7654 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7655 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7656 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7657 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7658 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7659
5550af4d
SY		 7660 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7661 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7662 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7663 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7664 &kvm->arch.irq_sources_bitmap);
5550af4d 7665
038f8c11 7666 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7667 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7668 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7669
7670 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7671
7e44e449 7672 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7673 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7674
d89f5eff 7675 return 0;
d19a9cd2
ZX		 7676}
7677
7678static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7679{
9fc77441
MT		 7680 int r;
7681 r = vcpu_load(vcpu);
7682 BUG_ON(r);
d19a9cd2
ZX		 7683 kvm_mmu_unload(vcpu);
7684 vcpu_put(vcpu);
7685}
7686
7687static void kvm_free_vcpus(struct kvm *kvm)
7688{
7689 unsigned int i;
988a2cae 7690 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7691
7692 /*
7693 * Unpin any mmu pages first.
7694 */
af585b92
GN		 7695 kvm_for_each_vcpu(i, vcpu, kvm) {
7696 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7697 kvm_unload_vcpu_mmu(vcpu);
af585b92 7698 }
988a2cae
GN		 7699 kvm_for_each_vcpu(i, vcpu, kvm)
7700 kvm_arch_vcpu_free(vcpu);
7701
7702 mutex_lock(&kvm->lock);
7703 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7704 kvm->vcpus[i] = NULL;
d19a9cd2 7705
988a2cae
GN		 7706 atomic_set(&kvm->online_vcpus, 0);
7707 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7708}
7709
ad8ba2cd
SY		 7710void kvm_arch_sync_events(struct kvm *kvm)
7711{
332967a3 7712 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7713 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7714 kvm_free_all_assigned_devices(kvm);
aea924f6 7715 kvm_free_pit(kvm);
ad8ba2cd
SY		 7716}
7717
9da0e4d5
PB		 7718int __x86_set_memory_region(struct kvm *kvm,
7719 const struct kvm_userspace_memory_region *mem)
7720{
7721 int i, r;
7722
7723 /* Called with kvm->slots_lock held. */
7724 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7725
7726 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7727 struct kvm_userspace_memory_region m = *mem;
7728
7729 m.slot |= i << 16;
7730 r = __kvm_set_memory_region(kvm, &m);
7731 if (r < 0)
7732 return r;
7733 }
7734
7735 return 0;
7736}
7737EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7738
7739int x86_set_memory_region(struct kvm *kvm,
7740 const struct kvm_userspace_memory_region *mem)
7741{
7742 int r;
7743
7744 mutex_lock(&kvm->slots_lock);
7745 r = __x86_set_memory_region(kvm, mem);
7746 mutex_unlock(&kvm->slots_lock);
7747
7748 return r;
7749}
7750EXPORT_SYMBOL_GPL(x86_set_memory_region);
7751
d19a9cd2
ZX		 7752void kvm_arch_destroy_vm(struct kvm *kvm)
7753{
27469d29
AH		 7754 if (current->mm == kvm->mm) {
7755 /*
7756 * Free memory regions allocated on behalf of userspace,
7757 * unless the the memory map has changed due to process exit
7758 * or fd copying.
7759 */
7760 struct kvm_userspace_memory_region mem;
7761 memset(&mem, 0, sizeof(mem));
7762 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7763 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7764
7765 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7766 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7767
7768 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7769 x86_set_memory_region(kvm, &mem);
27469d29 7770 }
6eb55818 7771 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7772 kfree(kvm->arch.vpic);
7773 kfree(kvm->arch.vioapic);
d19a9cd2 7774 kvm_free_vcpus(kvm);
1e08ec4a 7775 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7776}
0de10343 7777
5587027c 7778void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7779 struct kvm_memory_slot *dont)
7780{
7781 int i;
7782
d89cc617
TY		 7783 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7784 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7785 kvfree(free->arch.rmap[i]);
d89cc617 7786 free->arch.rmap[i] = NULL;
77d11309 7787 }
d89cc617
TY		 7788 if (i == 0)
7789 continue;
7790
7791 if (!dont || free->arch.lpage_info[i - 1] !=
7792 dont->arch.lpage_info[i - 1]) {
548ef284 7793 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7794 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7795 }
7796 }
7797}
7798
5587027c
AK		 7799int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7800 unsigned long npages)
db3fe4eb
TY		 7801{
7802 int i;
7803
d89cc617 7804 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7805 unsigned long ugfn;
7806 int lpages;
d89cc617 7807 int level = i + 1;
db3fe4eb
TY		 7808
7809 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7810 slot->base_gfn, level) + 1;
7811
d89cc617
TY		 7812 slot->arch.rmap[i] =
7813 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7814 if (!slot->arch.rmap[i])
77d11309 7815 goto out_free;
d89cc617
TY		 7816 if (i == 0)
7817 continue;
77d11309 7818
d89cc617
TY		 7819 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7820 sizeof(*slot->arch.lpage_info[i - 1]));
7821 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7822 goto out_free;
7823
7824 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7825 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7826 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7827 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7828 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7829 /*
7830 * If the gfn and userspace address are not aligned wrt each
7831 * other, or if explicitly asked to, disable large page
7832 * support for this slot
7833 */
7834 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7835 !kvm_largepages_enabled()) {
7836 unsigned long j;
7837
7838 for (j = 0; j < lpages; ++j)
d89cc617 7839 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7840 }
7841 }
7842
7843 return 0;
7844
7845out_free:
d89cc617 7846 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7847 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7848 slot->arch.rmap[i] = NULL;
7849 if (i == 0)
7850 continue;
7851
548ef284 7852 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7853 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7854 }
7855 return -ENOMEM;
7856}
7857
15f46015 7858void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7859{
e6dff7d1
TY		 7860 /*
7861 * memslots->generation has been incremented.
7862 * mmio generation may have reached its maximum value.
7863 */
54bf36aa 7864 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7865}
7866
f7784b8e
MT		 7867int kvm_arch_prepare_memory_region(struct kvm *kvm,
7868 struct kvm_memory_slot *memslot,
09170a49 7869 const struct kvm_userspace_memory_region *mem,
7b6195a9 7870 enum kvm_mr_change change)
0de10343 7871{
7a905b14
TY		 7872 /*
7873 * Only private memory slots need to be mapped here since
7874 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7875 */
7b6195a9 7876 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7877 unsigned long userspace_addr;
604b38ac 7878
7a905b14
TY		 7879 /*
7880 * MAP_SHARED to prevent internal slot pages from being moved
7881 * by fork()/COW.
7882 */
7b6195a9 7883 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7884 PROT_READ | PROT_WRITE,
7885 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7886
7a905b14
TY		 7887 if (IS_ERR((void *)userspace_addr))
7888 return PTR_ERR((void *)userspace_addr);
604b38ac 7889
7a905b14 7890 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7891 }
7892
f7784b8e
MT		 7893 return 0;
7894}
7895
88178fd4
KH		 7896static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7897 struct kvm_memory_slot *new)
7898{
7899 /* Still write protect RO slot */
7900 if (new->flags & KVM_MEM_READONLY) {
7901 kvm_mmu_slot_remove_write_access(kvm, new);
7902 return;
7903 }
7904
7905 /*
7906 * Call kvm_x86_ops dirty logging hooks when they are valid.
7907 *
7908 * kvm_x86_ops->slot_disable_log_dirty is called when:
7909 *
7910 * - KVM_MR_CREATE with dirty logging is disabled
7911 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7912 *
7913 * The reason is, in case of PML, we need to set D-bit for any slots
7914 * with dirty logging disabled in order to eliminate unnecessary GPA
7915 * logging in PML buffer (and potential PML buffer full VMEXT). This
7916 * guarantees leaving PML enabled during guest's lifetime won't have
7917 * any additonal overhead from PML when guest is running with dirty
7918 * logging disabled for memory slots.
7919 *
7920 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7921 * to dirty logging mode.
7922 *
7923 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7924 *
7925 * In case of write protect:
7926 *
7927 * Write protect all pages for dirty logging.
7928 *
7929 * All the sptes including the large sptes which point to this
7930 * slot are set to readonly. We can not create any new large
7931 * spte on this slot until the end of the logging.
7932 *
7933 * See the comments in fast_page_fault().
7934 */
7935 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7936 if (kvm_x86_ops->slot_enable_log_dirty)
7937 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7938 else
7939 kvm_mmu_slot_remove_write_access(kvm, new);
7940 } else {
7941 if (kvm_x86_ops->slot_disable_log_dirty)
7942 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7943 }
7944}
7945
f7784b8e 7946void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7947 const struct kvm_userspace_memory_region *mem,
8482644a 7948 const struct kvm_memory_slot *old,
f36f3f28 7949 const struct kvm_memory_slot *new,
8482644a 7950 enum kvm_mr_change change)
f7784b8e 7951{
8482644a 7952 int nr_mmu_pages = 0;
f7784b8e 7953
f36f3f28 7954 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7955 int ret;
7956
8482644a
TY		 7957 ret = vm_munmap(old->userspace_addr,
7958 old->npages * PAGE_SIZE);
f7784b8e
MT		 7959 if (ret < 0)
7960 printk(KERN_WARNING
7961 "kvm_vm_ioctl_set_memory_region: "
7962 "failed to munmap memory\n");
7963 }
7964
48c0e4e9
XG		 7965 if (!kvm->arch.n_requested_mmu_pages)
7966 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7967
48c0e4e9 7968 if (nr_mmu_pages)
0de10343 7969 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7970
3ea3b7fa
WL		 7971 /*
7972 * Dirty logging tracks sptes in 4k granularity, meaning that large
7973 * sptes have to be split. If live migration is successful, the guest
7974 * in the source machine will be destroyed and large sptes will be
7975 * created in the destination. However, if the guest continues to run
7976 * in the source machine (for example if live migration fails), small
7977 * sptes will remain around and cause bad performance.
7978 *
7979 * Scan sptes if dirty logging has been stopped, dropping those
7980 * which can be collapsed into a single large-page spte. Later
7981 * page faults will create the large-page sptes.
7982 */
7983 if ((change != KVM_MR_DELETE) &&
7984 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7985 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7986 kvm_mmu_zap_collapsible_sptes(kvm, new);
7987
c972f3b1 7988 /*
88178fd4 7989 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7990 *
88178fd4
KH		 7991 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7992 * been zapped so no dirty logging staff is needed for old slot. For
7993 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7994 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7995 *
7996 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7997 */
88178fd4 7998 if (change != KVM_MR_DELETE)
f36f3f28 7999 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8000}
1d737c8a 8001
2df72e9b 8002void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8003{
6ca18b69 8004 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8005}
8006
2df72e9b
MT		 8007void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8008 struct kvm_memory_slot *slot)
8009{
6ca18b69 8010 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8011}
8012
1d737c8a
ZX		 8013int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8014{
b6b8a145
JK		 8015 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8016 kvm_x86_ops->check_nested_events(vcpu, false);
8017
af585b92
GN		 8018 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8019 !vcpu->arch.apf.halted)
8020 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 8021 || kvm_apic_has_events(vcpu)
6aef266c 8022 || vcpu->arch.pv.pv_unhalted
7460fb4a 8023 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 8024 (kvm_arch_interrupt_allowed(vcpu) &&
8025 kvm_cpu_has_interrupt(vcpu));
1d737c8a 8026}
5736199a 8027
b6d33834 8028int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8029{
b6d33834 8030 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8031}
78646121
GN		 8032
8033int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8034{
8035 return kvm_x86_ops->interrupt_allowed(vcpu);
8036}
229456fc 8037
82b32774 8038unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8039{
82b32774
NA		 8040 if (is_64_bit_mode(vcpu))
8041 return kvm_rip_read(vcpu);
8042 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8043 kvm_rip_read(vcpu));
8044}
8045EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8046
82b32774
NA		 8047bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8048{
8049 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8050}
8051EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8052
94fe45da
JK		 8053unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8054{
8055 unsigned long rflags;
8056
8057 rflags = kvm_x86_ops->get_rflags(vcpu);
8058 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8059 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8060 return rflags;
8061}
8062EXPORT_SYMBOL_GPL(kvm_get_rflags);
8063
6addfc42 8064static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8065{
8066 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8067 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8068 rflags |= X86_EFLAGS_TF;
94fe45da 8069 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8070}
8071
8072void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8073{
8074 __kvm_set_rflags(vcpu, rflags);
3842d135 8075 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8076}
8077EXPORT_SYMBOL_GPL(kvm_set_rflags);
8078
56028d08
GN		 8079void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8080{
8081 int r;
8082
fb67e14f 8083 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8084 work->wakeup_all)
56028d08
GN		 8085 return;
8086
8087 r = kvm_mmu_reload(vcpu);
8088 if (unlikely(r))
8089 return;
8090
fb67e14f
XG		 8091 if (!vcpu->arch.mmu.direct_map &&
8092 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8093 return;
8094
56028d08
GN		 8095 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8096}
8097
af585b92
GN		 8098static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8099{
8100 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8101}
8102
8103static inline u32 kvm_async_pf_next_probe(u32 key)
8104{
8105 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8106}
8107
8108static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8109{
8110 u32 key = kvm_async_pf_hash_fn(gfn);
8111
8112 while (vcpu->arch.apf.gfns[key] != ~0)
8113 key = kvm_async_pf_next_probe(key);
8114
8115 vcpu->arch.apf.gfns[key] = gfn;
8116}
8117
8118static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8119{
8120 int i;
8121 u32 key = kvm_async_pf_hash_fn(gfn);
8122
8123 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8124 (vcpu->arch.apf.gfns[key] != gfn &&
8125 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8126 key = kvm_async_pf_next_probe(key);
8127
8128 return key;
8129}
8130
8131bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8132{
8133 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8134}
8135
8136static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8137{
8138 u32 i, j, k;
8139
8140 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8141 while (true) {
8142 vcpu->arch.apf.gfns[i] = ~0;
8143 do {
8144 j = kvm_async_pf_next_probe(j);
8145 if (vcpu->arch.apf.gfns[j] == ~0)
8146 return;
8147 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8148 /*
8149 * k lies cyclically in ]i,j]
8150 * | i.k.j |
8151 * |....j i.k.| or |.k..j i...|
8152 */
8153 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8154 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8155 i = j;
8156 }
8157}
8158
7c90705b
GN		 8159static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8160{
8161
8162 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8163 sizeof(val));
8164}
8165
af585b92
GN		 8166void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8167 struct kvm_async_pf *work)
8168{
6389ee94
AK		 8169 struct x86_exception fault;
8170
7c90705b 8171 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8172 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8173
8174 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8175 (vcpu->arch.apf.send_user_only &&
8176 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8177 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8178 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8179 fault.vector = PF_VECTOR;
8180 fault.error_code_valid = true;
8181 fault.error_code = 0;
8182 fault.nested_page_fault = false;
8183 fault.address = work->arch.token;
8184 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8185 }
af585b92
GN		 8186}
8187
8188void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8189 struct kvm_async_pf *work)
8190{
6389ee94
AK		 8191 struct x86_exception fault;
8192
7c90705b 8193 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8194 if (work->wakeup_all)
7c90705b
GN		 8195 work->arch.token = ~0; /* broadcast wakeup */
8196 else
8197 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8198
8199 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8200 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8201 fault.vector = PF_VECTOR;
8202 fault.error_code_valid = true;
8203 fault.error_code = 0;
8204 fault.nested_page_fault = false;
8205 fault.address = work->arch.token;
8206 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8207 }
e6d53e3b 8208 vcpu->arch.apf.halted = false;
a4fa1635 8209 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8210}
8211
8212bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8213{
8214 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8215 return true;
8216 else
8217 return !kvm_event_needs_reinjection(vcpu) &&
8218 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8219}
8220
e0f0bbc5
AW		 8221void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8222{
8223 atomic_inc(&kvm->arch.noncoherent_dma_count);
8224}
8225EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8226
8227void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8228{
8229 atomic_dec(&kvm->arch.noncoherent_dma_count);
8230}
8231EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8232
8233bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8234{
8235 return atomic_read(&kvm->arch.noncoherent_dma_count);
8236}
8237EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8238
229456fc
MT		 8239EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8240EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8241EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8242EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8243EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8244EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8245EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8246EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8247EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8248EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8249EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8250EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8251EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8252EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8253EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
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