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kvm: Add arch specific mmu notifier for page invalidation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
13a34e06 249static void drop_user_return_notifiers(void)
3548bab5 250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
ef54bcfe 411static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 417
418 return fault->nested_page_fault;
d4f8cf66
JR		 419}
420
3419ffc8
SY		 421void kvm_inject_nmi(struct kvm_vcpu *vcpu)
422{
7460fb4a
AK		 423 atomic_inc(&vcpu->arch.nmi_queued);
424 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 425}
426EXPORT_SYMBOL_GPL(kvm_inject_nmi);
427
298101da
AK		 428void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
429{
ce7ddec4 430 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 431}
432EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
433
ce7ddec4
JR		 434void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
435{
436 kvm_multiple_exception(vcpu, nr, true, error_code, true);
437}
438EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
439
0a79b009
AK		 440/*
441 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
442 * a #GP and return false.
443 */
444bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 445{
0a79b009
AK		 446 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
447 return true;
448 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
449 return false;
298101da 450}
0a79b009 451EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 452
ec92fe44
JR		 453/*
454 * This function will be used to read from the physical memory of the currently
455 * running guest. The difference to kvm_read_guest_page is that this function
456 * can read from guest physical or from the guest's guest physical memory.
457 */
458int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
459 gfn_t ngfn, void *data, int offset, int len,
460 u32 access)
461{
54987b7a 462 struct x86_exception exception;
ec92fe44
JR		 463 gfn_t real_gfn;
464 gpa_t ngpa;
465
466 ngpa = gfn_to_gpa(ngfn);
54987b7a 467 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 468 if (real_gfn == UNMAPPED_GVA)
469 return -EFAULT;
470
471 real_gfn = gpa_to_gfn(real_gfn);
472
473 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
474}
475EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
476
3d06b8bf
JR		 477int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
478 void *data, int offset, int len, u32 access)
479{
480 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
481 data, offset, len, access);
482}
483
a03490ed
CO		 484/*
485 * Load the pae pdptrs. Return true is they are all valid.
486 */
ff03a073 487int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 488{
489 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
490 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
491 int i;
492 int ret;
ff03a073 493 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 494
ff03a073
JR		 495 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
496 offset * sizeof(u64), sizeof(pdpte),
497 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 498 if (ret < 0) {
499 ret = 0;
500 goto out;
501 }
502 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 503 if (is_present_gpte(pdpte[i]) &&
20c466b5 504 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 505 ret = 0;
506 goto out;
507 }
508 }
509 ret = 1;
510
ff03a073 511 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 512 __set_bit(VCPU_EXREG_PDPTR,
513 (unsigned long *)&vcpu->arch.regs_avail);
514 __set_bit(VCPU_EXREG_PDPTR,
515 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 516out:
a03490ed
CO		 517
518 return ret;
519}
cc4b6871 520EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 521
d835dfec
AK		 522static bool pdptrs_changed(struct kvm_vcpu *vcpu)
523{
ff03a073 524 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 525 bool changed = true;
3d06b8bf
JR		 526 int offset;
527 gfn_t gfn;
d835dfec
AK		 528 int r;
529
530 if (is_long_mode(vcpu) || !is_pae(vcpu))
531 return false;
532
6de4f3ad
AK		 533 if (!test_bit(VCPU_EXREG_PDPTR,
534 (unsigned long *)&vcpu->arch.regs_avail))
535 return true;
536
9f8fe504
AK		 537 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
538 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 539 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
540 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 541 if (r < 0)
542 goto out;
ff03a073 543 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 544out:
d835dfec
AK		 545
546 return changed;
547}
548
49a9b07e 549int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 550{
aad82703
SY		 551 unsigned long old_cr0 = kvm_read_cr0(vcpu);
552 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
553 X86_CR0_CD | X86_CR0_NW;
554
f9a48e6a
AK		 555 cr0 |= X86_CR0_ET;
556
ab344828 557#ifdef CONFIG_X86_64
0f12244f
GN		 558 if (cr0 & 0xffffffff00000000UL)
559 return 1;
ab344828
GN		 560#endif
561
562 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
565 return 1;
a03490ed 566
0f12244f
GN		 567 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
568 return 1;
a03490ed
CO		 569
570 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
571#ifdef CONFIG_X86_64
f6801dff 572 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 573 int cs_db, cs_l;
574
0f12244f
GN		 575 if (!is_pae(vcpu))
576 return 1;
a03490ed 577 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 578 if (cs_l)
579 return 1;
a03490ed
CO		 580 } else
581#endif
ff03a073 582 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 583 kvm_read_cr3(vcpu)))
0f12244f 584 return 1;
a03490ed
CO		 585 }
586
ad756a16
MJ		 587 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
588 return 1;
589
a03490ed 590 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 591
d170c419 592 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 593 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 594 kvm_async_pf_hash_reset(vcpu);
595 }
e5f3f027 596
aad82703
SY		 597 if ((cr0 ^ old_cr0) & update_bits)
598 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 599 return 0;
600}
2d3ad1f4 601EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 602
2d3ad1f4 603void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 604{
49a9b07e 605 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 608
42bdf991
MT		 609static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
610{
611 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
612 !vcpu->guest_xcr0_loaded) {
613 /* kvm_set_xcr() also depends on this */
614 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
615 vcpu->guest_xcr0_loaded = 1;
616 }
617}
618
619static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
620{
621 if (vcpu->guest_xcr0_loaded) {
622 if (vcpu->arch.xcr0 != host_xcr0)
623 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
624 vcpu->guest_xcr0_loaded = 0;
625 }
626}
627
2acf923e
DC		 628int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
629{
56c103ec
LJ		 630 u64 xcr0 = xcr;
631 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 632 u64 valid_bits;
2acf923e
DC		 633
634 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
635 if (index != XCR_XFEATURE_ENABLED_MASK)
636 return 1;
2acf923e
DC		 637 if (!(xcr0 & XSTATE_FP))
638 return 1;
639 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
640 return 1;
46c34cb0
PB		 641
642 /*
643 * Do not allow the guest to set bits that we do not support
644 * saving. However, xcr0 bit 0 is always set, even if the
645 * emulated CPU does not support XSAVE (see fx_init).
646 */
647 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
648 if (xcr0 & ~valid_bits)
2acf923e 649 return 1;
46c34cb0 650
390bd528
LJ		 651 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
652 return 1;
653
42bdf991 654 kvm_put_guest_xcr0(vcpu);
2acf923e 655 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 656
657 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
658 kvm_update_cpuid(vcpu);
2acf923e
DC		 659 return 0;
660}
661
662int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
663{
764bcbc5
Z		 664 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
665 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 666 kvm_inject_gp(vcpu, 0);
667 return 1;
668 }
669 return 0;
670}
671EXPORT_SYMBOL_GPL(kvm_set_xcr);
672
a83b29c6 673int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 674{
fc78f519 675 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 676 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
677 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 678 if (cr4 & CR4_RESERVED_BITS)
679 return 1;
a03490ed 680
2acf923e
DC		 681 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
682 return 1;
683
c68b734f
YW		 684 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
685 return 1;
686
97ec8c06
FW		 687 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
688 return 1;
689
afcbf13f 690 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 691 return 1;
692
a03490ed 693 if (is_long_mode(vcpu)) {
0f12244f
GN		 694 if (!(cr4 & X86_CR4_PAE))
695 return 1;
a2edf57f
AK		 696 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
697 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 698 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
699 kvm_read_cr3(vcpu)))
0f12244f
GN		 700 return 1;
701
ad756a16
MJ		 702 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
703 if (!guest_cpuid_has_pcid(vcpu))
704 return 1;
705
706 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
707 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
708 return 1;
709 }
710
5e1746d6 711 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 712 return 1;
a03490ed 713
ad756a16
MJ		 714 if (((cr4 ^ old_cr4) & pdptr_bits) ||
715 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 716 kvm_mmu_reset_context(vcpu);
0f12244f 717
97ec8c06
FW		 718 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
719 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
720
2acf923e 721 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 722 kvm_update_cpuid(vcpu);
2acf923e 723
0f12244f
GN		 724 return 0;
725}
2d3ad1f4 726EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 727
2390218b 728int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 729{
9f8fe504 730 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 731 kvm_mmu_sync_roots(vcpu);
77c3913b 732 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 733 return 0;
d835dfec
AK		 734 }
735
a03490ed 736 if (is_long_mode(vcpu)) {
d9f89b88
JK		 737 if (cr3 & CR3_L_MODE_RESERVED_BITS)
738 return 1;
739 } else if (is_pae(vcpu) && is_paging(vcpu) &&
740 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 741 return 1;
a03490ed 742
0f12244f 743 vcpu->arch.cr3 = cr3;
aff48baa 744 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 745 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 746 return 0;
747}
2d3ad1f4 748EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 749
eea1cff9 750int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 751{
0f12244f
GN		 752 if (cr8 & CR8_RESERVED_BITS)
753 return 1;
a03490ed
CO		 754 if (irqchip_in_kernel(vcpu->kvm))
755 kvm_lapic_set_tpr(vcpu, cr8);
756 else
ad312c7c 757 vcpu->arch.cr8 = cr8;
0f12244f
GN		 758 return 0;
759}
2d3ad1f4 760EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 761
2d3ad1f4 762unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 763{
764 if (irqchip_in_kernel(vcpu->kvm))
765 return kvm_lapic_get_cr8(vcpu);
766 else
ad312c7c 767 return vcpu->arch.cr8;
a03490ed 768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 770
73aaf249
JK		 771static void kvm_update_dr6(struct kvm_vcpu *vcpu)
772{
773 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
774 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
775}
776
c8639010
JK		 777static void kvm_update_dr7(struct kvm_vcpu *vcpu)
778{
779 unsigned long dr7;
780
781 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
782 dr7 = vcpu->arch.guest_debug_dr7;
783 else
784 dr7 = vcpu->arch.dr7;
785 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 786 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
787 if (dr7 & DR7_BP_EN_MASK)
788 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 789}
790
6f43ed01
NA		 791static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
792{
793 u64 fixed = DR6_FIXED_1;
794
795 if (!guest_cpuid_has_rtm(vcpu))
796 fixed |= DR6_RTM;
797 return fixed;
798}
799
338dbc97 800static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 801{
802 switch (dr) {
803 case 0 ... 3:
804 vcpu->arch.db[dr] = val;
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 vcpu->arch.eff_db[dr] = val;
807 break;
808 case 4:
338dbc97
GN		 809 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
810 return 1; /* #UD */
020df079
GN		 811 /* fall through */
812 case 6:
338dbc97
GN		 813 if (val & 0xffffffff00000000ULL)
814 return -1; /* #GP */
6f43ed01 815 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 816 kvm_update_dr6(vcpu);
020df079
GN		 817 break;
818 case 5:
338dbc97
GN		 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
820 return 1; /* #UD */
020df079
GN		 821 /* fall through */
822 default: /* 7 */
338dbc97
GN		 823 if (val & 0xffffffff00000000ULL)
824 return -1; /* #GP */
020df079 825 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 826 kvm_update_dr7(vcpu);
020df079
GN		 827 break;
828 }
829
830 return 0;
831}
338dbc97
GN		 832
833int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
834{
835 int res;
836
837 res = __kvm_set_dr(vcpu, dr, val);
838 if (res > 0)
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 else if (res < 0)
841 kvm_inject_gp(vcpu, 0);
842
843 return res;
844}
020df079
GN		 845EXPORT_SYMBOL_GPL(kvm_set_dr);
846
338dbc97 847static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 *val = vcpu->arch.db[dr];
852 break;
853 case 4:
338dbc97 854 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 855 return 1;
020df079
GN		 856 /* fall through */
857 case 6:
73aaf249
JK		 858 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
859 *val = vcpu->arch.dr6;
860 else
861 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
338dbc97 864 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 865 return 1;
020df079
GN		 866 /* fall through */
867 default: /* 7 */
868 *val = vcpu->arch.dr7;
869 break;
870 }
871
872 return 0;
873}
338dbc97
GN		 874
875int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
876{
877 if (_kvm_get_dr(vcpu, dr, val)) {
878 kvm_queue_exception(vcpu, UD_VECTOR);
879 return 1;
880 }
881 return 0;
882}
020df079
GN		 883EXPORT_SYMBOL_GPL(kvm_get_dr);
884
022cd0e8
AK		 885bool kvm_rdpmc(struct kvm_vcpu *vcpu)
886{
887 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
888 u64 data;
889 int err;
890
891 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
892 if (err)
893 return err;
894 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
895 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
896 return err;
897}
898EXPORT_SYMBOL_GPL(kvm_rdpmc);
899
043405e1
CO		 900/*
901 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
902 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
903 *
904 * This list is modified at module load time to reflect the
e3267cbb
GC		 905 * capabilities of the host cpu. This capabilities test skips MSRs that are
906 * kvm-specific. Those are put in the beginning of the list.
043405e1 907 */
e3267cbb 908
e984097b 909#define KVM_SAVE_MSRS_BEGIN 12
043405e1 910static u32 msrs_to_save[] = {
e3267cbb 911 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 912 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 913 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 914 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 915 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 916 MSR_KVM_PV_EOI_EN,
043405e1 917 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 918 MSR_STAR,
043405e1
CO		 919#ifdef CONFIG_X86_64
920 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
921#endif
b3897a49 922 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 923 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 924};
925
926static unsigned num_msrs_to_save;
927
f1d24831 928static const u32 emulated_msrs[] = {
ba904635 929 MSR_IA32_TSC_ADJUST,
a3e06bbe 930 MSR_IA32_TSCDEADLINE,
043405e1 931 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 932 MSR_IA32_MCG_STATUS,
933 MSR_IA32_MCG_CTL,
043405e1
CO		 934};
935
384bb783 936bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 937{
b69e8cae 938 if (efer & efer_reserved_bits)
384bb783 939 return false;
15c4a640 940
1b2fd70c
AG		 941 if (efer & EFER_FFXSR) {
942 struct kvm_cpuid_entry2 *feat;
943
944 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 945 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 946 return false;
1b2fd70c
AG		 947 }
948
d8017474
AG		 949 if (efer & EFER_SVME) {
950 struct kvm_cpuid_entry2 *feat;
951
952 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 953 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 954 return false;
d8017474
AG		 955 }
956
384bb783
JK		 957 return true;
958}
959EXPORT_SYMBOL_GPL(kvm_valid_efer);
960
961static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
962{
963 u64 old_efer = vcpu->arch.efer;
964
965 if (!kvm_valid_efer(vcpu, efer))
966 return 1;
967
968 if (is_paging(vcpu)
969 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
970 return 1;
971
15c4a640 972 efer &= ~EFER_LMA;
f6801dff 973 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 974
a3d204e2
SY		 975 kvm_x86_ops->set_efer(vcpu, efer);
976
aad82703
SY		 977 /* Update reserved bits */
978 if ((efer ^ old_efer) & EFER_NX)
979 kvm_mmu_reset_context(vcpu);
980
b69e8cae 981 return 0;
15c4a640
CO		 982}
983
f2b4b7dd
JR		 984void kvm_enable_efer_bits(u64 mask)
985{
986 efer_reserved_bits &= ~mask;
987}
988EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
989
990
15c4a640
CO		 991/*
992 * Writes msr value into into the appropriate "register".
993 * Returns 0 on success, non-0 otherwise.
994 * Assumes vcpu_load() was already called.
995 */
8fe8ab46 996int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 997{
8fe8ab46 998 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 999}
1000
313a3dc7
CO		 1001/*
1002 * Adapt set_msr() to msr_io()'s calling convention
1003 */
1004static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1005{
8fe8ab46
WA		 1006 struct msr_data msr;
1007
1008 msr.data = *data;
1009 msr.index = index;
1010 msr.host_initiated = true;
1011 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1012}
1013
16e8d74d
MT		 1014#ifdef CONFIG_X86_64
1015struct pvclock_gtod_data {
1016 seqcount_t seq;
1017
1018 struct { /* extract of a clocksource struct */
1019 int vclock_mode;
1020 cycle_t cycle_last;
1021 cycle_t mask;
1022 u32 mult;
1023 u32 shift;
1024 } clock;
1025
cbcf2dd3
TG		 1026 u64 boot_ns;
1027 u64 nsec_base;
16e8d74d
MT		 1028};
1029
1030static struct pvclock_gtod_data pvclock_gtod_data;
1031
1032static void update_pvclock_gtod(struct timekeeper *tk)
1033{
1034 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1035 u64 boot_ns;
1036
d28ede83 1037 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1038
1039 write_seqcount_begin(&vdata->seq);
1040
1041 /* copy pvclock gtod data */
d28ede83
TG		 1042 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1043 vdata->clock.cycle_last = tk->tkr.cycle_last;
1044 vdata->clock.mask = tk->tkr.mask;
1045 vdata->clock.mult = tk->tkr.mult;
1046 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1047
cbcf2dd3 1048 vdata->boot_ns = boot_ns;
d28ede83 1049 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1050
1051 write_seqcount_end(&vdata->seq);
1052}
1053#endif
1054
1055
18068523
GOC		 1056static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1057{
9ed3c444
AK		 1058 int version;
1059 int r;
50d0a0f9 1060 struct pvclock_wall_clock wc;
923de3cf 1061 struct timespec boot;
18068523
GOC		 1062
1063 if (!wall_clock)
1064 return;
1065
9ed3c444
AK		 1066 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1067 if (r)
1068 return;
1069
1070 if (version & 1)
1071 ++version; /* first time write, random junk */
1072
1073 ++version;
18068523 1074
18068523
GOC		 1075 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1076
50d0a0f9
GH		 1077 /*
1078 * The guest calculates current wall clock time by adding
34c238a1 1079 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1080 * wall clock specified here. guest system time equals host
1081 * system time for us, thus we must fill in host boot time here.
1082 */
923de3cf 1083 getboottime(&boot);
50d0a0f9 1084
4b648665
BR		 1085 if (kvm->arch.kvmclock_offset) {
1086 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1087 boot = timespec_sub(boot, ts);
1088 }
50d0a0f9
GH		 1089 wc.sec = boot.tv_sec;
1090 wc.nsec = boot.tv_nsec;
1091 wc.version = version;
18068523
GOC		 1092
1093 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1094
1095 version++;
1096 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1097}
1098
50d0a0f9
GH		 1099static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1100{
1101 uint32_t quotient, remainder;
1102
1103 /* Don't try to replace with do_div(), this one calculates
1104 * "(dividend << 32) / divisor" */
1105 __asm__ ( "divl %4"
1106 : "=a" (quotient), "=d" (remainder)
1107 : "0" (0), "1" (dividend), "r" (divisor) );
1108 return quotient;
1109}
1110
5f4e3f88
ZA		 1111static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1112 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1113{
5f4e3f88 1114 uint64_t scaled64;
50d0a0f9
GH		 1115 int32_t shift = 0;
1116 uint64_t tps64;
1117 uint32_t tps32;
1118
5f4e3f88
ZA		 1119 tps64 = base_khz * 1000LL;
1120 scaled64 = scaled_khz * 1000LL;
50933623 1121 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1122 tps64 >>= 1;
1123 shift--;
1124 }
1125
1126 tps32 = (uint32_t)tps64;
50933623
JK		 1127 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1128 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1129 scaled64 >>= 1;
1130 else
1131 tps32 <<= 1;
50d0a0f9
GH		 1132 shift++;
1133 }
1134
5f4e3f88
ZA		 1135 *pshift = shift;
1136 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1137
5f4e3f88
ZA		 1138 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1139 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1140}
1141
759379dd
ZA		 1142static inline u64 get_kernel_ns(void)
1143{
bb0b5812 1144 return ktime_get_boot_ns();
50d0a0f9
GH		 1145}
1146
d828199e 1147#ifdef CONFIG_X86_64
16e8d74d 1148static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1149#endif
16e8d74d 1150
c8076604 1151static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1152unsigned long max_tsc_khz;
c8076604 1153
cc578287 1154static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1155{
cc578287
ZA		 1156 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1158}
1159
cc578287 1160static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1161{
cc578287
ZA		 1162 u64 v = (u64)khz * (1000000 + ppm);
1163 do_div(v, 1000000);
1164 return v;
1e993611
JR		 1165}
1166
cc578287 1167static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1168{
cc578287
ZA		 1169 u32 thresh_lo, thresh_hi;
1170 int use_scaling = 0;
217fc9cf 1171
03ba32ca
MT		 1172 /* tsc_khz can be zero if TSC calibration fails */
1173 if (this_tsc_khz == 0)
1174 return;
1175
c285545f
ZA		 1176 /* Compute a scale to convert nanoseconds in TSC cycles */
1177 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1178 &vcpu->arch.virtual_tsc_shift,
1179 &vcpu->arch.virtual_tsc_mult);
1180 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1181
1182 /*
1183 * Compute the variation in TSC rate which is acceptable
1184 * within the range of tolerance and decide if the
1185 * rate being applied is within that bounds of the hardware
1186 * rate. If so, no scaling or compensation need be done.
1187 */
1188 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1192 use_scaling = 1;
1193 }
1194 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1195}
1196
1197static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1198{
e26101b1 1199 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1200 vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
e26101b1 1202 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1203 return tsc;
1204}
1205
b48aa97e
MT		 1206void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1207{
1208#ifdef CONFIG_X86_64
1209 bool vcpus_matched;
1210 bool do_request = false;
1211 struct kvm_arch *ka = &vcpu->kvm->arch;
1212 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1213
1214 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215 atomic_read(&vcpu->kvm->online_vcpus));
1216
1217 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218 if (!ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (!vcpus_matched && ka->use_master_clock)
1222 do_request = 1;
1223
1224 if (do_request)
1225 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1226
1227 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228 atomic_read(&vcpu->kvm->online_vcpus),
1229 ka->use_master_clock, gtod->clock.vclock_mode);
1230#endif
1231}
1232
ba904635
WA		 1233static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1234{
1235 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1237}
1238
8fe8ab46 1239void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1240{
1241 struct kvm *kvm = vcpu->kvm;
f38e098f 1242 u64 offset, ns, elapsed;
99e3e30a 1243 unsigned long flags;
02626b6a 1244 s64 usdiff;
b48aa97e 1245 bool matched;
0d3da0d2 1246 bool already_matched;
8fe8ab46 1247 u64 data = msr->data;
99e3e30a 1248
038f8c11 1249 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1250 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1251 ns = get_kernel_ns();
f38e098f 1252 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1253
03ba32ca 1254 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1255 int faulted = 0;
1256
03ba32ca
MT		 1257 /* n.b - signed multiplication and division required */
1258 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1259#ifdef CONFIG_X86_64
03ba32ca 1260 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1261#else
03ba32ca 1262 /* do_div() only does unsigned */
8915aa27
MT		 1263 asm("1: idivl %[divisor]\n"
1264 "2: xor %%edx, %%edx\n"
1265 " movl $0, %[faulted]\n"
1266 "3:\n"
1267 ".section .fixup,\"ax\"\n"
1268 "4: movl $1, %[faulted]\n"
1269 " jmp 3b\n"
1270 ".previous\n"
1271
1272 _ASM_EXTABLE(1b, 4b)
1273
1274 : "=A"(usdiff), [faulted] "=r" (faulted)
1275 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1276
5d3cb0f6 1277#endif
03ba32ca
MT		 1278 do_div(elapsed, 1000);
1279 usdiff -= elapsed;
1280 if (usdiff < 0)
1281 usdiff = -usdiff;
8915aa27
MT		 1282
1283 /* idivl overflow => difference is larger than USEC_PER_SEC */
1284 if (faulted)
1285 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1286 } else
1287 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1288
1289 /*
5d3cb0f6
ZA		 1290 * Special case: TSC write with a small delta (1 second) of virtual
1291 * cycle time against real time is interpreted as an attempt to
1292 * synchronize the CPU.
1293 *
1294 * For a reliable TSC, we can match TSC offsets, and for an unstable
1295 * TSC, we add elapsed time in this computation. We could let the
1296 * compensation code attempt to catch up if we fall behind, but
1297 * it's better to try to match offsets from the beginning.
1298 */
02626b6a 1299 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1300 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1301 if (!check_tsc_unstable()) {
e26101b1 1302 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1303 pr_debug("kvm: matched tsc offset for %llu\n", data);
1304 } else {
857e4099 1305 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1306 data += delta;
1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1309 }
b48aa97e 1310 matched = true;
0d3da0d2 1311 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1312 } else {
1313 /*
1314 * We split periods of matched TSC writes into generations.
1315 * For each generation, we track the original measured
1316 * nanosecond time, offset, and write, so if TSCs are in
1317 * sync, we can match exact offset, and if not, we can match
4a969980 1318 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1319 *
1320 * These values are tracked in kvm->arch.cur_xxx variables.
1321 */
1322 kvm->arch.cur_tsc_generation++;
1323 kvm->arch.cur_tsc_nsec = ns;
1324 kvm->arch.cur_tsc_write = data;
1325 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1326 matched = false;
0d3da0d2 1327 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1328 kvm->arch.cur_tsc_generation, data);
f38e098f 1329 }
e26101b1
ZA		 1330
1331 /*
1332 * We also track th most recent recorded KHZ, write and time to
1333 * allow the matching interval to be extended at each write.
1334 */
f38e098f
ZA		 1335 kvm->arch.last_tsc_nsec = ns;
1336 kvm->arch.last_tsc_write = data;
5d3cb0f6 1337 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1338
b183aa58 1339 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1340
1341 /* Keep track of which generation this VCPU has synchronized to */
1342 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1343 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1344 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1345
ba904635
WA		 1346 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1347 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1348 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1349 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1350
1351 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1352 if (!matched) {
b48aa97e 1353 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1354 } else if (!already_matched) {
1355 kvm->arch.nr_vcpus_matched_tsc++;
1356 }
b48aa97e
MT		 1357
1358 kvm_track_tsc_matching(vcpu);
1359 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1360}
e26101b1 1361
99e3e30a
ZA		 1362EXPORT_SYMBOL_GPL(kvm_write_tsc);
1363
d828199e
MT		 1364#ifdef CONFIG_X86_64
1365
1366static cycle_t read_tsc(void)
1367{
1368 cycle_t ret;
1369 u64 last;
1370
1371 /*
1372 * Empirically, a fence (of type that depends on the CPU)
1373 * before rdtsc is enough to ensure that rdtsc is ordered
1374 * with respect to loads. The various CPU manuals are unclear
1375 * as to whether rdtsc can be reordered with later loads,
1376 * but no one has ever seen it happen.
1377 */
1378 rdtsc_barrier();
1379 ret = (cycle_t)vget_cycles();
1380
1381 last = pvclock_gtod_data.clock.cycle_last;
1382
1383 if (likely(ret >= last))
1384 return ret;
1385
1386 /*
1387 * GCC likes to generate cmov here, but this branch is extremely
1388 * predictable (it's just a funciton of time and the likely is
1389 * very likely) and there's a data dependence, so force GCC
1390 * to generate a branch instead. I don't barrier() because
1391 * we don't actually need a barrier, and if this function
1392 * ever gets inlined it will generate worse code.
1393 */
1394 asm volatile ("");
1395 return last;
1396}
1397
1398static inline u64 vgettsc(cycle_t *cycle_now)
1399{
1400 long v;
1401 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1402
1403 *cycle_now = read_tsc();
1404
1405 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1406 return v * gtod->clock.mult;
1407}
1408
cbcf2dd3 1409static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1410{
cbcf2dd3 1411 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1412 unsigned long seq;
d828199e 1413 int mode;
cbcf2dd3 1414 u64 ns;
d828199e 1415
d828199e
MT		 1416 do {
1417 seq = read_seqcount_begin(&gtod->seq);
1418 mode = gtod->clock.vclock_mode;
cbcf2dd3 1419 ns = gtod->nsec_base;
d828199e
MT		 1420 ns += vgettsc(cycle_now);
1421 ns >>= gtod->clock.shift;
cbcf2dd3 1422 ns += gtod->boot_ns;
d828199e 1423 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1424 *t = ns;
d828199e
MT		 1425
1426 return mode;
1427}
1428
1429/* returns true if host is using tsc clocksource */
1430static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1431{
d828199e
MT		 1432 /* checked again under seqlock below */
1433 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1434 return false;
1435
cbcf2dd3 1436 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1437}
1438#endif
1439
1440/*
1441 *
b48aa97e
MT		 1442 * Assuming a stable TSC across physical CPUS, and a stable TSC
1443 * across virtual CPUs, the following condition is possible.
1444 * Each numbered line represents an event visible to both
d828199e
MT		 1445 * CPUs at the next numbered event.
1446 *
1447 * "timespecX" represents host monotonic time. "tscX" represents
1448 * RDTSC value.
1449 *
1450 * VCPU0 on CPU0 | VCPU1 on CPU1
1451 *
1452 * 1. read timespec0,tsc0
1453 * 2. | timespec1 = timespec0 + N
1454 * | tsc1 = tsc0 + M
1455 * 3. transition to guest | transition to guest
1456 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1457 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1458 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1459 *
1460 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1461 *
1462 * - ret0 < ret1
1463 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1464 * ...
1465 * - 0 < N - M => M < N
1466 *
1467 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1468 * always the case (the difference between two distinct xtime instances
1469 * might be smaller then the difference between corresponding TSC reads,
1470 * when updating guest vcpus pvclock areas).
1471 *
1472 * To avoid that problem, do not allow visibility of distinct
1473 * system_timestamp/tsc_timestamp values simultaneously: use a master
1474 * copy of host monotonic time values. Update that master copy
1475 * in lockstep.
1476 *
b48aa97e 1477 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1478 *
1479 */
1480
1481static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1482{
1483#ifdef CONFIG_X86_64
1484 struct kvm_arch *ka = &kvm->arch;
1485 int vclock_mode;
b48aa97e
MT		 1486 bool host_tsc_clocksource, vcpus_matched;
1487
1488 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1489 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1490
1491 /*
1492 * If the host uses TSC clock, then passthrough TSC as stable
1493 * to the guest.
1494 */
b48aa97e 1495 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1496 &ka->master_kernel_ns,
1497 &ka->master_cycle_now);
1498
16a96021
MT		 1499 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1500 && !backwards_tsc_observed;
b48aa97e 1501
d828199e
MT		 1502 if (ka->use_master_clock)
1503 atomic_set(&kvm_guest_has_master_clock, 1);
1504
1505 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1506 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1507 vcpus_matched);
d828199e
MT		 1508#endif
1509}
1510
2e762ff7
MT		 1511static void kvm_gen_update_masterclock(struct kvm *kvm)
1512{
1513#ifdef CONFIG_X86_64
1514 int i;
1515 struct kvm_vcpu *vcpu;
1516 struct kvm_arch *ka = &kvm->arch;
1517
1518 spin_lock(&ka->pvclock_gtod_sync_lock);
1519 kvm_make_mclock_inprogress_request(kvm);
1520 /* no guest entries from this point */
1521 pvclock_update_vm_gtod_copy(kvm);
1522
1523 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1524 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1525
1526 /* guest entries allowed */
1527 kvm_for_each_vcpu(i, vcpu, kvm)
1528 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1529
1530 spin_unlock(&ka->pvclock_gtod_sync_lock);
1531#endif
1532}
1533
34c238a1 1534static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1535{
d828199e 1536 unsigned long flags, this_tsc_khz;
18068523 1537 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1538 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1539 s64 kernel_ns;
d828199e 1540 u64 tsc_timestamp, host_tsc;
0b79459b 1541 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1542 u8 pvclock_flags;
d828199e
MT		 1543 bool use_master_clock;
1544
1545 kernel_ns = 0;
1546 host_tsc = 0;
18068523 1547
d828199e
MT		 1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
1552 spin_lock(&ka->pvclock_gtod_sync_lock);
1553 use_master_clock = ka->use_master_clock;
1554 if (use_master_clock) {
1555 host_tsc = ka->master_cycle_now;
1556 kernel_ns = ka->master_kernel_ns;
1557 }
1558 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1559
1560 /* Keep irq disabled to prevent changes to the clock */
1561 local_irq_save(flags);
1562 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1563 if (unlikely(this_tsc_khz == 0)) {
1564 local_irq_restore(flags);
1565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1566 return 1;
1567 }
d828199e
MT		 1568 if (!use_master_clock) {
1569 host_tsc = native_read_tsc();
1570 kernel_ns = get_kernel_ns();
1571 }
1572
1573 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1574
c285545f
ZA		 1575 /*
1576 * We may have to catch up the TSC to match elapsed wall clock
1577 * time for two reasons, even if kvmclock is used.
1578 * 1) CPU could have been running below the maximum TSC rate
1579 * 2) Broken TSC compensation resets the base at each VCPU
1580 * entry to avoid unknown leaps of TSC even when running
1581 * again on the same CPU. This may cause apparent elapsed
1582 * time to disappear, and the guest to stand still or run
1583 * very slowly.
1584 */
1585 if (vcpu->tsc_catchup) {
1586 u64 tsc = compute_guest_tsc(v, kernel_ns);
1587 if (tsc > tsc_timestamp) {
f1e2b260 1588 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1589 tsc_timestamp = tsc;
1590 }
50d0a0f9
GH		 1591 }
1592
18068523
GOC		 1593 local_irq_restore(flags);
1594
0b79459b 1595 if (!vcpu->pv_time_enabled)
c285545f 1596 return 0;
18068523 1597
e48672fa 1598 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1599 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600 &vcpu->hv_clock.tsc_shift,
1601 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1602 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1603 }
1604
1605 /* With all the info we got, fill in the values */
1d5f066e 1606 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1607 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1608 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1609
18068523
GOC		 1610 /*
1611 * The interface expects us to write an even number signaling that the
1612 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1613 * state, we just increase by 2 at the end.
18068523 1614 */
50d0a0f9 1615 vcpu->hv_clock.version += 2;
18068523 1616
0b79459b
AH		 1617 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618 &guest_hv_clock, sizeof(guest_hv_clock))))
1619 return 0;
78c0337a
MT		 1620
1621 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1622 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1623
1624 if (vcpu->pvclock_set_guest_stopped_request) {
1625 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626 vcpu->pvclock_set_guest_stopped_request = false;
1627 }
1628
d828199e
MT		 1629 /* If the host uses TSC clocksource, then it is stable */
1630 if (use_master_clock)
1631 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632
78c0337a
MT		 1633 vcpu->hv_clock.flags = pvclock_flags;
1634
0b79459b
AH		 1635 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636 &vcpu->hv_clock,
1637 sizeof(vcpu->hv_clock));
8cfdc000 1638 return 0;
c8076604
GH		 1639}
1640
0061d53d
MT		 1641/*
1642 * kvmclock updates which are isolated to a given vcpu, such as
1643 * vcpu->cpu migration, should not allow system_timestamp from
1644 * the rest of the vcpus to remain static. Otherwise ntp frequency
1645 * correction applies to one vcpu's system_timestamp but not
1646 * the others.
1647 *
1648 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1649 * We need to rate-limit these requests though, as they can
1650 * considerably slow guests that have a large number of vcpus.
1651 * The time for a remote vcpu to update its kvmclock is bound
1652 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1653 */
1654
7e44e449
AJ		 1655#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1656
1657static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1658{
1659 int i;
7e44e449
AJ		 1660 struct delayed_work *dwork = to_delayed_work(work);
1661 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1662 kvmclock_update_work);
1663 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1664 struct kvm_vcpu *vcpu;
1665
1666 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1667 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1668 kvm_vcpu_kick(vcpu);
1669 }
1670}
1671
7e44e449
AJ		 1672static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1673{
1674 struct kvm *kvm = v->kvm;
1675
105b21bb 1676 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1677 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1678 KVMCLOCK_UPDATE_DELAY);
1679}
1680
332967a3
AJ		 1681#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1682
1683static void kvmclock_sync_fn(struct work_struct *work)
1684{
1685 struct delayed_work *dwork = to_delayed_work(work);
1686 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687 kvmclock_sync_work);
1688 struct kvm *kvm = container_of(ka, struct kvm, arch);
1689
1690 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1691 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1692 KVMCLOCK_SYNC_PERIOD);
1693}
1694
9ba075a6
AK		 1695static bool msr_mtrr_valid(unsigned msr)
1696{
1697 switch (msr) {
1698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1699 case MSR_MTRRfix64K_00000:
1700 case MSR_MTRRfix16K_80000:
1701 case MSR_MTRRfix16K_A0000:
1702 case MSR_MTRRfix4K_C0000:
1703 case MSR_MTRRfix4K_C8000:
1704 case MSR_MTRRfix4K_D0000:
1705 case MSR_MTRRfix4K_D8000:
1706 case MSR_MTRRfix4K_E0000:
1707 case MSR_MTRRfix4K_E8000:
1708 case MSR_MTRRfix4K_F0000:
1709 case MSR_MTRRfix4K_F8000:
1710 case MSR_MTRRdefType:
1711 case MSR_IA32_CR_PAT:
1712 return true;
1713 case 0x2f8:
1714 return true;
1715 }
1716 return false;
1717}
1718
d6289b93
MT		 1719static bool valid_pat_type(unsigned t)
1720{
1721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1722}
1723
1724static bool valid_mtrr_type(unsigned t)
1725{
1726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1727}
1728
4566654b 1729bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1730{
1731 int i;
fd275235 1732 u64 mask;
d6289b93
MT		 1733
1734 if (!msr_mtrr_valid(msr))
1735 return false;
1736
1737 if (msr == MSR_IA32_CR_PAT) {
1738 for (i = 0; i < 8; i++)
1739 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1740 return false;
1741 return true;
1742 } else if (msr == MSR_MTRRdefType) {
1743 if (data & ~0xcff)
1744 return false;
1745 return valid_mtrr_type(data & 0xff);
1746 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1747 for (i = 0; i < 8 ; i++)
1748 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1749 return false;
1750 return true;
1751 }
1752
1753 /* variable MTRRs */
adfb5d27
WL		 1754 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1755
fd275235 1756 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1757 if ((msr & 1) == 0) {
adfb5d27 1758 /* MTRR base */
d7a2a246
WL		 1759 if (!valid_mtrr_type(data & 0xff))
1760 return false;
1761 mask |= 0xf00;
1762 } else
1763 /* MTRR mask */
1764 mask |= 0x7ff;
1765 if (data & mask) {
1766 kvm_inject_gp(vcpu, 0);
1767 return false;
1768 }
1769
adfb5d27 1770 return true;
d6289b93 1771}
4566654b 1772EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1773
9ba075a6
AK		 1774static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1775{
0bed3b56
SY		 1776 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1777
4566654b 1778 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1779 return 1;
1780
0bed3b56
SY		 1781 if (msr == MSR_MTRRdefType) {
1782 vcpu->arch.mtrr_state.def_type = data;
1783 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1784 } else if (msr == MSR_MTRRfix64K_00000)
1785 p[0] = data;
1786 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1787 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1788 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1789 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1790 else if (msr == MSR_IA32_CR_PAT)
1791 vcpu->arch.pat = data;
1792 else { /* Variable MTRRs */
1793 int idx, is_mtrr_mask;
1794 u64 *pt;
1795
1796 idx = (msr - 0x200) / 2;
1797 is_mtrr_mask = msr - 0x200 - 2 * idx;
1798 if (!is_mtrr_mask)
1799 pt =
1800 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1801 else
1802 pt =
1803 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1804 *pt = data;
1805 }
1806
1807 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1808 return 0;
1809}
15c4a640 1810
890ca9ae 1811static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1812{
890ca9ae
HY		 1813 u64 mcg_cap = vcpu->arch.mcg_cap;
1814 unsigned bank_num = mcg_cap & 0xff;
1815
15c4a640 1816 switch (msr) {
15c4a640 1817 case MSR_IA32_MCG_STATUS:
890ca9ae 1818 vcpu->arch.mcg_status = data;
15c4a640 1819 break;
c7ac679c 1820 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1821 if (!(mcg_cap & MCG_CTL_P))
1822 return 1;
1823 if (data != 0 && data != ~(u64)0)
1824 return -1;
1825 vcpu->arch.mcg_ctl = data;
1826 break;
1827 default:
1828 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1829 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1830 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1831 /* only 0 or all 1s can be written to IA32_MCi_CTL
1832 * some Linux kernels though clear bit 10 in bank 4 to
1833 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1834 * this to avoid an uncatched #GP in the guest
1835 */
890ca9ae 1836 if ((offset & 0x3) == 0 &&
114be429 1837 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1838 return -1;
1839 vcpu->arch.mce_banks[offset] = data;
1840 break;
1841 }
1842 return 1;
1843 }
1844 return 0;
1845}
1846
ffde22ac
ES		 1847static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1848{
1849 struct kvm *kvm = vcpu->kvm;
1850 int lm = is_long_mode(vcpu);
1851 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1852 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1853 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1854 : kvm->arch.xen_hvm_config.blob_size_32;
1855 u32 page_num = data & ~PAGE_MASK;
1856 u64 page_addr = data & PAGE_MASK;
1857 u8 *page;
1858 int r;
1859
1860 r = -E2BIG;
1861 if (page_num >= blob_size)
1862 goto out;
1863 r = -ENOMEM;
ff5c2c03
SL		 1864 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1865 if (IS_ERR(page)) {
1866 r = PTR_ERR(page);
ffde22ac 1867 goto out;
ff5c2c03 1868 }
ffde22ac
ES		 1869 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1870 goto out_free;
1871 r = 0;
1872out_free:
1873 kfree(page);
1874out:
1875 return r;
1876}
1877
55cd8e5a
GN		 1878static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1879{
1880 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1881}
1882
1883static bool kvm_hv_msr_partition_wide(u32 msr)
1884{
1885 bool r = false;
1886 switch (msr) {
1887 case HV_X64_MSR_GUEST_OS_ID:
1888 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1889 case HV_X64_MSR_REFERENCE_TSC:
1890 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1891 r = true;
1892 break;
1893 }
1894
1895 return r;
1896}
1897
1898static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1899{
1900 struct kvm *kvm = vcpu->kvm;
1901
1902 switch (msr) {
1903 case HV_X64_MSR_GUEST_OS_ID:
1904 kvm->arch.hv_guest_os_id = data;
1905 /* setting guest os id to zero disables hypercall page */
1906 if (!kvm->arch.hv_guest_os_id)
1907 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1908 break;
1909 case HV_X64_MSR_HYPERCALL: {
1910 u64 gfn;
1911 unsigned long addr;
1912 u8 instructions[4];
1913
1914 /* if guest os id is not set hypercall should remain disabled */
1915 if (!kvm->arch.hv_guest_os_id)
1916 break;
1917 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1918 kvm->arch.hv_hypercall = data;
1919 break;
1920 }
1921 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1922 addr = gfn_to_hva(kvm, gfn);
1923 if (kvm_is_error_hva(addr))
1924 return 1;
1925 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1926 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1927 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1928 return 1;
1929 kvm->arch.hv_hypercall = data;
b94b64c9 1930 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1931 break;
1932 }
e984097b
VR		 1933 case HV_X64_MSR_REFERENCE_TSC: {
1934 u64 gfn;
1935 HV_REFERENCE_TSC_PAGE tsc_ref;
1936 memset(&tsc_ref, 0, sizeof(tsc_ref));
1937 kvm->arch.hv_tsc_page = data;
1938 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1939 break;
1940 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1941 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1942 &tsc_ref, sizeof(tsc_ref)))
1943 return 1;
1944 mark_page_dirty(kvm, gfn);
1945 break;
1946 }
55cd8e5a 1947 default:
a737f256
CD		 1948 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1949 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1950 return 1;
1951 }
1952 return 0;
1953}
1954
1955static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1956{
10388a07
GN		 1957 switch (msr) {
1958 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1959 u64 gfn;
10388a07 1960 unsigned long addr;
55cd8e5a 1961
10388a07
GN		 1962 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1963 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1964 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1965 return 1;
10388a07
GN		 1966 break;
1967 }
b3af1e88
VR		 1968 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1969 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1970 if (kvm_is_error_hva(addr))
1971 return 1;
8b0cedff 1972 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1973 return 1;
1974 vcpu->arch.hv_vapic = data;
b3af1e88 1975 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1976 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1977 return 1;
10388a07
GN		 1978 break;
1979 }
1980 case HV_X64_MSR_EOI:
1981 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1982 case HV_X64_MSR_ICR:
1983 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1984 case HV_X64_MSR_TPR:
1985 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1986 default:
a737f256
CD		 1987 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1988 "data 0x%llx\n", msr, data);
10388a07
GN		 1989 return 1;
1990 }
1991
1992 return 0;
55cd8e5a
GN		 1993}
1994
344d9588
GN		 1995static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1996{
1997 gpa_t gpa = data & ~0x3f;
1998
4a969980 1999 /* Bits 2:5 are reserved, Should be zero */
6adba527 2000 if (data & 0x3c)
344d9588
GN		 2001 return 1;
2002
2003 vcpu->arch.apf.msr_val = data;
2004
2005 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2006 kvm_clear_async_pf_completion_queue(vcpu);
2007 kvm_async_pf_hash_reset(vcpu);
2008 return 0;
2009 }
2010
8f964525
AH		 2011 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2012 sizeof(u32)))
344d9588
GN		 2013 return 1;
2014
6adba527 2015 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2016 kvm_async_pf_wakeup_all(vcpu);
2017 return 0;
2018}
2019
12f9a48f
GC		 2020static void kvmclock_reset(struct kvm_vcpu *vcpu)
2021{
0b79459b 2022 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2023}
2024
c9aaa895
GC		 2025static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2026{
2027 u64 delta;
2028
2029 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2030 return;
2031
2032 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2033 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2034 vcpu->arch.st.accum_steal = delta;
2035}
2036
2037static void record_steal_time(struct kvm_vcpu *vcpu)
2038{
2039 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2040 return;
2041
2042 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2043 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2044 return;
2045
2046 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2047 vcpu->arch.st.steal.version += 2;
2048 vcpu->arch.st.accum_steal = 0;
2049
2050 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2051 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2052}
2053
8fe8ab46 2054int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2055{
5753785f 2056 bool pr = false;
8fe8ab46
WA		 2057 u32 msr = msr_info->index;
2058 u64 data = msr_info->data;
5753785f 2059
15c4a640 2060 switch (msr) {
2e32b719
BP		 2061 case MSR_AMD64_NB_CFG:
2062 case MSR_IA32_UCODE_REV:
2063 case MSR_IA32_UCODE_WRITE:
2064 case MSR_VM_HSAVE_PA:
2065 case MSR_AMD64_PATCH_LOADER:
2066 case MSR_AMD64_BU_CFG2:
2067 break;
2068
15c4a640 2069 case MSR_EFER:
b69e8cae 2070 return set_efer(vcpu, data);
8f1589d9
AP		 2071 case MSR_K7_HWCR:
2072 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2073 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2074 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2075 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2076 if (data != 0) {
a737f256
CD		 2077 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2078 data);
8f1589d9
AP		 2079 return 1;
2080 }
15c4a640 2081 break;
f7c6d140
AP		 2082 case MSR_FAM10H_MMIO_CONF_BASE:
2083 if (data != 0) {
a737f256
CD		 2084 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2085 "0x%llx\n", data);
f7c6d140
AP		 2086 return 1;
2087 }
15c4a640 2088 break;
b5e2fec0
AG		 2089 case MSR_IA32_DEBUGCTLMSR:
2090 if (!data) {
2091 /* We support the non-activated case already */
2092 break;
2093 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2094 /* Values other than LBR and BTF are vendor-specific,
2095 thus reserved and should throw a #GP */
2096 return 1;
2097 }
a737f256
CD		 2098 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2099 __func__, data);
b5e2fec0 2100 break;
9ba075a6
AK		 2101 case 0x200 ... 0x2ff:
2102 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2103 case MSR_IA32_APICBASE:
58cb628d 2104 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2105 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2106 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2107 case MSR_IA32_TSCDEADLINE:
2108 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2109 break;
ba904635
WA		 2110 case MSR_IA32_TSC_ADJUST:
2111 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2112 if (!msr_info->host_initiated) {
2113 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2114 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2115 }
2116 vcpu->arch.ia32_tsc_adjust_msr = data;
2117 }
2118 break;
15c4a640 2119 case MSR_IA32_MISC_ENABLE:
ad312c7c 2120 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2121 break;
11c6bffa 2122 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2123 case MSR_KVM_WALL_CLOCK:
2124 vcpu->kvm->arch.wall_clock = data;
2125 kvm_write_wall_clock(vcpu->kvm, data);
2126 break;
11c6bffa 2127 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2128 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2129 u64 gpa_offset;
12f9a48f 2130 kvmclock_reset(vcpu);
18068523
GOC		 2131
2132 vcpu->arch.time = data;
0061d53d 2133 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2134
2135 /* we verify if the enable bit is set... */
2136 if (!(data & 1))
2137 break;
2138
0b79459b 2139 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2140
0b79459b 2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2142 &vcpu->arch.pv_time, data & ~1ULL,
2143 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2144 vcpu->arch.pv_time_enabled = false;
2145 else
2146 vcpu->arch.pv_time_enabled = true;
32cad84f 2147
18068523
GOC		 2148 break;
2149 }
344d9588
GN		 2150 case MSR_KVM_ASYNC_PF_EN:
2151 if (kvm_pv_enable_async_pf(vcpu, data))
2152 return 1;
2153 break;
c9aaa895
GC		 2154 case MSR_KVM_STEAL_TIME:
2155
2156 if (unlikely(!sched_info_on()))
2157 return 1;
2158
2159 if (data & KVM_STEAL_RESERVED_MASK)
2160 return 1;
2161
2162 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2163 data & KVM_STEAL_VALID_BITS,
2164 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2165 return 1;
2166
2167 vcpu->arch.st.msr_val = data;
2168
2169 if (!(data & KVM_MSR_ENABLED))
2170 break;
2171
2172 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2173
2174 preempt_disable();
2175 accumulate_steal_time(vcpu);
2176 preempt_enable();
2177
2178 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2179
2180 break;
ae7a2a3f
MT		 2181 case MSR_KVM_PV_EOI_EN:
2182 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2183 return 1;
2184 break;
c9aaa895 2185
890ca9ae
HY		 2186 case MSR_IA32_MCG_CTL:
2187 case MSR_IA32_MCG_STATUS:
81760dcc 2188 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2189 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2190
2191 /* Performance counters are not protected by a CPUID bit,
2192 * so we should check all of them in the generic path for the sake of
2193 * cross vendor migration.
2194 * Writing a zero into the event select MSRs disables them,
2195 * which we perfectly emulate ;-). Any other value should be at least
2196 * reported, some guests depend on them.
2197 */
71db6023
AP		 2198 case MSR_K7_EVNTSEL0:
2199 case MSR_K7_EVNTSEL1:
2200 case MSR_K7_EVNTSEL2:
2201 case MSR_K7_EVNTSEL3:
2202 if (data != 0)
a737f256
CD		 2203 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2204 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2205 break;
2206 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2207 * so we ignore writes to make it happy.
2208 */
71db6023
AP		 2209 case MSR_K7_PERFCTR0:
2210 case MSR_K7_PERFCTR1:
2211 case MSR_K7_PERFCTR2:
2212 case MSR_K7_PERFCTR3:
a737f256
CD		 2213 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2214 "0x%x data 0x%llx\n", msr, data);
71db6023 2215 break;
5753785f
GN		 2216 case MSR_P6_PERFCTR0:
2217 case MSR_P6_PERFCTR1:
2218 pr = true;
2219 case MSR_P6_EVNTSEL0:
2220 case MSR_P6_EVNTSEL1:
2221 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2222 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2223
2224 if (pr || data != 0)
a737f256
CD		 2225 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2226 "0x%x data 0x%llx\n", msr, data);
5753785f 2227 break;
84e0cefa
JS		 2228 case MSR_K7_CLK_CTL:
2229 /*
2230 * Ignore all writes to this no longer documented MSR.
2231 * Writes are only relevant for old K7 processors,
2232 * all pre-dating SVM, but a recommended workaround from
4a969980 2233 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2234 * affected processor models on the command line, hence
2235 * the need to ignore the workaround.
2236 */
2237 break;
55cd8e5a
GN		 2238 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2239 if (kvm_hv_msr_partition_wide(msr)) {
2240 int r;
2241 mutex_lock(&vcpu->kvm->lock);
2242 r = set_msr_hyperv_pw(vcpu, msr, data);
2243 mutex_unlock(&vcpu->kvm->lock);
2244 return r;
2245 } else
2246 return set_msr_hyperv(vcpu, msr, data);
2247 break;
91c9c3ed 2248 case MSR_IA32_BBL_CR_CTL3:
2249 /* Drop writes to this legacy MSR -- see rdmsr
2250 * counterpart for further detail.
2251 */
a737f256 2252 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2253 break;
2b036c6b
BO		 2254 case MSR_AMD64_OSVW_ID_LENGTH:
2255 if (!guest_cpuid_has_osvw(vcpu))
2256 return 1;
2257 vcpu->arch.osvw.length = data;
2258 break;
2259 case MSR_AMD64_OSVW_STATUS:
2260 if (!guest_cpuid_has_osvw(vcpu))
2261 return 1;
2262 vcpu->arch.osvw.status = data;
2263 break;
15c4a640 2264 default:
ffde22ac
ES		 2265 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2266 return xen_hvm_config(vcpu, data);
f5132b01 2267 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2268 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2269 if (!ignore_msrs) {
a737f256
CD		 2270 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2271 msr, data);
ed85c068
AP		 2272 return 1;
2273 } else {
a737f256
CD		 2274 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2275 msr, data);
ed85c068
AP		 2276 break;
2277 }
15c4a640
CO		 2278 }
2279 return 0;
2280}
2281EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2282
2283
2284/*
2285 * Reads an msr value (of 'msr_index') into 'pdata'.
2286 * Returns 0 on success, non-0 otherwise.
2287 * Assumes vcpu_load() was already called.
2288 */
2289int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2290{
2291 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2292}
2293
9ba075a6
AK		 2294static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295{
0bed3b56
SY		 2296 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2297
9ba075a6
AK		 2298 if (!msr_mtrr_valid(msr))
2299 return 1;
2300
0bed3b56
SY		 2301 if (msr == MSR_MTRRdefType)
2302 *pdata = vcpu->arch.mtrr_state.def_type +
2303 (vcpu->arch.mtrr_state.enabled << 10);
2304 else if (msr == MSR_MTRRfix64K_00000)
2305 *pdata = p[0];
2306 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2307 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2308 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2309 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2310 else if (msr == MSR_IA32_CR_PAT)
2311 *pdata = vcpu->arch.pat;
2312 else { /* Variable MTRRs */
2313 int idx, is_mtrr_mask;
2314 u64 *pt;
2315
2316 idx = (msr - 0x200) / 2;
2317 is_mtrr_mask = msr - 0x200 - 2 * idx;
2318 if (!is_mtrr_mask)
2319 pt =
2320 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2321 else
2322 pt =
2323 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2324 *pdata = *pt;
2325 }
2326
9ba075a6
AK		 2327 return 0;
2328}
2329
890ca9ae 2330static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2331{
2332 u64 data;
890ca9ae
HY		 2333 u64 mcg_cap = vcpu->arch.mcg_cap;
2334 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2335
2336 switch (msr) {
15c4a640
CO		 2337 case MSR_IA32_P5_MC_ADDR:
2338 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2339 data = 0;
2340 break;
15c4a640 2341 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2342 data = vcpu->arch.mcg_cap;
2343 break;
c7ac679c 2344 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2345 if (!(mcg_cap & MCG_CTL_P))
2346 return 1;
2347 data = vcpu->arch.mcg_ctl;
2348 break;
2349 case MSR_IA32_MCG_STATUS:
2350 data = vcpu->arch.mcg_status;
2351 break;
2352 default:
2353 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2354 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2355 u32 offset = msr - MSR_IA32_MC0_CTL;
2356 data = vcpu->arch.mce_banks[offset];
2357 break;
2358 }
2359 return 1;
2360 }
2361 *pdata = data;
2362 return 0;
2363}
2364
55cd8e5a
GN		 2365static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2366{
2367 u64 data = 0;
2368 struct kvm *kvm = vcpu->kvm;
2369
2370 switch (msr) {
2371 case HV_X64_MSR_GUEST_OS_ID:
2372 data = kvm->arch.hv_guest_os_id;
2373 break;
2374 case HV_X64_MSR_HYPERCALL:
2375 data = kvm->arch.hv_hypercall;
2376 break;
e984097b
VR		 2377 case HV_X64_MSR_TIME_REF_COUNT: {
2378 data =
2379 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2380 break;
2381 }
2382 case HV_X64_MSR_REFERENCE_TSC:
2383 data = kvm->arch.hv_tsc_page;
2384 break;
55cd8e5a 2385 default:
a737f256 2386 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2387 return 1;
2388 }
2389
2390 *pdata = data;
2391 return 0;
2392}
2393
2394static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2395{
2396 u64 data = 0;
2397
2398 switch (msr) {
2399 case HV_X64_MSR_VP_INDEX: {
2400 int r;
2401 struct kvm_vcpu *v;
684851a1
TY		 2402 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2403 if (v == vcpu) {
55cd8e5a 2404 data = r;
684851a1
TY		 2405 break;
2406 }
2407 }
55cd8e5a
GN		 2408 break;
2409 }
10388a07
GN		 2410 case HV_X64_MSR_EOI:
2411 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2412 case HV_X64_MSR_ICR:
2413 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2414 case HV_X64_MSR_TPR:
2415 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2416 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2417 data = vcpu->arch.hv_vapic;
2418 break;
55cd8e5a 2419 default:
a737f256 2420 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2421 return 1;
2422 }
2423 *pdata = data;
2424 return 0;
2425}
2426
890ca9ae
HY		 2427int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2428{
2429 u64 data;
2430
2431 switch (msr) {
890ca9ae 2432 case MSR_IA32_PLATFORM_ID:
15c4a640 2433 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2434 case MSR_IA32_DEBUGCTLMSR:
2435 case MSR_IA32_LASTBRANCHFROMIP:
2436 case MSR_IA32_LASTBRANCHTOIP:
2437 case MSR_IA32_LASTINTFROMIP:
2438 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2439 case MSR_K8_SYSCFG:
2440 case MSR_K7_HWCR:
61a6bd67 2441 case MSR_VM_HSAVE_PA:
9e699624 2442 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2443 case MSR_K7_EVNTSEL1:
2444 case MSR_K7_EVNTSEL2:
2445 case MSR_K7_EVNTSEL3:
1f3ee616 2446 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2447 case MSR_K7_PERFCTR1:
2448 case MSR_K7_PERFCTR2:
2449 case MSR_K7_PERFCTR3:
1fdbd48c 2450 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2451 case MSR_AMD64_NB_CFG:
f7c6d140 2452 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2453 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2454 data = 0;
2455 break;
5753785f
GN		 2456 case MSR_P6_PERFCTR0:
2457 case MSR_P6_PERFCTR1:
2458 case MSR_P6_EVNTSEL0:
2459 case MSR_P6_EVNTSEL1:
2460 if (kvm_pmu_msr(vcpu, msr))
2461 return kvm_pmu_get_msr(vcpu, msr, pdata);
2462 data = 0;
2463 break;
742bc670
MT		 2464 case MSR_IA32_UCODE_REV:
2465 data = 0x100000000ULL;
2466 break;
9ba075a6
AK		 2467 case MSR_MTRRcap:
2468 data = 0x500 | KVM_NR_VAR_MTRR;
2469 break;
2470 case 0x200 ... 0x2ff:
2471 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2472 case 0xcd: /* fsb frequency */
2473 data = 3;
2474 break;
7b914098
JS		 2475 /*
2476 * MSR_EBC_FREQUENCY_ID
2477 * Conservative value valid for even the basic CPU models.
2478 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2479 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2480 * and 266MHz for model 3, or 4. Set Core Clock
2481 * Frequency to System Bus Frequency Ratio to 1 (bits
2482 * 31:24) even though these are only valid for CPU
2483 * models > 2, however guests may end up dividing or
2484 * multiplying by zero otherwise.
2485 */
2486 case MSR_EBC_FREQUENCY_ID:
2487 data = 1 << 24;
2488 break;
15c4a640
CO		 2489 case MSR_IA32_APICBASE:
2490 data = kvm_get_apic_base(vcpu);
2491 break;
0105d1a5
GN		 2492 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2493 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2494 break;
a3e06bbe
LJ		 2495 case MSR_IA32_TSCDEADLINE:
2496 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2497 break;
ba904635
WA		 2498 case MSR_IA32_TSC_ADJUST:
2499 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2500 break;
15c4a640 2501 case MSR_IA32_MISC_ENABLE:
ad312c7c 2502 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2503 break;
847f0ad8
AG		 2504 case MSR_IA32_PERF_STATUS:
2505 /* TSC increment by tick */
2506 data = 1000ULL;
2507 /* CPU multiplier */
2508 data |= (((uint64_t)4ULL) << 40);
2509 break;
15c4a640 2510 case MSR_EFER:
f6801dff 2511 data = vcpu->arch.efer;
15c4a640 2512 break;
18068523 2513 case MSR_KVM_WALL_CLOCK:
11c6bffa 2514 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2515 data = vcpu->kvm->arch.wall_clock;
2516 break;
2517 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2518 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2519 data = vcpu->arch.time;
2520 break;
344d9588
GN		 2521 case MSR_KVM_ASYNC_PF_EN:
2522 data = vcpu->arch.apf.msr_val;
2523 break;
c9aaa895
GC		 2524 case MSR_KVM_STEAL_TIME:
2525 data = vcpu->arch.st.msr_val;
2526 break;
1d92128f
MT		 2527 case MSR_KVM_PV_EOI_EN:
2528 data = vcpu->arch.pv_eoi.msr_val;
2529 break;
890ca9ae
HY		 2530 case MSR_IA32_P5_MC_ADDR:
2531 case MSR_IA32_P5_MC_TYPE:
2532 case MSR_IA32_MCG_CAP:
2533 case MSR_IA32_MCG_CTL:
2534 case MSR_IA32_MCG_STATUS:
81760dcc 2535 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2536 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2537 case MSR_K7_CLK_CTL:
2538 /*
2539 * Provide expected ramp-up count for K7. All other
2540 * are set to zero, indicating minimum divisors for
2541 * every field.
2542 *
2543 * This prevents guest kernels on AMD host with CPU
2544 * type 6, model 8 and higher from exploding due to
2545 * the rdmsr failing.
2546 */
2547 data = 0x20000000;
2548 break;
55cd8e5a
GN		 2549 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2550 if (kvm_hv_msr_partition_wide(msr)) {
2551 int r;
2552 mutex_lock(&vcpu->kvm->lock);
2553 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2554 mutex_unlock(&vcpu->kvm->lock);
2555 return r;
2556 } else
2557 return get_msr_hyperv(vcpu, msr, pdata);
2558 break;
91c9c3ed 2559 case MSR_IA32_BBL_CR_CTL3:
2560 /* This legacy MSR exists but isn't fully documented in current
2561 * silicon. It is however accessed by winxp in very narrow
2562 * scenarios where it sets bit #19, itself documented as
2563 * a "reserved" bit. Best effort attempt to source coherent
2564 * read data here should the balance of the register be
2565 * interpreted by the guest:
2566 *
2567 * L2 cache control register 3: 64GB range, 256KB size,
2568 * enabled, latency 0x1, configured
2569 */
2570 data = 0xbe702111;
2571 break;
2b036c6b
BO		 2572 case MSR_AMD64_OSVW_ID_LENGTH:
2573 if (!guest_cpuid_has_osvw(vcpu))
2574 return 1;
2575 data = vcpu->arch.osvw.length;
2576 break;
2577 case MSR_AMD64_OSVW_STATUS:
2578 if (!guest_cpuid_has_osvw(vcpu))
2579 return 1;
2580 data = vcpu->arch.osvw.status;
2581 break;
15c4a640 2582 default:
f5132b01
GN		 2583 if (kvm_pmu_msr(vcpu, msr))
2584 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2585 if (!ignore_msrs) {
a737f256 2586 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2587 return 1;
2588 } else {
a737f256 2589 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2590 data = 0;
2591 }
2592 break;
15c4a640
CO		 2593 }
2594 *pdata = data;
2595 return 0;
2596}
2597EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2598
313a3dc7
CO		 2599/*
2600 * Read or write a bunch of msrs. All parameters are kernel addresses.
2601 *
2602 * @return number of msrs set successfully.
2603 */
2604static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2605 struct kvm_msr_entry *entries,
2606 int (*do_msr)(struct kvm_vcpu *vcpu,
2607 unsigned index, u64 *data))
2608{
f656ce01 2609 int i, idx;
313a3dc7 2610
f656ce01 2611 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2612 for (i = 0; i < msrs->nmsrs; ++i)
2613 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2614 break;
f656ce01 2615 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2616
313a3dc7
CO		 2617 return i;
2618}
2619
2620/*
2621 * Read or write a bunch of msrs. Parameters are user addresses.
2622 *
2623 * @return number of msrs set successfully.
2624 */
2625static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2626 int (*do_msr)(struct kvm_vcpu *vcpu,
2627 unsigned index, u64 *data),
2628 int writeback)
2629{
2630 struct kvm_msrs msrs;
2631 struct kvm_msr_entry *entries;
2632 int r, n;
2633 unsigned size;
2634
2635 r = -EFAULT;
2636 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2637 goto out;
2638
2639 r = -E2BIG;
2640 if (msrs.nmsrs >= MAX_IO_MSRS)
2641 goto out;
2642
313a3dc7 2643 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2644 entries = memdup_user(user_msrs->entries, size);
2645 if (IS_ERR(entries)) {
2646 r = PTR_ERR(entries);
313a3dc7 2647 goto out;
ff5c2c03 2648 }
313a3dc7
CO		 2649
2650 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2651 if (r < 0)
2652 goto out_free;
2653
2654 r = -EFAULT;
2655 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2656 goto out_free;
2657
2658 r = n;
2659
2660out_free:
7a73c028 2661 kfree(entries);
313a3dc7
CO		 2662out:
2663 return r;
2664}
2665
784aa3d7 2666int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2667{
2668 int r;
2669
2670 switch (ext) {
2671 case KVM_CAP_IRQCHIP:
2672 case KVM_CAP_HLT:
2673 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2674 case KVM_CAP_SET_TSS_ADDR:
07716717 2675 case KVM_CAP_EXT_CPUID:
9c15bb1d 2676 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2677 case KVM_CAP_CLOCKSOURCE:
7837699f 2678 case KVM_CAP_PIT:
a28e4f5a 2679 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2680 case KVM_CAP_MP_STATE:
ed848624 2681 case KVM_CAP_SYNC_MMU:
a355c85c 2682 case KVM_CAP_USER_NMI:
52d939a0 2683 case KVM_CAP_REINJECT_CONTROL:
4925663a 2684 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2685 case KVM_CAP_IRQFD:
d34e6b17 2686 case KVM_CAP_IOEVENTFD:
f848a5a8 2687 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2688 case KVM_CAP_PIT2:
e9f42757 2689 case KVM_CAP_PIT_STATE2:
b927a3ce 2690 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2691 case KVM_CAP_XEN_HVM:
afbcf7ab 2692 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2693 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2694 case KVM_CAP_HYPERV:
10388a07 2695 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2696 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2697 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2698 case KVM_CAP_DEBUGREGS:
d2be1651 2699 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2700 case KVM_CAP_XSAVE:
344d9588 2701 case KVM_CAP_ASYNC_PF:
92a1f12d 2702 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2703 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2704 case KVM_CAP_READONLY_MEM:
5f66b620 2705 case KVM_CAP_HYPERV_TIME:
100943c5 2706 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2707#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2708 case KVM_CAP_ASSIGN_DEV_IRQ:
2709 case KVM_CAP_PCI_2_3:
2710#endif
018d00d2
ZX		 2711 r = 1;
2712 break;
542472b5
LV		 2713 case KVM_CAP_COALESCED_MMIO:
2714 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2715 break;
774ead3a
AK		 2716 case KVM_CAP_VAPIC:
2717 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2718 break;
f725230a 2719 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2720 r = KVM_SOFT_MAX_VCPUS;
2721 break;
2722 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2723 r = KVM_MAX_VCPUS;
2724 break;
a988b910 2725 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2726 r = KVM_USER_MEM_SLOTS;
a988b910 2727 break;
a68a6a72
MT		 2728 case KVM_CAP_PV_MMU: /* obsolete */
2729 r = 0;
2f333bcb 2730 break;
4cee4b72 2731#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2732 case KVM_CAP_IOMMU:
a1b60c1c 2733 r = iommu_present(&pci_bus_type);
62c476c7 2734 break;
4cee4b72 2735#endif
890ca9ae
HY		 2736 case KVM_CAP_MCE:
2737 r = KVM_MAX_MCE_BANKS;
2738 break;
2d5b5a66
SY		 2739 case KVM_CAP_XCRS:
2740 r = cpu_has_xsave;
2741 break;
92a1f12d
JR		 2742 case KVM_CAP_TSC_CONTROL:
2743 r = kvm_has_tsc_control;
2744 break;
4d25a066
JK		 2745 case KVM_CAP_TSC_DEADLINE_TIMER:
2746 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2747 break;
018d00d2
ZX		 2748 default:
2749 r = 0;
2750 break;
2751 }
2752 return r;
2753
2754}
2755
043405e1
CO		 2756long kvm_arch_dev_ioctl(struct file *filp,
2757 unsigned int ioctl, unsigned long arg)
2758{
2759 void __user *argp = (void __user *)arg;
2760 long r;
2761
2762 switch (ioctl) {
2763 case KVM_GET_MSR_INDEX_LIST: {
2764 struct kvm_msr_list __user *user_msr_list = argp;
2765 struct kvm_msr_list msr_list;
2766 unsigned n;
2767
2768 r = -EFAULT;
2769 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2770 goto out;
2771 n = msr_list.nmsrs;
2772 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2773 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2774 goto out;
2775 r = -E2BIG;
e125e7b6 2776 if (n < msr_list.nmsrs)
043405e1
CO		 2777 goto out;
2778 r = -EFAULT;
2779 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2780 num_msrs_to_save * sizeof(u32)))
2781 goto out;
e125e7b6 2782 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2783 &emulated_msrs,
2784 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2785 goto out;
2786 r = 0;
2787 break;
2788 }
9c15bb1d
BP		 2789 case KVM_GET_SUPPORTED_CPUID:
2790 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2791 struct kvm_cpuid2 __user *cpuid_arg = argp;
2792 struct kvm_cpuid2 cpuid;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2796 goto out;
9c15bb1d
BP		 2797
2798 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2799 ioctl);
674eea0f
AK		 2800 if (r)
2801 goto out;
2802
2803 r = -EFAULT;
2804 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2805 goto out;
2806 r = 0;
2807 break;
2808 }
890ca9ae
HY		 2809 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2810 u64 mce_cap;
2811
2812 mce_cap = KVM_MCE_CAP_SUPPORTED;
2813 r = -EFAULT;
2814 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2815 goto out;
2816 r = 0;
2817 break;
2818 }
043405e1
CO		 2819 default:
2820 r = -EINVAL;
2821 }
2822out:
2823 return r;
2824}
2825
f5f48ee1
SY		 2826static void wbinvd_ipi(void *garbage)
2827{
2828 wbinvd();
2829}
2830
2831static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2832{
e0f0bbc5 2833 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2834}
2835
313a3dc7
CO		 2836void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2837{
f5f48ee1
SY		 2838 /* Address WBINVD may be executed by guest */
2839 if (need_emulate_wbinvd(vcpu)) {
2840 if (kvm_x86_ops->has_wbinvd_exit())
2841 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2842 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2843 smp_call_function_single(vcpu->cpu,
2844 wbinvd_ipi, NULL, 1);
2845 }
2846
313a3dc7 2847 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2848
0dd6a6ed
ZA		 2849 /* Apply any externally detected TSC adjustments (due to suspend) */
2850 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2851 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2852 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2853 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2854 }
8f6055cb 2855
48434c20 2856 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2857 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2858 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2859 if (tsc_delta < 0)
2860 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2861 if (check_tsc_unstable()) {
b183aa58
ZA		 2862 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2863 vcpu->arch.last_guest_tsc);
2864 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2865 vcpu->arch.tsc_catchup = 1;
c285545f 2866 }
d98d07ca
MT		 2867 /*
2868 * On a host with synchronized TSC, there is no need to update
2869 * kvmclock on vcpu->cpu migration
2870 */
2871 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2872 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2873 if (vcpu->cpu != cpu)
2874 kvm_migrate_timers(vcpu);
e48672fa 2875 vcpu->cpu = cpu;
6b7d7e76 2876 }
c9aaa895
GC		 2877
2878 accumulate_steal_time(vcpu);
2879 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2880}
2881
2882void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2883{
02daab21 2884 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2885 kvm_put_guest_fpu(vcpu);
6f526ec5 2886 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2887}
2888
313a3dc7
CO		 2889static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2890 struct kvm_lapic_state *s)
2891{
5a71785d 2892 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2893 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2894
2895 return 0;
2896}
2897
2898static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2899 struct kvm_lapic_state *s)
2900{
64eb0620 2901 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2902 update_cr8_intercept(vcpu);
313a3dc7
CO		 2903
2904 return 0;
2905}
2906
f77bc6a4
ZX		 2907static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2908 struct kvm_interrupt *irq)
2909{
02cdb50f 2910 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2911 return -EINVAL;
2912 if (irqchip_in_kernel(vcpu->kvm))
2913 return -ENXIO;
f77bc6a4 2914
66fd3f7f 2915 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2916 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2917
f77bc6a4
ZX		 2918 return 0;
2919}
2920
c4abb7c9
JK		 2921static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2922{
c4abb7c9 2923 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2924
2925 return 0;
2926}
2927
b209749f
AK		 2928static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2929 struct kvm_tpr_access_ctl *tac)
2930{
2931 if (tac->flags)
2932 return -EINVAL;
2933 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2934 return 0;
2935}
2936
890ca9ae
HY		 2937static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2938 u64 mcg_cap)
2939{
2940 int r;
2941 unsigned bank_num = mcg_cap & 0xff, bank;
2942
2943 r = -EINVAL;
a9e38c3e 2944 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2945 goto out;
2946 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2947 goto out;
2948 r = 0;
2949 vcpu->arch.mcg_cap = mcg_cap;
2950 /* Init IA32_MCG_CTL to all 1s */
2951 if (mcg_cap & MCG_CTL_P)
2952 vcpu->arch.mcg_ctl = ~(u64)0;
2953 /* Init IA32_MCi_CTL to all 1s */
2954 for (bank = 0; bank < bank_num; bank++)
2955 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2956out:
2957 return r;
2958}
2959
2960static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2961 struct kvm_x86_mce *mce)
2962{
2963 u64 mcg_cap = vcpu->arch.mcg_cap;
2964 unsigned bank_num = mcg_cap & 0xff;
2965 u64 *banks = vcpu->arch.mce_banks;
2966
2967 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2968 return -EINVAL;
2969 /*
2970 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2971 * reporting is disabled
2972 */
2973 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2974 vcpu->arch.mcg_ctl != ~(u64)0)
2975 return 0;
2976 banks += 4 * mce->bank;
2977 /*
2978 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2979 * reporting is disabled for the bank
2980 */
2981 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2982 return 0;
2983 if (mce->status & MCI_STATUS_UC) {
2984 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2985 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2986 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2987 return 0;
2988 }
2989 if (banks[1] & MCI_STATUS_VAL)
2990 mce->status |= MCI_STATUS_OVER;
2991 banks[2] = mce->addr;
2992 banks[3] = mce->misc;
2993 vcpu->arch.mcg_status = mce->mcg_status;
2994 banks[1] = mce->status;
2995 kvm_queue_exception(vcpu, MC_VECTOR);
2996 } else if (!(banks[1] & MCI_STATUS_VAL)
2997 || !(banks[1] & MCI_STATUS_UC)) {
2998 if (banks[1] & MCI_STATUS_VAL)
2999 mce->status |= MCI_STATUS_OVER;
3000 banks[2] = mce->addr;
3001 banks[3] = mce->misc;
3002 banks[1] = mce->status;
3003 } else
3004 banks[1] |= MCI_STATUS_OVER;
3005 return 0;
3006}
3007
3cfc3092
JK		 3008static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3009 struct kvm_vcpu_events *events)
3010{
7460fb4a 3011 process_nmi(vcpu);
03b82a30
JK		 3012 events->exception.injected =
3013 vcpu->arch.exception.pending &&
3014 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3015 events->exception.nr = vcpu->arch.exception.nr;
3016 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3017 events->exception.pad = 0;
3cfc3092
JK		 3018 events->exception.error_code = vcpu->arch.exception.error_code;
3019
03b82a30
JK		 3020 events->interrupt.injected =
3021 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3022 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3023 events->interrupt.soft = 0;
37ccdcbe 3024 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3025
3026 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3027 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3028 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3029 events->nmi.pad = 0;
3cfc3092 3030
66450a21 3031 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3032
dab4b911 3033 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3034 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3035 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3036}
3037
3038static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3039 struct kvm_vcpu_events *events)
3040{
dab4b911 3041 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3042 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3043 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3044 return -EINVAL;
3045
7460fb4a 3046 process_nmi(vcpu);
3cfc3092
JK		 3047 vcpu->arch.exception.pending = events->exception.injected;
3048 vcpu->arch.exception.nr = events->exception.nr;
3049 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3050 vcpu->arch.exception.error_code = events->exception.error_code;
3051
3052 vcpu->arch.interrupt.pending = events->interrupt.injected;
3053 vcpu->arch.interrupt.nr = events->interrupt.nr;
3054 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3055 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3056 kvm_x86_ops->set_interrupt_shadow(vcpu,
3057 events->interrupt.shadow);
3cfc3092
JK		 3058
3059 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3060 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3061 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3062 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3063
66450a21
JK		 3064 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3065 kvm_vcpu_has_lapic(vcpu))
3066 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3067
3842d135
AK		 3068 kvm_make_request(KVM_REQ_EVENT, vcpu);
3069
3cfc3092
JK		 3070 return 0;
3071}
3072
a1efbe77
JK		 3073static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3074 struct kvm_debugregs *dbgregs)
3075{
73aaf249
JK		 3076 unsigned long val;
3077
a1efbe77 3078 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3079 _kvm_get_dr(vcpu, 6, &val);
3080 dbgregs->dr6 = val;
a1efbe77
JK		 3081 dbgregs->dr7 = vcpu->arch.dr7;
3082 dbgregs->flags = 0;
97e69aa6 3083 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3084}
3085
3086static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3087 struct kvm_debugregs *dbgregs)
3088{
3089 if (dbgregs->flags)
3090 return -EINVAL;
3091
a1efbe77
JK		 3092 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3093 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3094 kvm_update_dr6(vcpu);
a1efbe77 3095 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3096 kvm_update_dr7(vcpu);
a1efbe77 3097
a1efbe77
JK		 3098 return 0;
3099}
3100
2d5b5a66
SY		 3101static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3102 struct kvm_xsave *guest_xsave)
3103{
4344ee98 3104 if (cpu_has_xsave) {
2d5b5a66
SY		 3105 memcpy(guest_xsave->region,
3106 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3107 vcpu->arch.guest_xstate_size);
3108 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3109 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3110 } else {
2d5b5a66
SY		 3111 memcpy(guest_xsave->region,
3112 &vcpu->arch.guest_fpu.state->fxsave,
3113 sizeof(struct i387_fxsave_struct));
3114 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3115 XSTATE_FPSSE;
3116 }
3117}
3118
3119static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3120 struct kvm_xsave *guest_xsave)
3121{
3122 u64 xstate_bv =
3123 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3124
d7876f1b
PB		 3125 if (cpu_has_xsave) {
3126 /*
3127 * Here we allow setting states that are not present in
3128 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3129 * with old userspace.
3130 */
4ff41732 3131 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3132 return -EINVAL;
2d5b5a66 3133 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3134 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3135 } else {
2d5b5a66
SY		 3136 if (xstate_bv & ~XSTATE_FPSSE)
3137 return -EINVAL;
3138 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3139 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3140 }
3141 return 0;
3142}
3143
3144static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3145 struct kvm_xcrs *guest_xcrs)
3146{
3147 if (!cpu_has_xsave) {
3148 guest_xcrs->nr_xcrs = 0;
3149 return;
3150 }
3151
3152 guest_xcrs->nr_xcrs = 1;
3153 guest_xcrs->flags = 0;
3154 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3155 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3156}
3157
3158static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3159 struct kvm_xcrs *guest_xcrs)
3160{
3161 int i, r = 0;
3162
3163 if (!cpu_has_xsave)
3164 return -EINVAL;
3165
3166 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3167 return -EINVAL;
3168
3169 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3170 /* Only support XCR0 currently */
c67a04cb 3171 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3172 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3173 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3174 break;
3175 }
3176 if (r)
3177 r = -EINVAL;
3178 return r;
3179}
3180
1c0b28c2
EM		 3181/*
3182 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3183 * stopped by the hypervisor. This function will be called from the host only.
3184 * EINVAL is returned when the host attempts to set the flag for a guest that
3185 * does not support pv clocks.
3186 */
3187static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3188{
0b79459b 3189 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3190 return -EINVAL;
51d59c6b 3191 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3192 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3193 return 0;
3194}
3195
313a3dc7
CO		 3196long kvm_arch_vcpu_ioctl(struct file *filp,
3197 unsigned int ioctl, unsigned long arg)
3198{
3199 struct kvm_vcpu *vcpu = filp->private_data;
3200 void __user *argp = (void __user *)arg;
3201 int r;
d1ac91d8
AK		 3202 union {
3203 struct kvm_lapic_state *lapic;
3204 struct kvm_xsave *xsave;
3205 struct kvm_xcrs *xcrs;
3206 void *buffer;
3207 } u;
3208
3209 u.buffer = NULL;
313a3dc7
CO		 3210 switch (ioctl) {
3211 case KVM_GET_LAPIC: {
2204ae3c
MT		 3212 r = -EINVAL;
3213 if (!vcpu->arch.apic)
3214 goto out;
d1ac91d8 3215 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3216
b772ff36 3217 r = -ENOMEM;
d1ac91d8 3218 if (!u.lapic)
b772ff36 3219 goto out;
d1ac91d8 3220 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3221 if (r)
3222 goto out;
3223 r = -EFAULT;
d1ac91d8 3224 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3225 goto out;
3226 r = 0;
3227 break;
3228 }
3229 case KVM_SET_LAPIC: {
2204ae3c
MT		 3230 r = -EINVAL;
3231 if (!vcpu->arch.apic)
3232 goto out;
ff5c2c03 3233 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3234 if (IS_ERR(u.lapic))
3235 return PTR_ERR(u.lapic);
ff5c2c03 3236
d1ac91d8 3237 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3238 break;
3239 }
f77bc6a4
ZX		 3240 case KVM_INTERRUPT: {
3241 struct kvm_interrupt irq;
3242
3243 r = -EFAULT;
3244 if (copy_from_user(&irq, argp, sizeof irq))
3245 goto out;
3246 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3247 break;
3248 }
c4abb7c9
JK		 3249 case KVM_NMI: {
3250 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3251 break;
3252 }
313a3dc7
CO		 3253 case KVM_SET_CPUID: {
3254 struct kvm_cpuid __user *cpuid_arg = argp;
3255 struct kvm_cpuid cpuid;
3256
3257 r = -EFAULT;
3258 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3259 goto out;
3260 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3261 break;
3262 }
07716717
DK		 3263 case KVM_SET_CPUID2: {
3264 struct kvm_cpuid2 __user *cpuid_arg = argp;
3265 struct kvm_cpuid2 cpuid;
3266
3267 r = -EFAULT;
3268 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3269 goto out;
3270 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3271 cpuid_arg->entries);
07716717
DK		 3272 break;
3273 }
3274 case KVM_GET_CPUID2: {
3275 struct kvm_cpuid2 __user *cpuid_arg = argp;
3276 struct kvm_cpuid2 cpuid;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3280 goto out;
3281 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3282 cpuid_arg->entries);
07716717
DK		 3283 if (r)
3284 goto out;
3285 r = -EFAULT;
3286 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3287 goto out;
3288 r = 0;
3289 break;
3290 }
313a3dc7
CO		 3291 case KVM_GET_MSRS:
3292 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3293 break;
3294 case KVM_SET_MSRS:
3295 r = msr_io(vcpu, argp, do_set_msr, 0);
3296 break;
b209749f
AK		 3297 case KVM_TPR_ACCESS_REPORTING: {
3298 struct kvm_tpr_access_ctl tac;
3299
3300 r = -EFAULT;
3301 if (copy_from_user(&tac, argp, sizeof tac))
3302 goto out;
3303 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3304 if (r)
3305 goto out;
3306 r = -EFAULT;
3307 if (copy_to_user(argp, &tac, sizeof tac))
3308 goto out;
3309 r = 0;
3310 break;
3311 };
b93463aa
AK		 3312 case KVM_SET_VAPIC_ADDR: {
3313 struct kvm_vapic_addr va;
3314
3315 r = -EINVAL;
3316 if (!irqchip_in_kernel(vcpu->kvm))
3317 goto out;
3318 r = -EFAULT;
3319 if (copy_from_user(&va, argp, sizeof va))
3320 goto out;
fda4e2e8 3321 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3322 break;
3323 }
890ca9ae
HY		 3324 case KVM_X86_SETUP_MCE: {
3325 u64 mcg_cap;
3326
3327 r = -EFAULT;
3328 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3329 goto out;
3330 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3331 break;
3332 }
3333 case KVM_X86_SET_MCE: {
3334 struct kvm_x86_mce mce;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&mce, argp, sizeof mce))
3338 goto out;
3339 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3340 break;
3341 }
3cfc3092
JK		 3342 case KVM_GET_VCPU_EVENTS: {
3343 struct kvm_vcpu_events events;
3344
3345 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3346
3347 r = -EFAULT;
3348 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3349 break;
3350 r = 0;
3351 break;
3352 }
3353 case KVM_SET_VCPU_EVENTS: {
3354 struct kvm_vcpu_events events;
3355
3356 r = -EFAULT;
3357 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3358 break;
3359
3360 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3361 break;
3362 }
a1efbe77
JK		 3363 case KVM_GET_DEBUGREGS: {
3364 struct kvm_debugregs dbgregs;
3365
3366 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3367
3368 r = -EFAULT;
3369 if (copy_to_user(argp, &dbgregs,
3370 sizeof(struct kvm_debugregs)))
3371 break;
3372 r = 0;
3373 break;
3374 }
3375 case KVM_SET_DEBUGREGS: {
3376 struct kvm_debugregs dbgregs;
3377
3378 r = -EFAULT;
3379 if (copy_from_user(&dbgregs, argp,
3380 sizeof(struct kvm_debugregs)))
3381 break;
3382
3383 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3384 break;
3385 }
2d5b5a66 3386 case KVM_GET_XSAVE: {
d1ac91d8 3387 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3388 r = -ENOMEM;
d1ac91d8 3389 if (!u.xsave)
2d5b5a66
SY		 3390 break;
3391
d1ac91d8 3392 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3393
3394 r = -EFAULT;
d1ac91d8 3395 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3396 break;
3397 r = 0;
3398 break;
3399 }
3400 case KVM_SET_XSAVE: {
ff5c2c03 3401 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3402 if (IS_ERR(u.xsave))
3403 return PTR_ERR(u.xsave);
2d5b5a66 3404
d1ac91d8 3405 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3406 break;
3407 }
3408 case KVM_GET_XCRS: {
d1ac91d8 3409 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3410 r = -ENOMEM;
d1ac91d8 3411 if (!u.xcrs)
2d5b5a66
SY		 3412 break;
3413
d1ac91d8 3414 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3415
3416 r = -EFAULT;
d1ac91d8 3417 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3418 sizeof(struct kvm_xcrs)))
3419 break;
3420 r = 0;
3421 break;
3422 }
3423 case KVM_SET_XCRS: {
ff5c2c03 3424 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3425 if (IS_ERR(u.xcrs))
3426 return PTR_ERR(u.xcrs);
2d5b5a66 3427
d1ac91d8 3428 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3429 break;
3430 }
92a1f12d
JR		 3431 case KVM_SET_TSC_KHZ: {
3432 u32 user_tsc_khz;
3433
3434 r = -EINVAL;
92a1f12d
JR		 3435 user_tsc_khz = (u32)arg;
3436
3437 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3438 goto out;
3439
cc578287
ZA		 3440 if (user_tsc_khz == 0)
3441 user_tsc_khz = tsc_khz;
3442
3443 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3444
3445 r = 0;
3446 goto out;
3447 }
3448 case KVM_GET_TSC_KHZ: {
cc578287 3449 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3450 goto out;
3451 }
1c0b28c2
EM		 3452 case KVM_KVMCLOCK_CTRL: {
3453 r = kvm_set_guest_paused(vcpu);
3454 goto out;
3455 }
313a3dc7
CO		 3456 default:
3457 r = -EINVAL;
3458 }
3459out:
d1ac91d8 3460 kfree(u.buffer);
313a3dc7
CO		 3461 return r;
3462}
3463
5b1c1493
CO		 3464int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3465{
3466 return VM_FAULT_SIGBUS;
3467}
3468
1fe779f8
CO		 3469static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3470{
3471 int ret;
3472
3473 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3474 return -EINVAL;
1fe779f8
CO		 3475 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3476 return ret;
3477}
3478
b927a3ce
SY		 3479static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3480 u64 ident_addr)
3481{
3482 kvm->arch.ept_identity_map_addr = ident_addr;
3483 return 0;
3484}
3485
1fe779f8
CO		 3486static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3487 u32 kvm_nr_mmu_pages)
3488{
3489 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3490 return -EINVAL;
3491
79fac95e 3492 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3493
3494 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3495 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3496
79fac95e 3497 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3498 return 0;
3499}
3500
3501static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3502{
39de71ec 3503 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3504}
3505
1fe779f8
CO		 3506static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3507{
3508 int r;
3509
3510 r = 0;
3511 switch (chip->chip_id) {
3512 case KVM_IRQCHIP_PIC_MASTER:
3513 memcpy(&chip->chip.pic,
3514 &pic_irqchip(kvm)->pics[0],
3515 sizeof(struct kvm_pic_state));
3516 break;
3517 case KVM_IRQCHIP_PIC_SLAVE:
3518 memcpy(&chip->chip.pic,
3519 &pic_irqchip(kvm)->pics[1],
3520 sizeof(struct kvm_pic_state));
3521 break;
3522 case KVM_IRQCHIP_IOAPIC:
eba0226b 3523 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3524 break;
3525 default:
3526 r = -EINVAL;
3527 break;
3528 }
3529 return r;
3530}
3531
3532static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3533{
3534 int r;
3535
3536 r = 0;
3537 switch (chip->chip_id) {
3538 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3539 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3540 memcpy(&pic_irqchip(kvm)->pics[0],
3541 &chip->chip.pic,
3542 sizeof(struct kvm_pic_state));
f4f51050 3543 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3544 break;
3545 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3546 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3547 memcpy(&pic_irqchip(kvm)->pics[1],
3548 &chip->chip.pic,
3549 sizeof(struct kvm_pic_state));
f4f51050 3550 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3551 break;
3552 case KVM_IRQCHIP_IOAPIC:
eba0226b 3553 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3554 break;
3555 default:
3556 r = -EINVAL;
3557 break;
3558 }
3559 kvm_pic_update_irq(pic_irqchip(kvm));
3560 return r;
3561}
3562
e0f63cb9
SY		 3563static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3564{
3565 int r = 0;
3566
894a9c55 3567 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3568 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3569 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3570 return r;
3571}
3572
3573static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3574{
3575 int r = 0;
3576
894a9c55 3577 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3578 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3579 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3580 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3581 return r;
3582}
3583
3584static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3585{
3586 int r = 0;
3587
3588 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3589 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3590 sizeof(ps->channels));
3591 ps->flags = kvm->arch.vpit->pit_state.flags;
3592 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3593 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3594 return r;
3595}
3596
3597static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3598{
3599 int r = 0, start = 0;
3600 u32 prev_legacy, cur_legacy;
3601 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3602 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3603 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3604 if (!prev_legacy && cur_legacy)
3605 start = 1;
3606 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3607 sizeof(kvm->arch.vpit->pit_state.channels));
3608 kvm->arch.vpit->pit_state.flags = ps->flags;
3609 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3610 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3611 return r;
3612}
3613
52d939a0
MT		 3614static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3615 struct kvm_reinject_control *control)
3616{
3617 if (!kvm->arch.vpit)
3618 return -ENXIO;
894a9c55 3619 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3620 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3622 return 0;
3623}
3624
95d4c16c 3625/**
60c34612
TY		 3626 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3627 * @kvm: kvm instance
3628 * @log: slot id and address to which we copy the log
95d4c16c 3629 *
60c34612
TY		 3630 * We need to keep it in mind that VCPU threads can write to the bitmap
3631 * concurrently. So, to avoid losing data, we keep the following order for
3632 * each bit:
95d4c16c 3633 *
60c34612
TY		 3634 * 1. Take a snapshot of the bit and clear it if needed.
3635 * 2. Write protect the corresponding page.
3636 * 3. Flush TLB's if needed.
3637 * 4. Copy the snapshot to the userspace.
95d4c16c 3638 *
60c34612
TY		 3639 * Between 2 and 3, the guest may write to the page using the remaining TLB
3640 * entry. This is not a problem because the page will be reported dirty at
3641 * step 4 using the snapshot taken before and step 3 ensures that successive
3642 * writes will be logged for the next call.
5bb064dc 3643 */
60c34612 3644int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3645{
7850ac54 3646 int r;
5bb064dc 3647 struct kvm_memory_slot *memslot;
60c34612
TY		 3648 unsigned long n, i;
3649 unsigned long *dirty_bitmap;
3650 unsigned long *dirty_bitmap_buffer;
3651 bool is_dirty = false;
5bb064dc 3652
79fac95e 3653 mutex_lock(&kvm->slots_lock);
5bb064dc 3654
b050b015 3655 r = -EINVAL;
bbacc0c1 3656 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3657 goto out;
3658
28a37544 3659 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3660
3661 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3662 r = -ENOENT;
60c34612 3663 if (!dirty_bitmap)
b050b015
MT		 3664 goto out;
3665
87bf6e7d 3666 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3667
60c34612
TY		 3668 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3669 memset(dirty_bitmap_buffer, 0, n);
b050b015 3670
60c34612 3671 spin_lock(&kvm->mmu_lock);
b050b015 3672
60c34612
TY		 3673 for (i = 0; i < n / sizeof(long); i++) {
3674 unsigned long mask;
3675 gfn_t offset;
cdfca7b3 3676
60c34612
TY		 3677 if (!dirty_bitmap[i])
3678 continue;
b050b015 3679
60c34612 3680 is_dirty = true;
914ebccd 3681
60c34612
TY		 3682 mask = xchg(&dirty_bitmap[i], 0);
3683 dirty_bitmap_buffer[i] = mask;
edde99ce 3684
60c34612
TY		 3685 offset = i * BITS_PER_LONG;
3686 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3687 }
60c34612
TY		 3688
3689 spin_unlock(&kvm->mmu_lock);
3690
198c74f4
XG		 3691 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3692 lockdep_assert_held(&kvm->slots_lock);
3693
3694 /*
3695 * All the TLBs can be flushed out of mmu lock, see the comments in
3696 * kvm_mmu_slot_remove_write_access().
3697 */
3698 if (is_dirty)
3699 kvm_flush_remote_tlbs(kvm);
3700
60c34612
TY		 3701 r = -EFAULT;
3702 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3703 goto out;
b050b015 3704
5bb064dc
ZX		 3705 r = 0;
3706out:
79fac95e 3707 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3708 return r;
3709}
3710
aa2fbe6d
YZ		 3711int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3712 bool line_status)
23d43cf9
CD		 3713{
3714 if (!irqchip_in_kernel(kvm))
3715 return -ENXIO;
3716
3717 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3718 irq_event->irq, irq_event->level,
3719 line_status);
23d43cf9
CD		 3720 return 0;
3721}
3722
1fe779f8
CO		 3723long kvm_arch_vm_ioctl(struct file *filp,
3724 unsigned int ioctl, unsigned long arg)
3725{
3726 struct kvm *kvm = filp->private_data;
3727 void __user *argp = (void __user *)arg;
367e1319 3728 int r = -ENOTTY;
f0d66275
DH		 3729 /*
3730 * This union makes it completely explicit to gcc-3.x
3731 * that these two variables' stack usage should be
3732 * combined, not added together.
3733 */
3734 union {
3735 struct kvm_pit_state ps;
e9f42757 3736 struct kvm_pit_state2 ps2;
c5ff41ce 3737 struct kvm_pit_config pit_config;
f0d66275 3738 } u;
1fe779f8
CO		 3739
3740 switch (ioctl) {
3741 case KVM_SET_TSS_ADDR:
3742 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3743 break;
b927a3ce
SY		 3744 case KVM_SET_IDENTITY_MAP_ADDR: {
3745 u64 ident_addr;
3746
3747 r = -EFAULT;
3748 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3749 goto out;
3750 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3751 break;
3752 }
1fe779f8
CO		 3753 case KVM_SET_NR_MMU_PAGES:
3754 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3755 break;
3756 case KVM_GET_NR_MMU_PAGES:
3757 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3758 break;
3ddea128
MT		 3759 case KVM_CREATE_IRQCHIP: {
3760 struct kvm_pic *vpic;
3761
3762 mutex_lock(&kvm->lock);
3763 r = -EEXIST;
3764 if (kvm->arch.vpic)
3765 goto create_irqchip_unlock;
3e515705
AK		 3766 r = -EINVAL;
3767 if (atomic_read(&kvm->online_vcpus))
3768 goto create_irqchip_unlock;
1fe779f8 3769 r = -ENOMEM;
3ddea128
MT		 3770 vpic = kvm_create_pic(kvm);
3771 if (vpic) {
1fe779f8
CO		 3772 r = kvm_ioapic_init(kvm);
3773 if (r) {
175504cd 3774 mutex_lock(&kvm->slots_lock);
72bb2fcd 3775 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3776 &vpic->dev_master);
3777 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3778 &vpic->dev_slave);
3779 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3780 &vpic->dev_eclr);
175504cd 3781 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3782 kfree(vpic);
3783 goto create_irqchip_unlock;
1fe779f8
CO		 3784 }
3785 } else
3ddea128
MT		 3786 goto create_irqchip_unlock;
3787 smp_wmb();
3788 kvm->arch.vpic = vpic;
3789 smp_wmb();
399ec807
AK		 3790 r = kvm_setup_default_irq_routing(kvm);
3791 if (r) {
175504cd 3792 mutex_lock(&kvm->slots_lock);
3ddea128 3793 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3794 kvm_ioapic_destroy(kvm);
3795 kvm_destroy_pic(kvm);
3ddea128 3796 mutex_unlock(&kvm->irq_lock);
175504cd 3797 mutex_unlock(&kvm->slots_lock);
399ec807 3798 }
3ddea128
MT		 3799 create_irqchip_unlock:
3800 mutex_unlock(&kvm->lock);
1fe779f8 3801 break;
3ddea128 3802 }
7837699f 3803 case KVM_CREATE_PIT:
c5ff41ce
JK		 3804 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3805 goto create_pit;
3806 case KVM_CREATE_PIT2:
3807 r = -EFAULT;
3808 if (copy_from_user(&u.pit_config, argp,
3809 sizeof(struct kvm_pit_config)))
3810 goto out;
3811 create_pit:
79fac95e 3812 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3813 r = -EEXIST;
3814 if (kvm->arch.vpit)
3815 goto create_pit_unlock;
7837699f 3816 r = -ENOMEM;
c5ff41ce 3817 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3818 if (kvm->arch.vpit)
3819 r = 0;
269e05e4 3820 create_pit_unlock:
79fac95e 3821 mutex_unlock(&kvm->slots_lock);
7837699f 3822 break;
1fe779f8
CO		 3823 case KVM_GET_IRQCHIP: {
3824 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3825 struct kvm_irqchip *chip;
1fe779f8 3826
ff5c2c03
SL		 3827 chip = memdup_user(argp, sizeof(*chip));
3828 if (IS_ERR(chip)) {
3829 r = PTR_ERR(chip);
1fe779f8 3830 goto out;
ff5c2c03
SL		 3831 }
3832
1fe779f8
CO		 3833 r = -ENXIO;
3834 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3835 goto get_irqchip_out;
3836 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3837 if (r)
f0d66275 3838 goto get_irqchip_out;
1fe779f8 3839 r = -EFAULT;
f0d66275
DH		 3840 if (copy_to_user(argp, chip, sizeof *chip))
3841 goto get_irqchip_out;
1fe779f8 3842 r = 0;
f0d66275
DH		 3843 get_irqchip_out:
3844 kfree(chip);
1fe779f8
CO		 3845 break;
3846 }
3847 case KVM_SET_IRQCHIP: {
3848 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3849 struct kvm_irqchip *chip;
1fe779f8 3850
ff5c2c03
SL		 3851 chip = memdup_user(argp, sizeof(*chip));
3852 if (IS_ERR(chip)) {
3853 r = PTR_ERR(chip);
1fe779f8 3854 goto out;
ff5c2c03
SL		 3855 }
3856
1fe779f8
CO		 3857 r = -ENXIO;
3858 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3859 goto set_irqchip_out;
3860 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3861 if (r)
f0d66275 3862 goto set_irqchip_out;
1fe779f8 3863 r = 0;
f0d66275
DH		 3864 set_irqchip_out:
3865 kfree(chip);
1fe779f8
CO		 3866 break;
3867 }
e0f63cb9 3868 case KVM_GET_PIT: {
e0f63cb9 3869 r = -EFAULT;
f0d66275 3870 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3871 goto out;
3872 r = -ENXIO;
3873 if (!kvm->arch.vpit)
3874 goto out;
f0d66275 3875 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3876 if (r)
3877 goto out;
3878 r = -EFAULT;
f0d66275 3879 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3880 goto out;
3881 r = 0;
3882 break;
3883 }
3884 case KVM_SET_PIT: {
e0f63cb9 3885 r = -EFAULT;
f0d66275 3886 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3887 goto out;
3888 r = -ENXIO;
3889 if (!kvm->arch.vpit)
3890 goto out;
f0d66275 3891 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3892 break;
3893 }
e9f42757
BK		 3894 case KVM_GET_PIT2: {
3895 r = -ENXIO;
3896 if (!kvm->arch.vpit)
3897 goto out;
3898 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3899 if (r)
3900 goto out;
3901 r = -EFAULT;
3902 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3903 goto out;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_SET_PIT2: {
3908 r = -EFAULT;
3909 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3910 goto out;
3911 r = -ENXIO;
3912 if (!kvm->arch.vpit)
3913 goto out;
3914 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3915 break;
3916 }
52d939a0
MT		 3917 case KVM_REINJECT_CONTROL: {
3918 struct kvm_reinject_control control;
3919 r = -EFAULT;
3920 if (copy_from_user(&control, argp, sizeof(control)))
3921 goto out;
3922 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3923 break;
3924 }
ffde22ac
ES		 3925 case KVM_XEN_HVM_CONFIG: {
3926 r = -EFAULT;
3927 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3928 sizeof(struct kvm_xen_hvm_config)))
3929 goto out;
3930 r = -EINVAL;
3931 if (kvm->arch.xen_hvm_config.flags)
3932 goto out;
3933 r = 0;
3934 break;
3935 }
afbcf7ab 3936 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3937 struct kvm_clock_data user_ns;
3938 u64 now_ns;
3939 s64 delta;
3940
3941 r = -EFAULT;
3942 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3943 goto out;
3944
3945 r = -EINVAL;
3946 if (user_ns.flags)
3947 goto out;
3948
3949 r = 0;
395c6b0a 3950 local_irq_disable();
759379dd 3951 now_ns = get_kernel_ns();
afbcf7ab 3952 delta = user_ns.clock - now_ns;
395c6b0a 3953 local_irq_enable();
afbcf7ab 3954 kvm->arch.kvmclock_offset = delta;
2e762ff7 3955 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3956 break;
3957 }
3958 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3959 struct kvm_clock_data user_ns;
3960 u64 now_ns;
3961
395c6b0a 3962 local_irq_disable();
759379dd 3963 now_ns = get_kernel_ns();
afbcf7ab 3964 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3965 local_irq_enable();
afbcf7ab 3966 user_ns.flags = 0;
97e69aa6 3967 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3968
3969 r = -EFAULT;
3970 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3971 goto out;
3972 r = 0;
3973 break;
3974 }
3975
1fe779f8
CO		 3976 default:
3977 ;
3978 }
3979out:
3980 return r;
3981}
3982
a16b043c 3983static void kvm_init_msr_list(void)
043405e1
CO		 3984{
3985 u32 dummy[2];
3986 unsigned i, j;
3987
e3267cbb
GC		 3988 /* skip the first msrs in the list. KVM-specific */
3989 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3990 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3991 continue;
93c4adc7
PB		 3992
3993 /*
3994 * Even MSRs that are valid in the host may not be exposed
3995 * to the guests in some cases. We could work around this
3996 * in VMX with the generic MSR save/load machinery, but it
3997 * is not really worthwhile since it will really only
3998 * happen with nested virtualization.
3999 */
4000 switch (msrs_to_save[i]) {
4001 case MSR_IA32_BNDCFGS:
4002 if (!kvm_x86_ops->mpx_supported())
4003 continue;
4004 break;
4005 default:
4006 break;
4007 }
4008
043405e1
CO		 4009 if (j < i)
4010 msrs_to_save[j] = msrs_to_save[i];
4011 j++;
4012 }
4013 num_msrs_to_save = j;
4014}
4015
bda9020e
MT		 4016static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4017 const void *v)
bbd9b64e 4018{
70252a10
AK		 4019 int handled = 0;
4020 int n;
4021
4022 do {
4023 n = min(len, 8);
4024 if (!(vcpu->arch.apic &&
4025 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4026 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4027 break;
4028 handled += n;
4029 addr += n;
4030 len -= n;
4031 v += n;
4032 } while (len);
bbd9b64e 4033
70252a10 4034 return handled;
bbd9b64e
CO		 4035}
4036
bda9020e 4037static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4038{
70252a10
AK		 4039 int handled = 0;
4040 int n;
4041
4042 do {
4043 n = min(len, 8);
4044 if (!(vcpu->arch.apic &&
4045 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4046 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4047 break;
4048 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4049 handled += n;
4050 addr += n;
4051 len -= n;
4052 v += n;
4053 } while (len);
bbd9b64e 4054
70252a10 4055 return handled;
bbd9b64e
CO		 4056}
4057
2dafc6c2
GN		 4058static void kvm_set_segment(struct kvm_vcpu *vcpu,
4059 struct kvm_segment *var, int seg)
4060{
4061 kvm_x86_ops->set_segment(vcpu, var, seg);
4062}
4063
4064void kvm_get_segment(struct kvm_vcpu *vcpu,
4065 struct kvm_segment *var, int seg)
4066{
4067 kvm_x86_ops->get_segment(vcpu, var, seg);
4068}
4069
54987b7a
PB		 4070gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4071 struct x86_exception *exception)
02f59dc9
JR		 4072{
4073 gpa_t t_gpa;
02f59dc9
JR		 4074
4075 BUG_ON(!mmu_is_nested(vcpu));
4076
4077 /* NPT walks are always user-walks */
4078 access |= PFERR_USER_MASK;
54987b7a 4079 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4080
4081 return t_gpa;
4082}
4083
ab9ae313
AK		 4084gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4085 struct x86_exception *exception)
1871c602
GN		 4086{
4087 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4088 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4089}
4090
ab9ae313
AK		 4091 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4092 struct x86_exception *exception)
1871c602
GN		 4093{
4094 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4095 access |= PFERR_FETCH_MASK;
ab9ae313 4096 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4097}
4098
ab9ae313
AK		 4099gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4100 struct x86_exception *exception)
1871c602
GN		 4101{
4102 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4103 access |= PFERR_WRITE_MASK;
ab9ae313 4104 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4105}
4106
4107/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4108gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4109 struct x86_exception *exception)
1871c602 4110{
ab9ae313 4111 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4112}
4113
4114static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4115 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4116 struct x86_exception *exception)
bbd9b64e
CO		 4117{
4118 void *data = val;
10589a46 4119 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4120
4121 while (bytes) {
14dfe855 4122 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4123 exception);
bbd9b64e 4124 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4125 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4126 int ret;
4127
bcc55cba 4128 if (gpa == UNMAPPED_GVA)
ab9ae313 4129 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4130 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4131 offset, toread);
10589a46 4132 if (ret < 0) {
c3cd7ffa 4133 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4134 goto out;
4135 }
bbd9b64e 4136
77c2002e
IE		 4137 bytes -= toread;
4138 data += toread;
4139 addr += toread;
bbd9b64e 4140 }
10589a46 4141out:
10589a46 4142 return r;
bbd9b64e 4143}
77c2002e 4144
1871c602 4145/* used for instruction fetching */
0f65dd70
AK		 4146static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4147 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4148 struct x86_exception *exception)
1871c602 4149{
0f65dd70 4150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4151 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4152 unsigned offset;
4153 int ret;
0f65dd70 4154
44583cba
PB		 4155 /* Inline kvm_read_guest_virt_helper for speed. */
4156 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4157 exception);
4158 if (unlikely(gpa == UNMAPPED_GVA))
4159 return X86EMUL_PROPAGATE_FAULT;
4160
4161 offset = addr & (PAGE_SIZE-1);
4162 if (WARN_ON(offset + bytes > PAGE_SIZE))
4163 bytes = (unsigned)PAGE_SIZE - offset;
4164 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4165 offset, bytes);
4166 if (unlikely(ret < 0))
4167 return X86EMUL_IO_NEEDED;
4168
4169 return X86EMUL_CONTINUE;
1871c602
GN		 4170}
4171
064aea77 4172int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4173 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4174 struct x86_exception *exception)
1871c602 4175{
0f65dd70 4176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4178
1871c602 4179 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4180 exception);
1871c602 4181}
064aea77 4182EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4183
0f65dd70
AK		 4184static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4185 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4186 struct x86_exception *exception)
1871c602 4187{
0f65dd70 4188 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4189 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4190}
4191
6a4d7550 4192int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4193 gva_t addr, void *val,
2dafc6c2 4194 unsigned int bytes,
bcc55cba 4195 struct x86_exception *exception)
77c2002e 4196{
0f65dd70 4197 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4198 void *data = val;
4199 int r = X86EMUL_CONTINUE;
4200
4201 while (bytes) {
14dfe855
JR		 4202 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4203 PFERR_WRITE_MASK,
ab9ae313 4204 exception);
77c2002e
IE		 4205 unsigned offset = addr & (PAGE_SIZE-1);
4206 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4207 int ret;
4208
bcc55cba 4209 if (gpa == UNMAPPED_GVA)
ab9ae313 4210 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4211 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4212 if (ret < 0) {
c3cd7ffa 4213 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4214 goto out;
4215 }
4216
4217 bytes -= towrite;
4218 data += towrite;
4219 addr += towrite;
4220 }
4221out:
4222 return r;
4223}
6a4d7550 4224EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4225
af7cc7d1
XG		 4226static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4227 gpa_t *gpa, struct x86_exception *exception,
4228 bool write)
4229{
97d64b78
AK		 4230 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4231 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4232
97d64b78 4233 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4234 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4235 vcpu->arch.access, access)) {
bebb106a
XG		 4236 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4237 (gva & (PAGE_SIZE - 1));
4f022648 4238 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4239 return 1;
4240 }
4241
af7cc7d1
XG		 4242 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4243
4244 if (*gpa == UNMAPPED_GVA)
4245 return -1;
4246
4247 /* For APIC access vmexit */
4248 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4249 return 1;
4250
4f022648
XG		 4251 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4252 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4253 return 1;
4f022648 4254 }
bebb106a 4255
af7cc7d1
XG		 4256 return 0;
4257}
4258
3200f405 4259int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4260 const void *val, int bytes)
bbd9b64e
CO		 4261{
4262 int ret;
4263
4264 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4265 if (ret < 0)
bbd9b64e 4266 return 0;
f57f2ef5 4267 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4268 return 1;
4269}
4270
77d197b2
XG		 4271struct read_write_emulator_ops {
4272 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4273 int bytes);
4274 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4275 void *val, int bytes);
4276 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4277 int bytes, void *val);
4278 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4279 void *val, int bytes);
4280 bool write;
4281};
4282
4283static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4284{
4285 if (vcpu->mmio_read_completed) {
77d197b2 4286 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4287 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4288 vcpu->mmio_read_completed = 0;
4289 return 1;
4290 }
4291
4292 return 0;
4293}
4294
4295static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4296 void *val, int bytes)
4297{
4298 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4299}
4300
4301static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4302 void *val, int bytes)
4303{
4304 return emulator_write_phys(vcpu, gpa, val, bytes);
4305}
4306
4307static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4308{
4309 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4310 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4311}
4312
4313static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4314 void *val, int bytes)
4315{
4316 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4317 return X86EMUL_IO_NEEDED;
4318}
4319
4320static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4321 void *val, int bytes)
4322{
f78146b0
AK		 4323 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4324
87da7e66 4325 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4326 return X86EMUL_CONTINUE;
4327}
4328
0fbe9b0b 4329static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4330 .read_write_prepare = read_prepare,
4331 .read_write_emulate = read_emulate,
4332 .read_write_mmio = vcpu_mmio_read,
4333 .read_write_exit_mmio = read_exit_mmio,
4334};
4335
0fbe9b0b 4336static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4337 .read_write_emulate = write_emulate,
4338 .read_write_mmio = write_mmio,
4339 .read_write_exit_mmio = write_exit_mmio,
4340 .write = true,
4341};
4342
22388a3c
XG		 4343static int emulator_read_write_onepage(unsigned long addr, void *val,
4344 unsigned int bytes,
4345 struct x86_exception *exception,
4346 struct kvm_vcpu *vcpu,
0fbe9b0b 4347 const struct read_write_emulator_ops *ops)
bbd9b64e 4348{
af7cc7d1
XG		 4349 gpa_t gpa;
4350 int handled, ret;
22388a3c 4351 bool write = ops->write;
f78146b0 4352 struct kvm_mmio_fragment *frag;
10589a46 4353
22388a3c 4354 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4355
af7cc7d1 4356 if (ret < 0)
bbd9b64e 4357 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4358
4359 /* For APIC access vmexit */
af7cc7d1 4360 if (ret)
bbd9b64e
CO		 4361 goto mmio;
4362
22388a3c 4363 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4364 return X86EMUL_CONTINUE;
4365
4366mmio:
4367 /*
4368 * Is this MMIO handled locally?
4369 */
22388a3c 4370 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4371 if (handled == bytes)
bbd9b64e 4372 return X86EMUL_CONTINUE;
bbd9b64e 4373
70252a10
AK		 4374 gpa += handled;
4375 bytes -= handled;
4376 val += handled;
4377
87da7e66
XG		 4378 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4379 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4380 frag->gpa = gpa;
4381 frag->data = val;
4382 frag->len = bytes;
f78146b0 4383 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4384}
4385
22388a3c
XG		 4386int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4387 void *val, unsigned int bytes,
4388 struct x86_exception *exception,
0fbe9b0b 4389 const struct read_write_emulator_ops *ops)
bbd9b64e 4390{
0f65dd70 4391 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4392 gpa_t gpa;
4393 int rc;
4394
4395 if (ops->read_write_prepare &&
4396 ops->read_write_prepare(vcpu, val, bytes))
4397 return X86EMUL_CONTINUE;
4398
4399 vcpu->mmio_nr_fragments = 0;
0f65dd70 4400
bbd9b64e
CO		 4401 /* Crossing a page boundary? */
4402 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4403 int now;
bbd9b64e
CO		 4404
4405 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4406 rc = emulator_read_write_onepage(addr, val, now, exception,
4407 vcpu, ops);
4408
bbd9b64e
CO		 4409 if (rc != X86EMUL_CONTINUE)
4410 return rc;
4411 addr += now;
4412 val += now;
4413 bytes -= now;
4414 }
22388a3c 4415
f78146b0
AK		 4416 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4417 vcpu, ops);
4418 if (rc != X86EMUL_CONTINUE)
4419 return rc;
4420
4421 if (!vcpu->mmio_nr_fragments)
4422 return rc;
4423
4424 gpa = vcpu->mmio_fragments[0].gpa;
4425
4426 vcpu->mmio_needed = 1;
4427 vcpu->mmio_cur_fragment = 0;
4428
87da7e66 4429 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4430 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4431 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4432 vcpu->run->mmio.phys_addr = gpa;
4433
4434 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4435}
4436
4437static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4438 unsigned long addr,
4439 void *val,
4440 unsigned int bytes,
4441 struct x86_exception *exception)
4442{
4443 return emulator_read_write(ctxt, addr, val, bytes,
4444 exception, &read_emultor);
4445}
4446
4447int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4448 unsigned long addr,
4449 const void *val,
4450 unsigned int bytes,
4451 struct x86_exception *exception)
4452{
4453 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4454 exception, &write_emultor);
bbd9b64e 4455}
bbd9b64e 4456
daea3e73
AK		 4457#define CMPXCHG_TYPE(t, ptr, old, new) \
4458 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4459
4460#ifdef CONFIG_X86_64
4461# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4462#else
4463# define CMPXCHG64(ptr, old, new) \
9749a6c0 4464 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4465#endif
4466
0f65dd70
AK		 4467static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4468 unsigned long addr,
bbd9b64e
CO		 4469 const void *old,
4470 const void *new,
4471 unsigned int bytes,
0f65dd70 4472 struct x86_exception *exception)
bbd9b64e 4473{
0f65dd70 4474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4475 gpa_t gpa;
4476 struct page *page;
4477 char *kaddr;
4478 bool exchanged;
2bacc55c 4479
daea3e73
AK		 4480 /* guests cmpxchg8b have to be emulated atomically */
4481 if (bytes > 8 || (bytes & (bytes - 1)))
4482 goto emul_write;
10589a46 4483
daea3e73 4484 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4485
daea3e73
AK		 4486 if (gpa == UNMAPPED_GVA ||
4487 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4488 goto emul_write;
2bacc55c 4489
daea3e73
AK		 4490 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4491 goto emul_write;
72dc67a6 4492
daea3e73 4493 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4494 if (is_error_page(page))
c19b8bd6 4495 goto emul_write;
72dc67a6 4496
8fd75e12 4497 kaddr = kmap_atomic(page);
daea3e73
AK		 4498 kaddr += offset_in_page(gpa);
4499 switch (bytes) {
4500 case 1:
4501 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4502 break;
4503 case 2:
4504 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4505 break;
4506 case 4:
4507 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4508 break;
4509 case 8:
4510 exchanged = CMPXCHG64(kaddr, old, new);
4511 break;
4512 default:
4513 BUG();
2bacc55c 4514 }
8fd75e12 4515 kunmap_atomic(kaddr);
daea3e73
AK		 4516 kvm_release_page_dirty(page);
4517
4518 if (!exchanged)
4519 return X86EMUL_CMPXCHG_FAILED;
4520
d3714010 4521 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4522 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4523
4524 return X86EMUL_CONTINUE;
4a5f48f6 4525
3200f405 4526emul_write:
daea3e73 4527 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4528
0f65dd70 4529 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4530}
4531
cf8f70bf
GN		 4532static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4533{
4534 /* TODO: String I/O for in kernel device */
4535 int r;
4536
4537 if (vcpu->arch.pio.in)
4538 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4539 vcpu->arch.pio.size, pd);
4540 else
4541 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4542 vcpu->arch.pio.port, vcpu->arch.pio.size,
4543 pd);
4544 return r;
4545}
4546
6f6fbe98
XG		 4547static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4548 unsigned short port, void *val,
4549 unsigned int count, bool in)
cf8f70bf 4550{
cf8f70bf 4551 vcpu->arch.pio.port = port;
6f6fbe98 4552 vcpu->arch.pio.in = in;
7972995b 4553 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4554 vcpu->arch.pio.size = size;
4555
4556 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4557 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4558 return 1;
4559 }
4560
4561 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4562 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4563 vcpu->run->io.size = size;
4564 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4565 vcpu->run->io.count = count;
4566 vcpu->run->io.port = port;
4567
4568 return 0;
4569}
4570
6f6fbe98
XG		 4571static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4572 int size, unsigned short port, void *val,
4573 unsigned int count)
cf8f70bf 4574{
ca1d4a9e 4575 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4576 int ret;
ca1d4a9e 4577
6f6fbe98
XG		 4578 if (vcpu->arch.pio.count)
4579 goto data_avail;
cf8f70bf 4580
6f6fbe98
XG		 4581 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4582 if (ret) {
4583data_avail:
4584 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4585 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4586 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4587 return 1;
4588 }
4589
cf8f70bf
GN		 4590 return 0;
4591}
4592
6f6fbe98
XG		 4593static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4594 int size, unsigned short port,
4595 const void *val, unsigned int count)
4596{
4597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4598
4599 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4600 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4601 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4602}
4603
bbd9b64e
CO		 4604static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4605{
4606 return kvm_x86_ops->get_segment_base(vcpu, seg);
4607}
4608
3cb16fe7 4609static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4610{
3cb16fe7 4611 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4612}
4613
f5f48ee1
SY		 4614int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4615{
4616 if (!need_emulate_wbinvd(vcpu))
4617 return X86EMUL_CONTINUE;
4618
4619 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4620 int cpu = get_cpu();
4621
4622 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4623 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4624 wbinvd_ipi, NULL, 1);
2eec7343 4625 put_cpu();
f5f48ee1 4626 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4627 } else
4628 wbinvd();
f5f48ee1
SY		 4629 return X86EMUL_CONTINUE;
4630}
4631EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4632
bcaf5cc5
AK		 4633static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4634{
4635 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4636}
4637
717746e3 4638int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4639{
717746e3 4640 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4641}
4642
717746e3 4643int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4644{
338dbc97 4645
717746e3 4646 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4647}
4648
52a46617 4649static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4650{
52a46617 4651 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4652}
4653
717746e3 4654static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4655{
717746e3 4656 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4657 unsigned long value;
4658
4659 switch (cr) {
4660 case 0:
4661 value = kvm_read_cr0(vcpu);
4662 break;
4663 case 2:
4664 value = vcpu->arch.cr2;
4665 break;
4666 case 3:
9f8fe504 4667 value = kvm_read_cr3(vcpu);
52a46617
GN		 4668 break;
4669 case 4:
4670 value = kvm_read_cr4(vcpu);
4671 break;
4672 case 8:
4673 value = kvm_get_cr8(vcpu);
4674 break;
4675 default:
a737f256 4676 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4677 return 0;
4678 }
4679
4680 return value;
4681}
4682
717746e3 4683static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4684{
717746e3 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4686 int res = 0;
4687
52a46617
GN		 4688 switch (cr) {
4689 case 0:
49a9b07e 4690 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4691 break;
4692 case 2:
4693 vcpu->arch.cr2 = val;
4694 break;
4695 case 3:
2390218b 4696 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4697 break;
4698 case 4:
a83b29c6 4699 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4700 break;
4701 case 8:
eea1cff9 4702 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4703 break;
4704 default:
a737f256 4705 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4706 res = -1;
52a46617 4707 }
0f12244f
GN		 4708
4709 return res;
52a46617
GN		 4710}
4711
717746e3 4712static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4713{
717746e3 4714 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4715}
4716
4bff1e86 4717static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4718{
4bff1e86 4719 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4720}
4721
4bff1e86 4722static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4723{
4bff1e86 4724 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4725}
4726
1ac9d0cf
AK		 4727static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4728{
4729 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4730}
4731
4732static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4733{
4734 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4735}
4736
4bff1e86
AK		 4737static unsigned long emulator_get_cached_segment_base(
4738 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4739{
4bff1e86 4740 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4741}
4742
1aa36616
AK		 4743static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4744 struct desc_struct *desc, u32 *base3,
4745 int seg)
2dafc6c2
GN		 4746{
4747 struct kvm_segment var;
4748
4bff1e86 4749 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4750 *selector = var.selector;
2dafc6c2 4751
378a8b09
GN		 4752 if (var.unusable) {
4753 memset(desc, 0, sizeof(*desc));
2dafc6c2 4754 return false;
378a8b09 4755 }
2dafc6c2
GN		 4756
4757 if (var.g)
4758 var.limit >>= 12;
4759 set_desc_limit(desc, var.limit);
4760 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4761#ifdef CONFIG_X86_64
4762 if (base3)
4763 *base3 = var.base >> 32;
4764#endif
2dafc6c2
GN		 4765 desc->type = var.type;
4766 desc->s = var.s;
4767 desc->dpl = var.dpl;
4768 desc->p = var.present;
4769 desc->avl = var.avl;
4770 desc->l = var.l;
4771 desc->d = var.db;
4772 desc->g = var.g;
4773
4774 return true;
4775}
4776
1aa36616
AK		 4777static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4778 struct desc_struct *desc, u32 base3,
4779 int seg)
2dafc6c2 4780{
4bff1e86 4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4782 struct kvm_segment var;
4783
1aa36616 4784 var.selector = selector;
2dafc6c2 4785 var.base = get_desc_base(desc);
5601d05b
GN		 4786#ifdef CONFIG_X86_64
4787 var.base |= ((u64)base3) << 32;
4788#endif
2dafc6c2
GN		 4789 var.limit = get_desc_limit(desc);
4790 if (desc->g)
4791 var.limit = (var.limit << 12) | 0xfff;
4792 var.type = desc->type;
2dafc6c2
GN		 4793 var.dpl = desc->dpl;
4794 var.db = desc->d;
4795 var.s = desc->s;
4796 var.l = desc->l;
4797 var.g = desc->g;
4798 var.avl = desc->avl;
4799 var.present = desc->p;
4800 var.unusable = !var.present;
4801 var.padding = 0;
4802
4803 kvm_set_segment(vcpu, &var, seg);
4804 return;
4805}
4806
717746e3
AK		 4807static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4808 u32 msr_index, u64 *pdata)
4809{
4810 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4811}
4812
4813static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4814 u32 msr_index, u64 data)
4815{
8fe8ab46
WA		 4816 struct msr_data msr;
4817
4818 msr.data = data;
4819 msr.index = msr_index;
4820 msr.host_initiated = false;
4821 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4822}
4823
67f4d428
NA		 4824static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4825 u32 pmc)
4826{
4827 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4828}
4829
222d21aa
AK		 4830static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4831 u32 pmc, u64 *pdata)
4832{
4833 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4834}
4835
6c3287f7
AK		 4836static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4837{
4838 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4839}
4840
5037f6f3
AK		 4841static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4842{
4843 preempt_disable();
5197b808 4844 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4845 /*
4846 * CR0.TS may reference the host fpu state, not the guest fpu state,
4847 * so it may be clear at this point.
4848 */
4849 clts();
4850}
4851
4852static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4853{
4854 preempt_enable();
4855}
4856
2953538e 4857static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4858 struct x86_instruction_info *info,
c4f035c6
AK		 4859 enum x86_intercept_stage stage)
4860{
2953538e 4861 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4862}
4863
0017f93a 4864static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4865 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4866{
0017f93a 4867 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4868}
4869
dd856efa
AK		 4870static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4871{
4872 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4873}
4874
4875static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4876{
4877 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4878}
4879
0225fb50 4880static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4881 .read_gpr = emulator_read_gpr,
4882 .write_gpr = emulator_write_gpr,
1871c602 4883 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4884 .write_std = kvm_write_guest_virt_system,
1871c602 4885 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4886 .read_emulated = emulator_read_emulated,
4887 .write_emulated = emulator_write_emulated,
4888 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4889 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4890 .pio_in_emulated = emulator_pio_in_emulated,
4891 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4892 .get_segment = emulator_get_segment,
4893 .set_segment = emulator_set_segment,
5951c442 4894 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4895 .get_gdt = emulator_get_gdt,
160ce1f1 4896 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4897 .set_gdt = emulator_set_gdt,
4898 .set_idt = emulator_set_idt,
52a46617
GN		 4899 .get_cr = emulator_get_cr,
4900 .set_cr = emulator_set_cr,
9c537244 4901 .cpl = emulator_get_cpl,
35aa5375
GN		 4902 .get_dr = emulator_get_dr,
4903 .set_dr = emulator_set_dr,
717746e3
AK		 4904 .set_msr = emulator_set_msr,
4905 .get_msr = emulator_get_msr,
67f4d428 4906 .check_pmc = emulator_check_pmc,
222d21aa 4907 .read_pmc = emulator_read_pmc,
6c3287f7 4908 .halt = emulator_halt,
bcaf5cc5 4909 .wbinvd = emulator_wbinvd,
d6aa1000 4910 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4911 .get_fpu = emulator_get_fpu,
4912 .put_fpu = emulator_put_fpu,
c4f035c6 4913 .intercept = emulator_intercept,
bdb42f5a 4914 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4915};
4916
95cb2295
GN		 4917static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4918{
37ccdcbe 4919 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4920 /*
4921 * an sti; sti; sequence only disable interrupts for the first
4922 * instruction. So, if the last instruction, be it emulated or
4923 * not, left the system with the INT_STI flag enabled, it
4924 * means that the last instruction is an sti. We should not
4925 * leave the flag on in this case. The same goes for mov ss
4926 */
37ccdcbe
PB		 4927 if (int_shadow & mask)
4928 mask = 0;
6addfc42 4929 if (unlikely(int_shadow || mask)) {
95cb2295 4930 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4931 if (!mask)
4932 kvm_make_request(KVM_REQ_EVENT, vcpu);
4933 }
95cb2295
GN		 4934}
4935
ef54bcfe 4936static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4937{
4938 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4939 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4940 return kvm_propagate_fault(vcpu, &ctxt->exception);
4941
4942 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4943 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4944 ctxt->exception.error_code);
54b8486f 4945 else
da9cb575 4946 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4947 return false;
54b8486f
GN		 4948}
4949
8ec4722d
MG		 4950static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4951{
adf52235 4952 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4953 int cs_db, cs_l;
4954
8ec4722d
MG		 4955 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4956
adf52235
TY		 4957 ctxt->eflags = kvm_get_rflags(vcpu);
4958 ctxt->eip = kvm_rip_read(vcpu);
4959 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4960 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4961 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4962 cs_db ? X86EMUL_MODE_PROT32 :
4963 X86EMUL_MODE_PROT16;
4964 ctxt->guest_mode = is_guest_mode(vcpu);
4965
dd856efa 4966 init_decode_cache(ctxt);
7ae441ea 4967 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4968}
4969
71f9833b 4970int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4971{
9d74191a 4972 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4973 int ret;
4974
4975 init_emulate_ctxt(vcpu);
4976
9dac77fa
AK		 4977 ctxt->op_bytes = 2;
4978 ctxt->ad_bytes = 2;
4979 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4980 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4981
4982 if (ret != X86EMUL_CONTINUE)
4983 return EMULATE_FAIL;
4984
9dac77fa 4985 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4986 kvm_rip_write(vcpu, ctxt->eip);
4987 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4988
4989 if (irq == NMI_VECTOR)
7460fb4a 4990 vcpu->arch.nmi_pending = 0;
63995653
MG		 4991 else
4992 vcpu->arch.interrupt.pending = false;
4993
4994 return EMULATE_DONE;
4995}
4996EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4997
6d77dbfc
GN		 4998static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4999{
fc3a9157
JR		 5000 int r = EMULATE_DONE;
5001
6d77dbfc
GN		 5002 ++vcpu->stat.insn_emulation_fail;
5003 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5004 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5005 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5006 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5007 vcpu->run->internal.ndata = 0;
5008 r = EMULATE_FAIL;
5009 }
6d77dbfc 5010 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5011
5012 return r;
6d77dbfc
GN		 5013}
5014
93c05d3e 5015static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5016 bool write_fault_to_shadow_pgtable,
5017 int emulation_type)
a6f177ef 5018{
95b3cf69 5019 gpa_t gpa = cr2;
8e3d9d06 5020 pfn_t pfn;
a6f177ef 5021
991eebf9
GN		 5022 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5023 return false;
5024
95b3cf69
XG		 5025 if (!vcpu->arch.mmu.direct_map) {
5026 /*
5027 * Write permission should be allowed since only
5028 * write access need to be emulated.
5029 */
5030 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5031
95b3cf69
XG		 5032 /*
5033 * If the mapping is invalid in guest, let cpu retry
5034 * it to generate fault.
5035 */
5036 if (gpa == UNMAPPED_GVA)
5037 return true;
5038 }
a6f177ef 5039
8e3d9d06
XG		 5040 /*
5041 * Do not retry the unhandleable instruction if it faults on the
5042 * readonly host memory, otherwise it will goto a infinite loop:
5043 * retry instruction -> write #PF -> emulation fail -> retry
5044 * instruction -> ...
5045 */
5046 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5047
5048 /*
5049 * If the instruction failed on the error pfn, it can not be fixed,
5050 * report the error to userspace.
5051 */
5052 if (is_error_noslot_pfn(pfn))
5053 return false;
5054
5055 kvm_release_pfn_clean(pfn);
5056
5057 /* The instructions are well-emulated on direct mmu. */
5058 if (vcpu->arch.mmu.direct_map) {
5059 unsigned int indirect_shadow_pages;
5060
5061 spin_lock(&vcpu->kvm->mmu_lock);
5062 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5063 spin_unlock(&vcpu->kvm->mmu_lock);
5064
5065 if (indirect_shadow_pages)
5066 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5067
a6f177ef 5068 return true;
8e3d9d06 5069 }
a6f177ef 5070
95b3cf69
XG		 5071 /*
5072 * if emulation was due to access to shadowed page table
5073 * and it failed try to unshadow page and re-enter the
5074 * guest to let CPU execute the instruction.
5075 */
5076 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5077
5078 /*
5079 * If the access faults on its page table, it can not
5080 * be fixed by unprotecting shadow page and it should
5081 * be reported to userspace.
5082 */
5083 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5084}
5085
1cb3f3ae
XG		 5086static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5087 unsigned long cr2, int emulation_type)
5088{
5089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5090 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5091
5092 last_retry_eip = vcpu->arch.last_retry_eip;
5093 last_retry_addr = vcpu->arch.last_retry_addr;
5094
5095 /*
5096 * If the emulation is caused by #PF and it is non-page_table
5097 * writing instruction, it means the VM-EXIT is caused by shadow
5098 * page protected, we can zap the shadow page and retry this
5099 * instruction directly.
5100 *
5101 * Note: if the guest uses a non-page-table modifying instruction
5102 * on the PDE that points to the instruction, then we will unmap
5103 * the instruction and go to an infinite loop. So, we cache the
5104 * last retried eip and the last fault address, if we meet the eip
5105 * and the address again, we can break out of the potential infinite
5106 * loop.
5107 */
5108 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5109
5110 if (!(emulation_type & EMULTYPE_RETRY))
5111 return false;
5112
5113 if (x86_page_table_writing_insn(ctxt))
5114 return false;
5115
5116 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5117 return false;
5118
5119 vcpu->arch.last_retry_eip = ctxt->eip;
5120 vcpu->arch.last_retry_addr = cr2;
5121
5122 if (!vcpu->arch.mmu.direct_map)
5123 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5124
22368028 5125 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5126
5127 return true;
5128}
5129
716d51ab
GN		 5130static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5131static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5132
4a1e10d5
PB		 5133static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5134 unsigned long *db)
5135{
5136 u32 dr6 = 0;
5137 int i;
5138 u32 enable, rwlen;
5139
5140 enable = dr7;
5141 rwlen = dr7 >> 16;
5142 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5143 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5144 dr6 |= (1 << i);
5145 return dr6;
5146}
5147
6addfc42 5148static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5149{
5150 struct kvm_run *kvm_run = vcpu->run;
5151
5152 /*
6addfc42
PB		 5153 * rflags is the old, "raw" value of the flags. The new value has
5154 * not been saved yet.
663f4c61
PB		 5155 *
5156 * This is correct even for TF set by the guest, because "the
5157 * processor will not generate this exception after the instruction
5158 * that sets the TF flag".
5159 */
663f4c61
PB		 5160 if (unlikely(rflags & X86_EFLAGS_TF)) {
5161 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5162 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5163 DR6_RTM;
663f4c61
PB		 5164 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5165 kvm_run->debug.arch.exception = DB_VECTOR;
5166 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5167 *r = EMULATE_USER_EXIT;
5168 } else {
5169 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5170 /*
5171 * "Certain debug exceptions may clear bit 0-3. The
5172 * remaining contents of the DR6 register are never
5173 * cleared by the processor".
5174 */
5175 vcpu->arch.dr6 &= ~15;
6f43ed01 5176 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5177 kvm_queue_exception(vcpu, DB_VECTOR);
5178 }
5179 }
5180}
5181
4a1e10d5
PB		 5182static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5183{
5184 struct kvm_run *kvm_run = vcpu->run;
5185 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5186 u32 dr6 = 0;
5187
5188 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5189 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5190 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5191 vcpu->arch.guest_debug_dr7,
5192 vcpu->arch.eff_db);
5193
5194 if (dr6 != 0) {
6f43ed01 5195 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5196 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5197 get_segment_base(vcpu, VCPU_SREG_CS);
5198
5199 kvm_run->debug.arch.exception = DB_VECTOR;
5200 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5201 *r = EMULATE_USER_EXIT;
5202 return true;
5203 }
5204 }
5205
4161a569
NA		 5206 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5207 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5208 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5209 vcpu->arch.dr7,
5210 vcpu->arch.db);
5211
5212 if (dr6 != 0) {
5213 vcpu->arch.dr6 &= ~15;
6f43ed01 5214 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5215 kvm_queue_exception(vcpu, DB_VECTOR);
5216 *r = EMULATE_DONE;
5217 return true;
5218 }
5219 }
5220
5221 return false;
5222}
5223
51d8b661
AP		 5224int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5225 unsigned long cr2,
dc25e89e
AP		 5226 int emulation_type,
5227 void *insn,
5228 int insn_len)
bbd9b64e 5229{
95cb2295 5230 int r;
9d74191a 5231 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5232 bool writeback = true;
93c05d3e 5233 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5234
93c05d3e
XG		 5235 /*
5236 * Clear write_fault_to_shadow_pgtable here to ensure it is
5237 * never reused.
5238 */
5239 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5240 kvm_clear_exception_queue(vcpu);
8d7d8102 5241
571008da 5242 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5243 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5244
5245 /*
5246 * We will reenter on the same instruction since
5247 * we do not set complete_userspace_io. This does not
5248 * handle watchpoints yet, those would be handled in
5249 * the emulate_ops.
5250 */
5251 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5252 return r;
5253
9d74191a
TY		 5254 ctxt->interruptibility = 0;
5255 ctxt->have_exception = false;
e0ad0b47 5256 ctxt->exception.vector = -1;
9d74191a 5257 ctxt->perm_ok = false;
bbd9b64e 5258
b51e974f 5259 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5260
9d74191a 5261 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5262
e46479f8 5263 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5264 ++vcpu->stat.insn_emulation;
1d2887e2 5265 if (r != EMULATION_OK) {
4005996e
AK		 5266 if (emulation_type & EMULTYPE_TRAP_UD)
5267 return EMULATE_FAIL;
991eebf9
GN		 5268 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5269 emulation_type))
bbd9b64e 5270 return EMULATE_DONE;
6d77dbfc
GN		 5271 if (emulation_type & EMULTYPE_SKIP)
5272 return EMULATE_FAIL;
5273 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5274 }
5275 }
5276
ba8afb6b 5277 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5278 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5279 if (ctxt->eflags & X86_EFLAGS_RF)
5280 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5281 return EMULATE_DONE;
5282 }
5283
1cb3f3ae
XG		 5284 if (retry_instruction(ctxt, cr2, emulation_type))
5285 return EMULATE_DONE;
5286
7ae441ea 5287 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5288 changes registers values during IO operation */
7ae441ea
GN		 5289 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5290 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5291 emulator_invalidate_register_cache(ctxt);
7ae441ea 5292 }
4d2179e1 5293
5cd21917 5294restart:
9d74191a 5295 r = x86_emulate_insn(ctxt);
bbd9b64e 5296
775fde86
JR		 5297 if (r == EMULATION_INTERCEPTED)
5298 return EMULATE_DONE;
5299
d2ddd1c4 5300 if (r == EMULATION_FAILED) {
991eebf9
GN		 5301 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5302 emulation_type))
c3cd7ffa
GN		 5303 return EMULATE_DONE;
5304
6d77dbfc 5305 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5306 }
5307
9d74191a 5308 if (ctxt->have_exception) {
d2ddd1c4 5309 r = EMULATE_DONE;
ef54bcfe
PB		 5310 if (inject_emulated_exception(vcpu))
5311 return r;
d2ddd1c4 5312 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5313 if (!vcpu->arch.pio.in) {
5314 /* FIXME: return into emulator if single-stepping. */
3457e419 5315 vcpu->arch.pio.count = 0;
0912c977 5316 } else {
7ae441ea 5317 writeback = false;
716d51ab
GN		 5318 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5319 }
ac0a48c3 5320 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5321 } else if (vcpu->mmio_needed) {
5322 if (!vcpu->mmio_is_write)
5323 writeback = false;
ac0a48c3 5324 r = EMULATE_USER_EXIT;
716d51ab 5325 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5326 } else if (r == EMULATION_RESTART)
5cd21917 5327 goto restart;
d2ddd1c4
GN		 5328 else
5329 r = EMULATE_DONE;
f850e2e6 5330
7ae441ea 5331 if (writeback) {
6addfc42 5332 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5333 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5334 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5335 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5336 if (r == EMULATE_DONE)
6addfc42
PB		 5337 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5338 __kvm_set_rflags(vcpu, ctxt->eflags);
5339
5340 /*
5341 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5342 * do nothing, and it will be requested again as soon as
5343 * the shadow expires. But we still need to check here,
5344 * because POPF has no interrupt shadow.
5345 */
5346 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5347 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5348 } else
5349 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5350
5351 return r;
de7d789a 5352}
51d8b661 5353EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5354
cf8f70bf 5355int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5356{
cf8f70bf 5357 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5358 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5359 size, port, &val, 1);
cf8f70bf 5360 /* do not return to emulator after return from userspace */
7972995b 5361 vcpu->arch.pio.count = 0;
de7d789a
CO		 5362 return ret;
5363}
cf8f70bf 5364EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5365
8cfdc000
ZA		 5366static void tsc_bad(void *info)
5367{
0a3aee0d 5368 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5369}
5370
5371static void tsc_khz_changed(void *data)
c8076604 5372{
8cfdc000
ZA		 5373 struct cpufreq_freqs *freq = data;
5374 unsigned long khz = 0;
5375
5376 if (data)
5377 khz = freq->new;
5378 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5379 khz = cpufreq_quick_get(raw_smp_processor_id());
5380 if (!khz)
5381 khz = tsc_khz;
0a3aee0d 5382 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5383}
5384
c8076604
GH		 5385static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5386 void *data)
5387{
5388 struct cpufreq_freqs *freq = data;
5389 struct kvm *kvm;
5390 struct kvm_vcpu *vcpu;
5391 int i, send_ipi = 0;
5392
8cfdc000
ZA		 5393 /*
5394 * We allow guests to temporarily run on slowing clocks,
5395 * provided we notify them after, or to run on accelerating
5396 * clocks, provided we notify them before. Thus time never
5397 * goes backwards.
5398 *
5399 * However, we have a problem. We can't atomically update
5400 * the frequency of a given CPU from this function; it is
5401 * merely a notifier, which can be called from any CPU.
5402 * Changing the TSC frequency at arbitrary points in time
5403 * requires a recomputation of local variables related to
5404 * the TSC for each VCPU. We must flag these local variables
5405 * to be updated and be sure the update takes place with the
5406 * new frequency before any guests proceed.
5407 *
5408 * Unfortunately, the combination of hotplug CPU and frequency
5409 * change creates an intractable locking scenario; the order
5410 * of when these callouts happen is undefined with respect to
5411 * CPU hotplug, and they can race with each other. As such,
5412 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5413 * undefined; you can actually have a CPU frequency change take
5414 * place in between the computation of X and the setting of the
5415 * variable. To protect against this problem, all updates of
5416 * the per_cpu tsc_khz variable are done in an interrupt
5417 * protected IPI, and all callers wishing to update the value
5418 * must wait for a synchronous IPI to complete (which is trivial
5419 * if the caller is on the CPU already). This establishes the
5420 * necessary total order on variable updates.
5421 *
5422 * Note that because a guest time update may take place
5423 * anytime after the setting of the VCPU's request bit, the
5424 * correct TSC value must be set before the request. However,
5425 * to ensure the update actually makes it to any guest which
5426 * starts running in hardware virtualization between the set
5427 * and the acquisition of the spinlock, we must also ping the
5428 * CPU after setting the request bit.
5429 *
5430 */
5431
c8076604
GH		 5432 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5433 return 0;
5434 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5435 return 0;
8cfdc000
ZA		 5436
5437 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5438
2f303b74 5439 spin_lock(&kvm_lock);
c8076604 5440 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5441 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5442 if (vcpu->cpu != freq->cpu)
5443 continue;
c285545f 5444 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5445 if (vcpu->cpu != smp_processor_id())
8cfdc000 5446 send_ipi = 1;
c8076604
GH		 5447 }
5448 }
2f303b74 5449 spin_unlock(&kvm_lock);
c8076604
GH		 5450
5451 if (freq->old < freq->new && send_ipi) {
5452 /*
5453 * We upscale the frequency. Must make the guest
5454 * doesn't see old kvmclock values while running with
5455 * the new frequency, otherwise we risk the guest sees
5456 * time go backwards.
5457 *
5458 * In case we update the frequency for another cpu
5459 * (which might be in guest context) send an interrupt
5460 * to kick the cpu out of guest context. Next time
5461 * guest context is entered kvmclock will be updated,
5462 * so the guest will not see stale values.
5463 */
8cfdc000 5464 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5465 }
5466 return 0;
5467}
5468
5469static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5470 .notifier_call = kvmclock_cpufreq_notifier
5471};
5472
5473static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5474 unsigned long action, void *hcpu)
5475{
5476 unsigned int cpu = (unsigned long)hcpu;
5477
5478 switch (action) {
5479 case CPU_ONLINE:
5480 case CPU_DOWN_FAILED:
5481 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5482 break;
5483 case CPU_DOWN_PREPARE:
5484 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5485 break;
5486 }
5487 return NOTIFY_OK;
5488}
5489
5490static struct notifier_block kvmclock_cpu_notifier_block = {
5491 .notifier_call = kvmclock_cpu_notifier,
5492 .priority = -INT_MAX
c8076604
GH		 5493};
5494
b820cc0c
ZA		 5495static void kvm_timer_init(void)
5496{
5497 int cpu;
5498
c285545f 5499 max_tsc_khz = tsc_khz;
460dd42e
SB		 5500
5501 cpu_notifier_register_begin();
b820cc0c 5502 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5503#ifdef CONFIG_CPU_FREQ
5504 struct cpufreq_policy policy;
5505 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5506 cpu = get_cpu();
5507 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5508 if (policy.cpuinfo.max_freq)
5509 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5510 put_cpu();
c285545f 5511#endif
b820cc0c
ZA		 5512 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5513 CPUFREQ_TRANSITION_NOTIFIER);
5514 }
c285545f 5515 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5516 for_each_online_cpu(cpu)
5517 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5518
5519 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5520 cpu_notifier_register_done();
5521
b820cc0c
ZA		 5522}
5523
ff9d07a0
ZY		 5524static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5525
f5132b01 5526int kvm_is_in_guest(void)
ff9d07a0 5527{
086c9855 5528 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5529}
5530
5531static int kvm_is_user_mode(void)
5532{
5533 int user_mode = 3;
dcf46b94 5534
086c9855
AS		 5535 if (__this_cpu_read(current_vcpu))
5536 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5537
ff9d07a0
ZY		 5538 return user_mode != 0;
5539}
5540
5541static unsigned long kvm_get_guest_ip(void)
5542{
5543 unsigned long ip = 0;
dcf46b94 5544
086c9855
AS		 5545 if (__this_cpu_read(current_vcpu))
5546 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5547
ff9d07a0
ZY		 5548 return ip;
5549}
5550
5551static struct perf_guest_info_callbacks kvm_guest_cbs = {
5552 .is_in_guest = kvm_is_in_guest,
5553 .is_user_mode = kvm_is_user_mode,
5554 .get_guest_ip = kvm_get_guest_ip,
5555};
5556
5557void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5558{
086c9855 5559 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5560}
5561EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5562
5563void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5564{
086c9855 5565 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5566}
5567EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5568
ce88decf
XG		 5569static void kvm_set_mmio_spte_mask(void)
5570{
5571 u64 mask;
5572 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5573
5574 /*
5575 * Set the reserved bits and the present bit of an paging-structure
5576 * entry to generate page fault with PFER.RSV = 1.
5577 */
885032b9 5578 /* Mask the reserved physical address bits. */
d1431483 5579 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5580
5581 /* Bit 62 is always reserved for 32bit host. */
5582 mask |= 0x3ull << 62;
5583
5584 /* Set the present bit. */
ce88decf
XG		 5585 mask |= 1ull;
5586
5587#ifdef CONFIG_X86_64
5588 /*
5589 * If reserved bit is not supported, clear the present bit to disable
5590 * mmio page fault.
5591 */
5592 if (maxphyaddr == 52)
5593 mask &= ~1ull;
5594#endif
5595
5596 kvm_mmu_set_mmio_spte_mask(mask);
5597}
5598
16e8d74d
MT		 5599#ifdef CONFIG_X86_64
5600static void pvclock_gtod_update_fn(struct work_struct *work)
5601{
d828199e
MT		 5602 struct kvm *kvm;
5603
5604 struct kvm_vcpu *vcpu;
5605 int i;
5606
2f303b74 5607 spin_lock(&kvm_lock);
d828199e
MT		 5608 list_for_each_entry(kvm, &vm_list, vm_list)
5609 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5610 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5611 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5612 spin_unlock(&kvm_lock);
16e8d74d
MT		 5613}
5614
5615static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5616
5617/*
5618 * Notification about pvclock gtod data update.
5619 */
5620static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5621 void *priv)
5622{
5623 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5624 struct timekeeper *tk = priv;
5625
5626 update_pvclock_gtod(tk);
5627
5628 /* disable master clock if host does not trust, or does not
5629 * use, TSC clocksource
5630 */
5631 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5632 atomic_read(&kvm_guest_has_master_clock) != 0)
5633 queue_work(system_long_wq, &pvclock_gtod_work);
5634
5635 return 0;
5636}
5637
5638static struct notifier_block pvclock_gtod_notifier = {
5639 .notifier_call = pvclock_gtod_notify,
5640};
5641#endif
5642
f8c16bba 5643int kvm_arch_init(void *opaque)
043405e1 5644{
b820cc0c 5645 int r;
6b61edf7 5646 struct kvm_x86_ops *ops = opaque;
f8c16bba 5647
f8c16bba
ZX		 5648 if (kvm_x86_ops) {
5649 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5650 r = -EEXIST;
5651 goto out;
f8c16bba
ZX		 5652 }
5653
5654 if (!ops->cpu_has_kvm_support()) {
5655 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5656 r = -EOPNOTSUPP;
5657 goto out;
f8c16bba
ZX		 5658 }
5659 if (ops->disabled_by_bios()) {
5660 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5661 r = -EOPNOTSUPP;
5662 goto out;
f8c16bba
ZX		 5663 }
5664
013f6a5d
MT		 5665 r = -ENOMEM;
5666 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5667 if (!shared_msrs) {
5668 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5669 goto out;
5670 }
5671
97db56ce
AK		 5672 r = kvm_mmu_module_init();
5673 if (r)
013f6a5d 5674 goto out_free_percpu;
97db56ce 5675
ce88decf 5676 kvm_set_mmio_spte_mask();
97db56ce 5677
f8c16bba 5678 kvm_x86_ops = ops;
920c8377
PB		 5679 kvm_init_msr_list();
5680
7b52345e 5681 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5682 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5683
b820cc0c 5684 kvm_timer_init();
c8076604 5685
ff9d07a0
ZY		 5686 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5687
2acf923e
DC		 5688 if (cpu_has_xsave)
5689 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5690
c5cc421b 5691 kvm_lapic_init();
16e8d74d
MT		 5692#ifdef CONFIG_X86_64
5693 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5694#endif
5695
f8c16bba 5696 return 0;
56c6d28a 5697
013f6a5d
MT		 5698out_free_percpu:
5699 free_percpu(shared_msrs);
56c6d28a 5700out:
56c6d28a 5701 return r;
043405e1 5702}
8776e519 5703
f8c16bba
ZX		 5704void kvm_arch_exit(void)
5705{
ff9d07a0
ZY		 5706 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5707
888d256e
JK		 5708 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5709 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5710 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5711 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5712#ifdef CONFIG_X86_64
5713 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5714#endif
f8c16bba 5715 kvm_x86_ops = NULL;
56c6d28a 5716 kvm_mmu_module_exit();
013f6a5d 5717 free_percpu(shared_msrs);
56c6d28a 5718}
f8c16bba 5719
8776e519
HB		 5720int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5721{
5722 ++vcpu->stat.halt_exits;
5723 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5724 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5725 return 1;
5726 } else {
5727 vcpu->run->exit_reason = KVM_EXIT_HLT;
5728 return 0;
5729 }
5730}
5731EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5732
55cd8e5a
GN		 5733int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5734{
5735 u64 param, ingpa, outgpa, ret;
5736 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5737 bool fast, longmode;
55cd8e5a
GN		 5738
5739 /*
5740 * hypercall generates UD from non zero cpl and real mode
5741 * per HYPER-V spec
5742 */
3eeb3288 5743 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5744 kvm_queue_exception(vcpu, UD_VECTOR);
5745 return 0;
5746 }
5747
a449c7aa 5748 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5749
5750 if (!longmode) {
ccd46936
GN		 5751 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5752 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5753 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5754 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5755 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5756 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5757 }
5758#ifdef CONFIG_X86_64
5759 else {
5760 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5761 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5762 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5763 }
5764#endif
5765
5766 code = param & 0xffff;
5767 fast = (param >> 16) & 0x1;
5768 rep_cnt = (param >> 32) & 0xfff;
5769 rep_idx = (param >> 48) & 0xfff;
5770
5771 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5772
c25bc163
GN		 5773 switch (code) {
5774 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5775 kvm_vcpu_on_spin(vcpu);
5776 break;
5777 default:
5778 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5779 break;
5780 }
55cd8e5a
GN		 5781
5782 ret = res | (((u64)rep_done & 0xfff) << 32);
5783 if (longmode) {
5784 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5785 } else {
5786 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5787 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5788 }
5789
5790 return 1;
5791}
5792
6aef266c
SV		 5793/*
5794 * kvm_pv_kick_cpu_op: Kick a vcpu.
5795 *
5796 * @apicid - apicid of vcpu to be kicked.
5797 */
5798static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5799{
24d2166b 5800 struct kvm_lapic_irq lapic_irq;
6aef266c 5801
24d2166b
R		 5802 lapic_irq.shorthand = 0;
5803 lapic_irq.dest_mode = 0;
5804 lapic_irq.dest_id = apicid;
6aef266c 5805
24d2166b
R		 5806 lapic_irq.delivery_mode = APIC_DM_REMRD;
5807 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5808}
5809
8776e519
HB		 5810int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5811{
5812 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5813 int op_64_bit, r = 1;
8776e519 5814
55cd8e5a
GN		 5815 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5816 return kvm_hv_hypercall(vcpu);
5817
5fdbf976
MT		 5818 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5819 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5820 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5821 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5822 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5823
229456fc 5824 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5825
a449c7aa
NA		 5826 op_64_bit = is_64_bit_mode(vcpu);
5827 if (!op_64_bit) {
8776e519
HB		 5828 nr &= 0xFFFFFFFF;
5829 a0 &= 0xFFFFFFFF;
5830 a1 &= 0xFFFFFFFF;
5831 a2 &= 0xFFFFFFFF;
5832 a3 &= 0xFFFFFFFF;
5833 }
5834
07708c4a
JK		 5835 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5836 ret = -KVM_EPERM;
5837 goto out;
5838 }
5839
8776e519 5840 switch (nr) {
b93463aa
AK		 5841 case KVM_HC_VAPIC_POLL_IRQ:
5842 ret = 0;
5843 break;
6aef266c
SV		 5844 case KVM_HC_KICK_CPU:
5845 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5846 ret = 0;
5847 break;
8776e519
HB		 5848 default:
5849 ret = -KVM_ENOSYS;
5850 break;
5851 }
07708c4a 5852out:
a449c7aa
NA		 5853 if (!op_64_bit)
5854 ret = (u32)ret;
5fdbf976 5855 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5856 ++vcpu->stat.hypercalls;
2f333bcb 5857 return r;
8776e519
HB		 5858}
5859EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5860
b6785def 5861static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5862{
d6aa1000 5863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5864 char instruction[3];
5fdbf976 5865 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5866
8776e519 5867 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5868
9d74191a 5869 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5870}
5871
b6c7a5dc
HB		 5872/*
5873 * Check if userspace requested an interrupt window, and that the
5874 * interrupt window is open.
5875 *
5876 * No need to exit to userspace if we already have an interrupt queued.
5877 */
851ba692 5878static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5879{
8061823a 5880 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5881 vcpu->run->request_interrupt_window &&
5df56646 5882 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5883}
5884
851ba692 5885static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5886{
851ba692
AK		 5887 struct kvm_run *kvm_run = vcpu->run;
5888
91586a3b 5889 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5890 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5891 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5892 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5893 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5894 else
b6c7a5dc 5895 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5896 kvm_arch_interrupt_allowed(vcpu) &&
5897 !kvm_cpu_has_interrupt(vcpu) &&
5898 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5899}
5900
95ba8273
GN		 5901static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5902{
5903 int max_irr, tpr;
5904
5905 if (!kvm_x86_ops->update_cr8_intercept)
5906 return;
5907
88c808fd
AK		 5908 if (!vcpu->arch.apic)
5909 return;
5910
8db3baa2
GN		 5911 if (!vcpu->arch.apic->vapic_addr)
5912 max_irr = kvm_lapic_find_highest_irr(vcpu);
5913 else
5914 max_irr = -1;
95ba8273
GN		 5915
5916 if (max_irr != -1)
5917 max_irr >>= 4;
5918
5919 tpr = kvm_lapic_get_cr8(vcpu);
5920
5921 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5922}
5923
b6b8a145 5924static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5925{
b6b8a145
JK		 5926 int r;
5927
95ba8273 5928 /* try to reinject previous events if any */
b59bb7bd 5929 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5930 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5931 vcpu->arch.exception.has_error_code,
5932 vcpu->arch.exception.error_code);
d6e8c854
NA		 5933
5934 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5935 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5936 X86_EFLAGS_RF);
5937
b59bb7bd
GN		 5938 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5939 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5940 vcpu->arch.exception.error_code,
5941 vcpu->arch.exception.reinject);
b6b8a145 5942 return 0;
b59bb7bd
GN		 5943 }
5944
95ba8273
GN		 5945 if (vcpu->arch.nmi_injected) {
5946 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5947 return 0;
95ba8273
GN		 5948 }
5949
5950 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5951 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5952 return 0;
5953 }
5954
5955 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5956 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5957 if (r != 0)
5958 return r;
95ba8273
GN		 5959 }
5960
5961 /* try to inject new event if pending */
5962 if (vcpu->arch.nmi_pending) {
5963 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5964 --vcpu->arch.nmi_pending;
95ba8273
GN		 5965 vcpu->arch.nmi_injected = true;
5966 kvm_x86_ops->set_nmi(vcpu);
5967 }
c7c9c56c 5968 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5969 /*
5970 * Because interrupts can be injected asynchronously, we are
5971 * calling check_nested_events again here to avoid a race condition.
5972 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5973 * proposal and current concerns. Perhaps we should be setting
5974 * KVM_REQ_EVENT only on certain events and not unconditionally?
5975 */
5976 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5977 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5978 if (r != 0)
5979 return r;
5980 }
95ba8273 5981 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5982 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5983 false);
5984 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5985 }
5986 }
b6b8a145 5987 return 0;
95ba8273
GN		 5988}
5989
7460fb4a
AK		 5990static void process_nmi(struct kvm_vcpu *vcpu)
5991{
5992 unsigned limit = 2;
5993
5994 /*
5995 * x86 is limited to one NMI running, and one NMI pending after it.
5996 * If an NMI is already in progress, limit further NMIs to just one.
5997 * Otherwise, allow two (and we'll inject the first one immediately).
5998 */
5999 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6000 limit = 1;
6001
6002 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6003 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6004 kvm_make_request(KVM_REQ_EVENT, vcpu);
6005}
6006
3d81bc7e 6007static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6008{
6009 u64 eoi_exit_bitmap[4];
cf9e65b7 6010 u32 tmr[8];
c7c9c56c 6011
3d81bc7e
YZ		 6012 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6013 return;
c7c9c56c
YZ		 6014
6015 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6016 memset(tmr, 0, 32);
c7c9c56c 6017
cf9e65b7 6018 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6019 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6020 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6021}
6022
a70656b6
RK		 6023static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6024{
6025 ++vcpu->stat.tlb_flush;
6026 kvm_x86_ops->tlb_flush(vcpu);
6027}
6028
fe71557a
TC		 6029void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6030 unsigned long address)
6031{
6032}
6033
9357d939
TY		 6034/*
6035 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6036 * exiting to the userspace. Otherwise, the value will be returned to the
6037 * userspace.
6038 */
851ba692 6039static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6040{
6041 int r;
6a8b1d13 6042 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6043 vcpu->run->request_interrupt_window;
730dca42 6044 bool req_immediate_exit = false;
b6c7a5dc 6045
3e007509 6046 if (vcpu->requests) {
a8eeb04a 6047 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6048 kvm_mmu_unload(vcpu);
a8eeb04a 6049 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6050 __kvm_migrate_timers(vcpu);
d828199e
MT		 6051 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6052 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6053 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6054 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6055 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6056 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6057 if (unlikely(r))
6058 goto out;
6059 }
a8eeb04a 6060 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6061 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6062 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6063 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6064 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6065 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6066 r = 0;
6067 goto out;
6068 }
a8eeb04a 6069 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6070 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6071 r = 0;
6072 goto out;
6073 }
a8eeb04a 6074 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6075 vcpu->fpu_active = 0;
6076 kvm_x86_ops->fpu_deactivate(vcpu);
6077 }
af585b92
GN		 6078 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6079 /* Page is swapped out. Do synthetic halt */
6080 vcpu->arch.apf.halted = true;
6081 r = 1;
6082 goto out;
6083 }
c9aaa895
GC		 6084 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6085 record_steal_time(vcpu);
7460fb4a
AK		 6086 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6087 process_nmi(vcpu);
f5132b01
GN		 6088 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6089 kvm_handle_pmu_event(vcpu);
6090 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6091 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6092 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6093 vcpu_scan_ioapic(vcpu);
2f52d58c 6094 }
b93463aa 6095
b463a6f7 6096 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6097 kvm_apic_accept_events(vcpu);
6098 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6099 r = 1;
6100 goto out;
6101 }
6102
b6b8a145
JK		 6103 if (inject_pending_event(vcpu, req_int_win) != 0)
6104 req_immediate_exit = true;
b463a6f7 6105 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6106 else if (vcpu->arch.nmi_pending)
c9a7953f 6107 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6108 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6109 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6110
6111 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6112 /*
6113 * Update architecture specific hints for APIC
6114 * virtual interrupt delivery.
6115 */
6116 if (kvm_x86_ops->hwapic_irr_update)
6117 kvm_x86_ops->hwapic_irr_update(vcpu,
6118 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6119 update_cr8_intercept(vcpu);
6120 kvm_lapic_sync_to_vapic(vcpu);
6121 }
6122 }
6123
d8368af8
AK		 6124 r = kvm_mmu_reload(vcpu);
6125 if (unlikely(r)) {
d905c069 6126 goto cancel_injection;
d8368af8
AK		 6127 }
6128
b6c7a5dc
HB		 6129 preempt_disable();
6130
6131 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6132 if (vcpu->fpu_active)
6133 kvm_load_guest_fpu(vcpu);
2acf923e 6134 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6135
6b7e2d09
XG		 6136 vcpu->mode = IN_GUEST_MODE;
6137
01b71917
MT		 6138 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6139
6b7e2d09
XG		 6140 /* We should set ->mode before check ->requests,
6141 * see the comment in make_all_cpus_request.
6142 */
01b71917 6143 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6144
d94e1dc9 6145 local_irq_disable();
32f88400 6146
6b7e2d09 6147 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6148 || need_resched() || signal_pending(current)) {
6b7e2d09 6149 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6150 smp_wmb();
6c142801
AK		 6151 local_irq_enable();
6152 preempt_enable();
01b71917 6153 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6154 r = 1;
d905c069 6155 goto cancel_injection;
6c142801
AK		 6156 }
6157
d6185f20
NHE		 6158 if (req_immediate_exit)
6159 smp_send_reschedule(vcpu->cpu);
6160
b6c7a5dc
HB		 6161 kvm_guest_enter();
6162
42dbaa5a 6163 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6164 set_debugreg(0, 7);
6165 set_debugreg(vcpu->arch.eff_db[0], 0);
6166 set_debugreg(vcpu->arch.eff_db[1], 1);
6167 set_debugreg(vcpu->arch.eff_db[2], 2);
6168 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6169 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6170 }
b6c7a5dc 6171
229456fc 6172 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6173 kvm_x86_ops->run(vcpu);
b6c7a5dc 6174
c77fb5fe
PB		 6175 /*
6176 * Do this here before restoring debug registers on the host. And
6177 * since we do this before handling the vmexit, a DR access vmexit
6178 * can (a) read the correct value of the debug registers, (b) set
6179 * KVM_DEBUGREG_WONT_EXIT again.
6180 */
6181 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6182 int i;
6183
6184 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6185 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6186 for (i = 0; i < KVM_NR_DB_REGS; i++)
6187 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6188 }
6189
24f1e32c
FW		 6190 /*
6191 * If the guest has used debug registers, at least dr7
6192 * will be disabled while returning to the host.
6193 * If we don't have active breakpoints in the host, we don't
6194 * care about the messed up debug address registers. But if
6195 * we have some of them active, restore the old state.
6196 */
59d8eb53 6197 if (hw_breakpoint_active())
24f1e32c 6198 hw_breakpoint_restore();
42dbaa5a 6199
886b470c
MT		 6200 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6201 native_read_tsc());
1d5f066e 6202
6b7e2d09 6203 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6204 smp_wmb();
a547c6db
YZ		 6205
6206 /* Interrupt is enabled by handle_external_intr() */
6207 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6208
6209 ++vcpu->stat.exits;
6210
6211 /*
6212 * We must have an instruction between local_irq_enable() and
6213 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6214 * the interrupt shadow. The stat.exits increment will do nicely.
6215 * But we need to prevent reordering, hence this barrier():
6216 */
6217 barrier();
6218
6219 kvm_guest_exit();
6220
6221 preempt_enable();
6222
f656ce01 6223 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6224
b6c7a5dc
HB		 6225 /*
6226 * Profile KVM exit RIPs:
6227 */
6228 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6229 unsigned long rip = kvm_rip_read(vcpu);
6230 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6231 }
6232
cc578287
ZA		 6233 if (unlikely(vcpu->arch.tsc_always_catchup))
6234 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6235
5cfb1d5a
MT		 6236 if (vcpu->arch.apic_attention)
6237 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6238
851ba692 6239 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6240 return r;
6241
6242cancel_injection:
6243 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6244 if (unlikely(vcpu->arch.apic_attention))
6245 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6246out:
6247 return r;
6248}
b6c7a5dc 6249
09cec754 6250
851ba692 6251static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6252{
6253 int r;
f656ce01 6254 struct kvm *kvm = vcpu->kvm;
d7690175 6255
f656ce01 6256 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6257
6258 r = 1;
6259 while (r > 0) {
af585b92
GN		 6260 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6261 !vcpu->arch.apf.halted)
851ba692 6262 r = vcpu_enter_guest(vcpu);
d7690175 6263 else {
f656ce01 6264 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6265 kvm_vcpu_block(vcpu);
f656ce01 6266 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6267 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6268 kvm_apic_accept_events(vcpu);
09cec754
GN		 6269 switch(vcpu->arch.mp_state) {
6270 case KVM_MP_STATE_HALTED:
6aef266c 6271 vcpu->arch.pv.pv_unhalted = false;
d7690175 6272 vcpu->arch.mp_state =
09cec754
GN		 6273 KVM_MP_STATE_RUNNABLE;
6274 case KVM_MP_STATE_RUNNABLE:
af585b92 6275 vcpu->arch.apf.halted = false;
09cec754 6276 break;
66450a21
JK		 6277 case KVM_MP_STATE_INIT_RECEIVED:
6278 break;
09cec754
GN		 6279 default:
6280 r = -EINTR;
6281 break;
6282 }
6283 }
d7690175
MT		 6284 }
6285
09cec754
GN		 6286 if (r <= 0)
6287 break;
6288
6289 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6290 if (kvm_cpu_has_pending_timer(vcpu))
6291 kvm_inject_pending_timer_irqs(vcpu);
6292
851ba692 6293 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6294 r = -EINTR;
851ba692 6295 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6296 ++vcpu->stat.request_irq_exits;
6297 }
af585b92
GN		 6298
6299 kvm_check_async_pf_completion(vcpu);
6300
09cec754
GN		 6301 if (signal_pending(current)) {
6302 r = -EINTR;
851ba692 6303 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6304 ++vcpu->stat.signal_exits;
6305 }
6306 if (need_resched()) {
f656ce01 6307 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6308 cond_resched();
f656ce01 6309 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6310 }
b6c7a5dc
HB		 6311 }
6312
f656ce01 6313 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6314
6315 return r;
6316}
6317
716d51ab
GN		 6318static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6319{
6320 int r;
6321 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6322 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6323 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6324 if (r != EMULATE_DONE)
6325 return 0;
6326 return 1;
6327}
6328
6329static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6330{
6331 BUG_ON(!vcpu->arch.pio.count);
6332
6333 return complete_emulated_io(vcpu);
6334}
6335
f78146b0
AK		 6336/*
6337 * Implements the following, as a state machine:
6338 *
6339 * read:
6340 * for each fragment
87da7e66
XG		 6341 * for each mmio piece in the fragment
6342 * write gpa, len
6343 * exit
6344 * copy data
f78146b0
AK		 6345 * execute insn
6346 *
6347 * write:
6348 * for each fragment
87da7e66
XG		 6349 * for each mmio piece in the fragment
6350 * write gpa, len
6351 * copy data
6352 * exit
f78146b0 6353 */
716d51ab 6354static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6355{
6356 struct kvm_run *run = vcpu->run;
f78146b0 6357 struct kvm_mmio_fragment *frag;
87da7e66 6358 unsigned len;
5287f194 6359
716d51ab 6360 BUG_ON(!vcpu->mmio_needed);
5287f194 6361
716d51ab 6362 /* Complete previous fragment */
87da7e66
XG		 6363 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6364 len = min(8u, frag->len);
716d51ab 6365 if (!vcpu->mmio_is_write)
87da7e66
XG		 6366 memcpy(frag->data, run->mmio.data, len);
6367
6368 if (frag->len <= 8) {
6369 /* Switch to the next fragment. */
6370 frag++;
6371 vcpu->mmio_cur_fragment++;
6372 } else {
6373 /* Go forward to the next mmio piece. */
6374 frag->data += len;
6375 frag->gpa += len;
6376 frag->len -= len;
6377 }
6378
a08d3b3b 6379 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6380 vcpu->mmio_needed = 0;
0912c977
PB		 6381
6382 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6383 if (vcpu->mmio_is_write)
716d51ab
GN		 6384 return 1;
6385 vcpu->mmio_read_completed = 1;
6386 return complete_emulated_io(vcpu);
6387 }
87da7e66 6388
716d51ab
GN		 6389 run->exit_reason = KVM_EXIT_MMIO;
6390 run->mmio.phys_addr = frag->gpa;
6391 if (vcpu->mmio_is_write)
87da7e66
XG		 6392 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6393 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6394 run->mmio.is_write = vcpu->mmio_is_write;
6395 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6396 return 0;
5287f194
AK		 6397}
6398
716d51ab 6399
b6c7a5dc
HB		 6400int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6401{
6402 int r;
6403 sigset_t sigsaved;
6404
e5c30142
AK		 6405 if (!tsk_used_math(current) && init_fpu(current))
6406 return -ENOMEM;
6407
ac9f6dc0
AK		 6408 if (vcpu->sigset_active)
6409 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6410
a4535290 6411 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6412 kvm_vcpu_block(vcpu);
66450a21 6413 kvm_apic_accept_events(vcpu);
d7690175 6414 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6415 r = -EAGAIN;
6416 goto out;
b6c7a5dc
HB		 6417 }
6418
b6c7a5dc 6419 /* re-sync apic's tpr */
eea1cff9
AP		 6420 if (!irqchip_in_kernel(vcpu->kvm)) {
6421 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6422 r = -EINVAL;
6423 goto out;
6424 }
6425 }
b6c7a5dc 6426
716d51ab
GN		 6427 if (unlikely(vcpu->arch.complete_userspace_io)) {
6428 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6429 vcpu->arch.complete_userspace_io = NULL;
6430 r = cui(vcpu);
6431 if (r <= 0)
6432 goto out;
6433 } else
6434 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6435
851ba692 6436 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6437
6438out:
f1d86e46 6439 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6440 if (vcpu->sigset_active)
6441 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6442
b6c7a5dc
HB		 6443 return r;
6444}
6445
6446int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6447{
7ae441ea
GN		 6448 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6449 /*
6450 * We are here if userspace calls get_regs() in the middle of
6451 * instruction emulation. Registers state needs to be copied
4a969980 6452 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6453 * that usually, but some bad designed PV devices (vmware
6454 * backdoor interface) need this to work
6455 */
dd856efa 6456 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6457 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6458 }
5fdbf976
MT		 6459 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6460 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6461 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6462 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6463 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6464 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6465 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6466 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6467#ifdef CONFIG_X86_64
5fdbf976
MT		 6468 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6469 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6470 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6471 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6472 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6473 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6474 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6475 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6476#endif
6477
5fdbf976 6478 regs->rip = kvm_rip_read(vcpu);
91586a3b 6479 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6480
b6c7a5dc
HB		 6481 return 0;
6482}
6483
6484int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6485{
7ae441ea
GN		 6486 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6487 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6488
5fdbf976
MT		 6489 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6490 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6491 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6492 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6493 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6494 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6495 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6496 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6497#ifdef CONFIG_X86_64
5fdbf976
MT		 6498 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6499 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6500 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6501 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6502 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6503 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6504 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6505 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6506#endif
6507
5fdbf976 6508 kvm_rip_write(vcpu, regs->rip);
91586a3b 6509 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6510
b4f14abd
JK		 6511 vcpu->arch.exception.pending = false;
6512
3842d135
AK		 6513 kvm_make_request(KVM_REQ_EVENT, vcpu);
6514
b6c7a5dc
HB		 6515 return 0;
6516}
6517
b6c7a5dc
HB		 6518void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6519{
6520 struct kvm_segment cs;
6521
3e6e0aab 6522 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6523 *db = cs.db;
6524 *l = cs.l;
6525}
6526EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6527
6528int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6529 struct kvm_sregs *sregs)
6530{
89a27f4d 6531 struct desc_ptr dt;
b6c7a5dc 6532
3e6e0aab
GT		 6533 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6534 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6535 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6536 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6537 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6538 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6539
3e6e0aab
GT		 6540 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6541 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6542
6543 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6544 sregs->idt.limit = dt.size;
6545 sregs->idt.base = dt.address;
b6c7a5dc 6546 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6547 sregs->gdt.limit = dt.size;
6548 sregs->gdt.base = dt.address;
b6c7a5dc 6549
4d4ec087 6550 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6551 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6552 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6553 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6554 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6555 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6556 sregs->apic_base = kvm_get_apic_base(vcpu);
6557
923c61bb 6558 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6559
36752c9b 6560 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6561 set_bit(vcpu->arch.interrupt.nr,
6562 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6563
b6c7a5dc
HB		 6564 return 0;
6565}
6566
62d9f0db
MT		 6567int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6568 struct kvm_mp_state *mp_state)
6569{
66450a21 6570 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6571 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6572 vcpu->arch.pv.pv_unhalted)
6573 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6574 else
6575 mp_state->mp_state = vcpu->arch.mp_state;
6576
62d9f0db
MT		 6577 return 0;
6578}
6579
6580int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6581 struct kvm_mp_state *mp_state)
6582{
66450a21
JK		 6583 if (!kvm_vcpu_has_lapic(vcpu) &&
6584 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6585 return -EINVAL;
6586
6587 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6588 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6589 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6590 } else
6591 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6592 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6593 return 0;
6594}
6595
7f3d35fd
KW		 6596int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6597 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6598{
9d74191a 6599 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6600 int ret;
e01c2426 6601
8ec4722d 6602 init_emulate_ctxt(vcpu);
c697518a 6603
7f3d35fd 6604 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6605 has_error_code, error_code);
c697518a 6606
c697518a 6607 if (ret)
19d04437 6608 return EMULATE_FAIL;
37817f29 6609
9d74191a
TY		 6610 kvm_rip_write(vcpu, ctxt->eip);
6611 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6612 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6613 return EMULATE_DONE;
37817f29
IE		 6614}
6615EXPORT_SYMBOL_GPL(kvm_task_switch);
6616
b6c7a5dc
HB		 6617int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6618 struct kvm_sregs *sregs)
6619{
58cb628d 6620 struct msr_data apic_base_msr;
b6c7a5dc 6621 int mmu_reset_needed = 0;
63f42e02 6622 int pending_vec, max_bits, idx;
89a27f4d 6623 struct desc_ptr dt;
b6c7a5dc 6624
6d1068b3
PM		 6625 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6626 return -EINVAL;
6627
89a27f4d
GN		 6628 dt.size = sregs->idt.limit;
6629 dt.address = sregs->idt.base;
b6c7a5dc 6630 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6631 dt.size = sregs->gdt.limit;
6632 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6633 kvm_x86_ops->set_gdt(vcpu, &dt);
6634
ad312c7c 6635 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6636 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6637 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6638 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6639
2d3ad1f4 6640 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6641
f6801dff 6642 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6643 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6644 apic_base_msr.data = sregs->apic_base;
6645 apic_base_msr.host_initiated = true;
6646 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6647
4d4ec087 6648 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6649 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6650 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6651
fc78f519 6652 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6653 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6654 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6655 kvm_update_cpuid(vcpu);
63f42e02
XG		 6656
6657 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6658 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6659 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6660 mmu_reset_needed = 1;
6661 }
63f42e02 6662 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6663
6664 if (mmu_reset_needed)
6665 kvm_mmu_reset_context(vcpu);
6666
a50abc3b 6667 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6668 pending_vec = find_first_bit(
6669 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6670 if (pending_vec < max_bits) {
66fd3f7f 6671 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6672 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6673 }
6674
3e6e0aab
GT		 6675 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6676 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6677 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6678 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6679 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6680 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6681
3e6e0aab
GT		 6682 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6683 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6684
5f0269f5
ME		 6685 update_cr8_intercept(vcpu);
6686
9c3e4aab 6687 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6688 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6689 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6690 !is_protmode(vcpu))
9c3e4aab
MT		 6691 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6692
3842d135
AK		 6693 kvm_make_request(KVM_REQ_EVENT, vcpu);
6694
b6c7a5dc
HB		 6695 return 0;
6696}
6697
d0bfb940
JK		 6698int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6699 struct kvm_guest_debug *dbg)
b6c7a5dc 6700{
355be0b9 6701 unsigned long rflags;
ae675ef0 6702 int i, r;
b6c7a5dc 6703
4f926bf2
JK		 6704 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6705 r = -EBUSY;
6706 if (vcpu->arch.exception.pending)
2122ff5e 6707 goto out;
4f926bf2
JK		 6708 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6709 kvm_queue_exception(vcpu, DB_VECTOR);
6710 else
6711 kvm_queue_exception(vcpu, BP_VECTOR);
6712 }
6713
91586a3b
JK		 6714 /*
6715 * Read rflags as long as potentially injected trace flags are still
6716 * filtered out.
6717 */
6718 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6719
6720 vcpu->guest_debug = dbg->control;
6721 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6722 vcpu->guest_debug = 0;
6723
6724 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6725 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6726 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6727 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6728 } else {
6729 for (i = 0; i < KVM_NR_DB_REGS; i++)
6730 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6731 }
c8639010 6732 kvm_update_dr7(vcpu);
ae675ef0 6733
f92653ee
JK		 6734 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6735 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6736 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6737
91586a3b
JK		 6738 /*
6739 * Trigger an rflags update that will inject or remove the trace
6740 * flags.
6741 */
6742 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6743
c8639010 6744 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6745
4f926bf2 6746 r = 0;
d0bfb940 6747
2122ff5e 6748out:
b6c7a5dc
HB		 6749
6750 return r;
6751}
6752
8b006791
ZX		 6753/*
6754 * Translate a guest virtual address to a guest physical address.
6755 */
6756int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6757 struct kvm_translation *tr)
6758{
6759 unsigned long vaddr = tr->linear_address;
6760 gpa_t gpa;
f656ce01 6761 int idx;
8b006791 6762
f656ce01 6763 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6764 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6766 tr->physical_address = gpa;
6767 tr->valid = gpa != UNMAPPED_GVA;
6768 tr->writeable = 1;
6769 tr->usermode = 0;
8b006791
ZX		 6770
6771 return 0;
6772}
6773
d0752060
HB		 6774int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6775{
98918833
SY		 6776 struct i387_fxsave_struct *fxsave =
6777 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6778
d0752060
HB		 6779 memcpy(fpu->fpr, fxsave->st_space, 128);
6780 fpu->fcw = fxsave->cwd;
6781 fpu->fsw = fxsave->swd;
6782 fpu->ftwx = fxsave->twd;
6783 fpu->last_opcode = fxsave->fop;
6784 fpu->last_ip = fxsave->rip;
6785 fpu->last_dp = fxsave->rdp;
6786 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6787
d0752060
HB		 6788 return 0;
6789}
6790
6791int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6792{
98918833
SY		 6793 struct i387_fxsave_struct *fxsave =
6794 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6795
d0752060
HB		 6796 memcpy(fxsave->st_space, fpu->fpr, 128);
6797 fxsave->cwd = fpu->fcw;
6798 fxsave->swd = fpu->fsw;
6799 fxsave->twd = fpu->ftwx;
6800 fxsave->fop = fpu->last_opcode;
6801 fxsave->rip = fpu->last_ip;
6802 fxsave->rdp = fpu->last_dp;
6803 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6804
d0752060
HB		 6805 return 0;
6806}
6807
10ab25cd 6808int fx_init(struct kvm_vcpu *vcpu)
d0752060 6809{
10ab25cd
JK		 6810 int err;
6811
6812 err = fpu_alloc(&vcpu->arch.guest_fpu);
6813 if (err)
6814 return err;
6815
98918833 6816 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6817
2acf923e
DC		 6818 /*
6819 * Ensure guest xcr0 is valid for loading
6820 */
6821 vcpu->arch.xcr0 = XSTATE_FP;
6822
ad312c7c 6823 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6824
6825 return 0;
d0752060
HB		 6826}
6827EXPORT_SYMBOL_GPL(fx_init);
6828
98918833
SY		 6829static void fx_free(struct kvm_vcpu *vcpu)
6830{
6831 fpu_free(&vcpu->arch.guest_fpu);
6832}
6833
d0752060
HB		 6834void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6835{
2608d7a1 6836 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6837 return;
6838
2acf923e
DC		 6839 /*
6840 * Restore all possible states in the guest,
6841 * and assume host would use all available bits.
6842 * Guest xcr0 would be loaded later.
6843 */
6844 kvm_put_guest_xcr0(vcpu);
d0752060 6845 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6846 __kernel_fpu_begin();
98918833 6847 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6848 trace_kvm_fpu(1);
d0752060 6849}
d0752060
HB		 6850
6851void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6852{
2acf923e
DC		 6853 kvm_put_guest_xcr0(vcpu);
6854
d0752060
HB		 6855 if (!vcpu->guest_fpu_loaded)
6856 return;
6857
6858 vcpu->guest_fpu_loaded = 0;
98918833 6859 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6860 __kernel_fpu_end();
f096ed85 6861 ++vcpu->stat.fpu_reload;
a8eeb04a 6862 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6863 trace_kvm_fpu(0);
d0752060 6864}
e9b11c17
ZX		 6865
6866void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6867{
12f9a48f 6868 kvmclock_reset(vcpu);
7f1ea208 6869
f5f48ee1 6870 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6871 fx_free(vcpu);
e9b11c17
ZX		 6872 kvm_x86_ops->vcpu_free(vcpu);
6873}
6874
6875struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6876 unsigned int id)
6877{
6755bae8
ZA		 6878 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6879 printk_once(KERN_WARNING
6880 "kvm: SMP vm created on host with unstable TSC; "
6881 "guest TSC will not be reliable\n");
26e5215f
AK		 6882 return kvm_x86_ops->vcpu_create(kvm, id);
6883}
e9b11c17 6884
26e5215f
AK		 6885int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6886{
6887 int r;
e9b11c17 6888
0bed3b56 6889 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6890 r = vcpu_load(vcpu);
6891 if (r)
6892 return r;
57f252f2 6893 kvm_vcpu_reset(vcpu);
8a3c1a33 6894 kvm_mmu_setup(vcpu);
e9b11c17 6895 vcpu_put(vcpu);
e9b11c17 6896
26e5215f 6897 return r;
e9b11c17
ZX		 6898}
6899
42897d86
MT		 6900int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6901{
6902 int r;
8fe8ab46 6903 struct msr_data msr;
332967a3 6904 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6905
6906 r = vcpu_load(vcpu);
6907 if (r)
6908 return r;
8fe8ab46
WA		 6909 msr.data = 0x0;
6910 msr.index = MSR_IA32_TSC;
6911 msr.host_initiated = true;
6912 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6913 vcpu_put(vcpu);
6914
332967a3
AJ		 6915 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6916 KVMCLOCK_SYNC_PERIOD);
6917
42897d86
MT		 6918 return r;
6919}
6920
d40ccc62 6921void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6922{
9fc77441 6923 int r;
344d9588
GN		 6924 vcpu->arch.apf.msr_val = 0;
6925
9fc77441
MT		 6926 r = vcpu_load(vcpu);
6927 BUG_ON(r);
e9b11c17
ZX		 6928 kvm_mmu_unload(vcpu);
6929 vcpu_put(vcpu);
6930
98918833 6931 fx_free(vcpu);
e9b11c17
ZX		 6932 kvm_x86_ops->vcpu_free(vcpu);
6933}
6934
66450a21 6935void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6936{
7460fb4a
AK		 6937 atomic_set(&vcpu->arch.nmi_queued, 0);
6938 vcpu->arch.nmi_pending = 0;
448fa4a9 6939 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6940 kvm_clear_interrupt_queue(vcpu);
6941 kvm_clear_exception_queue(vcpu);
448fa4a9 6942
42dbaa5a 6943 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6944 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6945 kvm_update_dr6(vcpu);
42dbaa5a 6946 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6947 kvm_update_dr7(vcpu);
42dbaa5a 6948
3842d135 6949 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6950 vcpu->arch.apf.msr_val = 0;
c9aaa895 6951 vcpu->arch.st.msr_val = 0;
3842d135 6952
12f9a48f
GC		 6953 kvmclock_reset(vcpu);
6954
af585b92
GN		 6955 kvm_clear_async_pf_completion_queue(vcpu);
6956 kvm_async_pf_hash_reset(vcpu);
6957 vcpu->arch.apf.halted = false;
3842d135 6958
f5132b01
GN		 6959 kvm_pmu_reset(vcpu);
6960
66f7b72e
JS		 6961 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6962 vcpu->arch.regs_avail = ~0;
6963 vcpu->arch.regs_dirty = ~0;
6964
57f252f2 6965 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6966}
6967
66450a21
JK		 6968void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6969{
6970 struct kvm_segment cs;
6971
6972 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6973 cs.selector = vector << 8;
6974 cs.base = vector << 12;
6975 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6976 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6977}
6978
13a34e06 6979int kvm_arch_hardware_enable(void)
e9b11c17 6980{
ca84d1a2
ZA		 6981 struct kvm *kvm;
6982 struct kvm_vcpu *vcpu;
6983 int i;
0dd6a6ed
ZA		 6984 int ret;
6985 u64 local_tsc;
6986 u64 max_tsc = 0;
6987 bool stable, backwards_tsc = false;
18863bdd
AK		 6988
6989 kvm_shared_msr_cpu_online();
13a34e06 6990 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 6991 if (ret != 0)
6992 return ret;
6993
6994 local_tsc = native_read_tsc();
6995 stable = !check_tsc_unstable();
6996 list_for_each_entry(kvm, &vm_list, vm_list) {
6997 kvm_for_each_vcpu(i, vcpu, kvm) {
6998 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 6999 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7000 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7001 backwards_tsc = true;
7002 if (vcpu->arch.last_host_tsc > max_tsc)
7003 max_tsc = vcpu->arch.last_host_tsc;
7004 }
7005 }
7006 }
7007
7008 /*
7009 * Sometimes, even reliable TSCs go backwards. This happens on
7010 * platforms that reset TSC during suspend or hibernate actions, but
7011 * maintain synchronization. We must compensate. Fortunately, we can
7012 * detect that condition here, which happens early in CPU bringup,
7013 * before any KVM threads can be running. Unfortunately, we can't
7014 * bring the TSCs fully up to date with real time, as we aren't yet far
7015 * enough into CPU bringup that we know how much real time has actually
7016 * elapsed; our helper function, get_kernel_ns() will be using boot
7017 * variables that haven't been updated yet.
7018 *
7019 * So we simply find the maximum observed TSC above, then record the
7020 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7021 * the adjustment will be applied. Note that we accumulate
7022 * adjustments, in case multiple suspend cycles happen before some VCPU
7023 * gets a chance to run again. In the event that no KVM threads get a
7024 * chance to run, we will miss the entire elapsed period, as we'll have
7025 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7026 * loose cycle time. This isn't too big a deal, since the loss will be
7027 * uniform across all VCPUs (not to mention the scenario is extremely
7028 * unlikely). It is possible that a second hibernate recovery happens
7029 * much faster than a first, causing the observed TSC here to be
7030 * smaller; this would require additional padding adjustment, which is
7031 * why we set last_host_tsc to the local tsc observed here.
7032 *
7033 * N.B. - this code below runs only on platforms with reliable TSC,
7034 * as that is the only way backwards_tsc is set above. Also note
7035 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7036 * have the same delta_cyc adjustment applied if backwards_tsc
7037 * is detected. Note further, this adjustment is only done once,
7038 * as we reset last_host_tsc on all VCPUs to stop this from being
7039 * called multiple times (one for each physical CPU bringup).
7040 *
4a969980 7041 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7042 * will be compensated by the logic in vcpu_load, which sets the TSC to
7043 * catchup mode. This will catchup all VCPUs to real time, but cannot
7044 * guarantee that they stay in perfect synchronization.
7045 */
7046 if (backwards_tsc) {
7047 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7048 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7049 list_for_each_entry(kvm, &vm_list, vm_list) {
7050 kvm_for_each_vcpu(i, vcpu, kvm) {
7051 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7052 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7053 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7054 }
7055
7056 /*
7057 * We have to disable TSC offset matching.. if you were
7058 * booting a VM while issuing an S4 host suspend....
7059 * you may have some problem. Solving this issue is
7060 * left as an exercise to the reader.
7061 */
7062 kvm->arch.last_tsc_nsec = 0;
7063 kvm->arch.last_tsc_write = 0;
7064 }
7065
7066 }
7067 return 0;
e9b11c17
ZX		 7068}
7069
13a34e06 7070void kvm_arch_hardware_disable(void)
e9b11c17 7071{
13a34e06
RK		 7072 kvm_x86_ops->hardware_disable();
7073 drop_user_return_notifiers();
e9b11c17
ZX		 7074}
7075
7076int kvm_arch_hardware_setup(void)
7077{
7078 return kvm_x86_ops->hardware_setup();
7079}
7080
7081void kvm_arch_hardware_unsetup(void)
7082{
7083 kvm_x86_ops->hardware_unsetup();
7084}
7085
7086void kvm_arch_check_processor_compat(void *rtn)
7087{
7088 kvm_x86_ops->check_processor_compatibility(rtn);
7089}
7090
3e515705
AK		 7091bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7092{
7093 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7094}
7095
54e9818f
GN		 7096struct static_key kvm_no_apic_vcpu __read_mostly;
7097
e9b11c17
ZX		 7098int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7099{
7100 struct page *page;
7101 struct kvm *kvm;
7102 int r;
7103
7104 BUG_ON(vcpu->kvm == NULL);
7105 kvm = vcpu->kvm;
7106
6aef266c 7107 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7108 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7109 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7110 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7111 else
a4535290 7112 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7113
7114 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7115 if (!page) {
7116 r = -ENOMEM;
7117 goto fail;
7118 }
ad312c7c 7119 vcpu->arch.pio_data = page_address(page);
e9b11c17 7120
cc578287 7121 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7122
e9b11c17
ZX		 7123 r = kvm_mmu_create(vcpu);
7124 if (r < 0)
7125 goto fail_free_pio_data;
7126
7127 if (irqchip_in_kernel(kvm)) {
7128 r = kvm_create_lapic(vcpu);
7129 if (r < 0)
7130 goto fail_mmu_destroy;
54e9818f
GN		 7131 } else
7132 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7133
890ca9ae
HY		 7134 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7135 GFP_KERNEL);
7136 if (!vcpu->arch.mce_banks) {
7137 r = -ENOMEM;
443c39bc 7138 goto fail_free_lapic;
890ca9ae
HY		 7139 }
7140 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7141
f1797359
WY		 7142 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7143 r = -ENOMEM;
f5f48ee1 7144 goto fail_free_mce_banks;
f1797359 7145 }
f5f48ee1 7146
66f7b72e
JS		 7147 r = fx_init(vcpu);
7148 if (r)
7149 goto fail_free_wbinvd_dirty_mask;
7150
ba904635 7151 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7152 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7153
7154 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7155 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7156
af585b92 7157 kvm_async_pf_hash_reset(vcpu);
f5132b01 7158 kvm_pmu_init(vcpu);
af585b92 7159
e9b11c17 7160 return 0;
66f7b72e
JS		 7161fail_free_wbinvd_dirty_mask:
7162 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7163fail_free_mce_banks:
7164 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7165fail_free_lapic:
7166 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7167fail_mmu_destroy:
7168 kvm_mmu_destroy(vcpu);
7169fail_free_pio_data:
ad312c7c 7170 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7171fail:
7172 return r;
7173}
7174
7175void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7176{
f656ce01
MT		 7177 int idx;
7178
f5132b01 7179 kvm_pmu_destroy(vcpu);
36cb93fd 7180 kfree(vcpu->arch.mce_banks);
e9b11c17 7181 kvm_free_lapic(vcpu);
f656ce01 7182 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7183 kvm_mmu_destroy(vcpu);
f656ce01 7184 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7185 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7186 if (!irqchip_in_kernel(vcpu->kvm))
7187 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7188}
d19a9cd2 7189
e790d9ef
RK		 7190void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7191{
ae97a3b8 7192 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7193}
7194
e08b9637 7195int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7196{
e08b9637
CO		 7197 if (type)
7198 return -EINVAL;
7199
f05e70ac 7200 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7201 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7202 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7203 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7204
5550af4d
SY		 7205 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7206 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7207 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7208 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7209 &kvm->arch.irq_sources_bitmap);
5550af4d 7210
038f8c11 7211 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7212 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7213 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7214
7215 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7216
7e44e449 7217 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7218 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7219
d89f5eff 7220 return 0;
d19a9cd2
ZX		 7221}
7222
7223static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7224{
9fc77441
MT		 7225 int r;
7226 r = vcpu_load(vcpu);
7227 BUG_ON(r);
d19a9cd2
ZX		 7228 kvm_mmu_unload(vcpu);
7229 vcpu_put(vcpu);
7230}
7231
7232static void kvm_free_vcpus(struct kvm *kvm)
7233{
7234 unsigned int i;
988a2cae 7235 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7236
7237 /*
7238 * Unpin any mmu pages first.
7239 */
af585b92
GN		 7240 kvm_for_each_vcpu(i, vcpu, kvm) {
7241 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7242 kvm_unload_vcpu_mmu(vcpu);
af585b92 7243 }
988a2cae
GN		 7244 kvm_for_each_vcpu(i, vcpu, kvm)
7245 kvm_arch_vcpu_free(vcpu);
7246
7247 mutex_lock(&kvm->lock);
7248 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7249 kvm->vcpus[i] = NULL;
d19a9cd2 7250
988a2cae
GN		 7251 atomic_set(&kvm->online_vcpus, 0);
7252 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7253}
7254
ad8ba2cd
SY		 7255void kvm_arch_sync_events(struct kvm *kvm)
7256{
332967a3 7257 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7258 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7259 kvm_free_all_assigned_devices(kvm);
aea924f6 7260 kvm_free_pit(kvm);
ad8ba2cd
SY		 7261}
7262
d19a9cd2
ZX		 7263void kvm_arch_destroy_vm(struct kvm *kvm)
7264{
27469d29
AH		 7265 if (current->mm == kvm->mm) {
7266 /*
7267 * Free memory regions allocated on behalf of userspace,
7268 * unless the the memory map has changed due to process exit
7269 * or fd copying.
7270 */
7271 struct kvm_userspace_memory_region mem;
7272 memset(&mem, 0, sizeof(mem));
7273 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7274 kvm_set_memory_region(kvm, &mem);
7275
7276 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7277 kvm_set_memory_region(kvm, &mem);
7278
7279 mem.slot = TSS_PRIVATE_MEMSLOT;
7280 kvm_set_memory_region(kvm, &mem);
7281 }
6eb55818 7282 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7283 kfree(kvm->arch.vpic);
7284 kfree(kvm->arch.vioapic);
d19a9cd2 7285 kvm_free_vcpus(kvm);
3d45830c
AK		 7286 if (kvm->arch.apic_access_page)
7287 put_page(kvm->arch.apic_access_page);
1e08ec4a 7288 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7289}
0de10343 7290
5587027c 7291void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7292 struct kvm_memory_slot *dont)
7293{
7294 int i;
7295
d89cc617
TY		 7296 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7297 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7298 kvm_kvfree(free->arch.rmap[i]);
7299 free->arch.rmap[i] = NULL;
77d11309 7300 }
d89cc617
TY		 7301 if (i == 0)
7302 continue;
7303
7304 if (!dont || free->arch.lpage_info[i - 1] !=
7305 dont->arch.lpage_info[i - 1]) {
7306 kvm_kvfree(free->arch.lpage_info[i - 1]);
7307 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7308 }
7309 }
7310}
7311
5587027c
AK		 7312int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7313 unsigned long npages)
db3fe4eb
TY		 7314{
7315 int i;
7316
d89cc617 7317 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7318 unsigned long ugfn;
7319 int lpages;
d89cc617 7320 int level = i + 1;
db3fe4eb
TY		 7321
7322 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7323 slot->base_gfn, level) + 1;
7324
d89cc617
TY		 7325 slot->arch.rmap[i] =
7326 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7327 if (!slot->arch.rmap[i])
77d11309 7328 goto out_free;
d89cc617
TY		 7329 if (i == 0)
7330 continue;
77d11309 7331
d89cc617
TY		 7332 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7333 sizeof(*slot->arch.lpage_info[i - 1]));
7334 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7335 goto out_free;
7336
7337 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7338 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7339 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7340 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7341 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7342 /*
7343 * If the gfn and userspace address are not aligned wrt each
7344 * other, or if explicitly asked to, disable large page
7345 * support for this slot
7346 */
7347 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7348 !kvm_largepages_enabled()) {
7349 unsigned long j;
7350
7351 for (j = 0; j < lpages; ++j)
d89cc617 7352 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7353 }
7354 }
7355
7356 return 0;
7357
7358out_free:
d89cc617
TY		 7359 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7360 kvm_kvfree(slot->arch.rmap[i]);
7361 slot->arch.rmap[i] = NULL;
7362 if (i == 0)
7363 continue;
7364
7365 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7366 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7367 }
7368 return -ENOMEM;
7369}
7370
e59dbe09
TY		 7371void kvm_arch_memslots_updated(struct kvm *kvm)
7372{
e6dff7d1
TY		 7373 /*
7374 * memslots->generation has been incremented.
7375 * mmio generation may have reached its maximum value.
7376 */
7377 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7378}
7379
f7784b8e
MT		 7380int kvm_arch_prepare_memory_region(struct kvm *kvm,
7381 struct kvm_memory_slot *memslot,
f7784b8e 7382 struct kvm_userspace_memory_region *mem,
7b6195a9 7383 enum kvm_mr_change change)
0de10343 7384{
7a905b14
TY		 7385 /*
7386 * Only private memory slots need to be mapped here since
7387 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7388 */
7b6195a9 7389 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7390 unsigned long userspace_addr;
604b38ac 7391
7a905b14
TY		 7392 /*
7393 * MAP_SHARED to prevent internal slot pages from being moved
7394 * by fork()/COW.
7395 */
7b6195a9 7396 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7397 PROT_READ | PROT_WRITE,
7398 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7399
7a905b14
TY		 7400 if (IS_ERR((void *)userspace_addr))
7401 return PTR_ERR((void *)userspace_addr);
604b38ac 7402
7a905b14 7403 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7404 }
7405
f7784b8e
MT		 7406 return 0;
7407}
7408
7409void kvm_arch_commit_memory_region(struct kvm *kvm,
7410 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7411 const struct kvm_memory_slot *old,
7412 enum kvm_mr_change change)
f7784b8e
MT		 7413{
7414
8482644a 7415 int nr_mmu_pages = 0;
f7784b8e 7416
8482644a 7417 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7418 int ret;
7419
8482644a
TY		 7420 ret = vm_munmap(old->userspace_addr,
7421 old->npages * PAGE_SIZE);
f7784b8e
MT		 7422 if (ret < 0)
7423 printk(KERN_WARNING
7424 "kvm_vm_ioctl_set_memory_region: "
7425 "failed to munmap memory\n");
7426 }
7427
48c0e4e9
XG		 7428 if (!kvm->arch.n_requested_mmu_pages)
7429 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7430
48c0e4e9 7431 if (nr_mmu_pages)
0de10343 7432 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7433 /*
7434 * Write protect all pages for dirty logging.
c126d94f
XG		 7435 *
7436 * All the sptes including the large sptes which point to this
7437 * slot are set to readonly. We can not create any new large
7438 * spte on this slot until the end of the logging.
7439 *
7440 * See the comments in fast_page_fault().
c972f3b1 7441 */
8482644a 7442 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7443 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7444}
1d737c8a 7445
2df72e9b 7446void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7447{
6ca18b69 7448 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7449}
7450
2df72e9b
MT		 7451void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7452 struct kvm_memory_slot *slot)
7453{
6ca18b69 7454 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7455}
7456
1d737c8a
ZX		 7457int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7458{
b6b8a145
JK		 7459 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7460 kvm_x86_ops->check_nested_events(vcpu, false);
7461
af585b92
GN		 7462 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7463 !vcpu->arch.apf.halted)
7464 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7465 || kvm_apic_has_events(vcpu)
6aef266c 7466 || vcpu->arch.pv.pv_unhalted
7460fb4a 7467 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7468 (kvm_arch_interrupt_allowed(vcpu) &&
7469 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7470}
5736199a 7471
b6d33834 7472int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7473{
b6d33834 7474 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7475}
78646121
GN		 7476
7477int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7478{
7479 return kvm_x86_ops->interrupt_allowed(vcpu);
7480}
229456fc 7481
f92653ee
JK		 7482bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7483{
7484 unsigned long current_rip = kvm_rip_read(vcpu) +
7485 get_segment_base(vcpu, VCPU_SREG_CS);
7486
7487 return current_rip == linear_rip;
7488}
7489EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7490
94fe45da
JK		 7491unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7492{
7493 unsigned long rflags;
7494
7495 rflags = kvm_x86_ops->get_rflags(vcpu);
7496 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7497 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7498 return rflags;
7499}
7500EXPORT_SYMBOL_GPL(kvm_get_rflags);
7501
6addfc42 7502static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7503{
7504 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7505 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7506 rflags |= X86_EFLAGS_TF;
94fe45da 7507 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7508}
7509
7510void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7511{
7512 __kvm_set_rflags(vcpu, rflags);
3842d135 7513 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7514}
7515EXPORT_SYMBOL_GPL(kvm_set_rflags);
7516
56028d08
GN		 7517void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7518{
7519 int r;
7520
fb67e14f 7521 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7522 work->wakeup_all)
56028d08
GN		 7523 return;
7524
7525 r = kvm_mmu_reload(vcpu);
7526 if (unlikely(r))
7527 return;
7528
fb67e14f
XG		 7529 if (!vcpu->arch.mmu.direct_map &&
7530 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7531 return;
7532
56028d08
GN		 7533 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7534}
7535
af585b92
GN		 7536static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7537{
7538 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7539}
7540
7541static inline u32 kvm_async_pf_next_probe(u32 key)
7542{
7543 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7544}
7545
7546static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7547{
7548 u32 key = kvm_async_pf_hash_fn(gfn);
7549
7550 while (vcpu->arch.apf.gfns[key] != ~0)
7551 key = kvm_async_pf_next_probe(key);
7552
7553 vcpu->arch.apf.gfns[key] = gfn;
7554}
7555
7556static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7557{
7558 int i;
7559 u32 key = kvm_async_pf_hash_fn(gfn);
7560
7561 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7562 (vcpu->arch.apf.gfns[key] != gfn &&
7563 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7564 key = kvm_async_pf_next_probe(key);
7565
7566 return key;
7567}
7568
7569bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7570{
7571 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7572}
7573
7574static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7575{
7576 u32 i, j, k;
7577
7578 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7579 while (true) {
7580 vcpu->arch.apf.gfns[i] = ~0;
7581 do {
7582 j = kvm_async_pf_next_probe(j);
7583 if (vcpu->arch.apf.gfns[j] == ~0)
7584 return;
7585 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7586 /*
7587 * k lies cyclically in ]i,j]
7588 * | i.k.j |
7589 * |....j i.k.| or |.k..j i...|
7590 */
7591 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7592 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7593 i = j;
7594 }
7595}
7596
7c90705b
GN		 7597static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7598{
7599
7600 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7601 sizeof(val));
7602}
7603
af585b92
GN		 7604void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7605 struct kvm_async_pf *work)
7606{
6389ee94
AK		 7607 struct x86_exception fault;
7608
7c90705b 7609 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7610 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7611
7612 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7613 (vcpu->arch.apf.send_user_only &&
7614 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7615 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7616 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7617 fault.vector = PF_VECTOR;
7618 fault.error_code_valid = true;
7619 fault.error_code = 0;
7620 fault.nested_page_fault = false;
7621 fault.address = work->arch.token;
7622 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7623 }
af585b92
GN		 7624}
7625
7626void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7627 struct kvm_async_pf *work)
7628{
6389ee94
AK		 7629 struct x86_exception fault;
7630
7c90705b 7631 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7632 if (work->wakeup_all)
7c90705b
GN		 7633 work->arch.token = ~0; /* broadcast wakeup */
7634 else
7635 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7636
7637 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7638 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7639 fault.vector = PF_VECTOR;
7640 fault.error_code_valid = true;
7641 fault.error_code = 0;
7642 fault.nested_page_fault = false;
7643 fault.address = work->arch.token;
7644 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7645 }
e6d53e3b 7646 vcpu->arch.apf.halted = false;
a4fa1635 7647 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7648}
7649
7650bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7651{
7652 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7653 return true;
7654 else
7655 return !kvm_event_needs_reinjection(vcpu) &&
7656 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7657}
7658
e0f0bbc5
AW		 7659void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7660{
7661 atomic_inc(&kvm->arch.noncoherent_dma_count);
7662}
7663EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7664
7665void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7666{
7667 atomic_dec(&kvm->arch.noncoherent_dma_count);
7668}
7669EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7670
7671bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7672{
7673 return atomic_read(&kvm->arch.noncoherent_dma_count);
7674}
7675EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7676
229456fc
MT		 7677EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7678EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7679EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
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