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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
313a3dc7 | 32 | |
18068523 | 33 | #include <linux/clocksource.h> |
4d5c5d0f | 34 | #include <linux/interrupt.h> |
313a3dc7 CO |
35 | #include <linux/kvm.h> |
36 | #include <linux/fs.h> | |
37 | #include <linux/vmalloc.h> | |
1767e931 PG |
38 | #include <linux/export.h> |
39 | #include <linux/moduleparam.h> | |
0de10343 | 40 | #include <linux/mman.h> |
2bacc55c | 41 | #include <linux/highmem.h> |
19de40a8 | 42 | #include <linux/iommu.h> |
62c476c7 | 43 | #include <linux/intel-iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
3905f9ad | 59 | |
aec51dc4 | 60 | #include <trace/events/kvm.h> |
2ed152af | 61 | |
24f1e32c | 62 | #include <asm/debugreg.h> |
d825ed0a | 63 | #include <asm/msr.h> |
a5f61300 | 64 | #include <asm/desc.h> |
890ca9ae | 65 | #include <asm/mce.h> |
f89e32e0 | 66 | #include <linux/kernel_stat.h> |
78f7f1e5 | 67 | #include <asm/fpu/internal.h> /* Ugh! */ |
1d5f066e | 68 | #include <asm/pvclock.h> |
217fc9cf | 69 | #include <asm/div64.h> |
efc64404 | 70 | #include <asm/irq_remapping.h> |
b0c39dc6 | 71 | #include <asm/mshyperv.h> |
0092e434 | 72 | #include <asm/hypervisor.h> |
bf8c55d8 | 73 | #include <asm/intel_pt.h> |
b3dc0695 | 74 | #include <asm/emulate_prefix.h> |
dd2cb348 | 75 | #include <clocksource/hyperv_timer.h> |
043405e1 | 76 | |
d1898b73 DH |
77 | #define CREATE_TRACE_POINTS |
78 | #include "trace.h" | |
79 | ||
313a3dc7 | 80 | #define MAX_IO_MSRS 256 |
890ca9ae | 81 | #define KVM_MAX_MCE_BANKS 32 |
c45dcc71 AR |
82 | u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; |
83 | EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); | |
890ca9ae | 84 | |
0f65dd70 | 85 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 86 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 87 | |
50a37eb4 JR |
88 | /* EFER defaults: |
89 | * - enable syscall per default because its emulated by KVM | |
90 | * - enable LME and LMA per default on 64 bit KVM | |
91 | */ | |
92 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
93 | static |
94 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 95 | #else |
1260edbe | 96 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 97 | #endif |
313a3dc7 | 98 | |
b11306b5 SC |
99 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
100 | ||
c519265f RK |
101 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
102 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 103 | |
cb142eb7 | 104 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 105 | static void process_nmi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 106 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 107 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
108 | static void store_regs(struct kvm_vcpu *vcpu); |
109 | static int sync_regs(struct kvm_vcpu *vcpu); | |
674eea0f | 110 | |
afaf0b2f | 111 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
5fdbf976 | 112 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 113 | |
893590c7 | 114 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 115 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 116 | |
fab0aa3b EM |
117 | static bool __read_mostly report_ignored_msrs = true; |
118 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); | |
119 | ||
4c27625b | 120 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
121 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
122 | ||
630994b3 MT |
123 | static bool __read_mostly kvmclock_periodic_sync = true; |
124 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
125 | ||
893590c7 | 126 | bool __read_mostly kvm_has_tsc_control; |
92a1f12d | 127 | EXPORT_SYMBOL_GPL(kvm_has_tsc_control); |
893590c7 | 128 | u32 __read_mostly kvm_max_guest_tsc_khz; |
92a1f12d | 129 | EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); |
bc9b961b HZ |
130 | u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; |
131 | EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); | |
132 | u64 __read_mostly kvm_max_tsc_scaling_ratio; | |
133 | EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); | |
64672c95 YJ |
134 | u64 __read_mostly kvm_default_tsc_scaling_ratio; |
135 | EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); | |
92a1f12d | 136 | |
cc578287 | 137 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 138 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
139 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
140 | ||
c3941d9e SC |
141 | /* |
142 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
143 | * adaptive tuning starting from default advancment of 1000ns. '0' disables | |
144 | * advancement entirely. Any other value is used as-is and disables adaptive | |
145 | * tuning, i.e. allows priveleged userspace to set an exact advancement time. | |
146 | */ | |
147 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 148 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 149 | |
52004014 FW |
150 | static bool __read_mostly vector_hashing = true; |
151 | module_param(vector_hashing, bool, S_IRUGO); | |
152 | ||
c4ae60e4 LA |
153 | bool __read_mostly enable_vmware_backdoor = false; |
154 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
155 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
156 | ||
6c86eedc WL |
157 | static bool __read_mostly force_emulation_prefix = false; |
158 | module_param(force_emulation_prefix, bool, S_IRUGO); | |
159 | ||
0c5f81da WL |
160 | int __read_mostly pi_inject_timer = -1; |
161 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
162 | ||
18863bdd AK |
163 | #define KVM_NR_SHARED_MSRS 16 |
164 | ||
165 | struct kvm_shared_msrs_global { | |
166 | int nr; | |
2bf78fa7 | 167 | u32 msrs[KVM_NR_SHARED_MSRS]; |
18863bdd AK |
168 | }; |
169 | ||
170 | struct kvm_shared_msrs { | |
171 | struct user_return_notifier urn; | |
172 | bool registered; | |
2bf78fa7 SY |
173 | struct kvm_shared_msr_values { |
174 | u64 host; | |
175 | u64 curr; | |
176 | } values[KVM_NR_SHARED_MSRS]; | |
18863bdd AK |
177 | }; |
178 | ||
179 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
013f6a5d | 180 | static struct kvm_shared_msrs __percpu *shared_msrs; |
18863bdd | 181 | |
cfc48181 SC |
182 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
183 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
184 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
185 | | XFEATURE_MASK_PKRU) | |
186 | ||
91661989 SC |
187 | u64 __read_mostly host_efer; |
188 | EXPORT_SYMBOL_GPL(host_efer); | |
189 | ||
139a12cf | 190 | static u64 __read_mostly host_xss; |
408e9a31 PB |
191 | u64 __read_mostly supported_xss; |
192 | EXPORT_SYMBOL_GPL(supported_xss); | |
139a12cf | 193 | |
417bc304 | 194 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
812756a8 EGE |
195 | VCPU_STAT("pf_fixed", pf_fixed), |
196 | VCPU_STAT("pf_guest", pf_guest), | |
197 | VCPU_STAT("tlb_flush", tlb_flush), | |
198 | VCPU_STAT("invlpg", invlpg), | |
199 | VCPU_STAT("exits", exits), | |
200 | VCPU_STAT("io_exits", io_exits), | |
201 | VCPU_STAT("mmio_exits", mmio_exits), | |
202 | VCPU_STAT("signal_exits", signal_exits), | |
203 | VCPU_STAT("irq_window", irq_window_exits), | |
204 | VCPU_STAT("nmi_window", nmi_window_exits), | |
205 | VCPU_STAT("halt_exits", halt_exits), | |
206 | VCPU_STAT("halt_successful_poll", halt_successful_poll), | |
207 | VCPU_STAT("halt_attempted_poll", halt_attempted_poll), | |
208 | VCPU_STAT("halt_poll_invalid", halt_poll_invalid), | |
209 | VCPU_STAT("halt_wakeup", halt_wakeup), | |
210 | VCPU_STAT("hypercalls", hypercalls), | |
211 | VCPU_STAT("request_irq", request_irq_exits), | |
212 | VCPU_STAT("irq_exits", irq_exits), | |
213 | VCPU_STAT("host_state_reload", host_state_reload), | |
214 | VCPU_STAT("fpu_reload", fpu_reload), | |
215 | VCPU_STAT("insn_emulation", insn_emulation), | |
216 | VCPU_STAT("insn_emulation_fail", insn_emulation_fail), | |
217 | VCPU_STAT("irq_injections", irq_injections), | |
218 | VCPU_STAT("nmi_injections", nmi_injections), | |
219 | VCPU_STAT("req_event", req_event), | |
220 | VCPU_STAT("l1d_flush", l1d_flush), | |
cb953129 DM |
221 | VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), |
222 | VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), | |
812756a8 EGE |
223 | VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), |
224 | VM_STAT("mmu_pte_write", mmu_pte_write), | |
225 | VM_STAT("mmu_pte_updated", mmu_pte_updated), | |
226 | VM_STAT("mmu_pde_zapped", mmu_pde_zapped), | |
227 | VM_STAT("mmu_flooded", mmu_flooded), | |
228 | VM_STAT("mmu_recycled", mmu_recycled), | |
229 | VM_STAT("mmu_cache_miss", mmu_cache_miss), | |
230 | VM_STAT("mmu_unsync", mmu_unsync), | |
231 | VM_STAT("remote_tlb_flush", remote_tlb_flush), | |
232 | VM_STAT("largepages", lpages, .mode = 0444), | |
233 | VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), | |
234 | VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), | |
417bc304 HB |
235 | { NULL } |
236 | }; | |
237 | ||
2acf923e | 238 | u64 __read_mostly host_xcr0; |
cfc48181 SC |
239 | u64 __read_mostly supported_xcr0; |
240 | EXPORT_SYMBOL_GPL(supported_xcr0); | |
2acf923e | 241 | |
80fbd280 | 242 | static struct kmem_cache *x86_fpu_cache; |
b666a4b6 | 243 | |
c9b8b07c SC |
244 | static struct kmem_cache *x86_emulator_cache; |
245 | ||
6abe9c13 PX |
246 | /* |
247 | * When called, it means the previous get/set msr reached an invalid msr. | |
248 | * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want | |
249 | * to fail the caller. | |
250 | */ | |
251 | static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, | |
252 | u64 data, bool write) | |
253 | { | |
254 | const char *op = write ? "wrmsr" : "rdmsr"; | |
255 | ||
256 | if (ignore_msrs) { | |
257 | if (report_ignored_msrs) | |
258 | vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n", | |
259 | op, msr, data); | |
260 | /* Mask the error */ | |
261 | return 0; | |
262 | } else { | |
263 | vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n", | |
264 | op, msr, data); | |
265 | return 1; | |
266 | } | |
267 | } | |
268 | ||
c9b8b07c SC |
269 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
270 | { | |
06add254 SC |
271 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
272 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
273 | ||
274 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 275 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
276 | SLAB_ACCOUNT, useroffset, |
277 | size - useroffset, NULL); | |
c9b8b07c SC |
278 | } |
279 | ||
b6785def | 280 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 281 | |
af585b92 GN |
282 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
283 | { | |
284 | int i; | |
dd03bcaa | 285 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
286 | vcpu->arch.apf.gfns[i] = ~0; |
287 | } | |
288 | ||
18863bdd AK |
289 | static void kvm_on_user_return(struct user_return_notifier *urn) |
290 | { | |
291 | unsigned slot; | |
18863bdd AK |
292 | struct kvm_shared_msrs *locals |
293 | = container_of(urn, struct kvm_shared_msrs, urn); | |
2bf78fa7 | 294 | struct kvm_shared_msr_values *values; |
1650b4eb IA |
295 | unsigned long flags; |
296 | ||
297 | /* | |
298 | * Disabling irqs at this point since the following code could be | |
299 | * interrupted and executed through kvm_arch_hardware_disable() | |
300 | */ | |
301 | local_irq_save(flags); | |
302 | if (locals->registered) { | |
303 | locals->registered = false; | |
304 | user_return_notifier_unregister(urn); | |
305 | } | |
306 | local_irq_restore(flags); | |
18863bdd | 307 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { |
2bf78fa7 SY |
308 | values = &locals->values[slot]; |
309 | if (values->host != values->curr) { | |
310 | wrmsrl(shared_msrs_global.msrs[slot], values->host); | |
311 | values->curr = values->host; | |
18863bdd AK |
312 | } |
313 | } | |
18863bdd AK |
314 | } |
315 | ||
2bf78fa7 SY |
316 | void kvm_define_shared_msr(unsigned slot, u32 msr) |
317 | { | |
0123be42 | 318 | BUG_ON(slot >= KVM_NR_SHARED_MSRS); |
c847fe88 | 319 | shared_msrs_global.msrs[slot] = msr; |
18863bdd AK |
320 | if (slot >= shared_msrs_global.nr) |
321 | shared_msrs_global.nr = slot + 1; | |
18863bdd AK |
322 | } |
323 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
324 | ||
325 | static void kvm_shared_msr_cpu_online(void) | |
326 | { | |
05c19c2f SC |
327 | unsigned int cpu = smp_processor_id(); |
328 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
329 | u64 value; | |
330 | int i; | |
18863bdd | 331 | |
05c19c2f SC |
332 | for (i = 0; i < shared_msrs_global.nr; ++i) { |
333 | rdmsrl_safe(shared_msrs_global.msrs[i], &value); | |
334 | smsr->values[i].host = value; | |
335 | smsr->values[i].curr = value; | |
336 | } | |
18863bdd AK |
337 | } |
338 | ||
8b3c3104 | 339 | int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 340 | { |
013f6a5d MT |
341 | unsigned int cpu = smp_processor_id(); |
342 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
8b3c3104 | 343 | int err; |
18863bdd | 344 | |
de1fca5d PB |
345 | value = (value & mask) | (smsr->values[slot].host & ~mask); |
346 | if (value == smsr->values[slot].curr) | |
8b3c3104 | 347 | return 0; |
8b3c3104 AH |
348 | err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); |
349 | if (err) | |
350 | return 1; | |
351 | ||
de1fca5d | 352 | smsr->values[slot].curr = value; |
18863bdd AK |
353 | if (!smsr->registered) { |
354 | smsr->urn.on_user_return = kvm_on_user_return; | |
355 | user_return_notifier_register(&smsr->urn); | |
356 | smsr->registered = true; | |
357 | } | |
8b3c3104 | 358 | return 0; |
18863bdd AK |
359 | } |
360 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
361 | ||
13a34e06 | 362 | static void drop_user_return_notifiers(void) |
3548bab5 | 363 | { |
013f6a5d MT |
364 | unsigned int cpu = smp_processor_id(); |
365 | struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); | |
3548bab5 AK |
366 | |
367 | if (smsr->registered) | |
368 | kvm_on_user_return(&smsr->urn); | |
369 | } | |
370 | ||
6866b83e CO |
371 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
372 | { | |
8a5a87d9 | 373 | return vcpu->arch.apic_base; |
6866b83e CO |
374 | } |
375 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
376 | ||
58871649 JM |
377 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
378 | { | |
379 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
380 | } | |
381 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
382 | ||
58cb628d JK |
383 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384 | { | |
58871649 JM |
385 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
386 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
d6321d49 RK |
387 | u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | |
388 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); | |
58cb628d | 389 | |
58871649 | 390 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 391 | return 1; |
58871649 JM |
392 | if (!msr_info->host_initiated) { |
393 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
394 | return 1; | |
395 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
396 | return 1; | |
397 | } | |
58cb628d JK |
398 | |
399 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 400 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 401 | return 0; |
6866b83e CO |
402 | } |
403 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
404 | ||
3ebccdf3 | 405 | asmlinkage __visible noinstr void kvm_spurious_fault(void) |
e3ba45b8 GL |
406 | { |
407 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 408 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
409 | } |
410 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
411 | ||
3fd28fce ED |
412 | #define EXCPT_BENIGN 0 |
413 | #define EXCPT_CONTRIBUTORY 1 | |
414 | #define EXCPT_PF 2 | |
415 | ||
416 | static int exception_class(int vector) | |
417 | { | |
418 | switch (vector) { | |
419 | case PF_VECTOR: | |
420 | return EXCPT_PF; | |
421 | case DE_VECTOR: | |
422 | case TS_VECTOR: | |
423 | case NP_VECTOR: | |
424 | case SS_VECTOR: | |
425 | case GP_VECTOR: | |
426 | return EXCPT_CONTRIBUTORY; | |
427 | default: | |
428 | break; | |
429 | } | |
430 | return EXCPT_BENIGN; | |
431 | } | |
432 | ||
d6e8c854 NA |
433 | #define EXCPT_FAULT 0 |
434 | #define EXCPT_TRAP 1 | |
435 | #define EXCPT_ABORT 2 | |
436 | #define EXCPT_INTERRUPT 3 | |
437 | ||
438 | static int exception_type(int vector) | |
439 | { | |
440 | unsigned int mask; | |
441 | ||
442 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
443 | return EXCPT_INTERRUPT; | |
444 | ||
445 | mask = 1 << vector; | |
446 | ||
447 | /* #DB is trap, as instruction watchpoints are handled elsewhere */ | |
448 | if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
449 | return EXCPT_TRAP; | |
450 | ||
451 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
452 | return EXCPT_ABORT; | |
453 | ||
454 | /* Reserved exceptions will result in fault */ | |
455 | return EXCPT_FAULT; | |
456 | } | |
457 | ||
da998b46 JM |
458 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
459 | { | |
460 | unsigned nr = vcpu->arch.exception.nr; | |
461 | bool has_payload = vcpu->arch.exception.has_payload; | |
462 | unsigned long payload = vcpu->arch.exception.payload; | |
463 | ||
464 | if (!has_payload) | |
465 | return; | |
466 | ||
467 | switch (nr) { | |
f10c729f JM |
468 | case DB_VECTOR: |
469 | /* | |
470 | * "Certain debug exceptions may clear bit 0-3. The | |
471 | * remaining contents of the DR6 register are never | |
472 | * cleared by the processor". | |
473 | */ | |
474 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
475 | /* | |
476 | * DR6.RTM is set by all #DB exceptions that don't clear it. | |
477 | */ | |
478 | vcpu->arch.dr6 |= DR6_RTM; | |
479 | vcpu->arch.dr6 |= payload; | |
480 | /* | |
481 | * Bit 16 should be set in the payload whenever the #DB | |
482 | * exception should clear DR6.RTM. This makes the payload | |
483 | * compatible with the pending debug exceptions under VMX. | |
484 | * Though not currently documented in the SDM, this also | |
485 | * makes the payload compatible with the exit qualification | |
486 | * for #DB exceptions under VMX. | |
487 | */ | |
488 | vcpu->arch.dr6 ^= payload & DR6_RTM; | |
307f1cfa OU |
489 | |
490 | /* | |
491 | * The #DB payload is defined as compatible with the 'pending | |
492 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
493 | * defined in the 'pending debug exceptions' field (enabled | |
494 | * breakpoint), it is reserved and must be zero in DR6. | |
495 | */ | |
496 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 497 | break; |
da998b46 JM |
498 | case PF_VECTOR: |
499 | vcpu->arch.cr2 = payload; | |
500 | break; | |
501 | } | |
502 | ||
503 | vcpu->arch.exception.has_payload = false; | |
504 | vcpu->arch.exception.payload = 0; | |
505 | } | |
506 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
507 | ||
3fd28fce | 508 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 509 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 510 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
511 | { |
512 | u32 prev_nr; | |
513 | int class1, class2; | |
514 | ||
3842d135 AK |
515 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
516 | ||
664f8e26 | 517 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 518 | queue: |
3ffb2468 NA |
519 | if (has_error && !is_protmode(vcpu)) |
520 | has_error = false; | |
664f8e26 WL |
521 | if (reinject) { |
522 | /* | |
523 | * On vmentry, vcpu->arch.exception.pending is only | |
524 | * true if an event injection was blocked by | |
525 | * nested_run_pending. In that case, however, | |
526 | * vcpu_enter_guest requests an immediate exit, | |
527 | * and the guest shouldn't proceed far enough to | |
528 | * need reinjection. | |
529 | */ | |
530 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
531 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
532 | if (WARN_ON_ONCE(has_payload)) { |
533 | /* | |
534 | * A reinjected event has already | |
535 | * delivered its payload. | |
536 | */ | |
537 | has_payload = false; | |
538 | payload = 0; | |
539 | } | |
664f8e26 WL |
540 | } else { |
541 | vcpu->arch.exception.pending = true; | |
542 | vcpu->arch.exception.injected = false; | |
543 | } | |
3fd28fce ED |
544 | vcpu->arch.exception.has_error_code = has_error; |
545 | vcpu->arch.exception.nr = nr; | |
546 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
547 | vcpu->arch.exception.has_payload = has_payload; |
548 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 549 | if (!is_guest_mode(vcpu)) |
da998b46 | 550 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
551 | return; |
552 | } | |
553 | ||
554 | /* to check exception */ | |
555 | prev_nr = vcpu->arch.exception.nr; | |
556 | if (prev_nr == DF_VECTOR) { | |
557 | /* triple fault -> shutdown */ | |
a8eeb04a | 558 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
559 | return; |
560 | } | |
561 | class1 = exception_class(prev_nr); | |
562 | class2 = exception_class(nr); | |
563 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
564 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
565 | /* |
566 | * Generate double fault per SDM Table 5-5. Set | |
567 | * exception.pending = true so that the double fault | |
568 | * can trigger a nested vmexit. | |
569 | */ | |
3fd28fce | 570 | vcpu->arch.exception.pending = true; |
664f8e26 | 571 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
572 | vcpu->arch.exception.has_error_code = true; |
573 | vcpu->arch.exception.nr = DF_VECTOR; | |
574 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
575 | vcpu->arch.exception.has_payload = false; |
576 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
577 | } else |
578 | /* replace previous exception with a new one in a hope | |
579 | that instruction re-execution will regenerate lost | |
580 | exception */ | |
581 | goto queue; | |
582 | } | |
583 | ||
298101da AK |
584 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
585 | { | |
91e86d22 | 586 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
587 | } |
588 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
589 | ||
ce7ddec4 JR |
590 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
591 | { | |
91e86d22 | 592 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
593 | } |
594 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
595 | ||
4d5523cf PB |
596 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
597 | unsigned long payload) | |
f10c729f JM |
598 | { |
599 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
600 | } | |
4d5523cf | 601 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 602 | |
da998b46 JM |
603 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
604 | u32 error_code, unsigned long payload) | |
605 | { | |
606 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
607 | true, payload, false); | |
608 | } | |
609 | ||
6affcbed | 610 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 611 | { |
db8fcefa AP |
612 | if (err) |
613 | kvm_inject_gp(vcpu, 0); | |
614 | else | |
6affcbed KH |
615 | return kvm_skip_emulated_instruction(vcpu); |
616 | ||
617 | return 1; | |
db8fcefa AP |
618 | } |
619 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 620 | |
6389ee94 | 621 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
622 | { |
623 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
624 | vcpu->arch.exception.nested_apf = |
625 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 626 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 627 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
628 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
629 | } else { | |
630 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
631 | fault->address); | |
632 | } | |
c3c91fee | 633 | } |
27d6c865 | 634 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 635 | |
53b3d8e9 SC |
636 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
637 | struct x86_exception *fault) | |
d4f8cf66 | 638 | { |
0cd665bd | 639 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
640 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
641 | ||
0cd665bd PB |
642 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
643 | vcpu->arch.walk_mmu; | |
ef54bcfe | 644 | |
ee1fa209 JS |
645 | /* |
646 | * Invalidate the TLB entry for the faulting address, if it exists, | |
647 | * else the access will fault indefinitely (and to emulate hardware). | |
648 | */ | |
649 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
650 | !(fault->error_code & PFERR_RSVD_MASK)) | |
651 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
652 | fault_mmu->root_hpa); | |
653 | ||
654 | fault_mmu->inject_page_fault(vcpu, fault); | |
ef54bcfe | 655 | return fault->nested_page_fault; |
d4f8cf66 | 656 | } |
53b3d8e9 | 657 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 658 | |
3419ffc8 SY |
659 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
660 | { | |
7460fb4a AK |
661 | atomic_inc(&vcpu->arch.nmi_queued); |
662 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
663 | } |
664 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
665 | ||
298101da AK |
666 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
667 | { | |
91e86d22 | 668 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
669 | } |
670 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
671 | ||
ce7ddec4 JR |
672 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
673 | { | |
91e86d22 | 674 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
675 | } |
676 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
677 | ||
0a79b009 AK |
678 | /* |
679 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
680 | * a #GP and return false. | |
681 | */ | |
682 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 683 | { |
afaf0b2f | 684 | if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) |
0a79b009 AK |
685 | return true; |
686 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
687 | return false; | |
298101da | 688 | } |
0a79b009 | 689 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 690 | |
16f8a6f9 NA |
691 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
692 | { | |
693 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
694 | return true; | |
695 | ||
696 | kvm_queue_exception(vcpu, UD_VECTOR); | |
697 | return false; | |
698 | } | |
699 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
700 | ||
ec92fe44 JR |
701 | /* |
702 | * This function will be used to read from the physical memory of the currently | |
54bf36aa | 703 | * running guest. The difference to kvm_vcpu_read_guest_page is that this function |
ec92fe44 JR |
704 | * can read from guest physical or from the guest's guest physical memory. |
705 | */ | |
706 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
707 | gfn_t ngfn, void *data, int offset, int len, | |
708 | u32 access) | |
709 | { | |
54987b7a | 710 | struct x86_exception exception; |
ec92fe44 JR |
711 | gfn_t real_gfn; |
712 | gpa_t ngpa; | |
713 | ||
714 | ngpa = gfn_to_gpa(ngfn); | |
54987b7a | 715 | real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); |
ec92fe44 JR |
716 | if (real_gfn == UNMAPPED_GVA) |
717 | return -EFAULT; | |
718 | ||
719 | real_gfn = gpa_to_gfn(real_gfn); | |
720 | ||
54bf36aa | 721 | return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); |
ec92fe44 JR |
722 | } |
723 | EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); | |
724 | ||
69b0049a | 725 | static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, |
3d06b8bf JR |
726 | void *data, int offset, int len, u32 access) |
727 | { | |
728 | return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, | |
729 | data, offset, len, access); | |
730 | } | |
731 | ||
16cfacc8 SC |
732 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
733 | { | |
734 | return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | | |
735 | rsvd_bits(1, 2); | |
736 | } | |
737 | ||
a03490ed | 738 | /* |
16cfacc8 | 739 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 740 | */ |
ff03a073 | 741 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) |
a03490ed CO |
742 | { |
743 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
744 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
745 | int i; | |
746 | int ret; | |
ff03a073 | 747 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 748 | |
ff03a073 JR |
749 | ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, |
750 | offset * sizeof(u64), sizeof(pdpte), | |
751 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
a03490ed CO |
752 | if (ret < 0) { |
753 | ret = 0; | |
754 | goto out; | |
755 | } | |
756 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
812f30b2 | 757 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 758 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
a03490ed CO |
759 | ret = 0; |
760 | goto out; | |
761 | } | |
762 | } | |
763 | ret = 1; | |
764 | ||
ff03a073 | 765 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
cb3c1e2f SC |
766 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); |
767 | ||
a03490ed | 768 | out: |
a03490ed CO |
769 | |
770 | return ret; | |
771 | } | |
cc4b6871 | 772 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 773 | |
9ed38ffa | 774 | bool pdptrs_changed(struct kvm_vcpu *vcpu) |
d835dfec | 775 | { |
ff03a073 | 776 | u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; |
3d06b8bf JR |
777 | int offset; |
778 | gfn_t gfn; | |
d835dfec AK |
779 | int r; |
780 | ||
bf03d4f9 | 781 | if (!is_pae_paging(vcpu)) |
d835dfec AK |
782 | return false; |
783 | ||
cb3c1e2f | 784 | if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) |
6de4f3ad AK |
785 | return true; |
786 | ||
a512177e PB |
787 | gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; |
788 | offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); | |
3d06b8bf JR |
789 | r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), |
790 | PFERR_USER_MASK | PFERR_WRITE_MASK); | |
d835dfec | 791 | if (r < 0) |
7f7f0d9c | 792 | return true; |
d835dfec | 793 | |
7f7f0d9c | 794 | return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 795 | } |
9ed38ffa | 796 | EXPORT_SYMBOL_GPL(pdptrs_changed); |
d835dfec | 797 | |
49a9b07e | 798 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 799 | { |
aad82703 | 800 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
d42e3fae | 801 | unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; |
d81135a5 | 802 | unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; |
aad82703 | 803 | |
f9a48e6a AK |
804 | cr0 |= X86_CR0_ET; |
805 | ||
ab344828 | 806 | #ifdef CONFIG_X86_64 |
0f12244f GN |
807 | if (cr0 & 0xffffffff00000000UL) |
808 | return 1; | |
ab344828 GN |
809 | #endif |
810 | ||
811 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 812 | |
0f12244f GN |
813 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
814 | return 1; | |
a03490ed | 815 | |
0f12244f GN |
816 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
817 | return 1; | |
a03490ed | 818 | |
d42e3fae | 819 | if (cr0 & X86_CR0_PG) { |
a03490ed | 820 | #ifdef CONFIG_X86_64 |
d42e3fae | 821 | if (!is_paging(vcpu) && (vcpu->arch.efer & EFER_LME)) { |
a03490ed CO |
822 | int cs_db, cs_l; |
823 | ||
0f12244f GN |
824 | if (!is_pae(vcpu)) |
825 | return 1; | |
afaf0b2f | 826 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
0f12244f GN |
827 | if (cs_l) |
828 | return 1; | |
a03490ed CO |
829 | } else |
830 | #endif | |
d42e3fae JM |
831 | if (is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && |
832 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) | |
0f12244f | 833 | return 1; |
a03490ed CO |
834 | } |
835 | ||
ad756a16 MJ |
836 | if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) |
837 | return 1; | |
838 | ||
afaf0b2f | 839 | kvm_x86_ops.set_cr0(vcpu, cr0); |
a03490ed | 840 | |
d170c419 | 841 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
e5f3f027 | 842 | kvm_clear_async_pf_completion_queue(vcpu); |
d170c419 LJ |
843 | kvm_async_pf_hash_reset(vcpu); |
844 | } | |
e5f3f027 | 845 | |
aad82703 SY |
846 | if ((cr0 ^ old_cr0) & update_bits) |
847 | kvm_mmu_reset_context(vcpu); | |
b18d5431 | 848 | |
879ae188 LE |
849 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && |
850 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
851 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
b18d5431 XG |
852 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); |
853 | ||
0f12244f GN |
854 | return 0; |
855 | } | |
2d3ad1f4 | 856 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 857 | |
2d3ad1f4 | 858 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 859 | { |
49a9b07e | 860 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 861 | } |
2d3ad1f4 | 862 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 863 | |
139a12cf | 864 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 865 | { |
139a12cf AL |
866 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
867 | ||
868 | if (vcpu->arch.xcr0 != host_xcr0) | |
869 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
870 | ||
871 | if (vcpu->arch.xsaves_enabled && | |
872 | vcpu->arch.ia32_xss != host_xss) | |
873 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
874 | } | |
37486135 BM |
875 | |
876 | if (static_cpu_has(X86_FEATURE_PKU) && | |
877 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
878 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && | |
879 | vcpu->arch.pkru != vcpu->arch.host_pkru) | |
880 | __write_pkru(vcpu->arch.pkru); | |
42bdf991 | 881 | } |
139a12cf | 882 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 883 | |
139a12cf | 884 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 885 | { |
37486135 BM |
886 | if (static_cpu_has(X86_FEATURE_PKU) && |
887 | (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || | |
888 | (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { | |
889 | vcpu->arch.pkru = rdpkru(); | |
890 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
891 | __write_pkru(vcpu->arch.host_pkru); | |
892 | } | |
893 | ||
139a12cf AL |
894 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
895 | ||
896 | if (vcpu->arch.xcr0 != host_xcr0) | |
897 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
898 | ||
899 | if (vcpu->arch.xsaves_enabled && | |
900 | vcpu->arch.ia32_xss != host_xss) | |
901 | wrmsrl(MSR_IA32_XSS, host_xss); | |
902 | } | |
903 | ||
42bdf991 | 904 | } |
139a12cf | 905 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 906 | |
69b0049a | 907 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 908 | { |
56c103ec LJ |
909 | u64 xcr0 = xcr; |
910 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 911 | u64 valid_bits; |
2acf923e DC |
912 | |
913 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
914 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
915 | return 1; | |
d91cab78 | 916 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 917 | return 1; |
d91cab78 | 918 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 919 | return 1; |
46c34cb0 PB |
920 | |
921 | /* | |
922 | * Do not allow the guest to set bits that we do not support | |
923 | * saving. However, xcr0 bit 0 is always set, even if the | |
924 | * emulated CPU does not support XSAVE (see fx_init). | |
925 | */ | |
d91cab78 | 926 | valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; |
46c34cb0 | 927 | if (xcr0 & ~valid_bits) |
2acf923e | 928 | return 1; |
46c34cb0 | 929 | |
d91cab78 DH |
930 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
931 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
932 | return 1; |
933 | ||
d91cab78 DH |
934 | if (xcr0 & XFEATURE_MASK_AVX512) { |
935 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 936 | return 1; |
d91cab78 | 937 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
938 | return 1; |
939 | } | |
2acf923e | 940 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 941 | |
d91cab78 | 942 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 943 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
944 | return 0; |
945 | } | |
946 | ||
947 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) | |
948 | { | |
afaf0b2f | 949 | if (kvm_x86_ops.get_cpl(vcpu) != 0 || |
764bcbc5 | 950 | __kvm_set_xcr(vcpu, index, xcr)) { |
2acf923e DC |
951 | kvm_inject_gp(vcpu, 0); |
952 | return 1; | |
953 | } | |
954 | return 0; | |
955 | } | |
956 | EXPORT_SYMBOL_GPL(kvm_set_xcr); | |
957 | ||
761e4169 | 958 | int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 959 | { |
b11306b5 | 960 | if (cr4 & cr4_reserved_bits) |
3ca94192 | 961 | return -EINVAL; |
b9baba86 | 962 | |
b899c132 | 963 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
3ca94192 WL |
964 | return -EINVAL; |
965 | ||
966 | return 0; | |
967 | } | |
761e4169 | 968 | EXPORT_SYMBOL_GPL(kvm_valid_cr4); |
3ca94192 WL |
969 | |
970 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
971 | { | |
972 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
973 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | | |
974 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; | |
975 | ||
976 | if (kvm_valid_cr4(vcpu, cr4)) | |
ae3e61e1 PB |
977 | return 1; |
978 | ||
a03490ed | 979 | if (is_long_mode(vcpu)) { |
0f12244f GN |
980 | if (!(cr4 & X86_CR4_PAE)) |
981 | return 1; | |
d74fcfc1 SC |
982 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
983 | return 1; | |
a2edf57f AK |
984 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
985 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
9f8fe504 AK |
986 | && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, |
987 | kvm_read_cr3(vcpu))) | |
0f12244f GN |
988 | return 1; |
989 | ||
ad756a16 | 990 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 991 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
992 | return 1; |
993 | ||
994 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
995 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
996 | return 1; | |
997 | } | |
998 | ||
afaf0b2f | 999 | if (kvm_x86_ops.set_cr4(vcpu, cr4)) |
0f12244f | 1000 | return 1; |
a03490ed | 1001 | |
ad756a16 MJ |
1002 | if (((cr4 ^ old_cr4) & pdptr_bits) || |
1003 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
aad82703 | 1004 | kvm_mmu_reset_context(vcpu); |
0f12244f | 1005 | |
b9baba86 | 1006 | if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) |
aedbaf4f | 1007 | kvm_update_cpuid_runtime(vcpu); |
2acf923e | 1008 | |
0f12244f GN |
1009 | return 0; |
1010 | } | |
2d3ad1f4 | 1011 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1012 | |
2390218b | 1013 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1014 | { |
ade61e28 | 1015 | bool skip_tlb_flush = false; |
ac146235 | 1016 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1017 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1018 | ||
ade61e28 | 1019 | if (pcid_enabled) { |
208320ba JS |
1020 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1021 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
ade61e28 | 1022 | } |
ac146235 | 1023 | #endif |
9d88fca7 | 1024 | |
9f8fe504 | 1025 | if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { |
956bf353 JS |
1026 | if (!skip_tlb_flush) { |
1027 | kvm_mmu_sync_roots(vcpu); | |
eeeb4f67 | 1028 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
956bf353 | 1029 | } |
0f12244f | 1030 | return 0; |
d835dfec AK |
1031 | } |
1032 | ||
d1cd3ce9 | 1033 | if (is_long_mode(vcpu) && |
a780a3ea | 1034 | (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) |
d1cd3ce9 | 1035 | return 1; |
bf03d4f9 PB |
1036 | else if (is_pae_paging(vcpu) && |
1037 | !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) | |
346874c9 | 1038 | return 1; |
a03490ed | 1039 | |
be01e8e2 | 1040 | kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); |
0f12244f | 1041 | vcpu->arch.cr3 = cr3; |
cb3c1e2f | 1042 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
7c390d35 | 1043 | |
0f12244f GN |
1044 | return 0; |
1045 | } | |
2d3ad1f4 | 1046 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1047 | |
eea1cff9 | 1048 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1049 | { |
0f12244f GN |
1050 | if (cr8 & CR8_RESERVED_BITS) |
1051 | return 1; | |
35754c98 | 1052 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1053 | kvm_lapic_set_tpr(vcpu, cr8); |
1054 | else | |
ad312c7c | 1055 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1056 | return 0; |
1057 | } | |
2d3ad1f4 | 1058 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1059 | |
2d3ad1f4 | 1060 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1061 | { |
35754c98 | 1062 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1063 | return kvm_lapic_get_cr8(vcpu); |
1064 | else | |
ad312c7c | 1065 | return vcpu->arch.cr8; |
a03490ed | 1066 | } |
2d3ad1f4 | 1067 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1068 | |
ae561ede NA |
1069 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1070 | { | |
1071 | int i; | |
1072 | ||
1073 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1074 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1075 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
1076 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; | |
1077 | } | |
1078 | } | |
1079 | ||
7c86663b | 1080 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1081 | { |
1082 | unsigned long dr7; | |
1083 | ||
1084 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1085 | dr7 = vcpu->arch.guest_debug_dr7; | |
1086 | else | |
1087 | dr7 = vcpu->arch.dr7; | |
afaf0b2f | 1088 | kvm_x86_ops.set_dr7(vcpu, dr7); |
360b948d PB |
1089 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1090 | if (dr7 & DR7_BP_EN_MASK) | |
1091 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1092 | } |
7c86663b | 1093 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1094 | |
6f43ed01 NA |
1095 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1096 | { | |
1097 | u64 fixed = DR6_FIXED_1; | |
1098 | ||
d6321d49 | 1099 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 NA |
1100 | fixed |= DR6_RTM; |
1101 | return fixed; | |
1102 | } | |
1103 | ||
338dbc97 | 1104 | static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1105 | { |
ea740059 MP |
1106 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1107 | ||
020df079 GN |
1108 | switch (dr) { |
1109 | case 0 ... 3: | |
ea740059 | 1110 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1111 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1112 | vcpu->arch.eff_db[dr] = val; | |
1113 | break; | |
1114 | case 4: | |
020df079 GN |
1115 | /* fall through */ |
1116 | case 6: | |
f5f6145e | 1117 | if (!kvm_dr6_valid(val)) |
338dbc97 | 1118 | return -1; /* #GP */ |
6f43ed01 | 1119 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1120 | break; |
1121 | case 5: | |
020df079 GN |
1122 | /* fall through */ |
1123 | default: /* 7 */ | |
b91991bf | 1124 | if (!kvm_dr7_valid(val)) |
338dbc97 | 1125 | return -1; /* #GP */ |
020df079 | 1126 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1127 | kvm_update_dr7(vcpu); |
020df079 GN |
1128 | break; |
1129 | } | |
1130 | ||
1131 | return 0; | |
1132 | } | |
338dbc97 GN |
1133 | |
1134 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) | |
1135 | { | |
16f8a6f9 | 1136 | if (__kvm_set_dr(vcpu, dr, val)) { |
338dbc97 | 1137 | kvm_inject_gp(vcpu, 0); |
16f8a6f9 NA |
1138 | return 1; |
1139 | } | |
1140 | return 0; | |
338dbc97 | 1141 | } |
020df079 GN |
1142 | EXPORT_SYMBOL_GPL(kvm_set_dr); |
1143 | ||
16f8a6f9 | 1144 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1145 | { |
ea740059 MP |
1146 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1147 | ||
020df079 GN |
1148 | switch (dr) { |
1149 | case 0 ... 3: | |
ea740059 | 1150 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1151 | break; |
1152 | case 4: | |
020df079 GN |
1153 | /* fall through */ |
1154 | case 6: | |
5679b803 | 1155 | *val = vcpu->arch.dr6; |
020df079 GN |
1156 | break; |
1157 | case 5: | |
020df079 GN |
1158 | /* fall through */ |
1159 | default: /* 7 */ | |
1160 | *val = vcpu->arch.dr7; | |
1161 | break; | |
1162 | } | |
338dbc97 GN |
1163 | return 0; |
1164 | } | |
020df079 GN |
1165 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1166 | ||
022cd0e8 AK |
1167 | bool kvm_rdpmc(struct kvm_vcpu *vcpu) |
1168 | { | |
de3cd117 | 1169 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 AK |
1170 | u64 data; |
1171 | int err; | |
1172 | ||
c6702c9d | 1173 | err = kvm_pmu_rdpmc(vcpu, ecx, &data); |
022cd0e8 AK |
1174 | if (err) |
1175 | return err; | |
de3cd117 SC |
1176 | kvm_rax_write(vcpu, (u32)data); |
1177 | kvm_rdx_write(vcpu, data >> 32); | |
022cd0e8 AK |
1178 | return err; |
1179 | } | |
1180 | EXPORT_SYMBOL_GPL(kvm_rdpmc); | |
1181 | ||
043405e1 CO |
1182 | /* |
1183 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1184 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1185 | * | |
7a5ee6ed CQ |
1186 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1187 | * extract the supported MSRs from the related const lists. | |
1188 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1189 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1190 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1191 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1192 | */ |
e3267cbb | 1193 | |
7a5ee6ed | 1194 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1195 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1196 | MSR_STAR, |
043405e1 CO |
1197 | #ifdef CONFIG_X86_64 |
1198 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1199 | #endif | |
b3897a49 | 1200 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1201 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1202 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1203 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1204 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1205 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1206 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1207 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1208 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1209 | MSR_IA32_UMWAIT_CONTROL, |
1210 | ||
e2ada66e JM |
1211 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
1212 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, | |
1213 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, | |
1214 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1215 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1216 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1217 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1218 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1219 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1220 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1221 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1222 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1223 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1224 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1225 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1226 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1227 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1228 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1229 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1230 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1231 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1232 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
043405e1 CO |
1233 | }; |
1234 | ||
7a5ee6ed | 1235 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1236 | static unsigned num_msrs_to_save; |
1237 | ||
7a5ee6ed | 1238 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1239 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1240 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1241 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1242 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1243 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1244 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1245 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1246 | HV_X64_MSR_RESET, |
11c4b1ca | 1247 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1248 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1249 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1250 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1251 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1252 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1253 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1254 | HV_X64_MSR_SYNDBG_OPTIONS, |
1255 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1256 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1257 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1258 | |
1259 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1260 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1261 | |
ba904635 | 1262 | MSR_IA32_TSC_ADJUST, |
a3e06bbe | 1263 | MSR_IA32_TSCDEADLINE, |
2bdb76c0 | 1264 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1265 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1266 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1267 | MSR_IA32_MCG_STATUS, |
1268 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1269 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1270 | MSR_IA32_SMBASE, |
52797bf9 | 1271 | MSR_SMI_COUNT, |
db2336a8 KH |
1272 | MSR_PLATFORM_INFO, |
1273 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1274 | MSR_AMD64_VIRT_SPEC_CTRL, |
6c6a2ab9 | 1275 | MSR_IA32_POWER_CTL, |
99634e3e | 1276 | MSR_IA32_UCODE_REV, |
191c8137 | 1277 | |
95c5c7c7 PB |
1278 | /* |
1279 | * The following list leaves out MSRs whose values are determined | |
1280 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1281 | * We always support the "true" VMX control MSRs, even if the host | |
1282 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1283 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1284 | */ |
1285 | MSR_IA32_VMX_BASIC, | |
1286 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1287 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1288 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1289 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1290 | MSR_IA32_VMX_MISC, | |
1291 | MSR_IA32_VMX_CR0_FIXED0, | |
1292 | MSR_IA32_VMX_CR4_FIXED0, | |
1293 | MSR_IA32_VMX_VMCS_ENUM, | |
1294 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1295 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1296 | MSR_IA32_VMX_VMFUNC, | |
1297 | ||
191c8137 | 1298 | MSR_K7_HWCR, |
2d5ba19b | 1299 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1300 | }; |
1301 | ||
7a5ee6ed | 1302 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1303 | static unsigned num_emulated_msrs; |
1304 | ||
801e459a TL |
1305 | /* |
1306 | * List of msr numbers which are used to expose MSR-based features that | |
1307 | * can be used by a hypervisor to validate requested CPU features. | |
1308 | */ | |
7a5ee6ed | 1309 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1310 | MSR_IA32_VMX_BASIC, |
1311 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1312 | MSR_IA32_VMX_PINBASED_CTLS, | |
1313 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1314 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1315 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1316 | MSR_IA32_VMX_EXIT_CTLS, | |
1317 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1318 | MSR_IA32_VMX_ENTRY_CTLS, | |
1319 | MSR_IA32_VMX_MISC, | |
1320 | MSR_IA32_VMX_CR0_FIXED0, | |
1321 | MSR_IA32_VMX_CR0_FIXED1, | |
1322 | MSR_IA32_VMX_CR4_FIXED0, | |
1323 | MSR_IA32_VMX_CR4_FIXED1, | |
1324 | MSR_IA32_VMX_VMCS_ENUM, | |
1325 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1326 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1327 | MSR_IA32_VMX_VMFUNC, | |
1328 | ||
d1d93fa9 | 1329 | MSR_F10H_DECFG, |
518e7b94 | 1330 | MSR_IA32_UCODE_REV, |
cd283252 | 1331 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1332 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1333 | }; |
1334 | ||
7a5ee6ed | 1335 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1336 | static unsigned int num_msr_based_features; |
1337 | ||
4d22c17c | 1338 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1339 | { |
4d22c17c | 1340 | u64 data = 0; |
5b76a3cf | 1341 | |
4d22c17c XL |
1342 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1343 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1344 | |
b8e8c830 PB |
1345 | /* |
1346 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1347 | * the nested hypervisor runs with NX huge pages. If it is not, | |
1348 | * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other | |
1349 | * L1 guests, so it need not worry about its own (L2) guests. | |
1350 | */ | |
1351 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1352 | ||
5b76a3cf PB |
1353 | /* |
1354 | * If we're doing cache flushes (either "always" or "cond") | |
1355 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1356 | * If an outer hypervisor is doing the cache flush for us | |
1357 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1358 | * capability to the guest too, and if EPT is disabled we're not | |
1359 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1360 | * require a nested hypervisor to do a flush of its own. | |
1361 | */ | |
1362 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1363 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1364 | ||
0c54914d PB |
1365 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1366 | data |= ARCH_CAP_RDCL_NO; | |
1367 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1368 | data |= ARCH_CAP_SSB_NO; | |
1369 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1370 | data |= ARCH_CAP_MDS_NO; | |
1371 | ||
e1d38b63 | 1372 | /* |
c11f83e0 PB |
1373 | * On TAA affected systems: |
1374 | * - nothing to do if TSX is disabled on the host. | |
1375 | * - we emulate TSX_CTRL if present on the host. | |
1376 | * This lets the guest use VERW to clear CPU buffers. | |
e1d38b63 | 1377 | */ |
cbbaa272 | 1378 | if (!boot_cpu_has(X86_FEATURE_RTM)) |
c11f83e0 | 1379 | data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); |
cbbaa272 PB |
1380 | else if (!boot_cpu_has_bug(X86_BUG_TAA)) |
1381 | data |= ARCH_CAP_TAA_NO; | |
e1d38b63 | 1382 | |
5b76a3cf PB |
1383 | return data; |
1384 | } | |
5b76a3cf | 1385 | |
66421c1e WL |
1386 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1387 | { | |
1388 | switch (msr->index) { | |
cd283252 | 1389 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1390 | msr->data = kvm_get_arch_capabilities(); |
1391 | break; | |
1392 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1393 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1394 | break; |
66421c1e | 1395 | default: |
12bc2132 | 1396 | return kvm_x86_ops.get_msr_feature(msr); |
66421c1e WL |
1397 | } |
1398 | return 0; | |
1399 | } | |
1400 | ||
801e459a TL |
1401 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1402 | { | |
1403 | struct kvm_msr_entry msr; | |
66421c1e | 1404 | int r; |
801e459a TL |
1405 | |
1406 | msr.index = index; | |
66421c1e | 1407 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1408 | |
1409 | if (r == KVM_MSR_RET_INVALID) { | |
1410 | /* Unconditionally clear the output for simplicity */ | |
1411 | *data = 0; | |
1412 | r = kvm_msr_ignored_check(vcpu, index, 0, false); | |
1413 | } | |
1414 | ||
66421c1e WL |
1415 | if (r) |
1416 | return r; | |
801e459a TL |
1417 | |
1418 | *data = msr.data; | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
11988499 | 1423 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1424 | { |
1b4d56b8 | 1425 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1426 | return false; |
1b2fd70c | 1427 | |
1b4d56b8 | 1428 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1429 | return false; |
d8017474 | 1430 | |
0a629563 SC |
1431 | if (efer & (EFER_LME | EFER_LMA) && |
1432 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1433 | return false; | |
1434 | ||
1435 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1436 | return false; | |
d8017474 | 1437 | |
384bb783 | 1438 | return true; |
11988499 SC |
1439 | |
1440 | } | |
1441 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1442 | { | |
1443 | if (efer & efer_reserved_bits) | |
1444 | return false; | |
1445 | ||
1446 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1447 | } |
1448 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1449 | ||
11988499 | 1450 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1451 | { |
1452 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1453 | u64 efer = msr_info->data; |
384bb783 | 1454 | |
11988499 | 1455 | if (efer & efer_reserved_bits) |
66f61c92 | 1456 | return 1; |
384bb783 | 1457 | |
11988499 SC |
1458 | if (!msr_info->host_initiated) { |
1459 | if (!__kvm_valid_efer(vcpu, efer)) | |
1460 | return 1; | |
1461 | ||
1462 | if (is_paging(vcpu) && | |
1463 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1464 | return 1; | |
1465 | } | |
384bb783 | 1466 | |
15c4a640 | 1467 | efer &= ~EFER_LMA; |
f6801dff | 1468 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1469 | |
afaf0b2f | 1470 | kvm_x86_ops.set_efer(vcpu, efer); |
a3d204e2 | 1471 | |
aad82703 SY |
1472 | /* Update reserved bits */ |
1473 | if ((efer ^ old_efer) & EFER_NX) | |
1474 | kvm_mmu_reset_context(vcpu); | |
1475 | ||
b69e8cae | 1476 | return 0; |
15c4a640 CO |
1477 | } |
1478 | ||
f2b4b7dd JR |
1479 | void kvm_enable_efer_bits(u64 mask) |
1480 | { | |
1481 | efer_reserved_bits &= ~mask; | |
1482 | } | |
1483 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1484 | ||
15c4a640 | 1485 | /* |
f20935d8 SC |
1486 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1487 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1488 | * Returns 0 on success, non-0 otherwise. |
1489 | * Assumes vcpu_load() was already called. | |
1490 | */ | |
f20935d8 SC |
1491 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1492 | bool host_initiated) | |
15c4a640 | 1493 | { |
f20935d8 SC |
1494 | struct msr_data msr; |
1495 | ||
1496 | switch (index) { | |
854e8bb1 NA |
1497 | case MSR_FS_BASE: |
1498 | case MSR_GS_BASE: | |
1499 | case MSR_KERNEL_GS_BASE: | |
1500 | case MSR_CSTAR: | |
1501 | case MSR_LSTAR: | |
f20935d8 | 1502 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1503 | return 1; |
1504 | break; | |
1505 | case MSR_IA32_SYSENTER_EIP: | |
1506 | case MSR_IA32_SYSENTER_ESP: | |
1507 | /* | |
1508 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1509 | * non-canonical address is written on Intel but not on | |
1510 | * AMD (which ignores the top 32-bits, because it does | |
1511 | * not implement 64-bit SYSENTER). | |
1512 | * | |
1513 | * 64-bit code should hence be able to write a non-canonical | |
1514 | * value on AMD. Making the address canonical ensures that | |
1515 | * vmentry does not fail on Intel after writing a non-canonical | |
1516 | * value, and that something deterministic happens if the guest | |
1517 | * invokes 64-bit SYSENTER. | |
1518 | */ | |
f20935d8 | 1519 | data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); |
854e8bb1 | 1520 | } |
f20935d8 SC |
1521 | |
1522 | msr.data = data; | |
1523 | msr.index = index; | |
1524 | msr.host_initiated = host_initiated; | |
1525 | ||
afaf0b2f | 1526 | return kvm_x86_ops.set_msr(vcpu, &msr); |
15c4a640 CO |
1527 | } |
1528 | ||
6abe9c13 PX |
1529 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1530 | u32 index, u64 data, bool host_initiated) | |
1531 | { | |
1532 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1533 | ||
1534 | if (ret == KVM_MSR_RET_INVALID) | |
1535 | ret = kvm_msr_ignored_check(vcpu, index, data, true); | |
1536 | ||
1537 | return ret; | |
1538 | } | |
1539 | ||
313a3dc7 | 1540 | /* |
f20935d8 SC |
1541 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1542 | * checks are bypassed if @host_initiated is %true. | |
1543 | * Returns 0 on success, non-0 otherwise. | |
1544 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1545 | */ |
edef5c36 PB |
1546 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1547 | bool host_initiated) | |
609e36d3 PB |
1548 | { |
1549 | struct msr_data msr; | |
f20935d8 | 1550 | int ret; |
609e36d3 PB |
1551 | |
1552 | msr.index = index; | |
f20935d8 | 1553 | msr.host_initiated = host_initiated; |
609e36d3 | 1554 | |
afaf0b2f | 1555 | ret = kvm_x86_ops.get_msr(vcpu, &msr); |
f20935d8 SC |
1556 | if (!ret) |
1557 | *data = msr.data; | |
1558 | return ret; | |
609e36d3 PB |
1559 | } |
1560 | ||
6abe9c13 PX |
1561 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1562 | u32 index, u64 *data, bool host_initiated) | |
1563 | { | |
1564 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1565 | ||
1566 | if (ret == KVM_MSR_RET_INVALID) { | |
1567 | /* Unconditionally clear *data for simplicity */ | |
1568 | *data = 0; | |
1569 | ret = kvm_msr_ignored_check(vcpu, index, 0, false); | |
1570 | } | |
1571 | ||
1572 | return ret; | |
1573 | } | |
1574 | ||
f20935d8 | 1575 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1576 | { |
6abe9c13 | 1577 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1578 | } |
1579 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1580 | |
f20935d8 SC |
1581 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1582 | { | |
6abe9c13 | 1583 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1584 | } |
1585 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1586 | ||
1edce0a9 SC |
1587 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1588 | { | |
1589 | u32 ecx = kvm_rcx_read(vcpu); | |
1590 | u64 data; | |
1591 | ||
1592 | if (kvm_get_msr(vcpu, ecx, &data)) { | |
1593 | trace_kvm_msr_read_ex(ecx); | |
1594 | kvm_inject_gp(vcpu, 0); | |
1595 | return 1; | |
1596 | } | |
1597 | ||
1598 | trace_kvm_msr_read(ecx, data); | |
1599 | ||
1600 | kvm_rax_write(vcpu, data & -1u); | |
1601 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
1602 | return kvm_skip_emulated_instruction(vcpu); | |
1603 | } | |
1604 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
1605 | ||
1606 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
1607 | { | |
1608 | u32 ecx = kvm_rcx_read(vcpu); | |
1609 | u64 data = kvm_read_edx_eax(vcpu); | |
1610 | ||
1611 | if (kvm_set_msr(vcpu, ecx, data)) { | |
1612 | trace_kvm_msr_write_ex(ecx, data); | |
1613 | kvm_inject_gp(vcpu, 0); | |
1614 | return 1; | |
1615 | } | |
1616 | ||
1617 | trace_kvm_msr_write(ecx, data); | |
1618 | return kvm_skip_emulated_instruction(vcpu); | |
1619 | } | |
1620 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
1621 | ||
5a9f5443 WL |
1622 | bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
1623 | { | |
1624 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || | |
1625 | need_resched() || signal_pending(current); | |
1626 | } | |
1627 | EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); | |
1628 | ||
1e9e2622 WL |
1629 | /* |
1630 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
1631 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
1632 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
1633 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
1634 | * other cases which must be called after interrupts are enabled on the host. | |
1635 | */ | |
1636 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
1637 | { | |
e1be9ac8 WL |
1638 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
1639 | return 1; | |
1640 | ||
1641 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
1e9e2622 | 1642 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
4064a4c6 WL |
1643 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && |
1644 | ((u32)(data >> 32) != X2APIC_BROADCAST)) { | |
1e9e2622 | 1645 | |
d5361678 WL |
1646 | data &= ~(1 << 12); |
1647 | kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); | |
1e9e2622 | 1648 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); |
d5361678 WL |
1649 | kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); |
1650 | trace_kvm_apic_write(APIC_ICR, (u32)data); | |
1651 | return 0; | |
1e9e2622 WL |
1652 | } |
1653 | ||
1654 | return 1; | |
1655 | } | |
1656 | ||
ae95f566 WL |
1657 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
1658 | { | |
1659 | if (!kvm_can_use_hv_timer(vcpu)) | |
1660 | return 1; | |
1661 | ||
1662 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
1663 | return 0; | |
1664 | } | |
1665 | ||
404d5d7b | 1666 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
1667 | { |
1668 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 1669 | u64 data; |
404d5d7b | 1670 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
1671 | |
1672 | switch (msr) { | |
1673 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 1674 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
1675 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
1676 | kvm_skip_emulated_instruction(vcpu); | |
1677 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 1678 | } |
1e9e2622 | 1679 | break; |
ae95f566 WL |
1680 | case MSR_IA32_TSCDEADLINE: |
1681 | data = kvm_read_edx_eax(vcpu); | |
1682 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
1683 | kvm_skip_emulated_instruction(vcpu); | |
1684 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
1685 | } | |
1686 | break; | |
1e9e2622 | 1687 | default: |
404d5d7b | 1688 | break; |
1e9e2622 WL |
1689 | } |
1690 | ||
404d5d7b | 1691 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 1692 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 1693 | |
404d5d7b | 1694 | return ret; |
1e9e2622 WL |
1695 | } |
1696 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
1697 | ||
f20935d8 SC |
1698 | /* |
1699 | * Adapt set_msr() to msr_io()'s calling convention | |
1700 | */ | |
1701 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1702 | { | |
6abe9c13 | 1703 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
1704 | } |
1705 | ||
1706 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
1707 | { | |
6abe9c13 | 1708 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
1709 | } |
1710 | ||
16e8d74d | 1711 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
1712 | struct pvclock_clock { |
1713 | int vclock_mode; | |
1714 | u64 cycle_last; | |
1715 | u64 mask; | |
1716 | u32 mult; | |
1717 | u32 shift; | |
917f9475 PB |
1718 | u64 base_cycles; |
1719 | u64 offset; | |
53fafdbb MT |
1720 | }; |
1721 | ||
16e8d74d MT |
1722 | struct pvclock_gtod_data { |
1723 | seqcount_t seq; | |
1724 | ||
53fafdbb MT |
1725 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
1726 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 1727 | |
917f9475 | 1728 | ktime_t offs_boot; |
55dd00a7 | 1729 | u64 wall_time_sec; |
16e8d74d MT |
1730 | }; |
1731 | ||
1732 | static struct pvclock_gtod_data pvclock_gtod_data; | |
1733 | ||
1734 | static void update_pvclock_gtod(struct timekeeper *tk) | |
1735 | { | |
1736 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
1737 | ||
1738 | write_seqcount_begin(&vdata->seq); | |
1739 | ||
1740 | /* copy pvclock gtod data */ | |
b95a8a27 | 1741 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
1742 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
1743 | vdata->clock.mask = tk->tkr_mono.mask; | |
1744 | vdata->clock.mult = tk->tkr_mono.mult; | |
1745 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
1746 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
1747 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 1748 | |
b95a8a27 | 1749 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
1750 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
1751 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
1752 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
1753 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
1754 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
1755 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 1756 | |
55dd00a7 MT |
1757 | vdata->wall_time_sec = tk->xtime_sec; |
1758 | ||
917f9475 | 1759 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 1760 | |
16e8d74d MT |
1761 | write_seqcount_end(&vdata->seq); |
1762 | } | |
8171cd68 PB |
1763 | |
1764 | static s64 get_kvmclock_base_ns(void) | |
1765 | { | |
1766 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
1767 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
1768 | } | |
1769 | #else | |
1770 | static s64 get_kvmclock_base_ns(void) | |
1771 | { | |
1772 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
1773 | return ktime_get_boottime_ns(); | |
1774 | } | |
16e8d74d MT |
1775 | #endif |
1776 | ||
bab5bb39 NK |
1777 | void kvm_set_pending_timer(struct kvm_vcpu *vcpu) |
1778 | { | |
bab5bb39 | 1779 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); |
4d151bf3 | 1780 | kvm_vcpu_kick(vcpu); |
bab5bb39 | 1781 | } |
16e8d74d | 1782 | |
18068523 GOC |
1783 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
1784 | { | |
9ed3c444 AK |
1785 | int version; |
1786 | int r; | |
50d0a0f9 | 1787 | struct pvclock_wall_clock wc; |
8171cd68 | 1788 | u64 wall_nsec; |
18068523 GOC |
1789 | |
1790 | if (!wall_clock) | |
1791 | return; | |
1792 | ||
9ed3c444 AK |
1793 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
1794 | if (r) | |
1795 | return; | |
1796 | ||
1797 | if (version & 1) | |
1798 | ++version; /* first time write, random junk */ | |
1799 | ||
1800 | ++version; | |
18068523 | 1801 | |
1dab1345 NK |
1802 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
1803 | return; | |
18068523 | 1804 | |
50d0a0f9 GH |
1805 | /* |
1806 | * The guest calculates current wall clock time by adding | |
34c238a1 | 1807 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 1808 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 1809 | */ |
8171cd68 | 1810 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 1811 | |
8171cd68 PB |
1812 | wc.nsec = do_div(wall_nsec, 1000000000); |
1813 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 1814 | wc.version = version; |
18068523 GOC |
1815 | |
1816 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
1817 | ||
1818 | version++; | |
1819 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
1820 | } |
1821 | ||
50d0a0f9 GH |
1822 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
1823 | { | |
b51012de PB |
1824 | do_shl32_div32(dividend, divisor); |
1825 | return dividend; | |
50d0a0f9 GH |
1826 | } |
1827 | ||
3ae13faa | 1828 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 1829 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 1830 | { |
5f4e3f88 | 1831 | uint64_t scaled64; |
50d0a0f9 GH |
1832 | int32_t shift = 0; |
1833 | uint64_t tps64; | |
1834 | uint32_t tps32; | |
1835 | ||
3ae13faa PB |
1836 | tps64 = base_hz; |
1837 | scaled64 = scaled_hz; | |
50933623 | 1838 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
1839 | tps64 >>= 1; |
1840 | shift--; | |
1841 | } | |
1842 | ||
1843 | tps32 = (uint32_t)tps64; | |
50933623 JK |
1844 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
1845 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
1846 | scaled64 >>= 1; |
1847 | else | |
1848 | tps32 <<= 1; | |
50d0a0f9 GH |
1849 | shift++; |
1850 | } | |
1851 | ||
5f4e3f88 ZA |
1852 | *pshift = shift; |
1853 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
1854 | } |
1855 | ||
d828199e | 1856 | #ifdef CONFIG_X86_64 |
16e8d74d | 1857 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 1858 | #endif |
16e8d74d | 1859 | |
c8076604 | 1860 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 1861 | static unsigned long max_tsc_khz; |
c8076604 | 1862 | |
cc578287 | 1863 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 1864 | { |
cc578287 ZA |
1865 | u64 v = (u64)khz * (1000000 + ppm); |
1866 | do_div(v, 1000000); | |
1867 | return v; | |
1e993611 JR |
1868 | } |
1869 | ||
381d585c HZ |
1870 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
1871 | { | |
1872 | u64 ratio; | |
1873 | ||
1874 | /* Guest TSC same frequency as host TSC? */ | |
1875 | if (!scale) { | |
1876 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
1877 | return 0; | |
1878 | } | |
1879 | ||
1880 | /* TSC scaling supported? */ | |
1881 | if (!kvm_has_tsc_control) { | |
1882 | if (user_tsc_khz > tsc_khz) { | |
1883 | vcpu->arch.tsc_catchup = 1; | |
1884 | vcpu->arch.tsc_always_catchup = 1; | |
1885 | return 0; | |
1886 | } else { | |
3f16a5c3 | 1887 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
1888 | return -1; |
1889 | } | |
1890 | } | |
1891 | ||
1892 | /* TSC scaling required - calculate ratio */ | |
1893 | ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, | |
1894 | user_tsc_khz, tsc_khz); | |
1895 | ||
1896 | if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { | |
3f16a5c3 PB |
1897 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
1898 | user_tsc_khz); | |
381d585c HZ |
1899 | return -1; |
1900 | } | |
1901 | ||
1902 | vcpu->arch.tsc_scaling_ratio = ratio; | |
1903 | return 0; | |
1904 | } | |
1905 | ||
4941b8cb | 1906 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 1907 | { |
cc578287 ZA |
1908 | u32 thresh_lo, thresh_hi; |
1909 | int use_scaling = 0; | |
217fc9cf | 1910 | |
03ba32ca | 1911 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 1912 | if (user_tsc_khz == 0) { |
ad721883 HZ |
1913 | /* set tsc_scaling_ratio to a safe value */ |
1914 | vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; | |
381d585c | 1915 | return -1; |
ad721883 | 1916 | } |
03ba32ca | 1917 | |
c285545f | 1918 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 1919 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
1920 | &vcpu->arch.virtual_tsc_shift, |
1921 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 1922 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
1923 | |
1924 | /* | |
1925 | * Compute the variation in TSC rate which is acceptable | |
1926 | * within the range of tolerance and decide if the | |
1927 | * rate being applied is within that bounds of the hardware | |
1928 | * rate. If so, no scaling or compensation need be done. | |
1929 | */ | |
1930 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
1931 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
1932 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
1933 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
1934 | use_scaling = 1; |
1935 | } | |
4941b8cb | 1936 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
1937 | } |
1938 | ||
1939 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
1940 | { | |
e26101b1 | 1941 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
1942 | vcpu->arch.virtual_tsc_mult, |
1943 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 1944 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
1945 | return tsc; |
1946 | } | |
1947 | ||
b0c39dc6 VK |
1948 | static inline int gtod_is_based_on_tsc(int mode) |
1949 | { | |
b95a8a27 | 1950 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 VK |
1951 | } |
1952 | ||
69b0049a | 1953 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
1954 | { |
1955 | #ifdef CONFIG_X86_64 | |
1956 | bool vcpus_matched; | |
b48aa97e MT |
1957 | struct kvm_arch *ka = &vcpu->kvm->arch; |
1958 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
1959 | ||
1960 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
1961 | atomic_read(&vcpu->kvm->online_vcpus)); | |
1962 | ||
7f187922 MT |
1963 | /* |
1964 | * Once the masterclock is enabled, always perform request in | |
1965 | * order to update it. | |
1966 | * | |
1967 | * In order to enable masterclock, the host clocksource must be TSC | |
1968 | * and the vcpus need to have matched TSCs. When that happens, | |
1969 | * perform request to enable masterclock. | |
1970 | */ | |
1971 | if (ka->use_master_clock || | |
b0c39dc6 | 1972 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
1973 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
1974 | ||
1975 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
1976 | atomic_read(&vcpu->kvm->online_vcpus), | |
1977 | ka->use_master_clock, gtod->clock.vclock_mode); | |
1978 | #endif | |
1979 | } | |
1980 | ||
ba904635 WA |
1981 | static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) |
1982 | { | |
56ba77a4 | 1983 | u64 curr_offset = vcpu->arch.l1_tsc_offset; |
ba904635 WA |
1984 | vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; |
1985 | } | |
1986 | ||
35181e86 HZ |
1987 | /* |
1988 | * Multiply tsc by a fixed point number represented by ratio. | |
1989 | * | |
1990 | * The most significant 64-N bits (mult) of ratio represent the | |
1991 | * integral part of the fixed point number; the remaining N bits | |
1992 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
1993 | * point number (mult + frac * 2^(-N)). | |
1994 | * | |
1995 | * N equals to kvm_tsc_scaling_ratio_frac_bits. | |
1996 | */ | |
1997 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
1998 | { | |
1999 | return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); | |
2000 | } | |
2001 | ||
2002 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) | |
2003 | { | |
2004 | u64 _tsc = tsc; | |
2005 | u64 ratio = vcpu->arch.tsc_scaling_ratio; | |
2006 | ||
2007 | if (ratio != kvm_default_tsc_scaling_ratio) | |
2008 | _tsc = __scale_tsc(ratio, tsc); | |
2009 | ||
2010 | return _tsc; | |
2011 | } | |
2012 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2013 | ||
07c1419a HZ |
2014 | static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2015 | { | |
2016 | u64 tsc; | |
2017 | ||
2018 | tsc = kvm_scale_tsc(vcpu, rdtsc()); | |
2019 | ||
2020 | return target_tsc - tsc; | |
2021 | } | |
2022 | ||
4ba76538 HZ |
2023 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2024 | { | |
56ba77a4 | 2025 | return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); |
4ba76538 HZ |
2026 | } |
2027 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2028 | ||
a545ab6a LC |
2029 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
2030 | { | |
56ba77a4 | 2031 | vcpu->arch.l1_tsc_offset = offset; |
afaf0b2f | 2032 | vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); |
a545ab6a LC |
2033 | } |
2034 | ||
b0c39dc6 VK |
2035 | static inline bool kvm_check_tsc_unstable(void) |
2036 | { | |
2037 | #ifdef CONFIG_X86_64 | |
2038 | /* | |
2039 | * TSC is marked unstable when we're running on Hyper-V, | |
2040 | * 'TSC page' clocksource is good. | |
2041 | */ | |
b95a8a27 | 2042 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2043 | return false; |
2044 | #endif | |
2045 | return check_tsc_unstable(); | |
2046 | } | |
2047 | ||
8fe8ab46 | 2048 | void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) |
99e3e30a ZA |
2049 | { |
2050 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2051 | u64 offset, ns, elapsed; |
99e3e30a | 2052 | unsigned long flags; |
b48aa97e | 2053 | bool matched; |
0d3da0d2 | 2054 | bool already_matched; |
8fe8ab46 | 2055 | u64 data = msr->data; |
c5e8ec8e | 2056 | bool synchronizing = false; |
99e3e30a | 2057 | |
038f8c11 | 2058 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
07c1419a | 2059 | offset = kvm_compute_tsc_offset(vcpu, data); |
8171cd68 | 2060 | ns = get_kvmclock_base_ns(); |
f38e098f | 2061 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2062 | |
03ba32ca | 2063 | if (vcpu->arch.virtual_tsc_khz) { |
bd8fab39 DP |
2064 | if (data == 0 && msr->host_initiated) { |
2065 | /* | |
2066 | * detection of vcpu initialization -- need to sync | |
2067 | * with other vCPUs. This particularly helps to keep | |
2068 | * kvm_clock stable after CPU hotplug | |
2069 | */ | |
2070 | synchronizing = true; | |
2071 | } else { | |
2072 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2073 | nsec_to_cycles(vcpu, elapsed); | |
2074 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2075 | /* | |
2076 | * Special case: TSC write with a small delta (1 second) | |
2077 | * of virtual cycle time against real time is | |
2078 | * interpreted as an attempt to synchronize the CPU. | |
2079 | */ | |
2080 | synchronizing = data < tsc_exp + tsc_hz && | |
2081 | data + tsc_hz > tsc_exp; | |
2082 | } | |
c5e8ec8e | 2083 | } |
f38e098f ZA |
2084 | |
2085 | /* | |
5d3cb0f6 ZA |
2086 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2087 | * TSC, we add elapsed time in this computation. We could let the | |
2088 | * compensation code attempt to catch up if we fall behind, but | |
2089 | * it's better to try to match offsets from the beginning. | |
2090 | */ | |
c5e8ec8e | 2091 | if (synchronizing && |
5d3cb0f6 | 2092 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2093 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2094 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2095 | } else { |
857e4099 | 2096 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2097 | data += delta; |
07c1419a | 2098 | offset = kvm_compute_tsc_offset(vcpu, data); |
f38e098f | 2099 | } |
b48aa97e | 2100 | matched = true; |
0d3da0d2 | 2101 | already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); |
e26101b1 ZA |
2102 | } else { |
2103 | /* | |
2104 | * We split periods of matched TSC writes into generations. | |
2105 | * For each generation, we track the original measured | |
2106 | * nanosecond time, offset, and write, so if TSCs are in | |
2107 | * sync, we can match exact offset, and if not, we can match | |
4a969980 | 2108 | * exact software computation in compute_guest_tsc() |
e26101b1 ZA |
2109 | * |
2110 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2111 | */ | |
2112 | kvm->arch.cur_tsc_generation++; | |
2113 | kvm->arch.cur_tsc_nsec = ns; | |
2114 | kvm->arch.cur_tsc_write = data; | |
2115 | kvm->arch.cur_tsc_offset = offset; | |
b48aa97e | 2116 | matched = false; |
f38e098f | 2117 | } |
e26101b1 ZA |
2118 | |
2119 | /* | |
2120 | * We also track th most recent recorded KHZ, write and time to | |
2121 | * allow the matching interval to be extended at each write. | |
2122 | */ | |
f38e098f ZA |
2123 | kvm->arch.last_tsc_nsec = ns; |
2124 | kvm->arch.last_tsc_write = data; | |
5d3cb0f6 | 2125 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; |
99e3e30a | 2126 | |
b183aa58 | 2127 | vcpu->arch.last_guest_tsc = data; |
e26101b1 ZA |
2128 | |
2129 | /* Keep track of which generation this VCPU has synchronized to */ | |
2130 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2131 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2132 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2133 | ||
d6321d49 | 2134 | if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) |
ba904635 | 2135 | update_ia32_tsc_adjust_msr(vcpu, offset); |
d6321d49 | 2136 | |
a545ab6a | 2137 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
e26101b1 | 2138 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
b48aa97e MT |
2139 | |
2140 | spin_lock(&kvm->arch.pvclock_gtod_sync_lock); | |
0d3da0d2 | 2141 | if (!matched) { |
b48aa97e | 2142 | kvm->arch.nr_vcpus_matched_tsc = 0; |
0d3da0d2 TG |
2143 | } else if (!already_matched) { |
2144 | kvm->arch.nr_vcpus_matched_tsc++; | |
2145 | } | |
b48aa97e MT |
2146 | |
2147 | kvm_track_tsc_matching(vcpu); | |
2148 | spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); | |
99e3e30a | 2149 | } |
e26101b1 | 2150 | |
99e3e30a ZA |
2151 | EXPORT_SYMBOL_GPL(kvm_write_tsc); |
2152 | ||
58ea6767 HZ |
2153 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2154 | s64 adjustment) | |
2155 | { | |
56ba77a4 | 2156 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2157 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2158 | } |
2159 | ||
2160 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2161 | { | |
2162 | if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) | |
2163 | WARN_ON(adjustment < 0); | |
2164 | adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); | |
ea26e4ec | 2165 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2166 | } |
2167 | ||
d828199e MT |
2168 | #ifdef CONFIG_X86_64 |
2169 | ||
a5a1d1c2 | 2170 | static u64 read_tsc(void) |
d828199e | 2171 | { |
a5a1d1c2 | 2172 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2173 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2174 | |
2175 | if (likely(ret >= last)) | |
2176 | return ret; | |
2177 | ||
2178 | /* | |
2179 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2180 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2181 | * very likely) and there's a data dependence, so force GCC |
2182 | * to generate a branch instead. I don't barrier() because | |
2183 | * we don't actually need a barrier, and if this function | |
2184 | * ever gets inlined it will generate worse code. | |
2185 | */ | |
2186 | asm volatile (""); | |
2187 | return last; | |
2188 | } | |
2189 | ||
53fafdbb MT |
2190 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2191 | int *mode) | |
d828199e MT |
2192 | { |
2193 | long v; | |
b0c39dc6 VK |
2194 | u64 tsc_pg_val; |
2195 | ||
53fafdbb | 2196 | switch (clock->vclock_mode) { |
b95a8a27 | 2197 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2198 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2199 | tsc_timestamp); | |
2200 | if (tsc_pg_val != U64_MAX) { | |
2201 | /* TSC page valid */ | |
b95a8a27 | 2202 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2203 | v = (tsc_pg_val - clock->cycle_last) & |
2204 | clock->mask; | |
b0c39dc6 VK |
2205 | } else { |
2206 | /* TSC page invalid */ | |
b95a8a27 | 2207 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2208 | } |
2209 | break; | |
b95a8a27 TG |
2210 | case VDSO_CLOCKMODE_TSC: |
2211 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2212 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2213 | v = (*tsc_timestamp - clock->cycle_last) & |
2214 | clock->mask; | |
b0c39dc6 VK |
2215 | break; |
2216 | default: | |
b95a8a27 | 2217 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2218 | } |
d828199e | 2219 | |
b95a8a27 | 2220 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2221 | *tsc_timestamp = v = 0; |
d828199e | 2222 | |
53fafdbb | 2223 | return v * clock->mult; |
d828199e MT |
2224 | } |
2225 | ||
53fafdbb | 2226 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2227 | { |
cbcf2dd3 | 2228 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2229 | unsigned long seq; |
d828199e | 2230 | int mode; |
cbcf2dd3 | 2231 | u64 ns; |
d828199e | 2232 | |
d828199e MT |
2233 | do { |
2234 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2235 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2236 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2237 | ns >>= gtod->raw_clock.shift; |
2238 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2239 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2240 | *t = ns; |
d828199e MT |
2241 | |
2242 | return mode; | |
2243 | } | |
2244 | ||
899a31f5 | 2245 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2246 | { |
2247 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2248 | unsigned long seq; | |
2249 | int mode; | |
2250 | u64 ns; | |
2251 | ||
2252 | do { | |
2253 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2254 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2255 | ns = gtod->clock.base_cycles; |
53fafdbb | 2256 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2257 | ns >>= gtod->clock.shift; |
2258 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2259 | ||
2260 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2261 | ts->tv_nsec = ns; | |
2262 | ||
2263 | return mode; | |
2264 | } | |
2265 | ||
b0c39dc6 VK |
2266 | /* returns true if host is using TSC based clocksource */ |
2267 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2268 | { |
d828199e | 2269 | /* checked again under seqlock below */ |
b0c39dc6 | 2270 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2271 | return false; |
2272 | ||
53fafdbb | 2273 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2274 | tsc_timestamp)); |
d828199e | 2275 | } |
55dd00a7 | 2276 | |
b0c39dc6 | 2277 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2278 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2279 | u64 *tsc_timestamp) |
55dd00a7 MT |
2280 | { |
2281 | /* checked again under seqlock below */ | |
b0c39dc6 | 2282 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2283 | return false; |
2284 | ||
b0c39dc6 | 2285 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2286 | } |
d828199e MT |
2287 | #endif |
2288 | ||
2289 | /* | |
2290 | * | |
b48aa97e MT |
2291 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2292 | * across virtual CPUs, the following condition is possible. | |
2293 | * Each numbered line represents an event visible to both | |
d828199e MT |
2294 | * CPUs at the next numbered event. |
2295 | * | |
2296 | * "timespecX" represents host monotonic time. "tscX" represents | |
2297 | * RDTSC value. | |
2298 | * | |
2299 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2300 | * | |
2301 | * 1. read timespec0,tsc0 | |
2302 | * 2. | timespec1 = timespec0 + N | |
2303 | * | tsc1 = tsc0 + M | |
2304 | * 3. transition to guest | transition to guest | |
2305 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2306 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2307 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2308 | * | |
2309 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2310 | * | |
2311 | * - ret0 < ret1 | |
2312 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2313 | * ... | |
2314 | * - 0 < N - M => M < N | |
2315 | * | |
2316 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2317 | * always the case (the difference between two distinct xtime instances | |
2318 | * might be smaller then the difference between corresponding TSC reads, | |
2319 | * when updating guest vcpus pvclock areas). | |
2320 | * | |
2321 | * To avoid that problem, do not allow visibility of distinct | |
2322 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2323 | * copy of host monotonic time values. Update that master copy | |
2324 | * in lockstep. | |
2325 | * | |
b48aa97e | 2326 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2327 | * |
2328 | */ | |
2329 | ||
2330 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2331 | { | |
2332 | #ifdef CONFIG_X86_64 | |
2333 | struct kvm_arch *ka = &kvm->arch; | |
2334 | int vclock_mode; | |
b48aa97e MT |
2335 | bool host_tsc_clocksource, vcpus_matched; |
2336 | ||
2337 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2338 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2339 | |
2340 | /* | |
2341 | * If the host uses TSC clock, then passthrough TSC as stable | |
2342 | * to the guest. | |
2343 | */ | |
b48aa97e | 2344 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2345 | &ka->master_kernel_ns, |
2346 | &ka->master_cycle_now); | |
2347 | ||
16a96021 | 2348 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2349 | && !ka->backwards_tsc_observed |
54750f2c | 2350 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2351 | |
d828199e MT |
2352 | if (ka->use_master_clock) |
2353 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2354 | ||
2355 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2356 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2357 | vcpus_matched); | |
d828199e MT |
2358 | #endif |
2359 | } | |
2360 | ||
2860c4b1 PB |
2361 | void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2362 | { | |
2363 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2364 | } | |
2365 | ||
2e762ff7 MT |
2366 | static void kvm_gen_update_masterclock(struct kvm *kvm) |
2367 | { | |
2368 | #ifdef CONFIG_X86_64 | |
2369 | int i; | |
2370 | struct kvm_vcpu *vcpu; | |
2371 | struct kvm_arch *ka = &kvm->arch; | |
2372 | ||
2373 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2374 | kvm_make_mclock_inprogress_request(kvm); | |
2375 | /* no guest entries from this point */ | |
2376 | pvclock_update_vm_gtod_copy(kvm); | |
2377 | ||
2378 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 2379 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2380 | |
2381 | /* guest entries allowed */ | |
2382 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2383 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2384 | |
2385 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2386 | #endif | |
2387 | } | |
2388 | ||
e891a32e | 2389 | u64 get_kvmclock_ns(struct kvm *kvm) |
108b249c | 2390 | { |
108b249c | 2391 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2392 | struct pvclock_vcpu_time_info hv_clock; |
e2c2206a | 2393 | u64 ret; |
108b249c | 2394 | |
8b953440 PB |
2395 | spin_lock(&ka->pvclock_gtod_sync_lock); |
2396 | if (!ka->use_master_clock) { | |
2397 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
8171cd68 | 2398 | return get_kvmclock_base_ns() + ka->kvmclock_offset; |
108b249c PB |
2399 | } |
2400 | ||
8b953440 PB |
2401 | hv_clock.tsc_timestamp = ka->master_cycle_now; |
2402 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
2403 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
2404 | ||
e2c2206a WL |
2405 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2406 | get_cpu(); | |
2407 | ||
e70b57a6 WL |
2408 | if (__this_cpu_read(cpu_tsc_khz)) { |
2409 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, | |
2410 | &hv_clock.tsc_shift, | |
2411 | &hv_clock.tsc_to_system_mul); | |
2412 | ret = __pvclock_read_cycles(&hv_clock, rdtsc()); | |
2413 | } else | |
8171cd68 | 2414 | ret = get_kvmclock_base_ns() + ka->kvmclock_offset; |
e2c2206a WL |
2415 | |
2416 | put_cpu(); | |
2417 | ||
2418 | return ret; | |
108b249c PB |
2419 | } |
2420 | ||
0d6dd2ff PB |
2421 | static void kvm_setup_pvclock_page(struct kvm_vcpu *v) |
2422 | { | |
2423 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
2424 | struct pvclock_vcpu_time_info guest_hv_clock; | |
2425 | ||
4e335d9e | 2426 | if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, |
0d6dd2ff PB |
2427 | &guest_hv_clock, sizeof(guest_hv_clock)))) |
2428 | return; | |
2429 | ||
2430 | /* This VCPU is paused, but it's legal for a guest to read another | |
2431 | * VCPU's kvmclock, so we really have to follow the specification where | |
2432 | * it says that version is odd if data is being modified, and even after | |
2433 | * it is consistent. | |
2434 | * | |
2435 | * Version field updates must be kept separate. This is because | |
2436 | * kvm_write_guest_cached might use a "rep movs" instruction, and | |
2437 | * writes within a string instruction are weakly ordered. So there | |
2438 | * are three writes overall. | |
2439 | * | |
2440 | * As a small optimization, only write the version field in the first | |
2441 | * and third write. The vcpu->pv_time cache is still valid, because the | |
2442 | * version field is the first in the struct. | |
2443 | */ | |
2444 | BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); | |
2445 | ||
51c4b8bb LA |
2446 | if (guest_hv_clock.version & 1) |
2447 | ++guest_hv_clock.version; /* first time write, random junk */ | |
2448 | ||
0d6dd2ff | 2449 | vcpu->hv_clock.version = guest_hv_clock.version + 1; |
4e335d9e PB |
2450 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2451 | &vcpu->hv_clock, | |
2452 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2453 | |
2454 | smp_wmb(); | |
2455 | ||
2456 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
2457 | vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); | |
2458 | ||
2459 | if (vcpu->pvclock_set_guest_stopped_request) { | |
2460 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
2461 | vcpu->pvclock_set_guest_stopped_request = false; | |
2462 | } | |
2463 | ||
2464 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); | |
2465 | ||
4e335d9e PB |
2466 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2467 | &vcpu->hv_clock, | |
2468 | sizeof(vcpu->hv_clock)); | |
0d6dd2ff PB |
2469 | |
2470 | smp_wmb(); | |
2471 | ||
2472 | vcpu->hv_clock.version++; | |
4e335d9e PB |
2473 | kvm_write_guest_cached(v->kvm, &vcpu->pv_time, |
2474 | &vcpu->hv_clock, | |
2475 | sizeof(vcpu->hv_clock.version)); | |
0d6dd2ff PB |
2476 | } |
2477 | ||
34c238a1 | 2478 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 2479 | { |
78db6a50 | 2480 | unsigned long flags, tgt_tsc_khz; |
18068523 | 2481 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 2482 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 2483 | s64 kernel_ns; |
d828199e | 2484 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 2485 | u8 pvclock_flags; |
d828199e MT |
2486 | bool use_master_clock; |
2487 | ||
2488 | kernel_ns = 0; | |
2489 | host_tsc = 0; | |
18068523 | 2490 | |
d828199e MT |
2491 | /* |
2492 | * If the host uses TSC clock, then passthrough TSC as stable | |
2493 | * to the guest. | |
2494 | */ | |
2495 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
2496 | use_master_clock = ka->use_master_clock; | |
2497 | if (use_master_clock) { | |
2498 | host_tsc = ka->master_cycle_now; | |
2499 | kernel_ns = ka->master_kernel_ns; | |
2500 | } | |
2501 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
c09664bb MT |
2502 | |
2503 | /* Keep irq disabled to prevent changes to the clock */ | |
2504 | local_irq_save(flags); | |
78db6a50 PB |
2505 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
2506 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
2507 | local_irq_restore(flags); |
2508 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
2509 | return 1; | |
2510 | } | |
d828199e | 2511 | if (!use_master_clock) { |
4ea1636b | 2512 | host_tsc = rdtsc(); |
8171cd68 | 2513 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
2514 | } |
2515 | ||
4ba76538 | 2516 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 2517 | |
c285545f ZA |
2518 | /* |
2519 | * We may have to catch up the TSC to match elapsed wall clock | |
2520 | * time for two reasons, even if kvmclock is used. | |
2521 | * 1) CPU could have been running below the maximum TSC rate | |
2522 | * 2) Broken TSC compensation resets the base at each VCPU | |
2523 | * entry to avoid unknown leaps of TSC even when running | |
2524 | * again on the same CPU. This may cause apparent elapsed | |
2525 | * time to disappear, and the guest to stand still or run | |
2526 | * very slowly. | |
2527 | */ | |
2528 | if (vcpu->tsc_catchup) { | |
2529 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
2530 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 2531 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
2532 | tsc_timestamp = tsc; |
2533 | } | |
50d0a0f9 GH |
2534 | } |
2535 | ||
18068523 GOC |
2536 | local_irq_restore(flags); |
2537 | ||
0d6dd2ff | 2538 | /* With all the info we got, fill in the values */ |
18068523 | 2539 | |
78db6a50 PB |
2540 | if (kvm_has_tsc_control) |
2541 | tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); | |
2542 | ||
2543 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 2544 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
2545 | &vcpu->hv_clock.tsc_shift, |
2546 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 2547 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
2548 | } |
2549 | ||
1d5f066e | 2550 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 2551 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 2552 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 2553 | |
d828199e | 2554 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 2555 | pvclock_flags = 0; |
d828199e MT |
2556 | if (use_master_clock) |
2557 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
2558 | ||
78c0337a MT |
2559 | vcpu->hv_clock.flags = pvclock_flags; |
2560 | ||
095cf55d PB |
2561 | if (vcpu->pv_time_enabled) |
2562 | kvm_setup_pvclock_page(v); | |
2563 | if (v == kvm_get_vcpu(v->kvm, 0)) | |
2564 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); | |
8cfdc000 | 2565 | return 0; |
c8076604 GH |
2566 | } |
2567 | ||
0061d53d MT |
2568 | /* |
2569 | * kvmclock updates which are isolated to a given vcpu, such as | |
2570 | * vcpu->cpu migration, should not allow system_timestamp from | |
2571 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
2572 | * correction applies to one vcpu's system_timestamp but not | |
2573 | * the others. | |
2574 | * | |
2575 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
2576 | * We need to rate-limit these requests though, as they can |
2577 | * considerably slow guests that have a large number of vcpus. | |
2578 | * The time for a remote vcpu to update its kvmclock is bound | |
2579 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
2580 | */ |
2581 | ||
7e44e449 AJ |
2582 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
2583 | ||
2584 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d MT |
2585 | { |
2586 | int i; | |
7e44e449 AJ |
2587 | struct delayed_work *dwork = to_delayed_work(work); |
2588 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2589 | kvmclock_update_work); | |
2590 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
2591 | struct kvm_vcpu *vcpu; |
2592 | ||
2593 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 2594 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
2595 | kvm_vcpu_kick(vcpu); |
2596 | } | |
2597 | } | |
2598 | ||
7e44e449 AJ |
2599 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
2600 | { | |
2601 | struct kvm *kvm = v->kvm; | |
2602 | ||
105b21bb | 2603 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
2604 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
2605 | KVMCLOCK_UPDATE_DELAY); | |
2606 | } | |
2607 | ||
332967a3 AJ |
2608 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
2609 | ||
2610 | static void kvmclock_sync_fn(struct work_struct *work) | |
2611 | { | |
2612 | struct delayed_work *dwork = to_delayed_work(work); | |
2613 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
2614 | kvmclock_sync_work); | |
2615 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
2616 | ||
630994b3 MT |
2617 | if (!kvmclock_periodic_sync) |
2618 | return; | |
2619 | ||
332967a3 AJ |
2620 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
2621 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
2622 | KVMCLOCK_SYNC_PERIOD); | |
2623 | } | |
2624 | ||
191c8137 BP |
2625 | /* |
2626 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
2627 | */ | |
2628 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
2629 | { | |
2630 | /* McStatusWrEn enabled? */ | |
23493d0a | 2631 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
2632 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
2633 | ||
2634 | return false; | |
2635 | } | |
2636 | ||
9ffd986c | 2637 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2638 | { |
890ca9ae HY |
2639 | u64 mcg_cap = vcpu->arch.mcg_cap; |
2640 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
2641 | u32 msr = msr_info->index; |
2642 | u64 data = msr_info->data; | |
890ca9ae | 2643 | |
15c4a640 | 2644 | switch (msr) { |
15c4a640 | 2645 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 2646 | vcpu->arch.mcg_status = data; |
15c4a640 | 2647 | break; |
c7ac679c | 2648 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
2649 | if (!(mcg_cap & MCG_CTL_P) && |
2650 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
2651 | return 1; |
2652 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 2653 | return 1; |
890ca9ae HY |
2654 | vcpu->arch.mcg_ctl = data; |
2655 | break; | |
2656 | default: | |
2657 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 2658 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
2659 | u32 offset = array_index_nospec( |
2660 | msr - MSR_IA32_MC0_CTL, | |
2661 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
2662 | ||
114be429 AP |
2663 | /* only 0 or all 1s can be written to IA32_MCi_CTL |
2664 | * some Linux kernels though clear bit 10 in bank 4 to | |
2665 | * workaround a BIOS/GART TBL issue on AMD K8s, ignore | |
2666 | * this to avoid an uncatched #GP in the guest | |
2667 | */ | |
890ca9ae | 2668 | if ((offset & 0x3) == 0 && |
114be429 | 2669 | data != 0 && (data | (1 << 10)) != ~(u64)0) |
890ca9ae | 2670 | return -1; |
191c8137 BP |
2671 | |
2672 | /* MCi_STATUS */ | |
9ffd986c | 2673 | if (!msr_info->host_initiated && |
191c8137 BP |
2674 | (offset & 0x3) == 1 && data != 0) { |
2675 | if (!can_set_mci_status(vcpu)) | |
2676 | return -1; | |
2677 | } | |
2678 | ||
890ca9ae HY |
2679 | vcpu->arch.mce_banks[offset] = data; |
2680 | break; | |
2681 | } | |
2682 | return 1; | |
2683 | } | |
2684 | return 0; | |
2685 | } | |
2686 | ||
ffde22ac ES |
2687 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
2688 | { | |
2689 | struct kvm *kvm = vcpu->kvm; | |
2690 | int lm = is_long_mode(vcpu); | |
2691 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
2692 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
2693 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
2694 | : kvm->arch.xen_hvm_config.blob_size_32; | |
2695 | u32 page_num = data & ~PAGE_MASK; | |
2696 | u64 page_addr = data & PAGE_MASK; | |
2697 | u8 *page; | |
2698 | int r; | |
2699 | ||
2700 | r = -E2BIG; | |
2701 | if (page_num >= blob_size) | |
2702 | goto out; | |
2703 | r = -ENOMEM; | |
ff5c2c03 SL |
2704 | page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); |
2705 | if (IS_ERR(page)) { | |
2706 | r = PTR_ERR(page); | |
ffde22ac | 2707 | goto out; |
ff5c2c03 | 2708 | } |
54bf36aa | 2709 | if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) |
ffde22ac ES |
2710 | goto out_free; |
2711 | r = 0; | |
2712 | out_free: | |
2713 | kfree(page); | |
2714 | out: | |
2715 | return r; | |
2716 | } | |
2717 | ||
2635b5c4 VK |
2718 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
2719 | { | |
2720 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
2721 | ||
2722 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
2723 | } | |
2724 | ||
344d9588 GN |
2725 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
2726 | { | |
2727 | gpa_t gpa = data & ~0x3f; | |
2728 | ||
2635b5c4 VK |
2729 | /* Bits 4:5 are reserved, Should be zero */ |
2730 | if (data & 0x30) | |
344d9588 GN |
2731 | return 1; |
2732 | ||
9d3c447c WL |
2733 | if (!lapic_in_kernel(vcpu)) |
2734 | return 1; | |
2735 | ||
2635b5c4 | 2736 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 2737 | |
2635b5c4 | 2738 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
2739 | kvm_clear_async_pf_completion_queue(vcpu); |
2740 | kvm_async_pf_hash_reset(vcpu); | |
2741 | return 0; | |
2742 | } | |
2743 | ||
4e335d9e | 2744 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 2745 | sizeof(u64))) |
344d9588 GN |
2746 | return 1; |
2747 | ||
6adba527 | 2748 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 2749 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 2750 | |
344d9588 | 2751 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
2752 | |
2753 | return 0; | |
2754 | } | |
2755 | ||
2756 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
2757 | { | |
2758 | /* Bits 8-63 are reserved */ | |
2759 | if (data >> 8) | |
2760 | return 1; | |
2761 | ||
2762 | if (!lapic_in_kernel(vcpu)) | |
2763 | return 1; | |
2764 | ||
2765 | vcpu->arch.apf.msr_int_val = data; | |
2766 | ||
2767 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
2768 | ||
344d9588 GN |
2769 | return 0; |
2770 | } | |
2771 | ||
12f9a48f GC |
2772 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
2773 | { | |
0b79459b | 2774 | vcpu->arch.pv_time_enabled = false; |
49dedf0d | 2775 | vcpu->arch.time = 0; |
12f9a48f GC |
2776 | } |
2777 | ||
7780938c | 2778 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
2779 | { |
2780 | ++vcpu->stat.tlb_flush; | |
7780938c | 2781 | kvm_x86_ops.tlb_flush_all(vcpu); |
f38a7b75 WL |
2782 | } |
2783 | ||
0baedd79 VK |
2784 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
2785 | { | |
2786 | ++vcpu->stat.tlb_flush; | |
2787 | kvm_x86_ops.tlb_flush_guest(vcpu); | |
2788 | } | |
2789 | ||
c9aaa895 GC |
2790 | static void record_steal_time(struct kvm_vcpu *vcpu) |
2791 | { | |
b0431382 BO |
2792 | struct kvm_host_map map; |
2793 | struct kvm_steal_time *st; | |
2794 | ||
c9aaa895 GC |
2795 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
2796 | return; | |
2797 | ||
b0431382 BO |
2798 | /* -EAGAIN is returned in atomic context so we can just return. */ |
2799 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, | |
2800 | &map, &vcpu->arch.st.cache, false)) | |
c9aaa895 GC |
2801 | return; |
2802 | ||
b0431382 BO |
2803 | st = map.hva + |
2804 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
2805 | ||
f38a7b75 WL |
2806 | /* |
2807 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
2808 | * expensive IPIs. | |
2809 | */ | |
b382f44e | 2810 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
b0431382 BO |
2811 | st->preempted & KVM_VCPU_FLUSH_TLB); |
2812 | if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) | |
0baedd79 | 2813 | kvm_vcpu_flush_tlb_guest(vcpu); |
0b9f6c46 | 2814 | |
a6bd811f | 2815 | vcpu->arch.st.preempted = 0; |
35f3fae1 | 2816 | |
b0431382 BO |
2817 | if (st->version & 1) |
2818 | st->version += 1; /* first time write, random junk */ | |
35f3fae1 | 2819 | |
b0431382 | 2820 | st->version += 1; |
35f3fae1 WL |
2821 | |
2822 | smp_wmb(); | |
2823 | ||
b0431382 | 2824 | st->steal += current->sched_info.run_delay - |
c54cdf14 LC |
2825 | vcpu->arch.st.last_steal; |
2826 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
35f3fae1 | 2827 | |
35f3fae1 WL |
2828 | smp_wmb(); |
2829 | ||
b0431382 | 2830 | st->version += 1; |
c9aaa895 | 2831 | |
b0431382 | 2832 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); |
c9aaa895 GC |
2833 | } |
2834 | ||
8fe8ab46 | 2835 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 2836 | { |
5753785f | 2837 | bool pr = false; |
8fe8ab46 WA |
2838 | u32 msr = msr_info->index; |
2839 | u64 data = msr_info->data; | |
5753785f | 2840 | |
15c4a640 | 2841 | switch (msr) { |
2e32b719 | 2842 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
2843 | case MSR_IA32_UCODE_WRITE: |
2844 | case MSR_VM_HSAVE_PA: | |
2845 | case MSR_AMD64_PATCH_LOADER: | |
2846 | case MSR_AMD64_BU_CFG2: | |
405a353a | 2847 | case MSR_AMD64_DC_CFG: |
0e1b869f | 2848 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
2849 | break; |
2850 | ||
518e7b94 WL |
2851 | case MSR_IA32_UCODE_REV: |
2852 | if (msr_info->host_initiated) | |
2853 | vcpu->arch.microcode_version = data; | |
2854 | break; | |
0cf9135b SC |
2855 | case MSR_IA32_ARCH_CAPABILITIES: |
2856 | if (!msr_info->host_initiated) | |
2857 | return 1; | |
2858 | vcpu->arch.arch_capabilities = data; | |
2859 | break; | |
d574c539 VK |
2860 | case MSR_IA32_PERF_CAPABILITIES: { |
2861 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
2862 | ||
2863 | if (!msr_info->host_initiated) | |
2864 | return 1; | |
2865 | if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) | |
2866 | return 1; | |
2867 | if (data & ~msr_ent.data) | |
2868 | return 1; | |
2869 | ||
2870 | vcpu->arch.perf_capabilities = data; | |
2871 | ||
2872 | return 0; | |
2873 | } | |
15c4a640 | 2874 | case MSR_EFER: |
11988499 | 2875 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
2876 | case MSR_K7_HWCR: |
2877 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 2878 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 2879 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
2880 | |
2881 | /* Handle McStatusWrEn */ | |
2882 | if (data == BIT_ULL(18)) { | |
2883 | vcpu->arch.msr_hwcr = data; | |
2884 | } else if (data != 0) { | |
a737f256 CD |
2885 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
2886 | data); | |
8f1589d9 AP |
2887 | return 1; |
2888 | } | |
15c4a640 | 2889 | break; |
f7c6d140 AP |
2890 | case MSR_FAM10H_MMIO_CONF_BASE: |
2891 | if (data != 0) { | |
a737f256 CD |
2892 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
2893 | "0x%llx\n", data); | |
f7c6d140 AP |
2894 | return 1; |
2895 | } | |
15c4a640 | 2896 | break; |
b5e2fec0 AG |
2897 | case MSR_IA32_DEBUGCTLMSR: |
2898 | if (!data) { | |
2899 | /* We support the non-activated case already */ | |
2900 | break; | |
2901 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
2902 | /* Values other than LBR and BTF are vendor-specific, | |
2903 | thus reserved and should throw a #GP */ | |
2904 | return 1; | |
2905 | } | |
a737f256 CD |
2906 | vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", |
2907 | __func__, data); | |
b5e2fec0 | 2908 | break; |
9ba075a6 | 2909 | case 0x200 ... 0x2ff: |
ff53604b | 2910 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 2911 | case MSR_IA32_APICBASE: |
58cb628d | 2912 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 2913 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 2914 | return kvm_x2apic_msr_write(vcpu, msr, data); |
a3e06bbe LJ |
2915 | case MSR_IA32_TSCDEADLINE: |
2916 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2917 | break; | |
ba904635 | 2918 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 2919 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 2920 | if (!msr_info->host_initiated) { |
d913b904 | 2921 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 2922 | adjust_tsc_offset_guest(vcpu, adj); |
ba904635 WA |
2923 | } |
2924 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
2925 | } | |
2926 | break; | |
15c4a640 | 2927 | case MSR_IA32_MISC_ENABLE: |
511a8556 WL |
2928 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
2929 | ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { | |
2930 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) | |
2931 | return 1; | |
2932 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 2933 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
2934 | } else { |
2935 | vcpu->arch.ia32_misc_enable_msr = data; | |
2936 | } | |
15c4a640 | 2937 | break; |
64d60670 PB |
2938 | case MSR_IA32_SMBASE: |
2939 | if (!msr_info->host_initiated) | |
2940 | return 1; | |
2941 | vcpu->arch.smbase = data; | |
2942 | break; | |
73f624f4 PB |
2943 | case MSR_IA32_POWER_CTL: |
2944 | vcpu->arch.msr_ia32_power_ctl = data; | |
2945 | break; | |
dd259935 PB |
2946 | case MSR_IA32_TSC: |
2947 | kvm_write_tsc(vcpu, msr_info); | |
2948 | break; | |
864e2ab2 AL |
2949 | case MSR_IA32_XSS: |
2950 | if (!msr_info->host_initiated && | |
2951 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
2952 | return 1; | |
2953 | /* | |
a1bead2a SC |
2954 | * KVM supports exposing PT to the guest, but does not support |
2955 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
2956 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 2957 | */ |
408e9a31 | 2958 | if (data & ~supported_xss) |
864e2ab2 AL |
2959 | return 1; |
2960 | vcpu->arch.ia32_xss = data; | |
2961 | break; | |
52797bf9 LA |
2962 | case MSR_SMI_COUNT: |
2963 | if (!msr_info->host_initiated) | |
2964 | return 1; | |
2965 | vcpu->arch.smi_count = data; | |
2966 | break; | |
11c6bffa | 2967 | case MSR_KVM_WALL_CLOCK_NEW: |
18068523 GOC |
2968 | case MSR_KVM_WALL_CLOCK: |
2969 | vcpu->kvm->arch.wall_clock = data; | |
2970 | kvm_write_wall_clock(vcpu->kvm, data); | |
2971 | break; | |
11c6bffa | 2972 | case MSR_KVM_SYSTEM_TIME_NEW: |
18068523 | 2973 | case MSR_KVM_SYSTEM_TIME: { |
54750f2c MT |
2974 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2975 | ||
54750f2c MT |
2976 | if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { |
2977 | bool tmp = (msr == MSR_KVM_SYSTEM_TIME); | |
2978 | ||
2979 | if (ka->boot_vcpu_runs_old_kvmclock != tmp) | |
1bd2009e | 2980 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
54750f2c MT |
2981 | |
2982 | ka->boot_vcpu_runs_old_kvmclock = tmp; | |
2983 | } | |
2984 | ||
18068523 | 2985 | vcpu->arch.time = data; |
0061d53d | 2986 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
18068523 GOC |
2987 | |
2988 | /* we verify if the enable bit is set... */ | |
49dedf0d | 2989 | vcpu->arch.pv_time_enabled = false; |
18068523 GOC |
2990 | if (!(data & 1)) |
2991 | break; | |
2992 | ||
49dedf0d | 2993 | if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, |
8f964525 AH |
2994 | &vcpu->arch.pv_time, data & ~1ULL, |
2995 | sizeof(struct pvclock_vcpu_time_info))) | |
0b79459b | 2996 | vcpu->arch.pv_time_enabled = true; |
32cad84f | 2997 | |
18068523 GOC |
2998 | break; |
2999 | } | |
344d9588 GN |
3000 | case MSR_KVM_ASYNC_PF_EN: |
3001 | if (kvm_pv_enable_async_pf(vcpu, data)) | |
3002 | return 1; | |
3003 | break; | |
2635b5c4 VK |
3004 | case MSR_KVM_ASYNC_PF_INT: |
3005 | if (kvm_pv_enable_async_pf_int(vcpu, data)) | |
3006 | return 1; | |
3007 | break; | |
557a961a VK |
3008 | case MSR_KVM_ASYNC_PF_ACK: |
3009 | if (data & 0x1) { | |
3010 | vcpu->arch.apf.pageready_pending = false; | |
3011 | kvm_check_async_pf_completion(vcpu); | |
3012 | } | |
3013 | break; | |
c9aaa895 GC |
3014 | case MSR_KVM_STEAL_TIME: |
3015 | ||
3016 | if (unlikely(!sched_info_on())) | |
3017 | return 1; | |
3018 | ||
3019 | if (data & KVM_STEAL_RESERVED_MASK) | |
3020 | return 1; | |
3021 | ||
c9aaa895 GC |
3022 | vcpu->arch.st.msr_val = data; |
3023 | ||
3024 | if (!(data & KVM_MSR_ENABLED)) | |
3025 | break; | |
3026 | ||
c9aaa895 GC |
3027 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3028 | ||
3029 | break; | |
ae7a2a3f | 3030 | case MSR_KVM_PV_EOI_EN: |
72bbf935 | 3031 | if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3032 | return 1; |
3033 | break; | |
c9aaa895 | 3034 | |
2d5ba19b MT |
3035 | case MSR_KVM_POLL_CONTROL: |
3036 | /* only enable bit supported */ | |
3037 | if (data & (-1ULL << 1)) | |
3038 | return 1; | |
3039 | ||
3040 | vcpu->arch.msr_kvm_poll_control = data; | |
3041 | break; | |
3042 | ||
890ca9ae HY |
3043 | case MSR_IA32_MCG_CTL: |
3044 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3045 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3046 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3047 | |
6912ac32 WH |
3048 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3049 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3050 | pr = true; /* fall through */ | |
3051 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: | |
3052 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3053 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3054 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3055 | |
3056 | if (pr || data != 0) | |
a737f256 CD |
3057 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3058 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3059 | break; |
84e0cefa JS |
3060 | case MSR_K7_CLK_CTL: |
3061 | /* | |
3062 | * Ignore all writes to this no longer documented MSR. | |
3063 | * Writes are only relevant for old K7 processors, | |
3064 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3065 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3066 | * affected processor models on the command line, hence |
3067 | * the need to ignore the workaround. | |
3068 | */ | |
3069 | break; | |
55cd8e5a | 3070 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3071 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3072 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3073 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3074 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3075 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3076 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3077 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3078 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3079 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3080 | msr_info->host_initiated); | |
91c9c3ed | 3081 | case MSR_IA32_BBL_CR_CTL3: |
3082 | /* Drop writes to this legacy MSR -- see rdmsr | |
3083 | * counterpart for further detail. | |
3084 | */ | |
fab0aa3b EM |
3085 | if (report_ignored_msrs) |
3086 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3087 | msr, data); | |
91c9c3ed | 3088 | break; |
2b036c6b | 3089 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3090 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3091 | return 1; |
3092 | vcpu->arch.osvw.length = data; | |
3093 | break; | |
3094 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3095 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3096 | return 1; |
3097 | vcpu->arch.osvw.status = data; | |
3098 | break; | |
db2336a8 KH |
3099 | case MSR_PLATFORM_INFO: |
3100 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3101 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3102 | cpuid_fault_enabled(vcpu))) | |
3103 | return 1; | |
3104 | vcpu->arch.msr_platform_info = data; | |
3105 | break; | |
3106 | case MSR_MISC_FEATURES_ENABLES: | |
3107 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3108 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3109 | !supports_cpuid_fault(vcpu))) | |
3110 | return 1; | |
3111 | vcpu->arch.msr_misc_features_enables = data; | |
3112 | break; | |
15c4a640 | 3113 | default: |
ffde22ac ES |
3114 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
3115 | return xen_hvm_config(vcpu, data); | |
c6702c9d | 3116 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3117 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3118 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3119 | } |
3120 | return 0; | |
3121 | } | |
3122 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3123 | ||
44883f01 | 3124 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3125 | { |
3126 | u64 data; | |
890ca9ae HY |
3127 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3128 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
3129 | |
3130 | switch (msr) { | |
15c4a640 CO |
3131 | case MSR_IA32_P5_MC_ADDR: |
3132 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3133 | data = 0; |
3134 | break; | |
15c4a640 | 3135 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3136 | data = vcpu->arch.mcg_cap; |
3137 | break; | |
c7ac679c | 3138 | case MSR_IA32_MCG_CTL: |
44883f01 | 3139 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3140 | return 1; |
3141 | data = vcpu->arch.mcg_ctl; | |
3142 | break; | |
3143 | case MSR_IA32_MCG_STATUS: | |
3144 | data = vcpu->arch.mcg_status; | |
3145 | break; | |
3146 | default: | |
3147 | if (msr >= MSR_IA32_MC0_CTL && | |
81760dcc | 3148 | msr < MSR_IA32_MCx_CTL(bank_num)) { |
6ec4c5ee MP |
3149 | u32 offset = array_index_nospec( |
3150 | msr - MSR_IA32_MC0_CTL, | |
3151 | MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); | |
3152 | ||
890ca9ae HY |
3153 | data = vcpu->arch.mce_banks[offset]; |
3154 | break; | |
3155 | } | |
3156 | return 1; | |
3157 | } | |
3158 | *pdata = data; | |
3159 | return 0; | |
3160 | } | |
3161 | ||
609e36d3 | 3162 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3163 | { |
609e36d3 | 3164 | switch (msr_info->index) { |
890ca9ae | 3165 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3166 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3167 | case MSR_IA32_DEBUGCTLMSR: |
3168 | case MSR_IA32_LASTBRANCHFROMIP: | |
3169 | case MSR_IA32_LASTBRANCHTOIP: | |
3170 | case MSR_IA32_LASTINTFROMIP: | |
3171 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd | 3172 | case MSR_K8_SYSCFG: |
3afb1121 PB |
3173 | case MSR_K8_TSEG_ADDR: |
3174 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3175 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3176 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3177 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3178 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3179 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3180 | case MSR_IA32_PERF_CTL: |
405a353a | 3181 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3182 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3183 | /* |
3184 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3185 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3186 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3187 | * so for existing CPU-specific MSRs. | |
3188 | */ | |
3189 | case MSR_RAPL_POWER_UNIT: | |
3190 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3191 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3192 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3193 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3194 | msr_info->data = 0; |
15c4a640 | 3195 | break; |
c51eb52b | 3196 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
6912ac32 WH |
3197 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3198 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3199 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3200 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3201 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3202 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3203 | msr_info->data = 0; |
5753785f | 3204 | break; |
742bc670 | 3205 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3206 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3207 | break; |
0cf9135b SC |
3208 | case MSR_IA32_ARCH_CAPABILITIES: |
3209 | if (!msr_info->host_initiated && | |
3210 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3211 | return 1; | |
3212 | msr_info->data = vcpu->arch.arch_capabilities; | |
3213 | break; | |
d574c539 VK |
3214 | case MSR_IA32_PERF_CAPABILITIES: |
3215 | if (!msr_info->host_initiated && | |
3216 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3217 | return 1; | |
3218 | msr_info->data = vcpu->arch.perf_capabilities; | |
3219 | break; | |
73f624f4 PB |
3220 | case MSR_IA32_POWER_CTL: |
3221 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3222 | break; | |
dd259935 PB |
3223 | case MSR_IA32_TSC: |
3224 | msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; | |
3225 | break; | |
9ba075a6 | 3226 | case MSR_MTRRcap: |
9ba075a6 | 3227 | case 0x200 ... 0x2ff: |
ff53604b | 3228 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 3229 | case 0xcd: /* fsb frequency */ |
609e36d3 | 3230 | msr_info->data = 3; |
15c4a640 | 3231 | break; |
7b914098 JS |
3232 | /* |
3233 | * MSR_EBC_FREQUENCY_ID | |
3234 | * Conservative value valid for even the basic CPU models. | |
3235 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
3236 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
3237 | * and 266MHz for model 3, or 4. Set Core Clock | |
3238 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
3239 | * 31:24) even though these are only valid for CPU | |
3240 | * models > 2, however guests may end up dividing or | |
3241 | * multiplying by zero otherwise. | |
3242 | */ | |
3243 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 3244 | msr_info->data = 1 << 24; |
7b914098 | 3245 | break; |
15c4a640 | 3246 | case MSR_IA32_APICBASE: |
609e36d3 | 3247 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 3248 | break; |
bf10bd0b | 3249 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 3250 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
a3e06bbe | 3251 | case MSR_IA32_TSCDEADLINE: |
609e36d3 | 3252 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 3253 | break; |
ba904635 | 3254 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 3255 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 3256 | break; |
15c4a640 | 3257 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 3258 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 3259 | break; |
64d60670 PB |
3260 | case MSR_IA32_SMBASE: |
3261 | if (!msr_info->host_initiated) | |
3262 | return 1; | |
3263 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 3264 | break; |
52797bf9 LA |
3265 | case MSR_SMI_COUNT: |
3266 | msr_info->data = vcpu->arch.smi_count; | |
3267 | break; | |
847f0ad8 AG |
3268 | case MSR_IA32_PERF_STATUS: |
3269 | /* TSC increment by tick */ | |
609e36d3 | 3270 | msr_info->data = 1000ULL; |
847f0ad8 | 3271 | /* CPU multiplier */ |
b0996ae4 | 3272 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 3273 | break; |
15c4a640 | 3274 | case MSR_EFER: |
609e36d3 | 3275 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 3276 | break; |
18068523 | 3277 | case MSR_KVM_WALL_CLOCK: |
11c6bffa | 3278 | case MSR_KVM_WALL_CLOCK_NEW: |
609e36d3 | 3279 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
3280 | break; |
3281 | case MSR_KVM_SYSTEM_TIME: | |
11c6bffa | 3282 | case MSR_KVM_SYSTEM_TIME_NEW: |
609e36d3 | 3283 | msr_info->data = vcpu->arch.time; |
18068523 | 3284 | break; |
344d9588 | 3285 | case MSR_KVM_ASYNC_PF_EN: |
2635b5c4 VK |
3286 | msr_info->data = vcpu->arch.apf.msr_en_val; |
3287 | break; | |
3288 | case MSR_KVM_ASYNC_PF_INT: | |
3289 | msr_info->data = vcpu->arch.apf.msr_int_val; | |
344d9588 | 3290 | break; |
557a961a VK |
3291 | case MSR_KVM_ASYNC_PF_ACK: |
3292 | msr_info->data = 0; | |
3293 | break; | |
c9aaa895 | 3294 | case MSR_KVM_STEAL_TIME: |
609e36d3 | 3295 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 3296 | break; |
1d92128f | 3297 | case MSR_KVM_PV_EOI_EN: |
609e36d3 | 3298 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 3299 | break; |
2d5ba19b MT |
3300 | case MSR_KVM_POLL_CONTROL: |
3301 | msr_info->data = vcpu->arch.msr_kvm_poll_control; | |
3302 | break; | |
890ca9ae HY |
3303 | case MSR_IA32_P5_MC_ADDR: |
3304 | case MSR_IA32_P5_MC_TYPE: | |
3305 | case MSR_IA32_MCG_CAP: | |
3306 | case MSR_IA32_MCG_CTL: | |
3307 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3308 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
3309 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
3310 | msr_info->host_initiated); | |
864e2ab2 AL |
3311 | case MSR_IA32_XSS: |
3312 | if (!msr_info->host_initiated && | |
3313 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3314 | return 1; | |
3315 | msr_info->data = vcpu->arch.ia32_xss; | |
3316 | break; | |
84e0cefa JS |
3317 | case MSR_K7_CLK_CTL: |
3318 | /* | |
3319 | * Provide expected ramp-up count for K7. All other | |
3320 | * are set to zero, indicating minimum divisors for | |
3321 | * every field. | |
3322 | * | |
3323 | * This prevents guest kernels on AMD host with CPU | |
3324 | * type 6, model 8 and higher from exploding due to | |
3325 | * the rdmsr failing. | |
3326 | */ | |
609e36d3 | 3327 | msr_info->data = 0x20000000; |
84e0cefa | 3328 | break; |
55cd8e5a | 3329 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3330 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3331 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3332 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3333 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3334 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3335 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3336 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3337 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 3338 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
3339 | msr_info->index, &msr_info->data, |
3340 | msr_info->host_initiated); | |
91c9c3ed | 3341 | case MSR_IA32_BBL_CR_CTL3: |
3342 | /* This legacy MSR exists but isn't fully documented in current | |
3343 | * silicon. It is however accessed by winxp in very narrow | |
3344 | * scenarios where it sets bit #19, itself documented as | |
3345 | * a "reserved" bit. Best effort attempt to source coherent | |
3346 | * read data here should the balance of the register be | |
3347 | * interpreted by the guest: | |
3348 | * | |
3349 | * L2 cache control register 3: 64GB range, 256KB size, | |
3350 | * enabled, latency 0x1, configured | |
3351 | */ | |
609e36d3 | 3352 | msr_info->data = 0xbe702111; |
91c9c3ed | 3353 | break; |
2b036c6b | 3354 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3355 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3356 | return 1; |
609e36d3 | 3357 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
3358 | break; |
3359 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3360 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 3361 | return 1; |
609e36d3 | 3362 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 3363 | break; |
db2336a8 | 3364 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
3365 | if (!msr_info->host_initiated && |
3366 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
3367 | return 1; | |
db2336a8 KH |
3368 | msr_info->data = vcpu->arch.msr_platform_info; |
3369 | break; | |
3370 | case MSR_MISC_FEATURES_ENABLES: | |
3371 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
3372 | break; | |
191c8137 BP |
3373 | case MSR_K7_HWCR: |
3374 | msr_info->data = vcpu->arch.msr_hwcr; | |
3375 | break; | |
15c4a640 | 3376 | default: |
c6702c9d | 3377 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3378 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 3379 | return KVM_MSR_RET_INVALID; |
15c4a640 | 3380 | } |
15c4a640 CO |
3381 | return 0; |
3382 | } | |
3383 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
3384 | ||
313a3dc7 CO |
3385 | /* |
3386 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
3387 | * | |
3388 | * @return number of msrs set successfully. | |
3389 | */ | |
3390 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
3391 | struct kvm_msr_entry *entries, | |
3392 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3393 | unsigned index, u64 *data)) | |
3394 | { | |
801e459a | 3395 | int i; |
313a3dc7 | 3396 | |
313a3dc7 CO |
3397 | for (i = 0; i < msrs->nmsrs; ++i) |
3398 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
3399 | break; | |
3400 | ||
313a3dc7 CO |
3401 | return i; |
3402 | } | |
3403 | ||
3404 | /* | |
3405 | * Read or write a bunch of msrs. Parameters are user addresses. | |
3406 | * | |
3407 | * @return number of msrs set successfully. | |
3408 | */ | |
3409 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
3410 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
3411 | unsigned index, u64 *data), | |
3412 | int writeback) | |
3413 | { | |
3414 | struct kvm_msrs msrs; | |
3415 | struct kvm_msr_entry *entries; | |
3416 | int r, n; | |
3417 | unsigned size; | |
3418 | ||
3419 | r = -EFAULT; | |
0e96f31e | 3420 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
3421 | goto out; |
3422 | ||
3423 | r = -E2BIG; | |
3424 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
3425 | goto out; | |
3426 | ||
313a3dc7 | 3427 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
3428 | entries = memdup_user(user_msrs->entries, size); |
3429 | if (IS_ERR(entries)) { | |
3430 | r = PTR_ERR(entries); | |
313a3dc7 | 3431 | goto out; |
ff5c2c03 | 3432 | } |
313a3dc7 CO |
3433 | |
3434 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
3435 | if (r < 0) | |
3436 | goto out_free; | |
3437 | ||
3438 | r = -EFAULT; | |
3439 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
3440 | goto out_free; | |
3441 | ||
3442 | r = n; | |
3443 | ||
3444 | out_free: | |
7a73c028 | 3445 | kfree(entries); |
313a3dc7 CO |
3446 | out: |
3447 | return r; | |
3448 | } | |
3449 | ||
4d5422ce WL |
3450 | static inline bool kvm_can_mwait_in_guest(void) |
3451 | { | |
3452 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
3453 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
3454 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
3455 | } |
3456 | ||
784aa3d7 | 3457 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 3458 | { |
4d5422ce | 3459 | int r = 0; |
018d00d2 ZX |
3460 | |
3461 | switch (ext) { | |
3462 | case KVM_CAP_IRQCHIP: | |
3463 | case KVM_CAP_HLT: | |
3464 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 3465 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 3466 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 3467 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 3468 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 3469 | case KVM_CAP_PIT: |
a28e4f5a | 3470 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 3471 | case KVM_CAP_MP_STATE: |
ed848624 | 3472 | case KVM_CAP_SYNC_MMU: |
a355c85c | 3473 | case KVM_CAP_USER_NMI: |
52d939a0 | 3474 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 3475 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 3476 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 3477 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 3478 | case KVM_CAP_PIT2: |
e9f42757 | 3479 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 3480 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 3481 | case KVM_CAP_XEN_HVM: |
3cfc3092 | 3482 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 3483 | case KVM_CAP_HYPERV: |
10388a07 | 3484 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 3485 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 3486 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 3487 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 3488 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 3489 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 3490 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 3491 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 3492 | case KVM_CAP_HYPERV_CPUID: |
ab9f4ecb | 3493 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 3494 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 3495 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 3496 | case KVM_CAP_XSAVE: |
344d9588 | 3497 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 3498 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 3499 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 3500 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 3501 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 3502 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 3503 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 3504 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 3505 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 3506 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 3507 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 3508 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 3509 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 3510 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 3511 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 3512 | case KVM_CAP_EXCEPTION_PAYLOAD: |
b9b2782c | 3513 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 3514 | case KVM_CAP_LAST_CPU: |
018d00d2 ZX |
3515 | r = 1; |
3516 | break; | |
01643c51 KH |
3517 | case KVM_CAP_SYNC_REGS: |
3518 | r = KVM_SYNC_X86_VALID_FIELDS; | |
3519 | break; | |
e3fd9a93 PB |
3520 | case KVM_CAP_ADJUST_CLOCK: |
3521 | r = KVM_CLOCK_TSC_STABLE; | |
3522 | break; | |
4d5422ce | 3523 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
3524 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
3525 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
3526 | if(kvm_can_mwait_in_guest()) |
3527 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 3528 | break; |
6d396b55 PB |
3529 | case KVM_CAP_X86_SMM: |
3530 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
3531 | * and SMM handlers might indeed rely on 4G segment limits, | |
3532 | * so do not report SMM to be available if real mode is | |
3533 | * emulated via vm86 mode. Still, do not go to great lengths | |
3534 | * to avoid userspace's usage of the feature, because it is a | |
3535 | * fringe case that is not enabled except via specific settings | |
3536 | * of the module parameters. | |
3537 | */ | |
afaf0b2f | 3538 | r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE); |
6d396b55 | 3539 | break; |
774ead3a | 3540 | case KVM_CAP_VAPIC: |
afaf0b2f | 3541 | r = !kvm_x86_ops.cpu_has_accelerated_tpr(); |
774ead3a | 3542 | break; |
f725230a | 3543 | case KVM_CAP_NR_VCPUS: |
8c3ba334 SL |
3544 | r = KVM_SOFT_MAX_VCPUS; |
3545 | break; | |
3546 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
3547 | r = KVM_MAX_VCPUS; |
3548 | break; | |
a86cb413 TH |
3549 | case KVM_CAP_MAX_VCPU_ID: |
3550 | r = KVM_MAX_VCPU_ID; | |
3551 | break; | |
a68a6a72 MT |
3552 | case KVM_CAP_PV_MMU: /* obsolete */ |
3553 | r = 0; | |
2f333bcb | 3554 | break; |
890ca9ae HY |
3555 | case KVM_CAP_MCE: |
3556 | r = KVM_MAX_MCE_BANKS; | |
3557 | break; | |
2d5b5a66 | 3558 | case KVM_CAP_XCRS: |
d366bf7e | 3559 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 3560 | break; |
92a1f12d JR |
3561 | case KVM_CAP_TSC_CONTROL: |
3562 | r = kvm_has_tsc_control; | |
3563 | break; | |
37131313 RK |
3564 | case KVM_CAP_X2APIC_API: |
3565 | r = KVM_X2APIC_API_VALID_FLAGS; | |
3566 | break; | |
8fcc4b59 | 3567 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
3568 | r = kvm_x86_ops.nested_ops->get_state ? |
3569 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 3570 | break; |
344c6c80 | 3571 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 3572 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
3573 | break; |
3574 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 3575 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 3576 | break; |
018d00d2 | 3577 | default: |
018d00d2 ZX |
3578 | break; |
3579 | } | |
3580 | return r; | |
3581 | ||
3582 | } | |
3583 | ||
043405e1 CO |
3584 | long kvm_arch_dev_ioctl(struct file *filp, |
3585 | unsigned int ioctl, unsigned long arg) | |
3586 | { | |
3587 | void __user *argp = (void __user *)arg; | |
3588 | long r; | |
3589 | ||
3590 | switch (ioctl) { | |
3591 | case KVM_GET_MSR_INDEX_LIST: { | |
3592 | struct kvm_msr_list __user *user_msr_list = argp; | |
3593 | struct kvm_msr_list msr_list; | |
3594 | unsigned n; | |
3595 | ||
3596 | r = -EFAULT; | |
0e96f31e | 3597 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
3598 | goto out; |
3599 | n = msr_list.nmsrs; | |
62ef68bb | 3600 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 3601 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
3602 | goto out; |
3603 | r = -E2BIG; | |
e125e7b6 | 3604 | if (n < msr_list.nmsrs) |
043405e1 CO |
3605 | goto out; |
3606 | r = -EFAULT; | |
3607 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
3608 | num_msrs_to_save * sizeof(u32))) | |
3609 | goto out; | |
e125e7b6 | 3610 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 3611 | &emulated_msrs, |
62ef68bb | 3612 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
3613 | goto out; |
3614 | r = 0; | |
3615 | break; | |
3616 | } | |
9c15bb1d BP |
3617 | case KVM_GET_SUPPORTED_CPUID: |
3618 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
3619 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
3620 | struct kvm_cpuid2 cpuid; | |
3621 | ||
3622 | r = -EFAULT; | |
0e96f31e | 3623 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 3624 | goto out; |
9c15bb1d BP |
3625 | |
3626 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
3627 | ioctl); | |
674eea0f AK |
3628 | if (r) |
3629 | goto out; | |
3630 | ||
3631 | r = -EFAULT; | |
0e96f31e | 3632 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
3633 | goto out; |
3634 | r = 0; | |
3635 | break; | |
3636 | } | |
cf6c26ec | 3637 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 3638 | r = -EFAULT; |
c45dcc71 AR |
3639 | if (copy_to_user(argp, &kvm_mce_cap_supported, |
3640 | sizeof(kvm_mce_cap_supported))) | |
890ca9ae HY |
3641 | goto out; |
3642 | r = 0; | |
3643 | break; | |
801e459a TL |
3644 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
3645 | struct kvm_msr_list __user *user_msr_list = argp; | |
3646 | struct kvm_msr_list msr_list; | |
3647 | unsigned int n; | |
3648 | ||
3649 | r = -EFAULT; | |
3650 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
3651 | goto out; | |
3652 | n = msr_list.nmsrs; | |
3653 | msr_list.nmsrs = num_msr_based_features; | |
3654 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
3655 | goto out; | |
3656 | r = -E2BIG; | |
3657 | if (n < msr_list.nmsrs) | |
3658 | goto out; | |
3659 | r = -EFAULT; | |
3660 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
3661 | num_msr_based_features * sizeof(u32))) | |
3662 | goto out; | |
3663 | r = 0; | |
3664 | break; | |
3665 | } | |
3666 | case KVM_GET_MSRS: | |
3667 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
3668 | break; | |
043405e1 CO |
3669 | default: |
3670 | r = -EINVAL; | |
cf6c26ec | 3671 | break; |
043405e1 CO |
3672 | } |
3673 | out: | |
3674 | return r; | |
3675 | } | |
3676 | ||
f5f48ee1 SY |
3677 | static void wbinvd_ipi(void *garbage) |
3678 | { | |
3679 | wbinvd(); | |
3680 | } | |
3681 | ||
3682 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
3683 | { | |
e0f0bbc5 | 3684 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
3685 | } |
3686 | ||
313a3dc7 CO |
3687 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
3688 | { | |
f5f48ee1 SY |
3689 | /* Address WBINVD may be executed by guest */ |
3690 | if (need_emulate_wbinvd(vcpu)) { | |
afaf0b2f | 3691 | if (kvm_x86_ops.has_wbinvd_exit()) |
f5f48ee1 SY |
3692 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
3693 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
3694 | smp_call_function_single(vcpu->cpu, | |
3695 | wbinvd_ipi, NULL, 1); | |
3696 | } | |
3697 | ||
afaf0b2f | 3698 | kvm_x86_ops.vcpu_load(vcpu, cpu); |
8f6055cb | 3699 | |
37486135 BM |
3700 | /* Save host pkru register if supported */ |
3701 | vcpu->arch.host_pkru = read_pkru(); | |
3702 | ||
0dd6a6ed ZA |
3703 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
3704 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
3705 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
3706 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 3707 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 3708 | } |
8f6055cb | 3709 | |
b0c39dc6 | 3710 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 3711 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 3712 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
3713 | if (tsc_delta < 0) |
3714 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 3715 | |
b0c39dc6 | 3716 | if (kvm_check_tsc_unstable()) { |
07c1419a | 3717 | u64 offset = kvm_compute_tsc_offset(vcpu, |
b183aa58 | 3718 | vcpu->arch.last_guest_tsc); |
a545ab6a | 3719 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 3720 | vcpu->arch.tsc_catchup = 1; |
c285545f | 3721 | } |
a749e247 PB |
3722 | |
3723 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
3724 | kvm_lapic_restart_hv_timer(vcpu); | |
3725 | ||
d98d07ca MT |
3726 | /* |
3727 | * On a host with synchronized TSC, there is no need to update | |
3728 | * kvmclock on vcpu->cpu migration | |
3729 | */ | |
3730 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 3731 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 3732 | if (vcpu->cpu != cpu) |
1bd2009e | 3733 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 3734 | vcpu->cpu = cpu; |
6b7d7e76 | 3735 | } |
c9aaa895 | 3736 | |
c9aaa895 | 3737 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
3738 | } |
3739 | ||
0b9f6c46 PX |
3740 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
3741 | { | |
b0431382 BO |
3742 | struct kvm_host_map map; |
3743 | struct kvm_steal_time *st; | |
3744 | ||
0b9f6c46 PX |
3745 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3746 | return; | |
3747 | ||
a6bd811f | 3748 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
3749 | return; |
3750 | ||
b0431382 BO |
3751 | if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, |
3752 | &vcpu->arch.st.cache, true)) | |
3753 | return; | |
3754 | ||
3755 | st = map.hva + | |
3756 | offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); | |
0b9f6c46 | 3757 | |
a6bd811f | 3758 | st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; |
0b9f6c46 | 3759 | |
b0431382 | 3760 | kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); |
0b9f6c46 PX |
3761 | } |
3762 | ||
313a3dc7 CO |
3763 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
3764 | { | |
cc0d907c | 3765 | int idx; |
de63ad4c LM |
3766 | |
3767 | if (vcpu->preempted) | |
afaf0b2f | 3768 | vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); |
de63ad4c | 3769 | |
931f261b AA |
3770 | /* |
3771 | * Disable page faults because we're in atomic context here. | |
3772 | * kvm_write_guest_offset_cached() would call might_fault() | |
3773 | * that relies on pagefault_disable() to tell if there's a | |
3774 | * bug. NOTE: the write to guest memory may not go through if | |
3775 | * during postcopy live migration or if there's heavy guest | |
3776 | * paging. | |
3777 | */ | |
3778 | pagefault_disable(); | |
cc0d907c AA |
3779 | /* |
3780 | * kvm_memslots() will be called by | |
3781 | * kvm_write_guest_offset_cached() so take the srcu lock. | |
3782 | */ | |
3783 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
0b9f6c46 | 3784 | kvm_steal_time_set_preempted(vcpu); |
cc0d907c | 3785 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
931f261b | 3786 | pagefault_enable(); |
afaf0b2f | 3787 | kvm_x86_ops.vcpu_put(vcpu); |
4ea1636b | 3788 | vcpu->arch.last_host_tsc = rdtsc(); |
efdab992 | 3789 | /* |
f9dcf08e RK |
3790 | * If userspace has set any breakpoints or watchpoints, dr6 is restored |
3791 | * on every vmexit, but if not, we might have a stale dr6 from the | |
3792 | * guest. do_debug expects dr6 to be cleared after it runs, do the same. | |
efdab992 | 3793 | */ |
f9dcf08e | 3794 | set_debugreg(0, 6); |
313a3dc7 CO |
3795 | } |
3796 | ||
313a3dc7 CO |
3797 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
3798 | struct kvm_lapic_state *s) | |
3799 | { | |
fa59cc00 | 3800 | if (vcpu->arch.apicv_active) |
afaf0b2f | 3801 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
d62caabb | 3802 | |
a92e2543 | 3803 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
3804 | } |
3805 | ||
3806 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
3807 | struct kvm_lapic_state *s) | |
3808 | { | |
a92e2543 RK |
3809 | int r; |
3810 | ||
3811 | r = kvm_apic_set_state(vcpu, s); | |
3812 | if (r) | |
3813 | return r; | |
cb142eb7 | 3814 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
3815 | |
3816 | return 0; | |
3817 | } | |
3818 | ||
127a457a MG |
3819 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
3820 | { | |
3821 | return (!lapic_in_kernel(vcpu) || | |
3822 | kvm_apic_accept_pic_intr(vcpu)); | |
3823 | } | |
3824 | ||
782d422b MG |
3825 | /* |
3826 | * if userspace requested an interrupt window, check that the | |
3827 | * interrupt window is open. | |
3828 | * | |
3829 | * No need to exit to userspace if we already have an interrupt queued. | |
3830 | */ | |
3831 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) | |
3832 | { | |
3833 | return kvm_arch_interrupt_allowed(vcpu) && | |
3834 | !kvm_cpu_has_interrupt(vcpu) && | |
3835 | !kvm_event_needs_reinjection(vcpu) && | |
3836 | kvm_cpu_accept_dm_intr(vcpu); | |
3837 | } | |
3838 | ||
f77bc6a4 ZX |
3839 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
3840 | struct kvm_interrupt *irq) | |
3841 | { | |
02cdb50f | 3842 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 3843 | return -EINVAL; |
1c1a9ce9 SR |
3844 | |
3845 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
3846 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
3847 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
3848 | return 0; | |
3849 | } | |
3850 | ||
3851 | /* | |
3852 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
3853 | * fail for in-kernel 8259. | |
3854 | */ | |
3855 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 3856 | return -ENXIO; |
f77bc6a4 | 3857 | |
1c1a9ce9 SR |
3858 | if (vcpu->arch.pending_external_vector != -1) |
3859 | return -EEXIST; | |
f77bc6a4 | 3860 | |
1c1a9ce9 | 3861 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 3862 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
3863 | return 0; |
3864 | } | |
3865 | ||
c4abb7c9 JK |
3866 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
3867 | { | |
c4abb7c9 | 3868 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
3869 | |
3870 | return 0; | |
3871 | } | |
3872 | ||
f077825a PB |
3873 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
3874 | { | |
64d60670 PB |
3875 | kvm_make_request(KVM_REQ_SMI, vcpu); |
3876 | ||
f077825a PB |
3877 | return 0; |
3878 | } | |
3879 | ||
b209749f AK |
3880 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
3881 | struct kvm_tpr_access_ctl *tac) | |
3882 | { | |
3883 | if (tac->flags) | |
3884 | return -EINVAL; | |
3885 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
3886 | return 0; | |
3887 | } | |
3888 | ||
890ca9ae HY |
3889 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
3890 | u64 mcg_cap) | |
3891 | { | |
3892 | int r; | |
3893 | unsigned bank_num = mcg_cap & 0xff, bank; | |
3894 | ||
3895 | r = -EINVAL; | |
c4e0e4ab | 3896 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 3897 | goto out; |
c45dcc71 | 3898 | if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) |
890ca9ae HY |
3899 | goto out; |
3900 | r = 0; | |
3901 | vcpu->arch.mcg_cap = mcg_cap; | |
3902 | /* Init IA32_MCG_CTL to all 1s */ | |
3903 | if (mcg_cap & MCG_CTL_P) | |
3904 | vcpu->arch.mcg_ctl = ~(u64)0; | |
3905 | /* Init IA32_MCi_CTL to all 1s */ | |
3906 | for (bank = 0; bank < bank_num; bank++) | |
3907 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
c45dcc71 | 3908 | |
afaf0b2f | 3909 | kvm_x86_ops.setup_mce(vcpu); |
890ca9ae HY |
3910 | out: |
3911 | return r; | |
3912 | } | |
3913 | ||
3914 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
3915 | struct kvm_x86_mce *mce) | |
3916 | { | |
3917 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
3918 | unsigned bank_num = mcg_cap & 0xff; | |
3919 | u64 *banks = vcpu->arch.mce_banks; | |
3920 | ||
3921 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
3922 | return -EINVAL; | |
3923 | /* | |
3924 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
3925 | * reporting is disabled | |
3926 | */ | |
3927 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
3928 | vcpu->arch.mcg_ctl != ~(u64)0) | |
3929 | return 0; | |
3930 | banks += 4 * mce->bank; | |
3931 | /* | |
3932 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
3933 | * reporting is disabled for the bank | |
3934 | */ | |
3935 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
3936 | return 0; | |
3937 | if (mce->status & MCI_STATUS_UC) { | |
3938 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 3939 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 3940 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
3941 | return 0; |
3942 | } | |
3943 | if (banks[1] & MCI_STATUS_VAL) | |
3944 | mce->status |= MCI_STATUS_OVER; | |
3945 | banks[2] = mce->addr; | |
3946 | banks[3] = mce->misc; | |
3947 | vcpu->arch.mcg_status = mce->mcg_status; | |
3948 | banks[1] = mce->status; | |
3949 | kvm_queue_exception(vcpu, MC_VECTOR); | |
3950 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
3951 | || !(banks[1] & MCI_STATUS_UC)) { | |
3952 | if (banks[1] & MCI_STATUS_VAL) | |
3953 | mce->status |= MCI_STATUS_OVER; | |
3954 | banks[2] = mce->addr; | |
3955 | banks[3] = mce->misc; | |
3956 | banks[1] = mce->status; | |
3957 | } else | |
3958 | banks[1] |= MCI_STATUS_OVER; | |
3959 | return 0; | |
3960 | } | |
3961 | ||
3cfc3092 JK |
3962 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
3963 | struct kvm_vcpu_events *events) | |
3964 | { | |
7460fb4a | 3965 | process_nmi(vcpu); |
59073aaf | 3966 | |
a06230b6 OU |
3967 | /* |
3968 | * In guest mode, payload delivery should be deferred, | |
3969 | * so that the L1 hypervisor can intercept #PF before | |
3970 | * CR2 is modified (or intercept #DB before DR6 is | |
3971 | * modified under nVMX). Unless the per-VM capability, | |
3972 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
3973 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
3974 | * opportunistically defer the exception payload, deliver it if the | |
3975 | * capability hasn't been requested before processing a | |
3976 | * KVM_GET_VCPU_EVENTS. | |
3977 | */ | |
3978 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
3979 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
3980 | kvm_deliver_exception_payload(vcpu); | |
3981 | ||
664f8e26 | 3982 | /* |
59073aaf JM |
3983 | * The API doesn't provide the instruction length for software |
3984 | * exceptions, so don't report them. As long as the guest RIP | |
3985 | * isn't advanced, we should expect to encounter the exception | |
3986 | * again. | |
664f8e26 | 3987 | */ |
59073aaf JM |
3988 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
3989 | events->exception.injected = 0; | |
3990 | events->exception.pending = 0; | |
3991 | } else { | |
3992 | events->exception.injected = vcpu->arch.exception.injected; | |
3993 | events->exception.pending = vcpu->arch.exception.pending; | |
3994 | /* | |
3995 | * For ABI compatibility, deliberately conflate | |
3996 | * pending and injected exceptions when | |
3997 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
3998 | */ | |
3999 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4000 | events->exception.injected |= | |
4001 | vcpu->arch.exception.pending; | |
4002 | } | |
3cfc3092 JK |
4003 | events->exception.nr = vcpu->arch.exception.nr; |
4004 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
4005 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
4006 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
4007 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 4008 | |
03b82a30 | 4009 | events->interrupt.injected = |
04140b41 | 4010 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 4011 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 4012 | events->interrupt.soft = 0; |
afaf0b2f | 4013 | events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
3cfc3092 JK |
4014 | |
4015 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 4016 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
afaf0b2f | 4017 | events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); |
97e69aa6 | 4018 | events->nmi.pad = 0; |
3cfc3092 | 4019 | |
66450a21 | 4020 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 4021 | |
f077825a PB |
4022 | events->smi.smm = is_smm(vcpu); |
4023 | events->smi.pending = vcpu->arch.smi_pending; | |
4024 | events->smi.smm_inside_nmi = | |
4025 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
4026 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
4027 | ||
dab4b911 | 4028 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
4029 | | KVM_VCPUEVENT_VALID_SHADOW |
4030 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
4031 | if (vcpu->kvm->arch.exception_payload_enabled) |
4032 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4033 | ||
97e69aa6 | 4034 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
4035 | } |
4036 | ||
c5833c7a | 4037 | static void kvm_smm_changed(struct kvm_vcpu *vcpu); |
6ef4e07e | 4038 | |
3cfc3092 JK |
4039 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
4040 | struct kvm_vcpu_events *events) | |
4041 | { | |
dab4b911 | 4042 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 4043 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 4044 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf JM |
4045 | | KVM_VCPUEVENT_VALID_SMM |
4046 | | KVM_VCPUEVENT_VALID_PAYLOAD)) | |
3cfc3092 JK |
4047 | return -EINVAL; |
4048 | ||
59073aaf JM |
4049 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
4050 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
4051 | return -EINVAL; | |
4052 | if (events->exception.pending) | |
4053 | events->exception.injected = 0; | |
4054 | else | |
4055 | events->exception_has_payload = 0; | |
4056 | } else { | |
4057 | events->exception.pending = 0; | |
4058 | events->exception_has_payload = 0; | |
4059 | } | |
4060 | ||
4061 | if ((events->exception.injected || events->exception.pending) && | |
4062 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
4063 | return -EINVAL; |
4064 | ||
28bf2888 DH |
4065 | /* INITs are latched while in SMM */ |
4066 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
4067 | (events->smi.smm || events->smi.pending) && | |
4068 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
4069 | return -EINVAL; | |
4070 | ||
7460fb4a | 4071 | process_nmi(vcpu); |
59073aaf JM |
4072 | vcpu->arch.exception.injected = events->exception.injected; |
4073 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
4074 | vcpu->arch.exception.nr = events->exception.nr; |
4075 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
4076 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
4077 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
4078 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 4079 | |
04140b41 | 4080 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
4081 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
4082 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 4083 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
afaf0b2f | 4084 | kvm_x86_ops.set_interrupt_shadow(vcpu, |
48005f64 | 4085 | events->interrupt.shadow); |
3cfc3092 JK |
4086 | |
4087 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
4088 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
4089 | vcpu->arch.nmi_pending = events->nmi.pending; | |
afaf0b2f | 4090 | kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); |
3cfc3092 | 4091 | |
66450a21 | 4092 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 4093 | lapic_in_kernel(vcpu)) |
66450a21 | 4094 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 4095 | |
f077825a | 4096 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
c5833c7a SC |
4097 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
4098 | if (events->smi.smm) | |
4099 | vcpu->arch.hflags |= HF_SMM_MASK; | |
4100 | else | |
4101 | vcpu->arch.hflags &= ~HF_SMM_MASK; | |
4102 | kvm_smm_changed(vcpu); | |
4103 | } | |
6ef4e07e | 4104 | |
f077825a | 4105 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
4106 | |
4107 | if (events->smi.smm) { | |
4108 | if (events->smi.smm_inside_nmi) | |
4109 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 4110 | else |
f4ef1910 | 4111 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
4112 | } |
4113 | ||
4114 | if (lapic_in_kernel(vcpu)) { | |
4115 | if (events->smi.latched_init) | |
4116 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
4117 | else | |
4118 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
4119 | } |
4120 | } | |
4121 | ||
3842d135 AK |
4122 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4123 | ||
3cfc3092 JK |
4124 | return 0; |
4125 | } | |
4126 | ||
a1efbe77 JK |
4127 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
4128 | struct kvm_debugregs *dbgregs) | |
4129 | { | |
73aaf249 JK |
4130 | unsigned long val; |
4131 | ||
a1efbe77 | 4132 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 4133 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 4134 | dbgregs->dr6 = val; |
a1efbe77 JK |
4135 | dbgregs->dr7 = vcpu->arch.dr7; |
4136 | dbgregs->flags = 0; | |
97e69aa6 | 4137 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
4138 | } |
4139 | ||
4140 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
4141 | struct kvm_debugregs *dbgregs) | |
4142 | { | |
4143 | if (dbgregs->flags) | |
4144 | return -EINVAL; | |
4145 | ||
d14bdb55 PB |
4146 | if (dbgregs->dr6 & ~0xffffffffull) |
4147 | return -EINVAL; | |
4148 | if (dbgregs->dr7 & ~0xffffffffull) | |
4149 | return -EINVAL; | |
4150 | ||
a1efbe77 | 4151 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 4152 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
4153 | vcpu->arch.dr6 = dbgregs->dr6; |
4154 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 4155 | kvm_update_dr7(vcpu); |
a1efbe77 | 4156 | |
a1efbe77 JK |
4157 | return 0; |
4158 | } | |
4159 | ||
df1daba7 PB |
4160 | #define XSTATE_COMPACTION_ENABLED (1ULL << 63) |
4161 | ||
4162 | static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) | |
4163 | { | |
b666a4b6 | 4164 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
400e4b20 | 4165 | u64 xstate_bv = xsave->header.xfeatures; |
df1daba7 PB |
4166 | u64 valid; |
4167 | ||
4168 | /* | |
4169 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4170 | * leaves 0 and 1 in the loop below. | |
4171 | */ | |
4172 | memcpy(dest, xsave, XSAVE_HDR_OFFSET); | |
4173 | ||
4174 | /* Set XSTATE_BV */ | |
00c87e9a | 4175 | xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; |
df1daba7 PB |
4176 | *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; |
4177 | ||
4178 | /* | |
4179 | * Copy each region from the possibly compacted offset to the | |
4180 | * non-compacted offset. | |
4181 | */ | |
d91cab78 | 4182 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4183 | while (valid) { |
abd16d68 SAS |
4184 | u64 xfeature_mask = valid & -valid; |
4185 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4186 | void *src = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4187 | |
4188 | if (src) { | |
4189 | u32 size, offset, ecx, edx; | |
abd16d68 | 4190 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4191 | &size, &offset, &ecx, &edx); |
abd16d68 | 4192 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4193 | memcpy(dest + offset, &vcpu->arch.pkru, |
4194 | sizeof(vcpu->arch.pkru)); | |
4195 | else | |
4196 | memcpy(dest + offset, src, size); | |
4197 | ||
df1daba7 PB |
4198 | } |
4199 | ||
abd16d68 | 4200 | valid -= xfeature_mask; |
df1daba7 PB |
4201 | } |
4202 | } | |
4203 | ||
4204 | static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) | |
4205 | { | |
b666a4b6 | 4206 | struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; |
df1daba7 PB |
4207 | u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); |
4208 | u64 valid; | |
4209 | ||
4210 | /* | |
4211 | * Copy legacy XSAVE area, to avoid complications with CPUID | |
4212 | * leaves 0 and 1 in the loop below. | |
4213 | */ | |
4214 | memcpy(xsave, src, XSAVE_HDR_OFFSET); | |
4215 | ||
4216 | /* Set XSTATE_BV and possibly XCOMP_BV. */ | |
400e4b20 | 4217 | xsave->header.xfeatures = xstate_bv; |
782511b0 | 4218 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
3a54450b | 4219 | xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; |
df1daba7 PB |
4220 | |
4221 | /* | |
4222 | * Copy each region from the non-compacted offset to the | |
4223 | * possibly compacted offset. | |
4224 | */ | |
d91cab78 | 4225 | valid = xstate_bv & ~XFEATURE_MASK_FPSSE; |
df1daba7 | 4226 | while (valid) { |
abd16d68 SAS |
4227 | u64 xfeature_mask = valid & -valid; |
4228 | int xfeature_nr = fls64(xfeature_mask) - 1; | |
4229 | void *dest = get_xsave_addr(xsave, xfeature_nr); | |
df1daba7 PB |
4230 | |
4231 | if (dest) { | |
4232 | u32 size, offset, ecx, edx; | |
abd16d68 | 4233 | cpuid_count(XSTATE_CPUID, xfeature_nr, |
df1daba7 | 4234 | &size, &offset, &ecx, &edx); |
abd16d68 | 4235 | if (xfeature_nr == XFEATURE_PKRU) |
38cfd5e3 PB |
4236 | memcpy(&vcpu->arch.pkru, src + offset, |
4237 | sizeof(vcpu->arch.pkru)); | |
4238 | else | |
4239 | memcpy(dest, src + offset, size); | |
ee4100da | 4240 | } |
df1daba7 | 4241 | |
abd16d68 | 4242 | valid -= xfeature_mask; |
df1daba7 PB |
4243 | } |
4244 | } | |
4245 | ||
2d5b5a66 SY |
4246 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
4247 | struct kvm_xsave *guest_xsave) | |
4248 | { | |
d366bf7e | 4249 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
df1daba7 PB |
4250 | memset(guest_xsave, 0, sizeof(struct kvm_xsave)); |
4251 | fill_xsave((u8 *) guest_xsave->region, vcpu); | |
4344ee98 | 4252 | } else { |
2d5b5a66 | 4253 | memcpy(guest_xsave->region, |
b666a4b6 | 4254 | &vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4255 | sizeof(struct fxregs_state)); |
2d5b5a66 | 4256 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = |
d91cab78 | 4257 | XFEATURE_MASK_FPSSE; |
2d5b5a66 SY |
4258 | } |
4259 | } | |
4260 | ||
a575813b WL |
4261 | #define XSAVE_MXCSR_OFFSET 24 |
4262 | ||
2d5b5a66 SY |
4263 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
4264 | struct kvm_xsave *guest_xsave) | |
4265 | { | |
4266 | u64 xstate_bv = | |
4267 | *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; | |
a575813b | 4268 | u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; |
2d5b5a66 | 4269 | |
d366bf7e | 4270 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
d7876f1b PB |
4271 | /* |
4272 | * Here we allow setting states that are not present in | |
4273 | * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility | |
4274 | * with old userspace. | |
4275 | */ | |
cfc48181 | 4276 | if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) |
d7876f1b | 4277 | return -EINVAL; |
df1daba7 | 4278 | load_xsave(vcpu, (u8 *)guest_xsave->region); |
d7876f1b | 4279 | } else { |
a575813b WL |
4280 | if (xstate_bv & ~XFEATURE_MASK_FPSSE || |
4281 | mxcsr & ~mxcsr_feature_mask) | |
2d5b5a66 | 4282 | return -EINVAL; |
b666a4b6 | 4283 | memcpy(&vcpu->arch.guest_fpu->state.fxsave, |
c47ada30 | 4284 | guest_xsave->region, sizeof(struct fxregs_state)); |
2d5b5a66 SY |
4285 | } |
4286 | return 0; | |
4287 | } | |
4288 | ||
4289 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
4290 | struct kvm_xcrs *guest_xcrs) | |
4291 | { | |
d366bf7e | 4292 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
4293 | guest_xcrs->nr_xcrs = 0; |
4294 | return; | |
4295 | } | |
4296 | ||
4297 | guest_xcrs->nr_xcrs = 1; | |
4298 | guest_xcrs->flags = 0; | |
4299 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
4300 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
4301 | } | |
4302 | ||
4303 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
4304 | struct kvm_xcrs *guest_xcrs) | |
4305 | { | |
4306 | int i, r = 0; | |
4307 | ||
d366bf7e | 4308 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
4309 | return -EINVAL; |
4310 | ||
4311 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
4312 | return -EINVAL; | |
4313 | ||
4314 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
4315 | /* Only support XCR0 currently */ | |
c67a04cb | 4316 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 4317 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 4318 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
4319 | break; |
4320 | } | |
4321 | if (r) | |
4322 | r = -EINVAL; | |
4323 | return r; | |
4324 | } | |
4325 | ||
1c0b28c2 EM |
4326 | /* |
4327 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
4328 | * stopped by the hypervisor. This function will be called from the host only. | |
4329 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
4330 | * does not support pv clocks. | |
4331 | */ | |
4332 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
4333 | { | |
0b79459b | 4334 | if (!vcpu->arch.pv_time_enabled) |
1c0b28c2 | 4335 | return -EINVAL; |
51d59c6b | 4336 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
4337 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
4338 | return 0; | |
4339 | } | |
4340 | ||
5c919412 AS |
4341 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
4342 | struct kvm_enable_cap *cap) | |
4343 | { | |
57b119da VK |
4344 | int r; |
4345 | uint16_t vmcs_version; | |
4346 | void __user *user_ptr; | |
4347 | ||
5c919412 AS |
4348 | if (cap->flags) |
4349 | return -EINVAL; | |
4350 | ||
4351 | switch (cap->cap) { | |
efc479e6 RK |
4352 | case KVM_CAP_HYPERV_SYNIC2: |
4353 | if (cap->args[0]) | |
4354 | return -EINVAL; | |
b2869f28 GS |
4355 | /* fall through */ |
4356 | ||
5c919412 | 4357 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
4358 | if (!irqchip_in_kernel(vcpu->kvm)) |
4359 | return -EINVAL; | |
efc479e6 RK |
4360 | return kvm_hv_activate_synic(vcpu, cap->cap == |
4361 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 4362 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 4363 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 4364 | return -ENOTTY; |
33b22172 | 4365 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
4366 | if (!r) { |
4367 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
4368 | if (copy_to_user(user_ptr, &vmcs_version, | |
4369 | sizeof(vmcs_version))) | |
4370 | r = -EFAULT; | |
4371 | } | |
4372 | return r; | |
344c6c80 | 4373 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4374 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
4375 | return -ENOTTY; |
4376 | ||
afaf0b2f | 4377 | return kvm_x86_ops.enable_direct_tlbflush(vcpu); |
57b119da | 4378 | |
5c919412 AS |
4379 | default: |
4380 | return -EINVAL; | |
4381 | } | |
4382 | } | |
4383 | ||
313a3dc7 CO |
4384 | long kvm_arch_vcpu_ioctl(struct file *filp, |
4385 | unsigned int ioctl, unsigned long arg) | |
4386 | { | |
4387 | struct kvm_vcpu *vcpu = filp->private_data; | |
4388 | void __user *argp = (void __user *)arg; | |
4389 | int r; | |
d1ac91d8 AK |
4390 | union { |
4391 | struct kvm_lapic_state *lapic; | |
4392 | struct kvm_xsave *xsave; | |
4393 | struct kvm_xcrs *xcrs; | |
4394 | void *buffer; | |
4395 | } u; | |
4396 | ||
9b062471 CD |
4397 | vcpu_load(vcpu); |
4398 | ||
d1ac91d8 | 4399 | u.buffer = NULL; |
313a3dc7 CO |
4400 | switch (ioctl) { |
4401 | case KVM_GET_LAPIC: { | |
2204ae3c | 4402 | r = -EINVAL; |
bce87cce | 4403 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4404 | goto out; |
254272ce BG |
4405 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
4406 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 4407 | |
b772ff36 | 4408 | r = -ENOMEM; |
d1ac91d8 | 4409 | if (!u.lapic) |
b772ff36 | 4410 | goto out; |
d1ac91d8 | 4411 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4412 | if (r) |
4413 | goto out; | |
4414 | r = -EFAULT; | |
d1ac91d8 | 4415 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
4416 | goto out; |
4417 | r = 0; | |
4418 | break; | |
4419 | } | |
4420 | case KVM_SET_LAPIC: { | |
2204ae3c | 4421 | r = -EINVAL; |
bce87cce | 4422 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 4423 | goto out; |
ff5c2c03 | 4424 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
4425 | if (IS_ERR(u.lapic)) { |
4426 | r = PTR_ERR(u.lapic); | |
4427 | goto out_nofree; | |
4428 | } | |
ff5c2c03 | 4429 | |
d1ac91d8 | 4430 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
4431 | break; |
4432 | } | |
f77bc6a4 ZX |
4433 | case KVM_INTERRUPT: { |
4434 | struct kvm_interrupt irq; | |
4435 | ||
4436 | r = -EFAULT; | |
0e96f31e | 4437 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
4438 | goto out; |
4439 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
4440 | break; |
4441 | } | |
c4abb7c9 JK |
4442 | case KVM_NMI: { |
4443 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
4444 | break; |
4445 | } | |
f077825a PB |
4446 | case KVM_SMI: { |
4447 | r = kvm_vcpu_ioctl_smi(vcpu); | |
4448 | break; | |
4449 | } | |
313a3dc7 CO |
4450 | case KVM_SET_CPUID: { |
4451 | struct kvm_cpuid __user *cpuid_arg = argp; | |
4452 | struct kvm_cpuid cpuid; | |
4453 | ||
4454 | r = -EFAULT; | |
0e96f31e | 4455 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
4456 | goto out; |
4457 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
4458 | break; |
4459 | } | |
07716717 DK |
4460 | case KVM_SET_CPUID2: { |
4461 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4462 | struct kvm_cpuid2 cpuid; | |
4463 | ||
4464 | r = -EFAULT; | |
0e96f31e | 4465 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4466 | goto out; |
4467 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 4468 | cpuid_arg->entries); |
07716717 DK |
4469 | break; |
4470 | } | |
4471 | case KVM_GET_CPUID2: { | |
4472 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4473 | struct kvm_cpuid2 cpuid; | |
4474 | ||
4475 | r = -EFAULT; | |
0e96f31e | 4476 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
4477 | goto out; |
4478 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 4479 | cpuid_arg->entries); |
07716717 DK |
4480 | if (r) |
4481 | goto out; | |
4482 | r = -EFAULT; | |
0e96f31e | 4483 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
4484 | goto out; |
4485 | r = 0; | |
4486 | break; | |
4487 | } | |
801e459a TL |
4488 | case KVM_GET_MSRS: { |
4489 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 4490 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 4491 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4492 | break; |
801e459a TL |
4493 | } |
4494 | case KVM_SET_MSRS: { | |
4495 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 4496 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 4497 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 4498 | break; |
801e459a | 4499 | } |
b209749f AK |
4500 | case KVM_TPR_ACCESS_REPORTING: { |
4501 | struct kvm_tpr_access_ctl tac; | |
4502 | ||
4503 | r = -EFAULT; | |
0e96f31e | 4504 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
4505 | goto out; |
4506 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
4507 | if (r) | |
4508 | goto out; | |
4509 | r = -EFAULT; | |
0e96f31e | 4510 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
4511 | goto out; |
4512 | r = 0; | |
4513 | break; | |
4514 | }; | |
b93463aa AK |
4515 | case KVM_SET_VAPIC_ADDR: { |
4516 | struct kvm_vapic_addr va; | |
7301d6ab | 4517 | int idx; |
b93463aa AK |
4518 | |
4519 | r = -EINVAL; | |
35754c98 | 4520 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
4521 | goto out; |
4522 | r = -EFAULT; | |
0e96f31e | 4523 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 4524 | goto out; |
7301d6ab | 4525 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 4526 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 4527 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
4528 | break; |
4529 | } | |
890ca9ae HY |
4530 | case KVM_X86_SETUP_MCE: { |
4531 | u64 mcg_cap; | |
4532 | ||
4533 | r = -EFAULT; | |
0e96f31e | 4534 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
4535 | goto out; |
4536 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
4537 | break; | |
4538 | } | |
4539 | case KVM_X86_SET_MCE: { | |
4540 | struct kvm_x86_mce mce; | |
4541 | ||
4542 | r = -EFAULT; | |
0e96f31e | 4543 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
4544 | goto out; |
4545 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
4546 | break; | |
4547 | } | |
3cfc3092 JK |
4548 | case KVM_GET_VCPU_EVENTS: { |
4549 | struct kvm_vcpu_events events; | |
4550 | ||
4551 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
4552 | ||
4553 | r = -EFAULT; | |
4554 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
4555 | break; | |
4556 | r = 0; | |
4557 | break; | |
4558 | } | |
4559 | case KVM_SET_VCPU_EVENTS: { | |
4560 | struct kvm_vcpu_events events; | |
4561 | ||
4562 | r = -EFAULT; | |
4563 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
4564 | break; | |
4565 | ||
4566 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
4567 | break; | |
4568 | } | |
a1efbe77 JK |
4569 | case KVM_GET_DEBUGREGS: { |
4570 | struct kvm_debugregs dbgregs; | |
4571 | ||
4572 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
4573 | ||
4574 | r = -EFAULT; | |
4575 | if (copy_to_user(argp, &dbgregs, | |
4576 | sizeof(struct kvm_debugregs))) | |
4577 | break; | |
4578 | r = 0; | |
4579 | break; | |
4580 | } | |
4581 | case KVM_SET_DEBUGREGS: { | |
4582 | struct kvm_debugregs dbgregs; | |
4583 | ||
4584 | r = -EFAULT; | |
4585 | if (copy_from_user(&dbgregs, argp, | |
4586 | sizeof(struct kvm_debugregs))) | |
4587 | break; | |
4588 | ||
4589 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
4590 | break; | |
4591 | } | |
2d5b5a66 | 4592 | case KVM_GET_XSAVE: { |
254272ce | 4593 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4594 | r = -ENOMEM; |
d1ac91d8 | 4595 | if (!u.xsave) |
2d5b5a66 SY |
4596 | break; |
4597 | ||
d1ac91d8 | 4598 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4599 | |
4600 | r = -EFAULT; | |
d1ac91d8 | 4601 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
4602 | break; |
4603 | r = 0; | |
4604 | break; | |
4605 | } | |
4606 | case KVM_SET_XSAVE: { | |
ff5c2c03 | 4607 | u.xsave = memdup_user(argp, sizeof(*u.xsave)); |
9b062471 CD |
4608 | if (IS_ERR(u.xsave)) { |
4609 | r = PTR_ERR(u.xsave); | |
4610 | goto out_nofree; | |
4611 | } | |
2d5b5a66 | 4612 | |
d1ac91d8 | 4613 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
4614 | break; |
4615 | } | |
4616 | case KVM_GET_XCRS: { | |
254272ce | 4617 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 4618 | r = -ENOMEM; |
d1ac91d8 | 4619 | if (!u.xcrs) |
2d5b5a66 SY |
4620 | break; |
4621 | ||
d1ac91d8 | 4622 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4623 | |
4624 | r = -EFAULT; | |
d1ac91d8 | 4625 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
4626 | sizeof(struct kvm_xcrs))) |
4627 | break; | |
4628 | r = 0; | |
4629 | break; | |
4630 | } | |
4631 | case KVM_SET_XCRS: { | |
ff5c2c03 | 4632 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
4633 | if (IS_ERR(u.xcrs)) { |
4634 | r = PTR_ERR(u.xcrs); | |
4635 | goto out_nofree; | |
4636 | } | |
2d5b5a66 | 4637 | |
d1ac91d8 | 4638 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
4639 | break; |
4640 | } | |
92a1f12d JR |
4641 | case KVM_SET_TSC_KHZ: { |
4642 | u32 user_tsc_khz; | |
4643 | ||
4644 | r = -EINVAL; | |
92a1f12d JR |
4645 | user_tsc_khz = (u32)arg; |
4646 | ||
26769f96 MT |
4647 | if (kvm_has_tsc_control && |
4648 | user_tsc_khz >= kvm_max_guest_tsc_khz) | |
92a1f12d JR |
4649 | goto out; |
4650 | ||
cc578287 ZA |
4651 | if (user_tsc_khz == 0) |
4652 | user_tsc_khz = tsc_khz; | |
4653 | ||
381d585c HZ |
4654 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
4655 | r = 0; | |
92a1f12d | 4656 | |
92a1f12d JR |
4657 | goto out; |
4658 | } | |
4659 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 4660 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
4661 | goto out; |
4662 | } | |
1c0b28c2 EM |
4663 | case KVM_KVMCLOCK_CTRL: { |
4664 | r = kvm_set_guest_paused(vcpu); | |
4665 | goto out; | |
4666 | } | |
5c919412 AS |
4667 | case KVM_ENABLE_CAP: { |
4668 | struct kvm_enable_cap cap; | |
4669 | ||
4670 | r = -EFAULT; | |
4671 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
4672 | goto out; | |
4673 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
4674 | break; | |
4675 | } | |
8fcc4b59 JM |
4676 | case KVM_GET_NESTED_STATE: { |
4677 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4678 | u32 user_data_size; | |
4679 | ||
4680 | r = -EINVAL; | |
33b22172 | 4681 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
4682 | break; |
4683 | ||
4684 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 4685 | r = -EFAULT; |
8fcc4b59 | 4686 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 4687 | break; |
8fcc4b59 | 4688 | |
33b22172 PB |
4689 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
4690 | user_data_size); | |
8fcc4b59 | 4691 | if (r < 0) |
26b471c7 | 4692 | break; |
8fcc4b59 JM |
4693 | |
4694 | if (r > user_data_size) { | |
4695 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
4696 | r = -EFAULT; |
4697 | else | |
4698 | r = -E2BIG; | |
4699 | break; | |
8fcc4b59 | 4700 | } |
26b471c7 | 4701 | |
8fcc4b59 JM |
4702 | r = 0; |
4703 | break; | |
4704 | } | |
4705 | case KVM_SET_NESTED_STATE: { | |
4706 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
4707 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 4708 | int idx; |
8fcc4b59 JM |
4709 | |
4710 | r = -EINVAL; | |
33b22172 | 4711 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
4712 | break; |
4713 | ||
26b471c7 | 4714 | r = -EFAULT; |
8fcc4b59 | 4715 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 4716 | break; |
8fcc4b59 | 4717 | |
26b471c7 | 4718 | r = -EINVAL; |
8fcc4b59 | 4719 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 4720 | break; |
8fcc4b59 JM |
4721 | |
4722 | if (kvm_state.flags & | |
8cab6507 | 4723 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
4724 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
4725 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 4726 | break; |
8fcc4b59 JM |
4727 | |
4728 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
4729 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
4730 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 4731 | break; |
8fcc4b59 | 4732 | |
ad5996d9 | 4733 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 4734 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 4735 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
4736 | break; |
4737 | } | |
2bc39970 VK |
4738 | case KVM_GET_SUPPORTED_HV_CPUID: { |
4739 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
4740 | struct kvm_cpuid2 cpuid; | |
4741 | ||
4742 | r = -EFAULT; | |
4743 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4744 | goto out; | |
4745 | ||
4746 | r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, | |
4747 | cpuid_arg->entries); | |
4748 | if (r) | |
4749 | goto out; | |
4750 | ||
4751 | r = -EFAULT; | |
4752 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4753 | goto out; | |
4754 | r = 0; | |
4755 | break; | |
4756 | } | |
313a3dc7 CO |
4757 | default: |
4758 | r = -EINVAL; | |
4759 | } | |
4760 | out: | |
d1ac91d8 | 4761 | kfree(u.buffer); |
9b062471 CD |
4762 | out_nofree: |
4763 | vcpu_put(vcpu); | |
313a3dc7 CO |
4764 | return r; |
4765 | } | |
4766 | ||
1499fa80 | 4767 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
4768 | { |
4769 | return VM_FAULT_SIGBUS; | |
4770 | } | |
4771 | ||
1fe779f8 CO |
4772 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
4773 | { | |
4774 | int ret; | |
4775 | ||
4776 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 4777 | return -EINVAL; |
afaf0b2f | 4778 | ret = kvm_x86_ops.set_tss_addr(kvm, addr); |
1fe779f8 CO |
4779 | return ret; |
4780 | } | |
4781 | ||
b927a3ce SY |
4782 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
4783 | u64 ident_addr) | |
4784 | { | |
afaf0b2f | 4785 | return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); |
b927a3ce SY |
4786 | } |
4787 | ||
1fe779f8 | 4788 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 4789 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
4790 | { |
4791 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
4792 | return -EINVAL; | |
4793 | ||
79fac95e | 4794 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
4795 | |
4796 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 4797 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 4798 | |
79fac95e | 4799 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
4800 | return 0; |
4801 | } | |
4802 | ||
bc8a3d89 | 4803 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 4804 | { |
39de71ec | 4805 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
4806 | } |
4807 | ||
1fe779f8 CO |
4808 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
4809 | { | |
90bca052 | 4810 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4811 | int r; |
4812 | ||
4813 | r = 0; | |
4814 | switch (chip->chip_id) { | |
4815 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 4816 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
4817 | sizeof(struct kvm_pic_state)); |
4818 | break; | |
4819 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 4820 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
4821 | sizeof(struct kvm_pic_state)); |
4822 | break; | |
4823 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4824 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4825 | break; |
4826 | default: | |
4827 | r = -EINVAL; | |
4828 | break; | |
4829 | } | |
4830 | return r; | |
4831 | } | |
4832 | ||
4833 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
4834 | { | |
90bca052 | 4835 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
4836 | int r; |
4837 | ||
4838 | r = 0; | |
4839 | switch (chip->chip_id) { | |
4840 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
4841 | spin_lock(&pic->lock); |
4842 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 4843 | sizeof(struct kvm_pic_state)); |
90bca052 | 4844 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4845 | break; |
4846 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
4847 | spin_lock(&pic->lock); |
4848 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 4849 | sizeof(struct kvm_pic_state)); |
90bca052 | 4850 | spin_unlock(&pic->lock); |
1fe779f8 CO |
4851 | break; |
4852 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 4853 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
4854 | break; |
4855 | default: | |
4856 | r = -EINVAL; | |
4857 | break; | |
4858 | } | |
90bca052 | 4859 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
4860 | return r; |
4861 | } | |
4862 | ||
e0f63cb9 SY |
4863 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
4864 | { | |
34f3941c RK |
4865 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
4866 | ||
4867 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
4868 | ||
4869 | mutex_lock(&kps->lock); | |
4870 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
4871 | mutex_unlock(&kps->lock); | |
2da29bcc | 4872 | return 0; |
e0f63cb9 SY |
4873 | } |
4874 | ||
4875 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
4876 | { | |
0185604c | 4877 | int i; |
09edea72 RK |
4878 | struct kvm_pit *pit = kvm->arch.vpit; |
4879 | ||
4880 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 4881 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 4882 | for (i = 0; i < 3; i++) |
09edea72 RK |
4883 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
4884 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 4885 | return 0; |
e9f42757 BK |
4886 | } |
4887 | ||
4888 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4889 | { | |
e9f42757 BK |
4890 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
4891 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
4892 | sizeof(ps->channels)); | |
4893 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
4894 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 4895 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 4896 | return 0; |
e9f42757 BK |
4897 | } |
4898 | ||
4899 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
4900 | { | |
2da29bcc | 4901 | int start = 0; |
0185604c | 4902 | int i; |
e9f42757 | 4903 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
4904 | struct kvm_pit *pit = kvm->arch.vpit; |
4905 | ||
4906 | mutex_lock(&pit->pit_state.lock); | |
4907 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
4908 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
4909 | if (!prev_legacy && cur_legacy) | |
4910 | start = 1; | |
09edea72 RK |
4911 | memcpy(&pit->pit_state.channels, &ps->channels, |
4912 | sizeof(pit->pit_state.channels)); | |
4913 | pit->pit_state.flags = ps->flags; | |
0185604c | 4914 | for (i = 0; i < 3; i++) |
09edea72 | 4915 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 4916 | start && i == 0); |
09edea72 | 4917 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 4918 | return 0; |
e0f63cb9 SY |
4919 | } |
4920 | ||
52d939a0 MT |
4921 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
4922 | struct kvm_reinject_control *control) | |
4923 | { | |
71474e2f RK |
4924 | struct kvm_pit *pit = kvm->arch.vpit; |
4925 | ||
71474e2f RK |
4926 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
4927 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
4928 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
4929 | */ | |
4930 | mutex_lock(&pit->pit_state.lock); | |
4931 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
4932 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 4933 | |
52d939a0 MT |
4934 | return 0; |
4935 | } | |
4936 | ||
0dff0846 | 4937 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 4938 | { |
88178fd4 KH |
4939 | /* |
4940 | * Flush potentially hardware-cached dirty pages to dirty_bitmap. | |
4941 | */ | |
afaf0b2f SC |
4942 | if (kvm_x86_ops.flush_log_dirty) |
4943 | kvm_x86_ops.flush_log_dirty(kvm); | |
5bb064dc ZX |
4944 | } |
4945 | ||
aa2fbe6d YZ |
4946 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
4947 | bool line_status) | |
23d43cf9 CD |
4948 | { |
4949 | if (!irqchip_in_kernel(kvm)) | |
4950 | return -ENXIO; | |
4951 | ||
4952 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
4953 | irq_event->irq, irq_event->level, |
4954 | line_status); | |
23d43cf9 CD |
4955 | return 0; |
4956 | } | |
4957 | ||
e5d83c74 PB |
4958 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
4959 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
4960 | { |
4961 | int r; | |
4962 | ||
4963 | if (cap->flags) | |
4964 | return -EINVAL; | |
4965 | ||
4966 | switch (cap->cap) { | |
4967 | case KVM_CAP_DISABLE_QUIRKS: | |
4968 | kvm->arch.disabled_quirks = cap->args[0]; | |
4969 | r = 0; | |
4970 | break; | |
49df6397 SR |
4971 | case KVM_CAP_SPLIT_IRQCHIP: { |
4972 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
4973 | r = -EINVAL; |
4974 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
4975 | goto split_irqchip_unlock; | |
49df6397 SR |
4976 | r = -EEXIST; |
4977 | if (irqchip_in_kernel(kvm)) | |
4978 | goto split_irqchip_unlock; | |
557abc40 | 4979 | if (kvm->created_vcpus) |
49df6397 SR |
4980 | goto split_irqchip_unlock; |
4981 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 4982 | if (r) |
49df6397 SR |
4983 | goto split_irqchip_unlock; |
4984 | /* Pairs with irqchip_in_kernel. */ | |
4985 | smp_wmb(); | |
49776faf | 4986 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 4987 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
49df6397 SR |
4988 | r = 0; |
4989 | split_irqchip_unlock: | |
4990 | mutex_unlock(&kvm->lock); | |
4991 | break; | |
4992 | } | |
37131313 RK |
4993 | case KVM_CAP_X2APIC_API: |
4994 | r = -EINVAL; | |
4995 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
4996 | break; | |
4997 | ||
4998 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
4999 | kvm->arch.x2apic_format = true; | |
c519265f RK |
5000 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
5001 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
5002 | |
5003 | r = 0; | |
5004 | break; | |
4d5422ce WL |
5005 | case KVM_CAP_X86_DISABLE_EXITS: |
5006 | r = -EINVAL; | |
5007 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
5008 | break; | |
5009 | ||
5010 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
5011 | kvm_can_mwait_in_guest()) | |
5012 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 5013 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 5014 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
5015 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
5016 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
5017 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
5018 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
5019 | r = 0; |
5020 | break; | |
6fbbde9a DS |
5021 | case KVM_CAP_MSR_PLATFORM_INFO: |
5022 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
5023 | r = 0; | |
c4f55198 JM |
5024 | break; |
5025 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
5026 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
5027 | r = 0; | |
6fbbde9a | 5028 | break; |
90de4a18 NA |
5029 | default: |
5030 | r = -EINVAL; | |
5031 | break; | |
5032 | } | |
5033 | return r; | |
5034 | } | |
5035 | ||
1fe779f8 CO |
5036 | long kvm_arch_vm_ioctl(struct file *filp, |
5037 | unsigned int ioctl, unsigned long arg) | |
5038 | { | |
5039 | struct kvm *kvm = filp->private_data; | |
5040 | void __user *argp = (void __user *)arg; | |
367e1319 | 5041 | int r = -ENOTTY; |
f0d66275 DH |
5042 | /* |
5043 | * This union makes it completely explicit to gcc-3.x | |
5044 | * that these two variables' stack usage should be | |
5045 | * combined, not added together. | |
5046 | */ | |
5047 | union { | |
5048 | struct kvm_pit_state ps; | |
e9f42757 | 5049 | struct kvm_pit_state2 ps2; |
c5ff41ce | 5050 | struct kvm_pit_config pit_config; |
f0d66275 | 5051 | } u; |
1fe779f8 CO |
5052 | |
5053 | switch (ioctl) { | |
5054 | case KVM_SET_TSS_ADDR: | |
5055 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 5056 | break; |
b927a3ce SY |
5057 | case KVM_SET_IDENTITY_MAP_ADDR: { |
5058 | u64 ident_addr; | |
5059 | ||
1af1ac91 DH |
5060 | mutex_lock(&kvm->lock); |
5061 | r = -EINVAL; | |
5062 | if (kvm->created_vcpus) | |
5063 | goto set_identity_unlock; | |
b927a3ce | 5064 | r = -EFAULT; |
0e96f31e | 5065 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 5066 | goto set_identity_unlock; |
b927a3ce | 5067 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
5068 | set_identity_unlock: |
5069 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
5070 | break; |
5071 | } | |
1fe779f8 CO |
5072 | case KVM_SET_NR_MMU_PAGES: |
5073 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
5074 | break; |
5075 | case KVM_GET_NR_MMU_PAGES: | |
5076 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
5077 | break; | |
3ddea128 | 5078 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 5079 | mutex_lock(&kvm->lock); |
09941366 | 5080 | |
3ddea128 | 5081 | r = -EEXIST; |
35e6eaa3 | 5082 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 5083 | goto create_irqchip_unlock; |
09941366 | 5084 | |
3e515705 | 5085 | r = -EINVAL; |
557abc40 | 5086 | if (kvm->created_vcpus) |
3e515705 | 5087 | goto create_irqchip_unlock; |
09941366 RK |
5088 | |
5089 | r = kvm_pic_init(kvm); | |
5090 | if (r) | |
3ddea128 | 5091 | goto create_irqchip_unlock; |
09941366 RK |
5092 | |
5093 | r = kvm_ioapic_init(kvm); | |
5094 | if (r) { | |
09941366 | 5095 | kvm_pic_destroy(kvm); |
3ddea128 | 5096 | goto create_irqchip_unlock; |
09941366 RK |
5097 | } |
5098 | ||
399ec807 AK |
5099 | r = kvm_setup_default_irq_routing(kvm); |
5100 | if (r) { | |
72bb2fcd | 5101 | kvm_ioapic_destroy(kvm); |
09941366 | 5102 | kvm_pic_destroy(kvm); |
71ba994c | 5103 | goto create_irqchip_unlock; |
399ec807 | 5104 | } |
49776faf | 5105 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 5106 | smp_wmb(); |
49776faf | 5107 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
3ddea128 MT |
5108 | create_irqchip_unlock: |
5109 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 5110 | break; |
3ddea128 | 5111 | } |
7837699f | 5112 | case KVM_CREATE_PIT: |
c5ff41ce JK |
5113 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
5114 | goto create_pit; | |
5115 | case KVM_CREATE_PIT2: | |
5116 | r = -EFAULT; | |
5117 | if (copy_from_user(&u.pit_config, argp, | |
5118 | sizeof(struct kvm_pit_config))) | |
5119 | goto out; | |
5120 | create_pit: | |
250715a6 | 5121 | mutex_lock(&kvm->lock); |
269e05e4 AK |
5122 | r = -EEXIST; |
5123 | if (kvm->arch.vpit) | |
5124 | goto create_pit_unlock; | |
7837699f | 5125 | r = -ENOMEM; |
c5ff41ce | 5126 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
5127 | if (kvm->arch.vpit) |
5128 | r = 0; | |
269e05e4 | 5129 | create_pit_unlock: |
250715a6 | 5130 | mutex_unlock(&kvm->lock); |
7837699f | 5131 | break; |
1fe779f8 CO |
5132 | case KVM_GET_IRQCHIP: { |
5133 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5134 | struct kvm_irqchip *chip; |
1fe779f8 | 5135 | |
ff5c2c03 SL |
5136 | chip = memdup_user(argp, sizeof(*chip)); |
5137 | if (IS_ERR(chip)) { | |
5138 | r = PTR_ERR(chip); | |
1fe779f8 | 5139 | goto out; |
ff5c2c03 SL |
5140 | } |
5141 | ||
1fe779f8 | 5142 | r = -ENXIO; |
826da321 | 5143 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5144 | goto get_irqchip_out; |
5145 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 5146 | if (r) |
f0d66275 | 5147 | goto get_irqchip_out; |
1fe779f8 | 5148 | r = -EFAULT; |
0e96f31e | 5149 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 5150 | goto get_irqchip_out; |
1fe779f8 | 5151 | r = 0; |
f0d66275 DH |
5152 | get_irqchip_out: |
5153 | kfree(chip); | |
1fe779f8 CO |
5154 | break; |
5155 | } | |
5156 | case KVM_SET_IRQCHIP: { | |
5157 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 5158 | struct kvm_irqchip *chip; |
1fe779f8 | 5159 | |
ff5c2c03 SL |
5160 | chip = memdup_user(argp, sizeof(*chip)); |
5161 | if (IS_ERR(chip)) { | |
5162 | r = PTR_ERR(chip); | |
1fe779f8 | 5163 | goto out; |
ff5c2c03 SL |
5164 | } |
5165 | ||
1fe779f8 | 5166 | r = -ENXIO; |
826da321 | 5167 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
5168 | goto set_irqchip_out; |
5169 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
5170 | set_irqchip_out: |
5171 | kfree(chip); | |
1fe779f8 CO |
5172 | break; |
5173 | } | |
e0f63cb9 | 5174 | case KVM_GET_PIT: { |
e0f63cb9 | 5175 | r = -EFAULT; |
f0d66275 | 5176 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5177 | goto out; |
5178 | r = -ENXIO; | |
5179 | if (!kvm->arch.vpit) | |
5180 | goto out; | |
f0d66275 | 5181 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
5182 | if (r) |
5183 | goto out; | |
5184 | r = -EFAULT; | |
f0d66275 | 5185 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
5186 | goto out; |
5187 | r = 0; | |
5188 | break; | |
5189 | } | |
5190 | case KVM_SET_PIT: { | |
e0f63cb9 | 5191 | r = -EFAULT; |
0e96f31e | 5192 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 5193 | goto out; |
7289fdb5 | 5194 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
5195 | r = -ENXIO; |
5196 | if (!kvm->arch.vpit) | |
7289fdb5 | 5197 | goto set_pit_out; |
f0d66275 | 5198 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
5199 | set_pit_out: |
5200 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
5201 | break; |
5202 | } | |
e9f42757 BK |
5203 | case KVM_GET_PIT2: { |
5204 | r = -ENXIO; | |
5205 | if (!kvm->arch.vpit) | |
5206 | goto out; | |
5207 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
5208 | if (r) | |
5209 | goto out; | |
5210 | r = -EFAULT; | |
5211 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
5212 | goto out; | |
5213 | r = 0; | |
5214 | break; | |
5215 | } | |
5216 | case KVM_SET_PIT2: { | |
5217 | r = -EFAULT; | |
5218 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
5219 | goto out; | |
7289fdb5 | 5220 | mutex_lock(&kvm->lock); |
e9f42757 BK |
5221 | r = -ENXIO; |
5222 | if (!kvm->arch.vpit) | |
7289fdb5 | 5223 | goto set_pit2_out; |
e9f42757 | 5224 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
5225 | set_pit2_out: |
5226 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
5227 | break; |
5228 | } | |
52d939a0 MT |
5229 | case KVM_REINJECT_CONTROL: { |
5230 | struct kvm_reinject_control control; | |
5231 | r = -EFAULT; | |
5232 | if (copy_from_user(&control, argp, sizeof(control))) | |
5233 | goto out; | |
cad23e72 ML |
5234 | r = -ENXIO; |
5235 | if (!kvm->arch.vpit) | |
5236 | goto out; | |
52d939a0 | 5237 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
5238 | break; |
5239 | } | |
d71ba788 PB |
5240 | case KVM_SET_BOOT_CPU_ID: |
5241 | r = 0; | |
5242 | mutex_lock(&kvm->lock); | |
557abc40 | 5243 | if (kvm->created_vcpus) |
d71ba788 PB |
5244 | r = -EBUSY; |
5245 | else | |
5246 | kvm->arch.bsp_vcpu_id = arg; | |
5247 | mutex_unlock(&kvm->lock); | |
5248 | break; | |
ffde22ac | 5249 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 5250 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 5251 | r = -EFAULT; |
51776043 | 5252 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac ES |
5253 | goto out; |
5254 | r = -EINVAL; | |
51776043 | 5255 | if (xhc.flags) |
ffde22ac | 5256 | goto out; |
51776043 | 5257 | memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); |
ffde22ac ES |
5258 | r = 0; |
5259 | break; | |
5260 | } | |
afbcf7ab | 5261 | case KVM_SET_CLOCK: { |
afbcf7ab GC |
5262 | struct kvm_clock_data user_ns; |
5263 | u64 now_ns; | |
afbcf7ab GC |
5264 | |
5265 | r = -EFAULT; | |
5266 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
5267 | goto out; | |
5268 | ||
5269 | r = -EINVAL; | |
5270 | if (user_ns.flags) | |
5271 | goto out; | |
5272 | ||
5273 | r = 0; | |
0bc48bea RK |
5274 | /* |
5275 | * TODO: userspace has to take care of races with VCPU_RUN, so | |
5276 | * kvm_gen_update_masterclock() can be cut down to locked | |
5277 | * pvclock_update_vm_gtod_copy(). | |
5278 | */ | |
5279 | kvm_gen_update_masterclock(kvm); | |
e891a32e | 5280 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5281 | kvm->arch.kvmclock_offset += user_ns.clock - now_ns; |
0bc48bea | 5282 | kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); |
afbcf7ab GC |
5283 | break; |
5284 | } | |
5285 | case KVM_GET_CLOCK: { | |
afbcf7ab GC |
5286 | struct kvm_clock_data user_ns; |
5287 | u64 now_ns; | |
5288 | ||
e891a32e | 5289 | now_ns = get_kvmclock_ns(kvm); |
108b249c | 5290 | user_ns.clock = now_ns; |
e3fd9a93 | 5291 | user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; |
97e69aa6 | 5292 | memset(&user_ns.pad, 0, sizeof(user_ns.pad)); |
afbcf7ab GC |
5293 | |
5294 | r = -EFAULT; | |
5295 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
5296 | goto out; | |
5297 | r = 0; | |
5298 | break; | |
5299 | } | |
5acc5c06 BS |
5300 | case KVM_MEMORY_ENCRYPT_OP: { |
5301 | r = -ENOTTY; | |
afaf0b2f SC |
5302 | if (kvm_x86_ops.mem_enc_op) |
5303 | r = kvm_x86_ops.mem_enc_op(kvm, argp); | |
5acc5c06 BS |
5304 | break; |
5305 | } | |
69eaedee BS |
5306 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
5307 | struct kvm_enc_region region; | |
5308 | ||
5309 | r = -EFAULT; | |
5310 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5311 | goto out; | |
5312 | ||
5313 | r = -ENOTTY; | |
afaf0b2f SC |
5314 | if (kvm_x86_ops.mem_enc_reg_region) |
5315 | r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); | |
69eaedee BS |
5316 | break; |
5317 | } | |
5318 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
5319 | struct kvm_enc_region region; | |
5320 | ||
5321 | r = -EFAULT; | |
5322 | if (copy_from_user(®ion, argp, sizeof(region))) | |
5323 | goto out; | |
5324 | ||
5325 | r = -ENOTTY; | |
afaf0b2f SC |
5326 | if (kvm_x86_ops.mem_enc_unreg_region) |
5327 | r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); | |
69eaedee BS |
5328 | break; |
5329 | } | |
faeb7833 RK |
5330 | case KVM_HYPERV_EVENTFD: { |
5331 | struct kvm_hyperv_eventfd hvevfd; | |
5332 | ||
5333 | r = -EFAULT; | |
5334 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
5335 | goto out; | |
5336 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
5337 | break; | |
5338 | } | |
66bb8a06 EH |
5339 | case KVM_SET_PMU_EVENT_FILTER: |
5340 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
5341 | break; | |
1fe779f8 | 5342 | default: |
ad6260da | 5343 | r = -ENOTTY; |
1fe779f8 CO |
5344 | } |
5345 | out: | |
5346 | return r; | |
5347 | } | |
5348 | ||
a16b043c | 5349 | static void kvm_init_msr_list(void) |
043405e1 | 5350 | { |
24c29b7a | 5351 | struct x86_pmu_capability x86_pmu; |
043405e1 | 5352 | u32 dummy[2]; |
7a5ee6ed | 5353 | unsigned i; |
043405e1 | 5354 | |
e2ada66e | 5355 | BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, |
7a5ee6ed | 5356 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a PB |
5357 | |
5358 | perf_get_x86_pmu_capability(&x86_pmu); | |
e2ada66e | 5359 | |
6cbee2b9 XL |
5360 | num_msrs_to_save = 0; |
5361 | num_emulated_msrs = 0; | |
5362 | num_msr_based_features = 0; | |
5363 | ||
7a5ee6ed CQ |
5364 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
5365 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 5366 | continue; |
93c4adc7 PB |
5367 | |
5368 | /* | |
5369 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 5370 | * to the guests in some cases. |
93c4adc7 | 5371 | */ |
7a5ee6ed | 5372 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 5373 | case MSR_IA32_BNDCFGS: |
503234b3 | 5374 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
5375 | continue; |
5376 | break; | |
9dbe6cf9 | 5377 | case MSR_TSC_AUX: |
13908510 | 5378 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) |
9dbe6cf9 PB |
5379 | continue; |
5380 | break; | |
f4cfcd2d ML |
5381 | case MSR_IA32_UMWAIT_CONTROL: |
5382 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
5383 | continue; | |
5384 | break; | |
bf8c55d8 CP |
5385 | case MSR_IA32_RTIT_CTL: |
5386 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 5387 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
5388 | continue; |
5389 | break; | |
5390 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 5391 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5392 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
5393 | continue; | |
5394 | break; | |
5395 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
5396 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 5397 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
5398 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
5399 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
5400 | continue; | |
5401 | break; | |
7cb85fc4 | 5402 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 5403 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 5404 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
5405 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
5406 | continue; | |
5407 | break; | |
cf05a67b | 5408 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 5409 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
24c29b7a PB |
5410 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5411 | continue; | |
5412 | break; | |
cf05a67b | 5413 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 5414 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
24c29b7a PB |
5415 | min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) |
5416 | continue; | |
7cb85fc4 | 5417 | break; |
93c4adc7 PB |
5418 | default: |
5419 | break; | |
5420 | } | |
5421 | ||
7a5ee6ed | 5422 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 5423 | } |
62ef68bb | 5424 | |
7a5ee6ed | 5425 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
afaf0b2f | 5426 | if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i])) |
bc226f07 | 5427 | continue; |
62ef68bb | 5428 | |
7a5ee6ed | 5429 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 5430 | } |
801e459a | 5431 | |
7a5ee6ed | 5432 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
5433 | struct kvm_msr_entry msr; |
5434 | ||
7a5ee6ed | 5435 | msr.index = msr_based_features_all[i]; |
66421c1e | 5436 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
5437 | continue; |
5438 | ||
7a5ee6ed | 5439 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 5440 | } |
043405e1 CO |
5441 | } |
5442 | ||
bda9020e MT |
5443 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
5444 | const void *v) | |
bbd9b64e | 5445 | { |
70252a10 AK |
5446 | int handled = 0; |
5447 | int n; | |
5448 | ||
5449 | do { | |
5450 | n = min(len, 8); | |
bce87cce | 5451 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5452 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
5453 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
5454 | break; |
5455 | handled += n; | |
5456 | addr += n; | |
5457 | len -= n; | |
5458 | v += n; | |
5459 | } while (len); | |
bbd9b64e | 5460 | |
70252a10 | 5461 | return handled; |
bbd9b64e CO |
5462 | } |
5463 | ||
bda9020e | 5464 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 5465 | { |
70252a10 AK |
5466 | int handled = 0; |
5467 | int n; | |
5468 | ||
5469 | do { | |
5470 | n = min(len, 8); | |
bce87cce | 5471 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
5472 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
5473 | addr, n, v)) | |
5474 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 5475 | break; |
e39d200f | 5476 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
5477 | handled += n; |
5478 | addr += n; | |
5479 | len -= n; | |
5480 | v += n; | |
5481 | } while (len); | |
bbd9b64e | 5482 | |
70252a10 | 5483 | return handled; |
bbd9b64e CO |
5484 | } |
5485 | ||
2dafc6c2 GN |
5486 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
5487 | struct kvm_segment *var, int seg) | |
5488 | { | |
afaf0b2f | 5489 | kvm_x86_ops.set_segment(vcpu, var, seg); |
2dafc6c2 GN |
5490 | } |
5491 | ||
5492 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
5493 | struct kvm_segment *var, int seg) | |
5494 | { | |
afaf0b2f | 5495 | kvm_x86_ops.get_segment(vcpu, var, seg); |
2dafc6c2 GN |
5496 | } |
5497 | ||
54987b7a PB |
5498 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
5499 | struct x86_exception *exception) | |
02f59dc9 JR |
5500 | { |
5501 | gpa_t t_gpa; | |
02f59dc9 JR |
5502 | |
5503 | BUG_ON(!mmu_is_nested(vcpu)); | |
5504 | ||
5505 | /* NPT walks are always user-walks */ | |
5506 | access |= PFERR_USER_MASK; | |
44dd3ffa | 5507 | t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); |
02f59dc9 JR |
5508 | |
5509 | return t_gpa; | |
5510 | } | |
5511 | ||
ab9ae313 AK |
5512 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
5513 | struct x86_exception *exception) | |
1871c602 | 5514 | { |
afaf0b2f | 5515 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
ab9ae313 | 5516 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5517 | } |
5518 | ||
ab9ae313 AK |
5519 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
5520 | struct x86_exception *exception) | |
1871c602 | 5521 | { |
afaf0b2f | 5522 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5523 | access |= PFERR_FETCH_MASK; |
ab9ae313 | 5524 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5525 | } |
5526 | ||
ab9ae313 AK |
5527 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
5528 | struct x86_exception *exception) | |
1871c602 | 5529 | { |
afaf0b2f | 5530 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 5531 | access |= PFERR_WRITE_MASK; |
ab9ae313 | 5532 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
1871c602 GN |
5533 | } |
5534 | ||
5535 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
5536 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
5537 | struct x86_exception *exception) | |
1871c602 | 5538 | { |
ab9ae313 | 5539 | return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); |
1871c602 GN |
5540 | } |
5541 | ||
5542 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5543 | struct kvm_vcpu *vcpu, u32 access, | |
bcc55cba | 5544 | struct x86_exception *exception) |
bbd9b64e CO |
5545 | { |
5546 | void *data = val; | |
10589a46 | 5547 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
5548 | |
5549 | while (bytes) { | |
14dfe855 | 5550 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, |
ab9ae313 | 5551 | exception); |
bbd9b64e | 5552 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 5553 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
5554 | int ret; |
5555 | ||
bcc55cba | 5556 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5557 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
5558 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
5559 | offset, toread); | |
10589a46 | 5560 | if (ret < 0) { |
c3cd7ffa | 5561 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
5562 | goto out; |
5563 | } | |
bbd9b64e | 5564 | |
77c2002e IE |
5565 | bytes -= toread; |
5566 | data += toread; | |
5567 | addr += toread; | |
bbd9b64e | 5568 | } |
10589a46 | 5569 | out: |
10589a46 | 5570 | return r; |
bbd9b64e | 5571 | } |
77c2002e | 5572 | |
1871c602 | 5573 | /* used for instruction fetching */ |
0f65dd70 AK |
5574 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
5575 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 5576 | struct x86_exception *exception) |
1871c602 | 5577 | { |
0f65dd70 | 5578 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
afaf0b2f | 5579 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
5580 | unsigned offset; |
5581 | int ret; | |
0f65dd70 | 5582 | |
44583cba PB |
5583 | /* Inline kvm_read_guest_virt_helper for speed. */ |
5584 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, | |
5585 | exception); | |
5586 | if (unlikely(gpa == UNMAPPED_GVA)) | |
5587 | return X86EMUL_PROPAGATE_FAULT; | |
5588 | ||
5589 | offset = addr & (PAGE_SIZE-1); | |
5590 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
5591 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
5592 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
5593 | offset, bytes); | |
44583cba PB |
5594 | if (unlikely(ret < 0)) |
5595 | return X86EMUL_IO_NEEDED; | |
5596 | ||
5597 | return X86EMUL_CONTINUE; | |
1871c602 GN |
5598 | } |
5599 | ||
ce14e868 | 5600 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 5601 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 5602 | struct x86_exception *exception) |
1871c602 | 5603 | { |
afaf0b2f | 5604 | u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 5605 | |
353c0956 PB |
5606 | /* |
5607 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
5608 | * is returned, but our callers are not ready for that and they blindly | |
5609 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
5610 | * uninitialized kernel stack memory into cr2 and error code. | |
5611 | */ | |
5612 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 5613 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 5614 | exception); |
1871c602 | 5615 | } |
064aea77 | 5616 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 5617 | |
ce14e868 PB |
5618 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
5619 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 5620 | struct x86_exception *exception, bool system) |
1871c602 | 5621 | { |
0f65dd70 | 5622 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3c9fa24c PB |
5623 | u32 access = 0; |
5624 | ||
afaf0b2f | 5625 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c PB |
5626 | access |= PFERR_USER_MASK; |
5627 | ||
5628 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
5629 | } |
5630 | ||
7a036a6f RK |
5631 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
5632 | unsigned long addr, void *val, unsigned int bytes) | |
5633 | { | |
5634 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5635 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
5636 | ||
5637 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
5638 | } | |
5639 | ||
ce14e868 PB |
5640 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5641 | struct kvm_vcpu *vcpu, u32 access, | |
5642 | struct x86_exception *exception) | |
77c2002e IE |
5643 | { |
5644 | void *data = val; | |
5645 | int r = X86EMUL_CONTINUE; | |
5646 | ||
5647 | while (bytes) { | |
14dfe855 | 5648 | gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, |
ce14e868 | 5649 | access, |
ab9ae313 | 5650 | exception); |
77c2002e IE |
5651 | unsigned offset = addr & (PAGE_SIZE-1); |
5652 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
5653 | int ret; | |
5654 | ||
bcc55cba | 5655 | if (gpa == UNMAPPED_GVA) |
ab9ae313 | 5656 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 5657 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 5658 | if (ret < 0) { |
c3cd7ffa | 5659 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
5660 | goto out; |
5661 | } | |
5662 | ||
5663 | bytes -= towrite; | |
5664 | data += towrite; | |
5665 | addr += towrite; | |
5666 | } | |
5667 | out: | |
5668 | return r; | |
5669 | } | |
ce14e868 PB |
5670 | |
5671 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
5672 | unsigned int bytes, struct x86_exception *exception, |
5673 | bool system) | |
ce14e868 PB |
5674 | { |
5675 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
3c9fa24c PB |
5676 | u32 access = PFERR_WRITE_MASK; |
5677 | ||
afaf0b2f | 5678 | if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) |
3c9fa24c | 5679 | access |= PFERR_USER_MASK; |
ce14e868 PB |
5680 | |
5681 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 5682 | access, exception); |
ce14e868 PB |
5683 | } |
5684 | ||
5685 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
5686 | unsigned int bytes, struct x86_exception *exception) | |
5687 | { | |
c595ceee PB |
5688 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
5689 | vcpu->arch.l1tf_flush_l1d = true; | |
5690 | ||
ce14e868 PB |
5691 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
5692 | PFERR_WRITE_MASK, exception); | |
5693 | } | |
6a4d7550 | 5694 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 5695 | |
082d06ed WL |
5696 | int handle_ud(struct kvm_vcpu *vcpu) |
5697 | { | |
b3dc0695 | 5698 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 5699 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
5700 | char sig[5]; /* ud2; .ascii "kvm" */ |
5701 | struct x86_exception e; | |
5702 | ||
5703 | if (force_emulation_prefix && | |
3c9fa24c PB |
5704 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
5705 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 5706 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
6c86eedc | 5707 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 5708 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 5709 | } |
082d06ed | 5710 | |
60fc3d02 | 5711 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
5712 | } |
5713 | EXPORT_SYMBOL_GPL(handle_ud); | |
5714 | ||
0f89b207 TL |
5715 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5716 | gpa_t gpa, bool write) | |
5717 | { | |
5718 | /* For APIC access vmexit */ | |
5719 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
5720 | return 1; | |
5721 | ||
5722 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
5723 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
5724 | return 1; | |
5725 | } | |
5726 | ||
5727 | return 0; | |
5728 | } | |
5729 | ||
af7cc7d1 XG |
5730 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
5731 | gpa_t *gpa, struct x86_exception *exception, | |
5732 | bool write) | |
5733 | { | |
afaf0b2f | 5734 | u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 5735 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 5736 | |
be94f6b7 HH |
5737 | /* |
5738 | * currently PKRU is only applied to ept enabled guest so | |
5739 | * there is no pkey in EPT page table for L1 guest or EPT | |
5740 | * shadow page table for L2 guest. | |
5741 | */ | |
97d64b78 | 5742 | if (vcpu_match_mmio_gva(vcpu, gva) |
97ec8c06 | 5743 | && !permission_fault(vcpu, vcpu->arch.walk_mmu, |
871bd034 | 5744 | vcpu->arch.mmio_access, 0, access)) { |
bebb106a XG |
5745 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
5746 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 5747 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
5748 | return 1; |
5749 | } | |
5750 | ||
af7cc7d1 XG |
5751 | *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); |
5752 | ||
5753 | if (*gpa == UNMAPPED_GVA) | |
5754 | return -1; | |
5755 | ||
0f89b207 | 5756 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
5757 | } |
5758 | ||
3200f405 | 5759 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 5760 | const void *val, int bytes) |
bbd9b64e CO |
5761 | { |
5762 | int ret; | |
5763 | ||
54bf36aa | 5764 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 5765 | if (ret < 0) |
bbd9b64e | 5766 | return 0; |
0eb05bf2 | 5767 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
5768 | return 1; |
5769 | } | |
5770 | ||
77d197b2 XG |
5771 | struct read_write_emulator_ops { |
5772 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
5773 | int bytes); | |
5774 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5775 | void *val, int bytes); | |
5776 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5777 | int bytes, void *val); | |
5778 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5779 | void *val, int bytes); | |
5780 | bool write; | |
5781 | }; | |
5782 | ||
5783 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
5784 | { | |
5785 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 5786 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 5787 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
5788 | vcpu->mmio_read_completed = 0; |
5789 | return 1; | |
5790 | } | |
5791 | ||
5792 | return 0; | |
5793 | } | |
5794 | ||
5795 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5796 | void *val, int bytes) | |
5797 | { | |
54bf36aa | 5798 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
5799 | } |
5800 | ||
5801 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5802 | void *val, int bytes) | |
5803 | { | |
5804 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
5805 | } | |
5806 | ||
5807 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
5808 | { | |
e39d200f | 5809 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
5810 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
5811 | } | |
5812 | ||
5813 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5814 | void *val, int bytes) | |
5815 | { | |
e39d200f | 5816 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
5817 | return X86EMUL_IO_NEEDED; |
5818 | } | |
5819 | ||
5820 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
5821 | void *val, int bytes) | |
5822 | { | |
f78146b0 AK |
5823 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
5824 | ||
87da7e66 | 5825 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
5826 | return X86EMUL_CONTINUE; |
5827 | } | |
5828 | ||
0fbe9b0b | 5829 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
5830 | .read_write_prepare = read_prepare, |
5831 | .read_write_emulate = read_emulate, | |
5832 | .read_write_mmio = vcpu_mmio_read, | |
5833 | .read_write_exit_mmio = read_exit_mmio, | |
5834 | }; | |
5835 | ||
0fbe9b0b | 5836 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
5837 | .read_write_emulate = write_emulate, |
5838 | .read_write_mmio = write_mmio, | |
5839 | .read_write_exit_mmio = write_exit_mmio, | |
5840 | .write = true, | |
5841 | }; | |
5842 | ||
22388a3c XG |
5843 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
5844 | unsigned int bytes, | |
5845 | struct x86_exception *exception, | |
5846 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 5847 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5848 | { |
af7cc7d1 XG |
5849 | gpa_t gpa; |
5850 | int handled, ret; | |
22388a3c | 5851 | bool write = ops->write; |
f78146b0 | 5852 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 5853 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
5854 | |
5855 | /* | |
5856 | * If the exit was due to a NPF we may already have a GPA. | |
5857 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
5858 | * Note, this cannot be used on string operations since string | |
5859 | * operation using rep will only have the initial GPA from the NPF | |
5860 | * occurred. | |
5861 | */ | |
744e699c SC |
5862 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
5863 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
5864 | gpa = ctxt->gpa_val; | |
618232e2 BS |
5865 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
5866 | } else { | |
5867 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
5868 | if (ret < 0) | |
5869 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 5870 | } |
10589a46 | 5871 | |
618232e2 | 5872 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
5873 | return X86EMUL_CONTINUE; |
5874 | ||
bbd9b64e CO |
5875 | /* |
5876 | * Is this MMIO handled locally? | |
5877 | */ | |
22388a3c | 5878 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 5879 | if (handled == bytes) |
bbd9b64e | 5880 | return X86EMUL_CONTINUE; |
bbd9b64e | 5881 | |
70252a10 AK |
5882 | gpa += handled; |
5883 | bytes -= handled; | |
5884 | val += handled; | |
5885 | ||
87da7e66 XG |
5886 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
5887 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
5888 | frag->gpa = gpa; | |
5889 | frag->data = val; | |
5890 | frag->len = bytes; | |
f78146b0 | 5891 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
5892 | } |
5893 | ||
52eb5a6d XL |
5894 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
5895 | unsigned long addr, | |
22388a3c XG |
5896 | void *val, unsigned int bytes, |
5897 | struct x86_exception *exception, | |
0fbe9b0b | 5898 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 5899 | { |
0f65dd70 | 5900 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
5901 | gpa_t gpa; |
5902 | int rc; | |
5903 | ||
5904 | if (ops->read_write_prepare && | |
5905 | ops->read_write_prepare(vcpu, val, bytes)) | |
5906 | return X86EMUL_CONTINUE; | |
5907 | ||
5908 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 5909 | |
bbd9b64e CO |
5910 | /* Crossing a page boundary? */ |
5911 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 5912 | int now; |
bbd9b64e CO |
5913 | |
5914 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
5915 | rc = emulator_read_write_onepage(addr, val, now, exception, |
5916 | vcpu, ops); | |
5917 | ||
bbd9b64e CO |
5918 | if (rc != X86EMUL_CONTINUE) |
5919 | return rc; | |
5920 | addr += now; | |
bac15531 NA |
5921 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
5922 | addr = (u32)addr; | |
bbd9b64e CO |
5923 | val += now; |
5924 | bytes -= now; | |
5925 | } | |
22388a3c | 5926 | |
f78146b0 AK |
5927 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
5928 | vcpu, ops); | |
5929 | if (rc != X86EMUL_CONTINUE) | |
5930 | return rc; | |
5931 | ||
5932 | if (!vcpu->mmio_nr_fragments) | |
5933 | return rc; | |
5934 | ||
5935 | gpa = vcpu->mmio_fragments[0].gpa; | |
5936 | ||
5937 | vcpu->mmio_needed = 1; | |
5938 | vcpu->mmio_cur_fragment = 0; | |
5939 | ||
87da7e66 | 5940 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
5941 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
5942 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
5943 | vcpu->run->mmio.phys_addr = gpa; | |
5944 | ||
5945 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
5946 | } |
5947 | ||
5948 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
5949 | unsigned long addr, | |
5950 | void *val, | |
5951 | unsigned int bytes, | |
5952 | struct x86_exception *exception) | |
5953 | { | |
5954 | return emulator_read_write(ctxt, addr, val, bytes, | |
5955 | exception, &read_emultor); | |
5956 | } | |
5957 | ||
52eb5a6d | 5958 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
5959 | unsigned long addr, |
5960 | const void *val, | |
5961 | unsigned int bytes, | |
5962 | struct x86_exception *exception) | |
5963 | { | |
5964 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
5965 | exception, &write_emultor); | |
bbd9b64e | 5966 | } |
bbd9b64e | 5967 | |
daea3e73 AK |
5968 | #define CMPXCHG_TYPE(t, ptr, old, new) \ |
5969 | (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) | |
5970 | ||
5971 | #ifdef CONFIG_X86_64 | |
5972 | # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) | |
5973 | #else | |
5974 | # define CMPXCHG64(ptr, old, new) \ | |
9749a6c0 | 5975 | (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) |
daea3e73 AK |
5976 | #endif |
5977 | ||
0f65dd70 AK |
5978 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
5979 | unsigned long addr, | |
bbd9b64e CO |
5980 | const void *old, |
5981 | const void *new, | |
5982 | unsigned int bytes, | |
0f65dd70 | 5983 | struct x86_exception *exception) |
bbd9b64e | 5984 | { |
42e35f80 | 5985 | struct kvm_host_map map; |
0f65dd70 | 5986 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 5987 | u64 page_line_mask; |
daea3e73 | 5988 | gpa_t gpa; |
daea3e73 AK |
5989 | char *kaddr; |
5990 | bool exchanged; | |
2bacc55c | 5991 | |
daea3e73 AK |
5992 | /* guests cmpxchg8b have to be emulated atomically */ |
5993 | if (bytes > 8 || (bytes & (bytes - 1))) | |
5994 | goto emul_write; | |
10589a46 | 5995 | |
daea3e73 | 5996 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 5997 | |
daea3e73 AK |
5998 | if (gpa == UNMAPPED_GVA || |
5999 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
6000 | goto emul_write; | |
2bacc55c | 6001 | |
9de6fe3c XL |
6002 | /* |
6003 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
6004 | * enabled in the host and the access splits a cache line. | |
6005 | */ | |
6006 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
6007 | page_line_mask = ~(cache_line_size() - 1); | |
6008 | else | |
6009 | page_line_mask = PAGE_MASK; | |
6010 | ||
6011 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 6012 | goto emul_write; |
72dc67a6 | 6013 | |
42e35f80 | 6014 | if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) |
c19b8bd6 | 6015 | goto emul_write; |
72dc67a6 | 6016 | |
42e35f80 KA |
6017 | kaddr = map.hva + offset_in_page(gpa); |
6018 | ||
daea3e73 AK |
6019 | switch (bytes) { |
6020 | case 1: | |
6021 | exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); | |
6022 | break; | |
6023 | case 2: | |
6024 | exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); | |
6025 | break; | |
6026 | case 4: | |
6027 | exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); | |
6028 | break; | |
6029 | case 8: | |
6030 | exchanged = CMPXCHG64(kaddr, old, new); | |
6031 | break; | |
6032 | default: | |
6033 | BUG(); | |
2bacc55c | 6034 | } |
42e35f80 KA |
6035 | |
6036 | kvm_vcpu_unmap(vcpu, &map, true); | |
daea3e73 AK |
6037 | |
6038 | if (!exchanged) | |
6039 | return X86EMUL_CMPXCHG_FAILED; | |
6040 | ||
0eb05bf2 | 6041 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
6042 | |
6043 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 6044 | |
3200f405 | 6045 | emul_write: |
daea3e73 | 6046 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 6047 | |
0f65dd70 | 6048 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
6049 | } |
6050 | ||
cf8f70bf GN |
6051 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
6052 | { | |
cbfc6c91 | 6053 | int r = 0, i; |
cf8f70bf | 6054 | |
cbfc6c91 WL |
6055 | for (i = 0; i < vcpu->arch.pio.count; i++) { |
6056 | if (vcpu->arch.pio.in) | |
6057 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, | |
6058 | vcpu->arch.pio.size, pd); | |
6059 | else | |
6060 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, | |
6061 | vcpu->arch.pio.port, vcpu->arch.pio.size, | |
6062 | pd); | |
6063 | if (r) | |
6064 | break; | |
6065 | pd += vcpu->arch.pio.size; | |
6066 | } | |
cf8f70bf GN |
6067 | return r; |
6068 | } | |
6069 | ||
6f6fbe98 XG |
6070 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
6071 | unsigned short port, void *val, | |
6072 | unsigned int count, bool in) | |
cf8f70bf | 6073 | { |
cf8f70bf | 6074 | vcpu->arch.pio.port = port; |
6f6fbe98 | 6075 | vcpu->arch.pio.in = in; |
7972995b | 6076 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
6077 | vcpu->arch.pio.size = size; |
6078 | ||
6079 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { | |
7972995b | 6080 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6081 | return 1; |
6082 | } | |
6083 | ||
6084 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 6085 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
6086 | vcpu->run->io.size = size; |
6087 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
6088 | vcpu->run->io.count = count; | |
6089 | vcpu->run->io.port = port; | |
6090 | ||
6091 | return 0; | |
6092 | } | |
6093 | ||
2e3bb4d8 SC |
6094 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
6095 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 6096 | { |
6f6fbe98 | 6097 | int ret; |
ca1d4a9e | 6098 | |
6f6fbe98 XG |
6099 | if (vcpu->arch.pio.count) |
6100 | goto data_avail; | |
cf8f70bf | 6101 | |
cbfc6c91 WL |
6102 | memset(vcpu->arch.pio_data, 0, size * count); |
6103 | ||
6f6fbe98 XG |
6104 | ret = emulator_pio_in_out(vcpu, size, port, val, count, true); |
6105 | if (ret) { | |
6106 | data_avail: | |
6107 | memcpy(val, vcpu->arch.pio_data, size * count); | |
1171903d | 6108 | trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); |
7972995b | 6109 | vcpu->arch.pio.count = 0; |
cf8f70bf GN |
6110 | return 1; |
6111 | } | |
6112 | ||
cf8f70bf GN |
6113 | return 0; |
6114 | } | |
6115 | ||
2e3bb4d8 SC |
6116 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
6117 | int size, unsigned short port, void *val, | |
6118 | unsigned int count) | |
6f6fbe98 | 6119 | { |
2e3bb4d8 | 6120 | return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); |
6f6fbe98 | 6121 | |
2e3bb4d8 | 6122 | } |
6f6fbe98 | 6123 | |
2e3bb4d8 SC |
6124 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
6125 | unsigned short port, const void *val, | |
6126 | unsigned int count) | |
6127 | { | |
6f6fbe98 | 6128 | memcpy(vcpu->arch.pio_data, val, size * count); |
1171903d | 6129 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); |
6f6fbe98 XG |
6130 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6131 | } | |
6132 | ||
2e3bb4d8 SC |
6133 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
6134 | int size, unsigned short port, | |
6135 | const void *val, unsigned int count) | |
6136 | { | |
6137 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
6138 | } | |
6139 | ||
bbd9b64e CO |
6140 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
6141 | { | |
afaf0b2f | 6142 | return kvm_x86_ops.get_segment_base(vcpu, seg); |
bbd9b64e CO |
6143 | } |
6144 | ||
3cb16fe7 | 6145 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 6146 | { |
3cb16fe7 | 6147 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
6148 | } |
6149 | ||
ae6a2375 | 6150 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
6151 | { |
6152 | if (!need_emulate_wbinvd(vcpu)) | |
6153 | return X86EMUL_CONTINUE; | |
6154 | ||
afaf0b2f | 6155 | if (kvm_x86_ops.has_wbinvd_exit()) { |
2eec7343 JK |
6156 | int cpu = get_cpu(); |
6157 | ||
6158 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
f5f48ee1 SY |
6159 | smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, |
6160 | wbinvd_ipi, NULL, 1); | |
2eec7343 | 6161 | put_cpu(); |
f5f48ee1 | 6162 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
6163 | } else |
6164 | wbinvd(); | |
f5f48ee1 SY |
6165 | return X86EMUL_CONTINUE; |
6166 | } | |
5cb56059 JS |
6167 | |
6168 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
6169 | { | |
6affcbed KH |
6170 | kvm_emulate_wbinvd_noskip(vcpu); |
6171 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 6172 | } |
f5f48ee1 SY |
6173 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
6174 | ||
5cb56059 JS |
6175 | |
6176 | ||
bcaf5cc5 AK |
6177 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
6178 | { | |
5cb56059 | 6179 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
6180 | } |
6181 | ||
52eb5a6d XL |
6182 | static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6183 | unsigned long *dest) | |
bbd9b64e | 6184 | { |
16f8a6f9 | 6185 | return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
6186 | } |
6187 | ||
52eb5a6d XL |
6188 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
6189 | unsigned long value) | |
bbd9b64e | 6190 | { |
338dbc97 | 6191 | |
717746e3 | 6192 | return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
6193 | } |
6194 | ||
52a46617 | 6195 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 6196 | { |
52a46617 | 6197 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
6198 | } |
6199 | ||
717746e3 | 6200 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 6201 | { |
717746e3 | 6202 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
6203 | unsigned long value; |
6204 | ||
6205 | switch (cr) { | |
6206 | case 0: | |
6207 | value = kvm_read_cr0(vcpu); | |
6208 | break; | |
6209 | case 2: | |
6210 | value = vcpu->arch.cr2; | |
6211 | break; | |
6212 | case 3: | |
9f8fe504 | 6213 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
6214 | break; |
6215 | case 4: | |
6216 | value = kvm_read_cr4(vcpu); | |
6217 | break; | |
6218 | case 8: | |
6219 | value = kvm_get_cr8(vcpu); | |
6220 | break; | |
6221 | default: | |
a737f256 | 6222 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
6223 | return 0; |
6224 | } | |
6225 | ||
6226 | return value; | |
6227 | } | |
6228 | ||
717746e3 | 6229 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 6230 | { |
717746e3 | 6231 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
6232 | int res = 0; |
6233 | ||
52a46617 GN |
6234 | switch (cr) { |
6235 | case 0: | |
49a9b07e | 6236 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
6237 | break; |
6238 | case 2: | |
6239 | vcpu->arch.cr2 = val; | |
6240 | break; | |
6241 | case 3: | |
2390218b | 6242 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
6243 | break; |
6244 | case 4: | |
a83b29c6 | 6245 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
6246 | break; |
6247 | case 8: | |
eea1cff9 | 6248 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
6249 | break; |
6250 | default: | |
a737f256 | 6251 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 6252 | res = -1; |
52a46617 | 6253 | } |
0f12244f GN |
6254 | |
6255 | return res; | |
52a46617 GN |
6256 | } |
6257 | ||
717746e3 | 6258 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 6259 | { |
afaf0b2f | 6260 | return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); |
9c537244 GN |
6261 | } |
6262 | ||
4bff1e86 | 6263 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 6264 | { |
afaf0b2f | 6265 | kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
6266 | } |
6267 | ||
4bff1e86 | 6268 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 6269 | { |
afaf0b2f | 6270 | kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
6271 | } |
6272 | ||
1ac9d0cf AK |
6273 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
6274 | { | |
afaf0b2f | 6275 | kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6276 | } |
6277 | ||
6278 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
6279 | { | |
afaf0b2f | 6280 | kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
6281 | } |
6282 | ||
4bff1e86 AK |
6283 | static unsigned long emulator_get_cached_segment_base( |
6284 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 6285 | { |
4bff1e86 | 6286 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
6287 | } |
6288 | ||
1aa36616 AK |
6289 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
6290 | struct desc_struct *desc, u32 *base3, | |
6291 | int seg) | |
2dafc6c2 GN |
6292 | { |
6293 | struct kvm_segment var; | |
6294 | ||
4bff1e86 | 6295 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 6296 | *selector = var.selector; |
2dafc6c2 | 6297 | |
378a8b09 GN |
6298 | if (var.unusable) { |
6299 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
6300 | if (base3) |
6301 | *base3 = 0; | |
2dafc6c2 | 6302 | return false; |
378a8b09 | 6303 | } |
2dafc6c2 GN |
6304 | |
6305 | if (var.g) | |
6306 | var.limit >>= 12; | |
6307 | set_desc_limit(desc, var.limit); | |
6308 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
6309 | #ifdef CONFIG_X86_64 |
6310 | if (base3) | |
6311 | *base3 = var.base >> 32; | |
6312 | #endif | |
2dafc6c2 GN |
6313 | desc->type = var.type; |
6314 | desc->s = var.s; | |
6315 | desc->dpl = var.dpl; | |
6316 | desc->p = var.present; | |
6317 | desc->avl = var.avl; | |
6318 | desc->l = var.l; | |
6319 | desc->d = var.db; | |
6320 | desc->g = var.g; | |
6321 | ||
6322 | return true; | |
6323 | } | |
6324 | ||
1aa36616 AK |
6325 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
6326 | struct desc_struct *desc, u32 base3, | |
6327 | int seg) | |
2dafc6c2 | 6328 | { |
4bff1e86 | 6329 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
6330 | struct kvm_segment var; |
6331 | ||
1aa36616 | 6332 | var.selector = selector; |
2dafc6c2 | 6333 | var.base = get_desc_base(desc); |
5601d05b GN |
6334 | #ifdef CONFIG_X86_64 |
6335 | var.base |= ((u64)base3) << 32; | |
6336 | #endif | |
2dafc6c2 GN |
6337 | var.limit = get_desc_limit(desc); |
6338 | if (desc->g) | |
6339 | var.limit = (var.limit << 12) | 0xfff; | |
6340 | var.type = desc->type; | |
2dafc6c2 GN |
6341 | var.dpl = desc->dpl; |
6342 | var.db = desc->d; | |
6343 | var.s = desc->s; | |
6344 | var.l = desc->l; | |
6345 | var.g = desc->g; | |
6346 | var.avl = desc->avl; | |
6347 | var.present = desc->p; | |
6348 | var.unusable = !var.present; | |
6349 | var.padding = 0; | |
6350 | ||
6351 | kvm_set_segment(vcpu, &var, seg); | |
6352 | return; | |
6353 | } | |
6354 | ||
717746e3 AK |
6355 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
6356 | u32 msr_index, u64 *pdata) | |
6357 | { | |
f20935d8 | 6358 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); |
717746e3 AK |
6359 | } |
6360 | ||
6361 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
6362 | u32 msr_index, u64 data) | |
6363 | { | |
f20935d8 | 6364 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); |
717746e3 AK |
6365 | } |
6366 | ||
64d60670 PB |
6367 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
6368 | { | |
6369 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6370 | ||
6371 | return vcpu->arch.smbase; | |
6372 | } | |
6373 | ||
6374 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
6375 | { | |
6376 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
6377 | ||
6378 | vcpu->arch.smbase = smbase; | |
6379 | } | |
6380 | ||
67f4d428 NA |
6381 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
6382 | u32 pmc) | |
6383 | { | |
98ff80f5 | 6384 | return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); |
67f4d428 NA |
6385 | } |
6386 | ||
222d21aa AK |
6387 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
6388 | u32 pmc, u64 *pdata) | |
6389 | { | |
c6702c9d | 6390 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
6391 | } |
6392 | ||
6c3287f7 AK |
6393 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
6394 | { | |
6395 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
6396 | } | |
6397 | ||
2953538e | 6398 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 6399 | struct x86_instruction_info *info, |
c4f035c6 AK |
6400 | enum x86_intercept_stage stage) |
6401 | { | |
afaf0b2f | 6402 | return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 6403 | &ctxt->exception); |
c4f035c6 AK |
6404 | } |
6405 | ||
e911eb3b | 6406 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
6407 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
6408 | bool exact_only) | |
bdb42f5a | 6409 | { |
f91af517 | 6410 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
6411 | } |
6412 | ||
5ae78e95 SC |
6413 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
6414 | { | |
6415 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
6416 | } | |
6417 | ||
6418 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
6419 | { | |
6420 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
6421 | } | |
6422 | ||
6423 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
6424 | { | |
6425 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
6426 | } | |
6427 | ||
dd856efa AK |
6428 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
6429 | { | |
6430 | return kvm_register_read(emul_to_vcpu(ctxt), reg); | |
6431 | } | |
6432 | ||
6433 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
6434 | { | |
6435 | kvm_register_write(emul_to_vcpu(ctxt), reg, val); | |
6436 | } | |
6437 | ||
801806d9 NA |
6438 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
6439 | { | |
afaf0b2f | 6440 | kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
6441 | } |
6442 | ||
6ed071f0 LP |
6443 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
6444 | { | |
6445 | return emul_to_vcpu(ctxt)->arch.hflags; | |
6446 | } | |
6447 | ||
6448 | static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) | |
6449 | { | |
c5833c7a | 6450 | emul_to_vcpu(ctxt)->arch.hflags = emul_flags; |
6ed071f0 LP |
6451 | } |
6452 | ||
ed19321f SC |
6453 | static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, |
6454 | const char *smstate) | |
0234bf88 | 6455 | { |
afaf0b2f | 6456 | return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
6457 | } |
6458 | ||
c5833c7a SC |
6459 | static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) |
6460 | { | |
6461 | kvm_smm_changed(emul_to_vcpu(ctxt)); | |
6462 | } | |
6463 | ||
02d4160f VK |
6464 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
6465 | { | |
6466 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
6467 | } | |
6468 | ||
0225fb50 | 6469 | static const struct x86_emulate_ops emulate_ops = { |
dd856efa AK |
6470 | .read_gpr = emulator_read_gpr, |
6471 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
6472 | .read_std = emulator_read_std, |
6473 | .write_std = emulator_write_std, | |
7a036a6f | 6474 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 6475 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
6476 | .read_emulated = emulator_read_emulated, |
6477 | .write_emulated = emulator_write_emulated, | |
6478 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 6479 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
6480 | .pio_in_emulated = emulator_pio_in_emulated, |
6481 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
6482 | .get_segment = emulator_get_segment, |
6483 | .set_segment = emulator_set_segment, | |
5951c442 | 6484 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 6485 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 6486 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
6487 | .set_gdt = emulator_set_gdt, |
6488 | .set_idt = emulator_set_idt, | |
52a46617 GN |
6489 | .get_cr = emulator_get_cr, |
6490 | .set_cr = emulator_set_cr, | |
9c537244 | 6491 | .cpl = emulator_get_cpl, |
35aa5375 GN |
6492 | .get_dr = emulator_get_dr, |
6493 | .set_dr = emulator_set_dr, | |
64d60670 PB |
6494 | .get_smbase = emulator_get_smbase, |
6495 | .set_smbase = emulator_set_smbase, | |
717746e3 AK |
6496 | .set_msr = emulator_set_msr, |
6497 | .get_msr = emulator_get_msr, | |
67f4d428 | 6498 | .check_pmc = emulator_check_pmc, |
222d21aa | 6499 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 6500 | .halt = emulator_halt, |
bcaf5cc5 | 6501 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 6502 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 6503 | .intercept = emulator_intercept, |
bdb42f5a | 6504 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
6505 | .guest_has_long_mode = emulator_guest_has_long_mode, |
6506 | .guest_has_movbe = emulator_guest_has_movbe, | |
6507 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
801806d9 | 6508 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 LP |
6509 | .get_hflags = emulator_get_hflags, |
6510 | .set_hflags = emulator_set_hflags, | |
0234bf88 | 6511 | .pre_leave_smm = emulator_pre_leave_smm, |
c5833c7a | 6512 | .post_leave_smm = emulator_post_leave_smm, |
02d4160f | 6513 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
6514 | }; |
6515 | ||
95cb2295 GN |
6516 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
6517 | { | |
afaf0b2f | 6518 | u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); |
95cb2295 GN |
6519 | /* |
6520 | * an sti; sti; sequence only disable interrupts for the first | |
6521 | * instruction. So, if the last instruction, be it emulated or | |
6522 | * not, left the system with the INT_STI flag enabled, it | |
6523 | * means that the last instruction is an sti. We should not | |
6524 | * leave the flag on in this case. The same goes for mov ss | |
6525 | */ | |
37ccdcbe PB |
6526 | if (int_shadow & mask) |
6527 | mask = 0; | |
6addfc42 | 6528 | if (unlikely(int_shadow || mask)) { |
afaf0b2f | 6529 | kvm_x86_ops.set_interrupt_shadow(vcpu, mask); |
6addfc42 PB |
6530 | if (!mask) |
6531 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6532 | } | |
95cb2295 GN |
6533 | } |
6534 | ||
ef54bcfe | 6535 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 6536 | { |
c9b8b07c | 6537 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 6538 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 6539 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
6540 | |
6541 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
6542 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
6543 | ctxt->exception.error_code); | |
54b8486f | 6544 | else |
da9cb575 | 6545 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 6546 | return false; |
54b8486f GN |
6547 | } |
6548 | ||
c9b8b07c SC |
6549 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
6550 | { | |
6551 | struct x86_emulate_ctxt *ctxt; | |
6552 | ||
6553 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
6554 | if (!ctxt) { | |
6555 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
6556 | return NULL; | |
6557 | } | |
6558 | ||
6559 | ctxt->vcpu = vcpu; | |
6560 | ctxt->ops = &emulate_ops; | |
6561 | vcpu->arch.emulate_ctxt = ctxt; | |
6562 | ||
6563 | return ctxt; | |
6564 | } | |
6565 | ||
8ec4722d MG |
6566 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
6567 | { | |
c9b8b07c | 6568 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
6569 | int cs_db, cs_l; |
6570 | ||
afaf0b2f | 6571 | kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); |
8ec4722d | 6572 | |
744e699c | 6573 | ctxt->gpa_available = false; |
adf52235 | 6574 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
6575 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
6576 | ||
adf52235 TY |
6577 | ctxt->eip = kvm_rip_read(vcpu); |
6578 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
6579 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 6580 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
6581 | cs_db ? X86EMUL_MODE_PROT32 : |
6582 | X86EMUL_MODE_PROT16; | |
a584539b | 6583 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
6584 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
6585 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 6586 | |
dd856efa | 6587 | init_decode_cache(ctxt); |
7ae441ea | 6588 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
6589 | } |
6590 | ||
9497e1f2 | 6591 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 6592 | { |
c9b8b07c | 6593 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
6594 | int ret; |
6595 | ||
6596 | init_emulate_ctxt(vcpu); | |
6597 | ||
9dac77fa AK |
6598 | ctxt->op_bytes = 2; |
6599 | ctxt->ad_bytes = 2; | |
6600 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 6601 | ret = emulate_int_real(ctxt, irq); |
63995653 | 6602 | |
9497e1f2 SC |
6603 | if (ret != X86EMUL_CONTINUE) { |
6604 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6605 | } else { | |
6606 | ctxt->eip = ctxt->_eip; | |
6607 | kvm_rip_write(vcpu, ctxt->eip); | |
6608 | kvm_set_rflags(vcpu, ctxt->eflags); | |
6609 | } | |
63995653 MG |
6610 | } |
6611 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
6612 | ||
e2366171 | 6613 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 6614 | { |
6d77dbfc GN |
6615 | ++vcpu->stat.insn_emulation_fail; |
6616 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 6617 | |
42cbf068 SC |
6618 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
6619 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 6620 | return 1; |
42cbf068 | 6621 | } |
e2366171 | 6622 | |
738fece4 SC |
6623 | if (emulation_type & EMULTYPE_SKIP) { |
6624 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
6625 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6626 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 6627 | return 0; |
738fece4 SC |
6628 | } |
6629 | ||
22da61c9 SC |
6630 | kvm_queue_exception(vcpu, UD_VECTOR); |
6631 | ||
afaf0b2f | 6632 | if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { |
fc3a9157 JR |
6633 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
6634 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
6635 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 6636 | return 0; |
fc3a9157 | 6637 | } |
e2366171 | 6638 | |
60fc3d02 | 6639 | return 1; |
6d77dbfc GN |
6640 | } |
6641 | ||
736c291c | 6642 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
6643 | bool write_fault_to_shadow_pgtable, |
6644 | int emulation_type) | |
a6f177ef | 6645 | { |
736c291c | 6646 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 6647 | kvm_pfn_t pfn; |
a6f177ef | 6648 | |
92daa48b | 6649 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
6650 | return false; |
6651 | ||
92daa48b SC |
6652 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
6653 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
6654 | return false; |
6655 | ||
44dd3ffa | 6656 | if (!vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6657 | /* |
6658 | * Write permission should be allowed since only | |
6659 | * write access need to be emulated. | |
6660 | */ | |
736c291c | 6661 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 6662 | |
95b3cf69 XG |
6663 | /* |
6664 | * If the mapping is invalid in guest, let cpu retry | |
6665 | * it to generate fault. | |
6666 | */ | |
6667 | if (gpa == UNMAPPED_GVA) | |
6668 | return true; | |
6669 | } | |
a6f177ef | 6670 | |
8e3d9d06 XG |
6671 | /* |
6672 | * Do not retry the unhandleable instruction if it faults on the | |
6673 | * readonly host memory, otherwise it will goto a infinite loop: | |
6674 | * retry instruction -> write #PF -> emulation fail -> retry | |
6675 | * instruction -> ... | |
6676 | */ | |
6677 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
6678 | |
6679 | /* | |
6680 | * If the instruction failed on the error pfn, it can not be fixed, | |
6681 | * report the error to userspace. | |
6682 | */ | |
6683 | if (is_error_noslot_pfn(pfn)) | |
6684 | return false; | |
6685 | ||
6686 | kvm_release_pfn_clean(pfn); | |
6687 | ||
6688 | /* The instructions are well-emulated on direct mmu. */ | |
44dd3ffa | 6689 | if (vcpu->arch.mmu->direct_map) { |
95b3cf69 XG |
6690 | unsigned int indirect_shadow_pages; |
6691 | ||
6692 | spin_lock(&vcpu->kvm->mmu_lock); | |
6693 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; | |
6694 | spin_unlock(&vcpu->kvm->mmu_lock); | |
6695 | ||
6696 | if (indirect_shadow_pages) | |
6697 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
6698 | ||
a6f177ef | 6699 | return true; |
8e3d9d06 | 6700 | } |
a6f177ef | 6701 | |
95b3cf69 XG |
6702 | /* |
6703 | * if emulation was due to access to shadowed page table | |
6704 | * and it failed try to unshadow page and re-enter the | |
6705 | * guest to let CPU execute the instruction. | |
6706 | */ | |
6707 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
6708 | |
6709 | /* | |
6710 | * If the access faults on its page table, it can not | |
6711 | * be fixed by unprotecting shadow page and it should | |
6712 | * be reported to userspace. | |
6713 | */ | |
6714 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
6715 | } |
6716 | ||
1cb3f3ae | 6717 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 6718 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
6719 | { |
6720 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 6721 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
6722 | |
6723 | last_retry_eip = vcpu->arch.last_retry_eip; | |
6724 | last_retry_addr = vcpu->arch.last_retry_addr; | |
6725 | ||
6726 | /* | |
6727 | * If the emulation is caused by #PF and it is non-page_table | |
6728 | * writing instruction, it means the VM-EXIT is caused by shadow | |
6729 | * page protected, we can zap the shadow page and retry this | |
6730 | * instruction directly. | |
6731 | * | |
6732 | * Note: if the guest uses a non-page-table modifying instruction | |
6733 | * on the PDE that points to the instruction, then we will unmap | |
6734 | * the instruction and go to an infinite loop. So, we cache the | |
6735 | * last retried eip and the last fault address, if we meet the eip | |
6736 | * and the address again, we can break out of the potential infinite | |
6737 | * loop. | |
6738 | */ | |
6739 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
6740 | ||
92daa48b | 6741 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
6742 | return false; |
6743 | ||
92daa48b SC |
6744 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
6745 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
6746 | return false; |
6747 | ||
1cb3f3ae XG |
6748 | if (x86_page_table_writing_insn(ctxt)) |
6749 | return false; | |
6750 | ||
736c291c | 6751 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
6752 | return false; |
6753 | ||
6754 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 6755 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 6756 | |
44dd3ffa | 6757 | if (!vcpu->arch.mmu->direct_map) |
736c291c | 6758 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 6759 | |
22368028 | 6760 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
6761 | |
6762 | return true; | |
6763 | } | |
6764 | ||
716d51ab GN |
6765 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
6766 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
6767 | ||
64d60670 | 6768 | static void kvm_smm_changed(struct kvm_vcpu *vcpu) |
a584539b | 6769 | { |
64d60670 | 6770 | if (!(vcpu->arch.hflags & HF_SMM_MASK)) { |
660a5d51 PB |
6771 | /* This is a good place to trace that we are exiting SMM. */ |
6772 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); | |
6773 | ||
c43203ca PB |
6774 | /* Process a latched INIT or SMI, if any. */ |
6775 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
64d60670 | 6776 | } |
699023e2 PB |
6777 | |
6778 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
6779 | } |
6780 | ||
4a1e10d5 PB |
6781 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
6782 | unsigned long *db) | |
6783 | { | |
6784 | u32 dr6 = 0; | |
6785 | int i; | |
6786 | u32 enable, rwlen; | |
6787 | ||
6788 | enable = dr7; | |
6789 | rwlen = dr7 >> 16; | |
6790 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
6791 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
6792 | dr6 |= (1 << i); | |
6793 | return dr6; | |
6794 | } | |
6795 | ||
120c2c4f | 6796 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
6797 | { |
6798 | struct kvm_run *kvm_run = vcpu->run; | |
6799 | ||
c8401dda PB |
6800 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
6801 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; | |
d5d260c5 | 6802 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
6803 | kvm_run->debug.arch.exception = DB_VECTOR; |
6804 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 6805 | return 0; |
663f4c61 | 6806 | } |
120c2c4f | 6807 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 6808 | return 1; |
663f4c61 PB |
6809 | } |
6810 | ||
6affcbed KH |
6811 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
6812 | { | |
afaf0b2f | 6813 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
f8ea7c60 | 6814 | int r; |
6affcbed | 6815 | |
afaf0b2f | 6816 | r = kvm_x86_ops.skip_emulated_instruction(vcpu); |
60fc3d02 | 6817 | if (unlikely(!r)) |
f8ea7c60 | 6818 | return 0; |
c8401dda PB |
6819 | |
6820 | /* | |
6821 | * rflags is the old, "raw" value of the flags. The new value has | |
6822 | * not been saved yet. | |
6823 | * | |
6824 | * This is correct even for TF set by the guest, because "the | |
6825 | * processor will not generate this exception after the instruction | |
6826 | * that sets the TF flag". | |
6827 | */ | |
6828 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 6829 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 6830 | return r; |
6affcbed KH |
6831 | } |
6832 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
6833 | ||
4a1e10d5 PB |
6834 | static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) |
6835 | { | |
4a1e10d5 PB |
6836 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
6837 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
6838 | struct kvm_run *kvm_run = vcpu->run; |
6839 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
6840 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6841 | vcpu->arch.guest_debug_dr7, |
6842 | vcpu->arch.eff_db); | |
6843 | ||
6844 | if (dr6 != 0) { | |
6f43ed01 | 6845 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; |
82b32774 | 6846 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
6847 | kvm_run->debug.arch.exception = DB_VECTOR; |
6848 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 6849 | *r = 0; |
4a1e10d5 PB |
6850 | return true; |
6851 | } | |
6852 | } | |
6853 | ||
4161a569 NA |
6854 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
6855 | !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { | |
82b32774 NA |
6856 | unsigned long eip = kvm_get_linear_rip(vcpu); |
6857 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
6858 | vcpu->arch.dr7, |
6859 | vcpu->arch.db); | |
6860 | ||
6861 | if (dr6 != 0) { | |
4d5523cf | 6862 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 6863 | *r = 1; |
4a1e10d5 PB |
6864 | return true; |
6865 | } | |
6866 | } | |
6867 | ||
6868 | return false; | |
6869 | } | |
6870 | ||
04789b66 LA |
6871 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
6872 | { | |
2d7921c4 AM |
6873 | switch (ctxt->opcode_len) { |
6874 | case 1: | |
6875 | switch (ctxt->b) { | |
6876 | case 0xe4: /* IN */ | |
6877 | case 0xe5: | |
6878 | case 0xec: | |
6879 | case 0xed: | |
6880 | case 0xe6: /* OUT */ | |
6881 | case 0xe7: | |
6882 | case 0xee: | |
6883 | case 0xef: | |
6884 | case 0x6c: /* INS */ | |
6885 | case 0x6d: | |
6886 | case 0x6e: /* OUTS */ | |
6887 | case 0x6f: | |
6888 | return true; | |
6889 | } | |
6890 | break; | |
6891 | case 2: | |
6892 | switch (ctxt->b) { | |
6893 | case 0x33: /* RDPMC */ | |
6894 | return true; | |
6895 | } | |
6896 | break; | |
04789b66 LA |
6897 | } |
6898 | ||
6899 | return false; | |
6900 | } | |
6901 | ||
736c291c SC |
6902 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
6903 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 6904 | { |
95cb2295 | 6905 | int r; |
c9b8b07c | 6906 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 6907 | bool writeback = true; |
93c05d3e | 6908 | bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
bbd9b64e | 6909 | |
c595ceee PB |
6910 | vcpu->arch.l1tf_flush_l1d = true; |
6911 | ||
93c05d3e XG |
6912 | /* |
6913 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
6914 | * never reused. | |
6915 | */ | |
6916 | vcpu->arch.write_fault_to_shadow_pgtable = false; | |
26eef70c | 6917 | kvm_clear_exception_queue(vcpu); |
8d7d8102 | 6918 | |
571008da | 6919 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
8ec4722d | 6920 | init_emulate_ctxt(vcpu); |
4a1e10d5 PB |
6921 | |
6922 | /* | |
6923 | * We will reenter on the same instruction since | |
6924 | * we do not set complete_userspace_io. This does not | |
6925 | * handle watchpoints yet, those would be handled in | |
6926 | * the emulate_ops. | |
6927 | */ | |
d391f120 VK |
6928 | if (!(emulation_type & EMULTYPE_SKIP) && |
6929 | kvm_vcpu_check_breakpoint(vcpu, &r)) | |
4a1e10d5 PB |
6930 | return r; |
6931 | ||
9d74191a TY |
6932 | ctxt->interruptibility = 0; |
6933 | ctxt->have_exception = false; | |
e0ad0b47 | 6934 | ctxt->exception.vector = -1; |
9d74191a | 6935 | ctxt->perm_ok = false; |
bbd9b64e | 6936 | |
b51e974f | 6937 | ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; |
4005996e | 6938 | |
9d74191a | 6939 | r = x86_decode_insn(ctxt, insn, insn_len); |
bbd9b64e | 6940 | |
e46479f8 | 6941 | trace_kvm_emulate_insn_start(vcpu); |
f2b5756b | 6942 | ++vcpu->stat.insn_emulation; |
1d2887e2 | 6943 | if (r != EMULATION_OK) { |
b4000606 | 6944 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
6945 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
6946 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 6947 | return 1; |
c83fad65 | 6948 | } |
736c291c SC |
6949 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
6950 | write_fault_to_spt, | |
6951 | emulation_type)) | |
60fc3d02 | 6952 | return 1; |
8530a79c | 6953 | if (ctxt->have_exception) { |
c8848cee JD |
6954 | /* |
6955 | * #UD should result in just EMULATION_FAILED, and trap-like | |
6956 | * exception should not be encountered during decode. | |
6957 | */ | |
6958 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
6959 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 6960 | inject_emulated_exception(vcpu); |
60fc3d02 | 6961 | return 1; |
8530a79c | 6962 | } |
e2366171 | 6963 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
6964 | } |
6965 | } | |
6966 | ||
42cbf068 SC |
6967 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
6968 | !is_vmware_backdoor_opcode(ctxt)) { | |
6969 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 6970 | return 1; |
42cbf068 | 6971 | } |
04789b66 | 6972 | |
1957aa63 SC |
6973 | /* |
6974 | * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks | |
6975 | * for kvm_skip_emulated_instruction(). The caller is responsible for | |
6976 | * updating interruptibility state and injecting single-step #DBs. | |
6977 | */ | |
ba8afb6b | 6978 | if (emulation_type & EMULTYPE_SKIP) { |
9dac77fa | 6979 | kvm_rip_write(vcpu, ctxt->_eip); |
bb663c7a NA |
6980 | if (ctxt->eflags & X86_EFLAGS_RF) |
6981 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 6982 | return 1; |
ba8afb6b GN |
6983 | } |
6984 | ||
736c291c | 6985 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 6986 | return 1; |
1cb3f3ae | 6987 | |
7ae441ea | 6988 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 6989 | changes registers values during IO operation */ |
7ae441ea GN |
6990 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
6991 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 6992 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 6993 | } |
4d2179e1 | 6994 | |
5cd21917 | 6995 | restart: |
92daa48b SC |
6996 | if (emulation_type & EMULTYPE_PF) { |
6997 | /* Save the faulting GPA (cr2) in the address field */ | |
6998 | ctxt->exception.address = cr2_or_gpa; | |
6999 | ||
7000 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
7001 | if (vcpu->arch.mmu->direct_map) { | |
744e699c SC |
7002 | ctxt->gpa_available = true; |
7003 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
7004 | } |
7005 | } else { | |
7006 | /* Sanitize the address out of an abundance of paranoia. */ | |
7007 | ctxt->exception.address = 0; | |
7008 | } | |
0f89b207 | 7009 | |
9d74191a | 7010 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 7011 | |
775fde86 | 7012 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 7013 | return 1; |
775fde86 | 7014 | |
d2ddd1c4 | 7015 | if (r == EMULATION_FAILED) { |
736c291c | 7016 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 7017 | emulation_type)) |
60fc3d02 | 7018 | return 1; |
c3cd7ffa | 7019 | |
e2366171 | 7020 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
7021 | } |
7022 | ||
9d74191a | 7023 | if (ctxt->have_exception) { |
60fc3d02 | 7024 | r = 1; |
ef54bcfe PB |
7025 | if (inject_emulated_exception(vcpu)) |
7026 | return r; | |
d2ddd1c4 | 7027 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
7028 | if (!vcpu->arch.pio.in) { |
7029 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 7030 | vcpu->arch.pio.count = 0; |
0912c977 | 7031 | } else { |
7ae441ea | 7032 | writeback = false; |
716d51ab GN |
7033 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
7034 | } | |
60fc3d02 | 7035 | r = 0; |
7ae441ea | 7036 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
7037 | ++vcpu->stat.mmio_exits; |
7038 | ||
7ae441ea GN |
7039 | if (!vcpu->mmio_is_write) |
7040 | writeback = false; | |
60fc3d02 | 7041 | r = 0; |
716d51ab | 7042 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
7ae441ea | 7043 | } else if (r == EMULATION_RESTART) |
5cd21917 | 7044 | goto restart; |
d2ddd1c4 | 7045 | else |
60fc3d02 | 7046 | r = 1; |
f850e2e6 | 7047 | |
7ae441ea | 7048 | if (writeback) { |
afaf0b2f | 7049 | unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); |
9d74191a | 7050 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 7051 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
38827dbd | 7052 | if (!ctxt->have_exception || |
75ee23b3 SC |
7053 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
7054 | kvm_rip_write(vcpu, ctxt->eip); | |
384dea1c | 7055 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 7056 | r = kvm_vcpu_do_singlestep(vcpu); |
afaf0b2f SC |
7057 | if (kvm_x86_ops.update_emulated_instruction) |
7058 | kvm_x86_ops.update_emulated_instruction(vcpu); | |
38827dbd | 7059 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 7060 | } |
6addfc42 PB |
7061 | |
7062 | /* | |
7063 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
7064 | * do nothing, and it will be requested again as soon as | |
7065 | * the shadow expires. But we still need to check here, | |
7066 | * because POPF has no interrupt shadow. | |
7067 | */ | |
7068 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
7069 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
7070 | } else |
7071 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
7072 | |
7073 | return r; | |
de7d789a | 7074 | } |
c60658d1 SC |
7075 | |
7076 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
7077 | { | |
7078 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
7079 | } | |
7080 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
7081 | ||
7082 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
7083 | void *insn, int insn_len) | |
7084 | { | |
7085 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
7086 | } | |
7087 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 7088 | |
8764ed55 SC |
7089 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
7090 | { | |
7091 | vcpu->arch.pio.count = 0; | |
7092 | return 1; | |
7093 | } | |
7094 | ||
45def77e SC |
7095 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
7096 | { | |
7097 | vcpu->arch.pio.count = 0; | |
7098 | ||
7099 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
7100 | return 1; | |
7101 | ||
7102 | return kvm_skip_emulated_instruction(vcpu); | |
7103 | } | |
7104 | ||
dca7f128 SC |
7105 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
7106 | unsigned short port) | |
de7d789a | 7107 | { |
de3cd117 | 7108 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
7109 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
7110 | ||
8764ed55 SC |
7111 | if (ret) |
7112 | return ret; | |
45def77e | 7113 | |
8764ed55 SC |
7114 | /* |
7115 | * Workaround userspace that relies on old KVM behavior of %rip being | |
7116 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
7117 | */ | |
7118 | if (port == 0x7e && | |
7119 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
7120 | vcpu->arch.complete_userspace_io = | |
7121 | complete_fast_pio_out_port_0x7e; | |
7122 | kvm_skip_emulated_instruction(vcpu); | |
7123 | } else { | |
45def77e SC |
7124 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
7125 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
7126 | } | |
8764ed55 | 7127 | return 0; |
de7d789a | 7128 | } |
de7d789a | 7129 | |
8370c3d0 TL |
7130 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
7131 | { | |
7132 | unsigned long val; | |
7133 | ||
7134 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
7135 | BUG_ON(vcpu->arch.pio.count != 1); | |
7136 | ||
45def77e SC |
7137 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
7138 | vcpu->arch.pio.count = 0; | |
7139 | return 1; | |
7140 | } | |
7141 | ||
8370c3d0 | 7142 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 7143 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 TL |
7144 | |
7145 | /* | |
2e3bb4d8 | 7146 | * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform |
8370c3d0 TL |
7147 | * the copy and tracing |
7148 | */ | |
2e3bb4d8 | 7149 | emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); |
de3cd117 | 7150 | kvm_rax_write(vcpu, val); |
8370c3d0 | 7151 | |
45def77e | 7152 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
7153 | } |
7154 | ||
dca7f128 SC |
7155 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
7156 | unsigned short port) | |
8370c3d0 TL |
7157 | { |
7158 | unsigned long val; | |
7159 | int ret; | |
7160 | ||
7161 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 7162 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 7163 | |
2e3bb4d8 | 7164 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 7165 | if (ret) { |
de3cd117 | 7166 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
7167 | return ret; |
7168 | } | |
7169 | ||
45def77e | 7170 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
7171 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
7172 | ||
7173 | return 0; | |
7174 | } | |
dca7f128 SC |
7175 | |
7176 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
7177 | { | |
45def77e | 7178 | int ret; |
dca7f128 | 7179 | |
dca7f128 | 7180 | if (in) |
45def77e | 7181 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 7182 | else |
45def77e SC |
7183 | ret = kvm_fast_pio_out(vcpu, size, port); |
7184 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
7185 | } |
7186 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 7187 | |
251a5fd6 | 7188 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 7189 | { |
0a3aee0d | 7190 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 7191 | return 0; |
8cfdc000 ZA |
7192 | } |
7193 | ||
7194 | static void tsc_khz_changed(void *data) | |
c8076604 | 7195 | { |
8cfdc000 ZA |
7196 | struct cpufreq_freqs *freq = data; |
7197 | unsigned long khz = 0; | |
7198 | ||
7199 | if (data) | |
7200 | khz = freq->new; | |
7201 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
7202 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
7203 | if (!khz) | |
7204 | khz = tsc_khz; | |
0a3aee0d | 7205 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
7206 | } |
7207 | ||
5fa4ec9c | 7208 | #ifdef CONFIG_X86_64 |
0092e434 VK |
7209 | static void kvm_hyperv_tsc_notifier(void) |
7210 | { | |
0092e434 VK |
7211 | struct kvm *kvm; |
7212 | struct kvm_vcpu *vcpu; | |
7213 | int cpu; | |
7214 | ||
0d9ce162 | 7215 | mutex_lock(&kvm_lock); |
0092e434 VK |
7216 | list_for_each_entry(kvm, &vm_list, vm_list) |
7217 | kvm_make_mclock_inprogress_request(kvm); | |
7218 | ||
7219 | hyperv_stop_tsc_emulation(); | |
7220 | ||
7221 | /* TSC frequency always matches when on Hyper-V */ | |
7222 | for_each_present_cpu(cpu) | |
7223 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
7224 | kvm_max_guest_tsc_khz = tsc_khz; | |
7225 | ||
7226 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
7227 | struct kvm_arch *ka = &kvm->arch; | |
7228 | ||
7229 | spin_lock(&ka->pvclock_gtod_sync_lock); | |
7230 | ||
7231 | pvclock_update_vm_gtod_copy(kvm); | |
7232 | ||
7233 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7234 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
7235 | ||
7236 | kvm_for_each_vcpu(cpu, vcpu, kvm) | |
7237 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); | |
7238 | ||
7239 | spin_unlock(&ka->pvclock_gtod_sync_lock); | |
7240 | } | |
0d9ce162 | 7241 | mutex_unlock(&kvm_lock); |
0092e434 | 7242 | } |
5fa4ec9c | 7243 | #endif |
0092e434 | 7244 | |
df24014a | 7245 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 7246 | { |
c8076604 GH |
7247 | struct kvm *kvm; |
7248 | struct kvm_vcpu *vcpu; | |
7249 | int i, send_ipi = 0; | |
7250 | ||
8cfdc000 ZA |
7251 | /* |
7252 | * We allow guests to temporarily run on slowing clocks, | |
7253 | * provided we notify them after, or to run on accelerating | |
7254 | * clocks, provided we notify them before. Thus time never | |
7255 | * goes backwards. | |
7256 | * | |
7257 | * However, we have a problem. We can't atomically update | |
7258 | * the frequency of a given CPU from this function; it is | |
7259 | * merely a notifier, which can be called from any CPU. | |
7260 | * Changing the TSC frequency at arbitrary points in time | |
7261 | * requires a recomputation of local variables related to | |
7262 | * the TSC for each VCPU. We must flag these local variables | |
7263 | * to be updated and be sure the update takes place with the | |
7264 | * new frequency before any guests proceed. | |
7265 | * | |
7266 | * Unfortunately, the combination of hotplug CPU and frequency | |
7267 | * change creates an intractable locking scenario; the order | |
7268 | * of when these callouts happen is undefined with respect to | |
7269 | * CPU hotplug, and they can race with each other. As such, | |
7270 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
7271 | * undefined; you can actually have a CPU frequency change take | |
7272 | * place in between the computation of X and the setting of the | |
7273 | * variable. To protect against this problem, all updates of | |
7274 | * the per_cpu tsc_khz variable are done in an interrupt | |
7275 | * protected IPI, and all callers wishing to update the value | |
7276 | * must wait for a synchronous IPI to complete (which is trivial | |
7277 | * if the caller is on the CPU already). This establishes the | |
7278 | * necessary total order on variable updates. | |
7279 | * | |
7280 | * Note that because a guest time update may take place | |
7281 | * anytime after the setting of the VCPU's request bit, the | |
7282 | * correct TSC value must be set before the request. However, | |
7283 | * to ensure the update actually makes it to any guest which | |
7284 | * starts running in hardware virtualization between the set | |
7285 | * and the acquisition of the spinlock, we must also ping the | |
7286 | * CPU after setting the request bit. | |
7287 | * | |
7288 | */ | |
7289 | ||
df24014a | 7290 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7291 | |
0d9ce162 | 7292 | mutex_lock(&kvm_lock); |
c8076604 | 7293 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 7294 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 7295 | if (vcpu->cpu != cpu) |
c8076604 | 7296 | continue; |
c285545f | 7297 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 7298 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 7299 | send_ipi = 1; |
c8076604 GH |
7300 | } |
7301 | } | |
0d9ce162 | 7302 | mutex_unlock(&kvm_lock); |
c8076604 GH |
7303 | |
7304 | if (freq->old < freq->new && send_ipi) { | |
7305 | /* | |
7306 | * We upscale the frequency. Must make the guest | |
7307 | * doesn't see old kvmclock values while running with | |
7308 | * the new frequency, otherwise we risk the guest sees | |
7309 | * time go backwards. | |
7310 | * | |
7311 | * In case we update the frequency for another cpu | |
7312 | * (which might be in guest context) send an interrupt | |
7313 | * to kick the cpu out of guest context. Next time | |
7314 | * guest context is entered kvmclock will be updated, | |
7315 | * so the guest will not see stale values. | |
7316 | */ | |
df24014a | 7317 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 7318 | } |
df24014a VK |
7319 | } |
7320 | ||
7321 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
7322 | void *data) | |
7323 | { | |
7324 | struct cpufreq_freqs *freq = data; | |
7325 | int cpu; | |
7326 | ||
7327 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
7328 | return 0; | |
7329 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
7330 | return 0; | |
7331 | ||
7332 | for_each_cpu(cpu, freq->policy->cpus) | |
7333 | __kvmclock_cpufreq_notifier(freq, cpu); | |
7334 | ||
c8076604 GH |
7335 | return 0; |
7336 | } | |
7337 | ||
7338 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
7339 | .notifier_call = kvmclock_cpufreq_notifier |
7340 | }; | |
7341 | ||
251a5fd6 | 7342 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 7343 | { |
251a5fd6 SAS |
7344 | tsc_khz_changed(NULL); |
7345 | return 0; | |
8cfdc000 ZA |
7346 | } |
7347 | ||
b820cc0c ZA |
7348 | static void kvm_timer_init(void) |
7349 | { | |
c285545f | 7350 | max_tsc_khz = tsc_khz; |
460dd42e | 7351 | |
b820cc0c | 7352 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
c285545f | 7353 | #ifdef CONFIG_CPU_FREQ |
aaec7c03 | 7354 | struct cpufreq_policy *policy; |
758f588d BP |
7355 | int cpu; |
7356 | ||
3e26f230 | 7357 | cpu = get_cpu(); |
aaec7c03 | 7358 | policy = cpufreq_cpu_get(cpu); |
9a11997e WL |
7359 | if (policy) { |
7360 | if (policy->cpuinfo.max_freq) | |
7361 | max_tsc_khz = policy->cpuinfo.max_freq; | |
7362 | cpufreq_cpu_put(policy); | |
7363 | } | |
3e26f230 | 7364 | put_cpu(); |
c285545f | 7365 | #endif |
b820cc0c ZA |
7366 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
7367 | CPUFREQ_TRANSITION_NOTIFIER); | |
7368 | } | |
460dd42e | 7369 | |
73c1b41e | 7370 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 7371 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
7372 | } |
7373 | ||
dd60d217 AK |
7374 | DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); |
7375 | EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); | |
ff9d07a0 | 7376 | |
f5132b01 | 7377 | int kvm_is_in_guest(void) |
ff9d07a0 | 7378 | { |
086c9855 | 7379 | return __this_cpu_read(current_vcpu) != NULL; |
ff9d07a0 ZY |
7380 | } |
7381 | ||
7382 | static int kvm_is_user_mode(void) | |
7383 | { | |
7384 | int user_mode = 3; | |
dcf46b94 | 7385 | |
086c9855 | 7386 | if (__this_cpu_read(current_vcpu)) |
afaf0b2f | 7387 | user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); |
dcf46b94 | 7388 | |
ff9d07a0 ZY |
7389 | return user_mode != 0; |
7390 | } | |
7391 | ||
7392 | static unsigned long kvm_get_guest_ip(void) | |
7393 | { | |
7394 | unsigned long ip = 0; | |
dcf46b94 | 7395 | |
086c9855 AS |
7396 | if (__this_cpu_read(current_vcpu)) |
7397 | ip = kvm_rip_read(__this_cpu_read(current_vcpu)); | |
dcf46b94 | 7398 | |
ff9d07a0 ZY |
7399 | return ip; |
7400 | } | |
7401 | ||
8479e04e LK |
7402 | static void kvm_handle_intel_pt_intr(void) |
7403 | { | |
7404 | struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); | |
7405 | ||
7406 | kvm_make_request(KVM_REQ_PMI, vcpu); | |
7407 | __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, | |
7408 | (unsigned long *)&vcpu->arch.pmu.global_status); | |
7409 | } | |
7410 | ||
ff9d07a0 ZY |
7411 | static struct perf_guest_info_callbacks kvm_guest_cbs = { |
7412 | .is_in_guest = kvm_is_in_guest, | |
7413 | .is_user_mode = kvm_is_user_mode, | |
7414 | .get_guest_ip = kvm_get_guest_ip, | |
8479e04e | 7415 | .handle_intel_pt_intr = kvm_handle_intel_pt_intr, |
ff9d07a0 ZY |
7416 | }; |
7417 | ||
16e8d74d MT |
7418 | #ifdef CONFIG_X86_64 |
7419 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
7420 | { | |
d828199e MT |
7421 | struct kvm *kvm; |
7422 | ||
7423 | struct kvm_vcpu *vcpu; | |
7424 | int i; | |
7425 | ||
0d9ce162 | 7426 | mutex_lock(&kvm_lock); |
d828199e MT |
7427 | list_for_each_entry(kvm, &vm_list, vm_list) |
7428 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 7429 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 7430 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 7431 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
7432 | } |
7433 | ||
7434 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
7435 | ||
7436 | /* | |
7437 | * Notification about pvclock gtod data update. | |
7438 | */ | |
7439 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
7440 | void *priv) | |
7441 | { | |
7442 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
7443 | struct timekeeper *tk = priv; | |
7444 | ||
7445 | update_pvclock_gtod(tk); | |
7446 | ||
7447 | /* disable master clock if host does not trust, or does not | |
b0c39dc6 | 7448 | * use, TSC based clocksource. |
16e8d74d | 7449 | */ |
b0c39dc6 | 7450 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d MT |
7451 | atomic_read(&kvm_guest_has_master_clock) != 0) |
7452 | queue_work(system_long_wq, &pvclock_gtod_work); | |
7453 | ||
7454 | return 0; | |
7455 | } | |
7456 | ||
7457 | static struct notifier_block pvclock_gtod_notifier = { | |
7458 | .notifier_call = pvclock_gtod_notify, | |
7459 | }; | |
7460 | #endif | |
7461 | ||
f8c16bba | 7462 | int kvm_arch_init(void *opaque) |
043405e1 | 7463 | { |
d008dfdb | 7464 | struct kvm_x86_init_ops *ops = opaque; |
b820cc0c | 7465 | int r; |
f8c16bba | 7466 | |
afaf0b2f | 7467 | if (kvm_x86_ops.hardware_enable) { |
f8c16bba | 7468 | printk(KERN_ERR "kvm: already loaded the other module\n"); |
56c6d28a ZX |
7469 | r = -EEXIST; |
7470 | goto out; | |
f8c16bba ZX |
7471 | } |
7472 | ||
7473 | if (!ops->cpu_has_kvm_support()) { | |
ef935c25 | 7474 | pr_err_ratelimited("kvm: no hardware support\n"); |
56c6d28a ZX |
7475 | r = -EOPNOTSUPP; |
7476 | goto out; | |
f8c16bba ZX |
7477 | } |
7478 | if (ops->disabled_by_bios()) { | |
ef935c25 | 7479 | pr_err_ratelimited("kvm: disabled by bios\n"); |
56c6d28a ZX |
7480 | r = -EOPNOTSUPP; |
7481 | goto out; | |
f8c16bba ZX |
7482 | } |
7483 | ||
b666a4b6 MO |
7484 | /* |
7485 | * KVM explicitly assumes that the guest has an FPU and | |
7486 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
7487 | * vCPU's FPU state as a fxregs_state struct. | |
7488 | */ | |
7489 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
7490 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
7491 | r = -EOPNOTSUPP; | |
7492 | goto out; | |
7493 | } | |
7494 | ||
013f6a5d | 7495 | r = -ENOMEM; |
ed8e4812 | 7496 | x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), |
b666a4b6 MO |
7497 | __alignof__(struct fpu), SLAB_ACCOUNT, |
7498 | NULL); | |
7499 | if (!x86_fpu_cache) { | |
7500 | printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); | |
7501 | goto out; | |
7502 | } | |
7503 | ||
c9b8b07c SC |
7504 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
7505 | if (!x86_emulator_cache) { | |
7506 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
7507 | goto out_free_x86_fpu_cache; | |
7508 | } | |
7509 | ||
013f6a5d MT |
7510 | shared_msrs = alloc_percpu(struct kvm_shared_msrs); |
7511 | if (!shared_msrs) { | |
7512 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); | |
c9b8b07c | 7513 | goto out_free_x86_emulator_cache; |
013f6a5d MT |
7514 | } |
7515 | ||
97db56ce AK |
7516 | r = kvm_mmu_module_init(); |
7517 | if (r) | |
013f6a5d | 7518 | goto out_free_percpu; |
97db56ce | 7519 | |
7b52345e | 7520 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, |
ffb128c8 | 7521 | PT_DIRTY_MASK, PT64_NX_MASK, 0, |
d0ec49d4 | 7522 | PT_PRESENT_MASK, 0, sme_me_mask); |
b820cc0c | 7523 | kvm_timer_init(); |
c8076604 | 7524 | |
ff9d07a0 ZY |
7525 | perf_register_guest_info_callbacks(&kvm_guest_cbs); |
7526 | ||
cfc48181 | 7527 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 7528 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
cfc48181 SC |
7529 | supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
7530 | } | |
2acf923e | 7531 | |
c5cc421b | 7532 | kvm_lapic_init(); |
0c5f81da WL |
7533 | if (pi_inject_timer == -1) |
7534 | pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); | |
16e8d74d MT |
7535 | #ifdef CONFIG_X86_64 |
7536 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 7537 | |
5fa4ec9c | 7538 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 7539 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
7540 | #endif |
7541 | ||
f8c16bba | 7542 | return 0; |
56c6d28a | 7543 | |
013f6a5d MT |
7544 | out_free_percpu: |
7545 | free_percpu(shared_msrs); | |
c9b8b07c SC |
7546 | out_free_x86_emulator_cache: |
7547 | kmem_cache_destroy(x86_emulator_cache); | |
b666a4b6 MO |
7548 | out_free_x86_fpu_cache: |
7549 | kmem_cache_destroy(x86_fpu_cache); | |
56c6d28a | 7550 | out: |
56c6d28a | 7551 | return r; |
043405e1 | 7552 | } |
8776e519 | 7553 | |
f8c16bba ZX |
7554 | void kvm_arch_exit(void) |
7555 | { | |
0092e434 | 7556 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 7557 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
7558 | clear_hv_tscchange_cb(); |
7559 | #endif | |
cef84c30 | 7560 | kvm_lapic_exit(); |
ff9d07a0 ZY |
7561 | perf_unregister_guest_info_callbacks(&kvm_guest_cbs); |
7562 | ||
888d256e JK |
7563 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
7564 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
7565 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 7566 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
7567 | #ifdef CONFIG_X86_64 |
7568 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
7569 | #endif | |
afaf0b2f | 7570 | kvm_x86_ops.hardware_enable = NULL; |
56c6d28a | 7571 | kvm_mmu_module_exit(); |
013f6a5d | 7572 | free_percpu(shared_msrs); |
b666a4b6 | 7573 | kmem_cache_destroy(x86_fpu_cache); |
56c6d28a | 7574 | } |
f8c16bba | 7575 | |
5cb56059 | 7576 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu) |
8776e519 HB |
7577 | { |
7578 | ++vcpu->stat.halt_exits; | |
35754c98 | 7579 | if (lapic_in_kernel(vcpu)) { |
a4535290 | 7580 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
7581 | return 1; |
7582 | } else { | |
7583 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
7584 | return 0; | |
7585 | } | |
7586 | } | |
5cb56059 JS |
7587 | EXPORT_SYMBOL_GPL(kvm_vcpu_halt); |
7588 | ||
7589 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
7590 | { | |
6affcbed KH |
7591 | int ret = kvm_skip_emulated_instruction(vcpu); |
7592 | /* | |
7593 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
7594 | * KVM_EXIT_DEBUG here. | |
7595 | */ | |
7596 | return kvm_vcpu_halt(vcpu) && ret; | |
5cb56059 | 7597 | } |
8776e519 HB |
7598 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
7599 | ||
8ef81a9a | 7600 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7601 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
7602 | unsigned long clock_type) | |
7603 | { | |
7604 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 7605 | struct timespec64 ts; |
80fbd89c | 7606 | u64 cycle; |
55dd00a7 MT |
7607 | int ret; |
7608 | ||
7609 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
7610 | return -KVM_EOPNOTSUPP; | |
7611 | ||
7612 | if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) | |
7613 | return -KVM_EOPNOTSUPP; | |
7614 | ||
7615 | clock_pairing.sec = ts.tv_sec; | |
7616 | clock_pairing.nsec = ts.tv_nsec; | |
7617 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
7618 | clock_pairing.flags = 0; | |
bcbfbd8e | 7619 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
7620 | |
7621 | ret = 0; | |
7622 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
7623 | sizeof(struct kvm_clock_pairing))) | |
7624 | ret = -KVM_EFAULT; | |
7625 | ||
7626 | return ret; | |
7627 | } | |
8ef81a9a | 7628 | #endif |
55dd00a7 | 7629 | |
6aef266c SV |
7630 | /* |
7631 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
7632 | * | |
7633 | * @apicid - apicid of vcpu to be kicked. | |
7634 | */ | |
7635 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) | |
7636 | { | |
24d2166b | 7637 | struct kvm_lapic_irq lapic_irq; |
6aef266c | 7638 | |
150a84fe | 7639 | lapic_irq.shorthand = APIC_DEST_NOSHORT; |
c96001c5 | 7640 | lapic_irq.dest_mode = APIC_DEST_PHYSICAL; |
ebd28fcb | 7641 | lapic_irq.level = 0; |
24d2166b | 7642 | lapic_irq.dest_id = apicid; |
93bbf0b8 | 7643 | lapic_irq.msi_redir_hint = false; |
6aef266c | 7644 | |
24d2166b | 7645 | lapic_irq.delivery_mode = APIC_DM_REMRD; |
795a149e | 7646 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
7647 | } |
7648 | ||
4e19c36f SS |
7649 | bool kvm_apicv_activated(struct kvm *kvm) |
7650 | { | |
7651 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
7652 | } | |
7653 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
7654 | ||
7655 | void kvm_apicv_init(struct kvm *kvm, bool enable) | |
7656 | { | |
7657 | if (enable) | |
7658 | clear_bit(APICV_INHIBIT_REASON_DISABLE, | |
7659 | &kvm->arch.apicv_inhibit_reasons); | |
7660 | else | |
7661 | set_bit(APICV_INHIBIT_REASON_DISABLE, | |
7662 | &kvm->arch.apicv_inhibit_reasons); | |
7663 | } | |
7664 | EXPORT_SYMBOL_GPL(kvm_apicv_init); | |
7665 | ||
71506297 WL |
7666 | static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) |
7667 | { | |
7668 | struct kvm_vcpu *target = NULL; | |
7669 | struct kvm_apic_map *map; | |
7670 | ||
7671 | rcu_read_lock(); | |
7672 | map = rcu_dereference(kvm->arch.apic_map); | |
7673 | ||
7674 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
7675 | target = map->phys_map[dest_id]->vcpu; | |
7676 | ||
7677 | rcu_read_unlock(); | |
7678 | ||
266e85a5 | 7679 | if (target && READ_ONCE(target->ready)) |
71506297 WL |
7680 | kvm_vcpu_yield_to(target); |
7681 | } | |
7682 | ||
8776e519 HB |
7683 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
7684 | { | |
7685 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 7686 | int op_64_bit; |
8776e519 | 7687 | |
696ca779 RK |
7688 | if (kvm_hv_hypercall_enabled(vcpu->kvm)) |
7689 | return kvm_hv_hypercall(vcpu); | |
55cd8e5a | 7690 | |
de3cd117 SC |
7691 | nr = kvm_rax_read(vcpu); |
7692 | a0 = kvm_rbx_read(vcpu); | |
7693 | a1 = kvm_rcx_read(vcpu); | |
7694 | a2 = kvm_rdx_read(vcpu); | |
7695 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 7696 | |
229456fc | 7697 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 7698 | |
a449c7aa NA |
7699 | op_64_bit = is_64_bit_mode(vcpu); |
7700 | if (!op_64_bit) { | |
8776e519 HB |
7701 | nr &= 0xFFFFFFFF; |
7702 | a0 &= 0xFFFFFFFF; | |
7703 | a1 &= 0xFFFFFFFF; | |
7704 | a2 &= 0xFFFFFFFF; | |
7705 | a3 &= 0xFFFFFFFF; | |
7706 | } | |
7707 | ||
afaf0b2f | 7708 | if (kvm_x86_ops.get_cpl(vcpu) != 0) { |
07708c4a | 7709 | ret = -KVM_EPERM; |
696ca779 | 7710 | goto out; |
07708c4a JK |
7711 | } |
7712 | ||
8776e519 | 7713 | switch (nr) { |
b93463aa AK |
7714 | case KVM_HC_VAPIC_POLL_IRQ: |
7715 | ret = 0; | |
7716 | break; | |
6aef266c SV |
7717 | case KVM_HC_KICK_CPU: |
7718 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | |
266e85a5 | 7719 | kvm_sched_yield(vcpu->kvm, a1); |
6aef266c SV |
7720 | ret = 0; |
7721 | break; | |
8ef81a9a | 7722 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
7723 | case KVM_HC_CLOCK_PAIRING: |
7724 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
7725 | break; | |
1ed199a4 | 7726 | #endif |
4180bf1b WL |
7727 | case KVM_HC_SEND_IPI: |
7728 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); | |
7729 | break; | |
71506297 WL |
7730 | case KVM_HC_SCHED_YIELD: |
7731 | kvm_sched_yield(vcpu->kvm, a0); | |
7732 | ret = 0; | |
7733 | break; | |
8776e519 HB |
7734 | default: |
7735 | ret = -KVM_ENOSYS; | |
7736 | break; | |
7737 | } | |
696ca779 | 7738 | out: |
a449c7aa NA |
7739 | if (!op_64_bit) |
7740 | ret = (u32)ret; | |
de3cd117 | 7741 | kvm_rax_write(vcpu, ret); |
6356ee0c | 7742 | |
f11c3a8d | 7743 | ++vcpu->stat.hypercalls; |
6356ee0c | 7744 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
7745 | } |
7746 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
7747 | ||
b6785def | 7748 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 7749 | { |
d6aa1000 | 7750 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 7751 | char instruction[3]; |
5fdbf976 | 7752 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 7753 | |
afaf0b2f | 7754 | kvm_x86_ops.patch_hypercall(vcpu, instruction); |
8776e519 | 7755 | |
ce2e852e DV |
7756 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
7757 | &ctxt->exception); | |
8776e519 HB |
7758 | } |
7759 | ||
851ba692 | 7760 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7761 | { |
782d422b MG |
7762 | return vcpu->run->request_interrupt_window && |
7763 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
7764 | } |
7765 | ||
851ba692 | 7766 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 7767 | { |
851ba692 AK |
7768 | struct kvm_run *kvm_run = vcpu->run; |
7769 | ||
91586a3b | 7770 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
f077825a | 7771 | kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; |
2d3ad1f4 | 7772 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 7773 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
127a457a MG |
7774 | kvm_run->ready_for_interrupt_injection = |
7775 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 7776 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
b6c7a5dc HB |
7777 | } |
7778 | ||
95ba8273 GN |
7779 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
7780 | { | |
7781 | int max_irr, tpr; | |
7782 | ||
afaf0b2f | 7783 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
7784 | return; |
7785 | ||
bce87cce | 7786 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
7787 | return; |
7788 | ||
d62caabb AS |
7789 | if (vcpu->arch.apicv_active) |
7790 | return; | |
7791 | ||
8db3baa2 GN |
7792 | if (!vcpu->arch.apic->vapic_addr) |
7793 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
7794 | else | |
7795 | max_irr = -1; | |
95ba8273 GN |
7796 | |
7797 | if (max_irr != -1) | |
7798 | max_irr >>= 4; | |
7799 | ||
7800 | tpr = kvm_lapic_get_cr8(vcpu); | |
7801 | ||
afaf0b2f | 7802 | kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); |
95ba8273 GN |
7803 | } |
7804 | ||
c9d40913 | 7805 | static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 7806 | { |
b6b8a145 | 7807 | int r; |
c6b22f59 | 7808 | bool can_inject = true; |
b6b8a145 | 7809 | |
95ba8273 | 7810 | /* try to reinject previous events if any */ |
664f8e26 | 7811 | |
c6b22f59 | 7812 | if (vcpu->arch.exception.injected) { |
afaf0b2f | 7813 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 PB |
7814 | can_inject = false; |
7815 | } | |
664f8e26 | 7816 | /* |
a042c26f LA |
7817 | * Do not inject an NMI or interrupt if there is a pending |
7818 | * exception. Exceptions and interrupts are recognized at | |
7819 | * instruction boundaries, i.e. the start of an instruction. | |
7820 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
7821 | * NMIs and interrupts, i.e. traps are recognized before an | |
7822 | * NMI/interrupt that's pending on the same instruction. | |
7823 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
7824 | * priority, but are only generated (pended) during instruction | |
7825 | * execution, i.e. a pending fault-like exception means the | |
7826 | * fault occurred on the *previous* instruction and must be | |
7827 | * serviced prior to recognizing any new events in order to | |
7828 | * fully complete the previous instruction. | |
664f8e26 | 7829 | */ |
1a680e35 | 7830 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 7831 | if (vcpu->arch.nmi_injected) { |
afaf0b2f | 7832 | kvm_x86_ops.set_nmi(vcpu); |
c6b22f59 PB |
7833 | can_inject = false; |
7834 | } else if (vcpu->arch.interrupt.injected) { | |
afaf0b2f | 7835 | kvm_x86_ops.set_irq(vcpu); |
c6b22f59 PB |
7836 | can_inject = false; |
7837 | } | |
664f8e26 WL |
7838 | } |
7839 | ||
3b82b8d7 SC |
7840 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
7841 | vcpu->arch.exception.pending); | |
7842 | ||
1a680e35 LA |
7843 | /* |
7844 | * Call check_nested_events() even if we reinjected a previous event | |
7845 | * in order for caller to determine if it should require immediate-exit | |
7846 | * from L2 to L1 due to pending L1 events which require exit | |
7847 | * from L2 to L1. | |
7848 | */ | |
56083bdf | 7849 | if (is_guest_mode(vcpu)) { |
33b22172 | 7850 | r = kvm_x86_ops.nested_ops->check_events(vcpu); |
c9d40913 PB |
7851 | if (r < 0) |
7852 | goto busy; | |
664f8e26 WL |
7853 | } |
7854 | ||
7855 | /* try to inject new event if pending */ | |
b59bb7bd | 7856 | if (vcpu->arch.exception.pending) { |
5c1c85d0 AK |
7857 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
7858 | vcpu->arch.exception.has_error_code, | |
7859 | vcpu->arch.exception.error_code); | |
d6e8c854 | 7860 | |
664f8e26 WL |
7861 | vcpu->arch.exception.pending = false; |
7862 | vcpu->arch.exception.injected = true; | |
7863 | ||
d6e8c854 NA |
7864 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
7865 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
7866 | X86_EFLAGS_RF); | |
7867 | ||
f10c729f | 7868 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
7869 | kvm_deliver_exception_payload(vcpu); |
7870 | if (vcpu->arch.dr7 & DR7_GD) { | |
7871 | vcpu->arch.dr7 &= ~DR7_GD; | |
7872 | kvm_update_dr7(vcpu); | |
7873 | } | |
6bdf0662 NA |
7874 | } |
7875 | ||
afaf0b2f | 7876 | kvm_x86_ops.queue_exception(vcpu); |
c6b22f59 | 7877 | can_inject = false; |
1a680e35 LA |
7878 | } |
7879 | ||
c9d40913 PB |
7880 | /* |
7881 | * Finally, inject interrupt events. If an event cannot be injected | |
7882 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
7883 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
7884 | * and can architecturally be injected, but we cannot do it right now: | |
7885 | * an interrupt could have arrived just now and we have to inject it | |
7886 | * as a vmexit, or there could already an event in the queue, which is | |
7887 | * indicated by can_inject. In that case we request an immediate exit | |
7888 | * in order to make progress and get back here for another iteration. | |
7889 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
7890 | */ | |
7891 | if (vcpu->arch.smi_pending) { | |
7892 | r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; | |
7893 | if (r < 0) | |
7894 | goto busy; | |
7895 | if (r) { | |
7896 | vcpu->arch.smi_pending = false; | |
7897 | ++vcpu->arch.smi_count; | |
7898 | enter_smm(vcpu); | |
7899 | can_inject = false; | |
7900 | } else | |
7901 | kvm_x86_ops.enable_smi_window(vcpu); | |
7902 | } | |
7903 | ||
7904 | if (vcpu->arch.nmi_pending) { | |
7905 | r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; | |
7906 | if (r < 0) | |
7907 | goto busy; | |
7908 | if (r) { | |
7909 | --vcpu->arch.nmi_pending; | |
7910 | vcpu->arch.nmi_injected = true; | |
7911 | kvm_x86_ops.set_nmi(vcpu); | |
7912 | can_inject = false; | |
7913 | WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); | |
7914 | } | |
7915 | if (vcpu->arch.nmi_pending) | |
7916 | kvm_x86_ops.enable_nmi_window(vcpu); | |
7917 | } | |
1a680e35 | 7918 | |
c9d40913 PB |
7919 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
7920 | r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; | |
7921 | if (r < 0) | |
7922 | goto busy; | |
7923 | if (r) { | |
7924 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
7925 | kvm_x86_ops.set_irq(vcpu); | |
7926 | WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); | |
7927 | } | |
7928 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
7929 | kvm_x86_ops.enable_irq_window(vcpu); | |
95ba8273 | 7930 | } |
ee2cd4b7 | 7931 | |
c9d40913 PB |
7932 | if (is_guest_mode(vcpu) && |
7933 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
7934 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
7935 | *req_immediate_exit = true; | |
7936 | ||
7937 | WARN_ON(vcpu->arch.exception.pending); | |
7938 | return; | |
7939 | ||
7940 | busy: | |
7941 | *req_immediate_exit = true; | |
7942 | return; | |
95ba8273 GN |
7943 | } |
7944 | ||
7460fb4a AK |
7945 | static void process_nmi(struct kvm_vcpu *vcpu) |
7946 | { | |
7947 | unsigned limit = 2; | |
7948 | ||
7949 | /* | |
7950 | * x86 is limited to one NMI running, and one NMI pending after it. | |
7951 | * If an NMI is already in progress, limit further NMIs to just one. | |
7952 | * Otherwise, allow two (and we'll inject the first one immediately). | |
7953 | */ | |
afaf0b2f | 7954 | if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
7955 | limit = 1; |
7956 | ||
7957 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
7958 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
7959 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7960 | } | |
7961 | ||
ee2cd4b7 | 7962 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
7963 | { |
7964 | u32 flags = 0; | |
7965 | flags |= seg->g << 23; | |
7966 | flags |= seg->db << 22; | |
7967 | flags |= seg->l << 21; | |
7968 | flags |= seg->avl << 20; | |
7969 | flags |= seg->present << 15; | |
7970 | flags |= seg->dpl << 13; | |
7971 | flags |= seg->s << 12; | |
7972 | flags |= seg->type << 8; | |
7973 | return flags; | |
7974 | } | |
7975 | ||
ee2cd4b7 | 7976 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7977 | { |
7978 | struct kvm_segment seg; | |
7979 | int offset; | |
7980 | ||
7981 | kvm_get_segment(vcpu, &seg, n); | |
7982 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
7983 | ||
7984 | if (n < 3) | |
7985 | offset = 0x7f84 + n * 12; | |
7986 | else | |
7987 | offset = 0x7f2c + (n - 3) * 12; | |
7988 | ||
7989 | put_smstate(u32, buf, offset + 8, seg.base); | |
7990 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 7991 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
7992 | } |
7993 | ||
efbb288a | 7994 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 7995 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
7996 | { |
7997 | struct kvm_segment seg; | |
7998 | int offset; | |
7999 | u16 flags; | |
8000 | ||
8001 | kvm_get_segment(vcpu, &seg, n); | |
8002 | offset = 0x7e00 + n * 16; | |
8003 | ||
ee2cd4b7 | 8004 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
8005 | put_smstate(u16, buf, offset, seg.selector); |
8006 | put_smstate(u16, buf, offset + 2, flags); | |
8007 | put_smstate(u32, buf, offset + 4, seg.limit); | |
8008 | put_smstate(u64, buf, offset + 8, seg.base); | |
8009 | } | |
efbb288a | 8010 | #endif |
660a5d51 | 8011 | |
ee2cd4b7 | 8012 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
8013 | { |
8014 | struct desc_ptr dt; | |
8015 | struct kvm_segment seg; | |
8016 | unsigned long val; | |
8017 | int i; | |
8018 | ||
8019 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
8020 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
8021 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
8022 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
8023 | ||
8024 | for (i = 0; i < 8; i++) | |
8025 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); | |
8026 | ||
8027 | kvm_get_dr(vcpu, 6, &val); | |
8028 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
8029 | kvm_get_dr(vcpu, 7, &val); | |
8030 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
8031 | ||
8032 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8033 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
8034 | put_smstate(u32, buf, 0x7f64, seg.base); | |
8035 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 8036 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
8037 | |
8038 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8039 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
8040 | put_smstate(u32, buf, 0x7f80, seg.base); | |
8041 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 8042 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 8043 | |
afaf0b2f | 8044 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8045 | put_smstate(u32, buf, 0x7f74, dt.address); |
8046 | put_smstate(u32, buf, 0x7f70, dt.size); | |
8047 | ||
afaf0b2f | 8048 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8049 | put_smstate(u32, buf, 0x7f58, dt.address); |
8050 | put_smstate(u32, buf, 0x7f54, dt.size); | |
8051 | ||
8052 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8053 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
8054 | |
8055 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
8056 | ||
8057 | /* revision id */ | |
8058 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
8059 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
8060 | } | |
8061 | ||
b68f3cc7 | 8062 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 8063 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 8064 | { |
660a5d51 PB |
8065 | struct desc_ptr dt; |
8066 | struct kvm_segment seg; | |
8067 | unsigned long val; | |
8068 | int i; | |
8069 | ||
8070 | for (i = 0; i < 16; i++) | |
8071 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); | |
8072 | ||
8073 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
8074 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
8075 | ||
8076 | kvm_get_dr(vcpu, 6, &val); | |
8077 | put_smstate(u64, buf, 0x7f68, val); | |
8078 | kvm_get_dr(vcpu, 7, &val); | |
8079 | put_smstate(u64, buf, 0x7f60, val); | |
8080 | ||
8081 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
8082 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
8083 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
8084 | ||
8085 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
8086 | ||
8087 | /* revision id */ | |
8088 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
8089 | ||
8090 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
8091 | ||
8092 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
8093 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 8094 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8095 | put_smstate(u32, buf, 0x7e94, seg.limit); |
8096 | put_smstate(u64, buf, 0x7e98, seg.base); | |
8097 | ||
afaf0b2f | 8098 | kvm_x86_ops.get_idt(vcpu, &dt); |
660a5d51 PB |
8099 | put_smstate(u32, buf, 0x7e84, dt.size); |
8100 | put_smstate(u64, buf, 0x7e88, dt.address); | |
8101 | ||
8102 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
8103 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 8104 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
8105 | put_smstate(u32, buf, 0x7e74, seg.limit); |
8106 | put_smstate(u64, buf, 0x7e78, seg.base); | |
8107 | ||
afaf0b2f | 8108 | kvm_x86_ops.get_gdt(vcpu, &dt); |
660a5d51 PB |
8109 | put_smstate(u32, buf, 0x7e64, dt.size); |
8110 | put_smstate(u64, buf, 0x7e68, dt.address); | |
8111 | ||
8112 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 8113 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 8114 | } |
b68f3cc7 | 8115 | #endif |
660a5d51 | 8116 | |
ee2cd4b7 | 8117 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 8118 | { |
660a5d51 | 8119 | struct kvm_segment cs, ds; |
18c3626e | 8120 | struct desc_ptr dt; |
660a5d51 PB |
8121 | char buf[512]; |
8122 | u32 cr0; | |
8123 | ||
660a5d51 | 8124 | trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); |
660a5d51 | 8125 | memset(buf, 0, 512); |
b68f3cc7 | 8126 | #ifdef CONFIG_X86_64 |
d6321d49 | 8127 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 8128 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 8129 | else |
b68f3cc7 | 8130 | #endif |
ee2cd4b7 | 8131 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 8132 | |
0234bf88 LP |
8133 | /* |
8134 | * Give pre_enter_smm() a chance to make ISA-specific changes to the | |
8135 | * vCPU state (e.g. leave guest mode) after we've saved the state into | |
8136 | * the SMM state-save area. | |
8137 | */ | |
afaf0b2f | 8138 | kvm_x86_ops.pre_enter_smm(vcpu, buf); |
0234bf88 LP |
8139 | |
8140 | vcpu->arch.hflags |= HF_SMM_MASK; | |
54bf36aa | 8141 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 8142 | |
afaf0b2f | 8143 | if (kvm_x86_ops.get_nmi_mask(vcpu)) |
660a5d51 PB |
8144 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
8145 | else | |
afaf0b2f | 8146 | kvm_x86_ops.set_nmi_mask(vcpu, true); |
660a5d51 PB |
8147 | |
8148 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
8149 | kvm_rip_write(vcpu, 0x8000); | |
8150 | ||
8151 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
afaf0b2f | 8152 | kvm_x86_ops.set_cr0(vcpu, cr0); |
660a5d51 PB |
8153 | vcpu->arch.cr0 = cr0; |
8154 | ||
afaf0b2f | 8155 | kvm_x86_ops.set_cr4(vcpu, 0); |
660a5d51 | 8156 | |
18c3626e PB |
8157 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
8158 | dt.address = dt.size = 0; | |
afaf0b2f | 8159 | kvm_x86_ops.set_idt(vcpu, &dt); |
18c3626e | 8160 | |
660a5d51 PB |
8161 | __kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
8162 | ||
8163 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
8164 | cs.base = vcpu->arch.smbase; | |
8165 | ||
8166 | ds.selector = 0; | |
8167 | ds.base = 0; | |
8168 | ||
8169 | cs.limit = ds.limit = 0xffffffff; | |
8170 | cs.type = ds.type = 0x3; | |
8171 | cs.dpl = ds.dpl = 0; | |
8172 | cs.db = ds.db = 0; | |
8173 | cs.s = ds.s = 1; | |
8174 | cs.l = ds.l = 0; | |
8175 | cs.g = ds.g = 1; | |
8176 | cs.avl = ds.avl = 0; | |
8177 | cs.present = ds.present = 1; | |
8178 | cs.unusable = ds.unusable = 0; | |
8179 | cs.padding = ds.padding = 0; | |
8180 | ||
8181 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
8182 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
8183 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
8184 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
8185 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
8186 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
8187 | ||
b68f3cc7 | 8188 | #ifdef CONFIG_X86_64 |
d6321d49 | 8189 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
afaf0b2f | 8190 | kvm_x86_ops.set_efer(vcpu, 0); |
b68f3cc7 | 8191 | #endif |
660a5d51 | 8192 | |
aedbaf4f | 8193 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 8194 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
8195 | } |
8196 | ||
ee2cd4b7 | 8197 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
8198 | { |
8199 | vcpu->arch.smi_pending = true; | |
8200 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8201 | } | |
8202 | ||
7ee30bc1 NNL |
8203 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
8204 | unsigned long *vcpu_bitmap) | |
8205 | { | |
8206 | cpumask_var_t cpus; | |
7ee30bc1 NNL |
8207 | |
8208 | zalloc_cpumask_var(&cpus, GFP_ATOMIC); | |
8209 | ||
db5a95ec | 8210 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, |
54163a34 | 8211 | NULL, vcpu_bitmap, cpus); |
7ee30bc1 NNL |
8212 | |
8213 | free_cpumask_var(cpus); | |
8214 | } | |
8215 | ||
2860c4b1 PB |
8216 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
8217 | { | |
8218 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
8219 | } | |
8220 | ||
8df14af4 SS |
8221 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
8222 | { | |
8223 | if (!lapic_in_kernel(vcpu)) | |
8224 | return; | |
8225 | ||
8226 | vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); | |
8227 | kvm_apic_update_apicv(vcpu); | |
afaf0b2f | 8228 | kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); |
8df14af4 SS |
8229 | } |
8230 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
8231 | ||
8232 | /* | |
8233 | * NOTE: Do not hold any lock prior to calling this. | |
8234 | * | |
8235 | * In particular, kvm_request_apicv_update() expects kvm->srcu not to be | |
8236 | * locked, because it calls __x86_set_memory_region() which does | |
8237 | * synchronize_srcu(&kvm->srcu). | |
8238 | */ | |
8239 | void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) | |
8240 | { | |
7d611233 | 8241 | struct kvm_vcpu *except; |
8e205a6b PB |
8242 | unsigned long old, new, expected; |
8243 | ||
afaf0b2f SC |
8244 | if (!kvm_x86_ops.check_apicv_inhibit_reasons || |
8245 | !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) | |
ef8efd7a SS |
8246 | return; |
8247 | ||
8e205a6b PB |
8248 | old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); |
8249 | do { | |
8250 | expected = new = old; | |
8251 | if (activate) | |
8252 | __clear_bit(bit, &new); | |
8253 | else | |
8254 | __set_bit(bit, &new); | |
8255 | if (new == old) | |
8256 | break; | |
8257 | old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); | |
8258 | } while (old != expected); | |
8259 | ||
8260 | if (!!old == !!new) | |
8261 | return; | |
8df14af4 | 8262 | |
24bbf74c | 8263 | trace_kvm_apicv_update_request(activate, bit); |
afaf0b2f SC |
8264 | if (kvm_x86_ops.pre_update_apicv_exec_ctrl) |
8265 | kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); | |
7d611233 SS |
8266 | |
8267 | /* | |
8268 | * Sending request to update APICV for all other vcpus, | |
8269 | * while update the calling vcpu immediately instead of | |
8270 | * waiting for another #VMEXIT to handle the request. | |
8271 | */ | |
8272 | except = kvm_get_running_vcpu(); | |
8273 | kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, | |
8274 | except); | |
8275 | if (except) | |
8276 | kvm_vcpu_update_apicv(except); | |
8df14af4 SS |
8277 | } |
8278 | EXPORT_SYMBOL_GPL(kvm_request_apicv_update); | |
8279 | ||
3d81bc7e | 8280 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 8281 | { |
dcbd3e49 | 8282 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 8283 | return; |
c7c9c56c | 8284 | |
6308630b | 8285 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 8286 | |
b053b2ae | 8287 | if (irqchip_split(vcpu->kvm)) |
6308630b | 8288 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 8289 | else { |
fa59cc00 | 8290 | if (vcpu->arch.apicv_active) |
afaf0b2f | 8291 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
e97f852f WL |
8292 | if (ioapic_in_kernel(vcpu->kvm)) |
8293 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 8294 | } |
e40ff1d6 LA |
8295 | |
8296 | if (is_guest_mode(vcpu)) | |
8297 | vcpu->arch.load_eoi_exitmap_pending = true; | |
8298 | else | |
8299 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
8300 | } | |
8301 | ||
8302 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
8303 | { | |
8304 | u64 eoi_exit_bitmap[4]; | |
8305 | ||
8306 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
8307 | return; | |
8308 | ||
5c919412 AS |
8309 | bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, |
8310 | vcpu_to_synic(vcpu)->vec_bitmap, 256); | |
afaf0b2f | 8311 | kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); |
c7c9c56c YZ |
8312 | } |
8313 | ||
e649b3f0 ET |
8314 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
8315 | unsigned long start, unsigned long end) | |
b1394e74 RK |
8316 | { |
8317 | unsigned long apic_address; | |
8318 | ||
8319 | /* | |
8320 | * The physical address of apic access page is stored in the VMCS. | |
8321 | * Update it when it becomes invalid. | |
8322 | */ | |
8323 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
8324 | if (start <= apic_address && apic_address < end) | |
8325 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
8326 | } | |
8327 | ||
4256f43f TC |
8328 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
8329 | { | |
35754c98 | 8330 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
8331 | return; |
8332 | ||
afaf0b2f | 8333 | if (!kvm_x86_ops.set_apic_access_page_addr) |
4256f43f TC |
8334 | return; |
8335 | ||
a4148b7c | 8336 | kvm_x86_ops.set_apic_access_page_addr(vcpu); |
4256f43f | 8337 | } |
4256f43f | 8338 | |
d264ee0c SC |
8339 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
8340 | { | |
8341 | smp_send_reschedule(vcpu->cpu); | |
8342 | } | |
8343 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
8344 | ||
9357d939 | 8345 | /* |
362c698f | 8346 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
8347 | * exiting to the userspace. Otherwise, the value will be returned to the |
8348 | * userspace. | |
8349 | */ | |
851ba692 | 8350 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
8351 | { |
8352 | int r; | |
62a193ed MG |
8353 | bool req_int_win = |
8354 | dm_request_for_irq_injection(vcpu) && | |
8355 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 8356 | fastpath_t exit_fastpath; |
62a193ed | 8357 | |
730dca42 | 8358 | bool req_immediate_exit = false; |
b6c7a5dc | 8359 | |
2fa6e1e1 | 8360 | if (kvm_request_pending(vcpu)) { |
671ddc70 | 8361 | if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) { |
33b22172 | 8362 | if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) { |
671ddc70 JM |
8363 | r = 0; |
8364 | goto out; | |
8365 | } | |
8366 | } | |
a8eeb04a | 8367 | if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) |
2e53d63a | 8368 | kvm_mmu_unload(vcpu); |
a8eeb04a | 8369 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 8370 | __kvm_migrate_timers(vcpu); |
d828199e MT |
8371 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
8372 | kvm_gen_update_masterclock(vcpu->kvm); | |
0061d53d MT |
8373 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
8374 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
8375 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
8376 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
8377 | if (unlikely(r)) |
8378 | goto out; | |
8379 | } | |
a8eeb04a | 8380 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 8381 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
8382 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
8383 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 8384 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 8385 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
8386 | |
8387 | /* Flushing all ASIDs flushes the current ASID... */ | |
8388 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
8389 | } | |
8390 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
8391 | kvm_vcpu_flush_tlb_current(vcpu); | |
0baedd79 VK |
8392 | if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) |
8393 | kvm_vcpu_flush_tlb_guest(vcpu); | |
eeeb4f67 | 8394 | |
a8eeb04a | 8395 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 8396 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
8397 | r = 0; |
8398 | goto out; | |
8399 | } | |
a8eeb04a | 8400 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
851ba692 | 8401 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
bbeac283 | 8402 | vcpu->mmio_needed = 0; |
71c4dfaf JR |
8403 | r = 0; |
8404 | goto out; | |
8405 | } | |
af585b92 GN |
8406 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
8407 | /* Page is swapped out. Do synthetic halt */ | |
8408 | vcpu->arch.apf.halted = true; | |
8409 | r = 1; | |
8410 | goto out; | |
8411 | } | |
c9aaa895 GC |
8412 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
8413 | record_steal_time(vcpu); | |
64d60670 PB |
8414 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
8415 | process_smi(vcpu); | |
7460fb4a AK |
8416 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
8417 | process_nmi(vcpu); | |
f5132b01 | 8418 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 8419 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 8420 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 8421 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
8422 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
8423 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
8424 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 8425 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
8426 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
8427 | vcpu->run->eoi.vector = | |
8428 | vcpu->arch.pending_ioapic_eoi; | |
8429 | r = 0; | |
8430 | goto out; | |
8431 | } | |
8432 | } | |
3d81bc7e YZ |
8433 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
8434 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
8435 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
8436 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
8437 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
8438 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
8439 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
8440 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8441 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
8442 | r = 0; | |
8443 | goto out; | |
8444 | } | |
e516cebb AS |
8445 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
8446 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
8447 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
8448 | r = 0; | |
8449 | goto out; | |
8450 | } | |
db397571 AS |
8451 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
8452 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; | |
8453 | vcpu->run->hyperv = vcpu->arch.hyperv.exit; | |
8454 | r = 0; | |
8455 | goto out; | |
8456 | } | |
f3b138c5 AS |
8457 | |
8458 | /* | |
8459 | * KVM_REQ_HV_STIMER has to be processed after | |
8460 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
8461 | * depend on the guest clock being up-to-date | |
8462 | */ | |
1f4b34f8 AS |
8463 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
8464 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
8465 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
8466 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
8467 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
8468 | kvm_check_async_pf_completion(vcpu); | |
2f52d58c | 8469 | } |
b93463aa | 8470 | |
b463a6f7 | 8471 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { |
0f1e261e | 8472 | ++vcpu->stat.req_event; |
66450a21 JK |
8473 | kvm_apic_accept_events(vcpu); |
8474 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
8475 | r = 1; | |
8476 | goto out; | |
8477 | } | |
8478 | ||
c9d40913 PB |
8479 | inject_pending_event(vcpu, &req_immediate_exit); |
8480 | if (req_int_win) | |
8481 | kvm_x86_ops.enable_irq_window(vcpu); | |
b463a6f7 AK |
8482 | |
8483 | if (kvm_lapic_enabled(vcpu)) { | |
8484 | update_cr8_intercept(vcpu); | |
8485 | kvm_lapic_sync_to_vapic(vcpu); | |
8486 | } | |
8487 | } | |
8488 | ||
d8368af8 AK |
8489 | r = kvm_mmu_reload(vcpu); |
8490 | if (unlikely(r)) { | |
d905c069 | 8491 | goto cancel_injection; |
d8368af8 AK |
8492 | } |
8493 | ||
b6c7a5dc HB |
8494 | preempt_disable(); |
8495 | ||
afaf0b2f | 8496 | kvm_x86_ops.prepare_guest_switch(vcpu); |
b95234c8 PB |
8497 | |
8498 | /* | |
8499 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
8500 | * IPI are then delayed after guest entry, which ensures that they | |
8501 | * result in virtual interrupt delivery. | |
8502 | */ | |
8503 | local_irq_disable(); | |
6b7e2d09 XG |
8504 | vcpu->mode = IN_GUEST_MODE; |
8505 | ||
01b71917 MT |
8506 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
8507 | ||
0f127d12 | 8508 | /* |
b95234c8 | 8509 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 8510 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 8511 | * |
81b01667 | 8512 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
8513 | * pairs with the memory barrier implicit in pi_test_and_set_on |
8514 | * (see vmx_deliver_posted_interrupt). | |
8515 | * | |
8516 | * 3) This also orders the write to mode from any reads to the page | |
8517 | * tables done while the VCPU is running. Please see the comment | |
8518 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 8519 | */ |
01b71917 | 8520 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 8521 | |
b95234c8 PB |
8522 | /* |
8523 | * This handles the case where a posted interrupt was | |
8524 | * notified with kvm_vcpu_kick. | |
8525 | */ | |
fa59cc00 | 8526 | if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) |
afaf0b2f | 8527 | kvm_x86_ops.sync_pir_to_irr(vcpu); |
32f88400 | 8528 | |
5a9f5443 | 8529 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 8530 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8531 | smp_wmb(); |
6c142801 AK |
8532 | local_irq_enable(); |
8533 | preempt_enable(); | |
01b71917 | 8534 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
6c142801 | 8535 | r = 1; |
d905c069 | 8536 | goto cancel_injection; |
6c142801 AK |
8537 | } |
8538 | ||
c43203ca PB |
8539 | if (req_immediate_exit) { |
8540 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 8541 | kvm_x86_ops.request_immediate_exit(vcpu); |
c43203ca | 8542 | } |
d6185f20 | 8543 | |
8b89fe1f | 8544 | trace_kvm_entry(vcpu->vcpu_id); |
b6c7a5dc | 8545 | |
2620fe26 SC |
8546 | fpregs_assert_state_consistent(); |
8547 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8548 | switch_fpu_return(); | |
5f409e20 | 8549 | |
42dbaa5a | 8550 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
8551 | set_debugreg(0, 7); |
8552 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
8553 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
8554 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
8555 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
c77fb5fe | 8556 | set_debugreg(vcpu->arch.dr6, 6); |
ae561ede | 8557 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; |
42dbaa5a | 8558 | } |
b6c7a5dc | 8559 | |
a9ab13ff | 8560 | exit_fastpath = kvm_x86_ops.run(vcpu); |
b6c7a5dc | 8561 | |
c77fb5fe PB |
8562 | /* |
8563 | * Do this here before restoring debug registers on the host. And | |
8564 | * since we do this before handling the vmexit, a DR access vmexit | |
8565 | * can (a) read the correct value of the debug registers, (b) set | |
8566 | * KVM_DEBUGREG_WONT_EXIT again. | |
8567 | */ | |
8568 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 8569 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
afaf0b2f | 8570 | kvm_x86_ops.sync_dirty_debug_regs(vcpu); |
70e4da7a | 8571 | kvm_update_dr0123(vcpu); |
70e4da7a PB |
8572 | kvm_update_dr7(vcpu); |
8573 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; | |
c77fb5fe PB |
8574 | } |
8575 | ||
24f1e32c FW |
8576 | /* |
8577 | * If the guest has used debug registers, at least dr7 | |
8578 | * will be disabled while returning to the host. | |
8579 | * If we don't have active breakpoints in the host, we don't | |
8580 | * care about the messed up debug address registers. But if | |
8581 | * we have some of them active, restore the old state. | |
8582 | */ | |
59d8eb53 | 8583 | if (hw_breakpoint_active()) |
24f1e32c | 8584 | hw_breakpoint_restore(); |
42dbaa5a | 8585 | |
c967118d | 8586 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 8587 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 8588 | |
6b7e2d09 | 8589 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 8590 | smp_wmb(); |
a547c6db | 8591 | |
a9ab13ff | 8592 | kvm_x86_ops.handle_exit_irqoff(vcpu); |
b6c7a5dc | 8593 | |
d7a08882 SC |
8594 | /* |
8595 | * Consume any pending interrupts, including the possible source of | |
8596 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
8597 | * An instruction is required after local_irq_enable() to fully unblock | |
8598 | * interrupts on processors that implement an interrupt shadow, the | |
8599 | * stat.exits increment will do nicely. | |
8600 | */ | |
8601 | kvm_before_interrupt(vcpu); | |
8602 | local_irq_enable(); | |
b6c7a5dc | 8603 | ++vcpu->stat.exits; |
d7a08882 SC |
8604 | local_irq_disable(); |
8605 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 8606 | |
ec0671d5 WL |
8607 | if (lapic_in_kernel(vcpu)) { |
8608 | s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; | |
8609 | if (delta != S64_MIN) { | |
8610 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); | |
8611 | vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; | |
8612 | } | |
8613 | } | |
b6c7a5dc | 8614 | |
f2485b3e | 8615 | local_irq_enable(); |
b6c7a5dc HB |
8616 | preempt_enable(); |
8617 | ||
f656ce01 | 8618 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
3200f405 | 8619 | |
b6c7a5dc HB |
8620 | /* |
8621 | * Profile KVM exit RIPs: | |
8622 | */ | |
8623 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
8624 | unsigned long rip = kvm_rip_read(vcpu); |
8625 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
8626 | } |
8627 | ||
cc578287 ZA |
8628 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
8629 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 8630 | |
5cfb1d5a MT |
8631 | if (vcpu->arch.apic_attention) |
8632 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 8633 | |
afaf0b2f | 8634 | r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); |
d905c069 MT |
8635 | return r; |
8636 | ||
8637 | cancel_injection: | |
8081ad06 SC |
8638 | if (req_immediate_exit) |
8639 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
afaf0b2f | 8640 | kvm_x86_ops.cancel_injection(vcpu); |
ae7a2a3f MT |
8641 | if (unlikely(vcpu->arch.apic_attention)) |
8642 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
8643 | out: |
8644 | return r; | |
8645 | } | |
b6c7a5dc | 8646 | |
362c698f PB |
8647 | static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) |
8648 | { | |
bf9f6ac8 | 8649 | if (!kvm_arch_vcpu_runnable(vcpu) && |
afaf0b2f | 8650 | (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { |
9c8fd1ba PB |
8651 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
8652 | kvm_vcpu_block(vcpu); | |
8653 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); | |
bf9f6ac8 | 8654 | |
afaf0b2f SC |
8655 | if (kvm_x86_ops.post_block) |
8656 | kvm_x86_ops.post_block(vcpu); | |
bf9f6ac8 | 8657 | |
9c8fd1ba PB |
8658 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
8659 | return 1; | |
8660 | } | |
362c698f PB |
8661 | |
8662 | kvm_apic_accept_events(vcpu); | |
8663 | switch(vcpu->arch.mp_state) { | |
8664 | case KVM_MP_STATE_HALTED: | |
8665 | vcpu->arch.pv.pv_unhalted = false; | |
8666 | vcpu->arch.mp_state = | |
8667 | KVM_MP_STATE_RUNNABLE; | |
b2869f28 | 8668 | /* fall through */ |
362c698f PB |
8669 | case KVM_MP_STATE_RUNNABLE: |
8670 | vcpu->arch.apf.halted = false; | |
8671 | break; | |
8672 | case KVM_MP_STATE_INIT_RECEIVED: | |
8673 | break; | |
8674 | default: | |
8675 | return -EINTR; | |
362c698f PB |
8676 | } |
8677 | return 1; | |
8678 | } | |
09cec754 | 8679 | |
5d9bc648 PB |
8680 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
8681 | { | |
56083bdf | 8682 | if (is_guest_mode(vcpu)) |
33b22172 | 8683 | kvm_x86_ops.nested_ops->check_events(vcpu); |
0ad3bed6 | 8684 | |
5d9bc648 PB |
8685 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
8686 | !vcpu->arch.apf.halted); | |
8687 | } | |
8688 | ||
362c698f | 8689 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
8690 | { |
8691 | int r; | |
f656ce01 | 8692 | struct kvm *kvm = vcpu->kvm; |
d7690175 | 8693 | |
f656ce01 | 8694 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
c595ceee | 8695 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 8696 | |
362c698f | 8697 | for (;;) { |
58f800d5 | 8698 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 8699 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 8700 | } else { |
362c698f | 8701 | r = vcpu_block(kvm, vcpu); |
bf9f6ac8 FW |
8702 | } |
8703 | ||
09cec754 GN |
8704 | if (r <= 0) |
8705 | break; | |
8706 | ||
72875d8a | 8707 | kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); |
09cec754 GN |
8708 | if (kvm_cpu_has_pending_timer(vcpu)) |
8709 | kvm_inject_pending_timer_irqs(vcpu); | |
8710 | ||
782d422b MG |
8711 | if (dm_request_for_irq_injection(vcpu) && |
8712 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
8713 | r = 0; |
8714 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 8715 | ++vcpu->stat.request_irq_exits; |
362c698f | 8716 | break; |
09cec754 | 8717 | } |
af585b92 | 8718 | |
09cec754 GN |
8719 | if (signal_pending(current)) { |
8720 | r = -EINTR; | |
851ba692 | 8721 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 | 8722 | ++vcpu->stat.signal_exits; |
362c698f | 8723 | break; |
09cec754 GN |
8724 | } |
8725 | if (need_resched()) { | |
f656ce01 | 8726 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
c08ac06a | 8727 | cond_resched(); |
f656ce01 | 8728 | vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); |
d7690175 | 8729 | } |
b6c7a5dc HB |
8730 | } |
8731 | ||
f656ce01 | 8732 | srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); |
b6c7a5dc HB |
8733 | |
8734 | return r; | |
8735 | } | |
8736 | ||
716d51ab GN |
8737 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
8738 | { | |
8739 | int r; | |
60fc3d02 | 8740 | |
716d51ab | 8741 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); |
0ce97a2b | 8742 | r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab | 8743 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); |
60fc3d02 | 8744 | return r; |
716d51ab GN |
8745 | } |
8746 | ||
8747 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
8748 | { | |
8749 | BUG_ON(!vcpu->arch.pio.count); | |
8750 | ||
8751 | return complete_emulated_io(vcpu); | |
8752 | } | |
8753 | ||
f78146b0 AK |
8754 | /* |
8755 | * Implements the following, as a state machine: | |
8756 | * | |
8757 | * read: | |
8758 | * for each fragment | |
87da7e66 XG |
8759 | * for each mmio piece in the fragment |
8760 | * write gpa, len | |
8761 | * exit | |
8762 | * copy data | |
f78146b0 AK |
8763 | * execute insn |
8764 | * | |
8765 | * write: | |
8766 | * for each fragment | |
87da7e66 XG |
8767 | * for each mmio piece in the fragment |
8768 | * write gpa, len | |
8769 | * copy data | |
8770 | * exit | |
f78146b0 | 8771 | */ |
716d51ab | 8772 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
8773 | { |
8774 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 8775 | struct kvm_mmio_fragment *frag; |
87da7e66 | 8776 | unsigned len; |
5287f194 | 8777 | |
716d51ab | 8778 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 8779 | |
716d51ab | 8780 | /* Complete previous fragment */ |
87da7e66 XG |
8781 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
8782 | len = min(8u, frag->len); | |
716d51ab | 8783 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
8784 | memcpy(frag->data, run->mmio.data, len); |
8785 | ||
8786 | if (frag->len <= 8) { | |
8787 | /* Switch to the next fragment. */ | |
8788 | frag++; | |
8789 | vcpu->mmio_cur_fragment++; | |
8790 | } else { | |
8791 | /* Go forward to the next mmio piece. */ | |
8792 | frag->data += len; | |
8793 | frag->gpa += len; | |
8794 | frag->len -= len; | |
8795 | } | |
8796 | ||
a08d3b3b | 8797 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 8798 | vcpu->mmio_needed = 0; |
0912c977 PB |
8799 | |
8800 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 8801 | if (vcpu->mmio_is_write) |
716d51ab GN |
8802 | return 1; |
8803 | vcpu->mmio_read_completed = 1; | |
8804 | return complete_emulated_io(vcpu); | |
8805 | } | |
87da7e66 | 8806 | |
716d51ab GN |
8807 | run->exit_reason = KVM_EXIT_MMIO; |
8808 | run->mmio.phys_addr = frag->gpa; | |
8809 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
8810 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
8811 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
8812 | run->mmio.is_write = vcpu->mmio_is_write; |
8813 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
8814 | return 0; | |
5287f194 AK |
8815 | } |
8816 | ||
c9aef3b8 SC |
8817 | static void kvm_save_current_fpu(struct fpu *fpu) |
8818 | { | |
8819 | /* | |
8820 | * If the target FPU state is not resident in the CPU registers, just | |
8821 | * memcpy() from current, else save CPU state directly to the target. | |
8822 | */ | |
8823 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
8824 | memcpy(&fpu->state, ¤t->thread.fpu.state, | |
8825 | fpu_kernel_xstate_size); | |
8826 | else | |
8827 | copy_fpregs_to_fpstate(fpu); | |
8828 | } | |
8829 | ||
822f312d SAS |
8830 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
8831 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
8832 | { | |
5f409e20 RR |
8833 | fpregs_lock(); |
8834 | ||
c9aef3b8 SC |
8835 | kvm_save_current_fpu(vcpu->arch.user_fpu); |
8836 | ||
afaf0b2f | 8837 | /* PKRU is separately restored in kvm_x86_ops.run. */ |
b666a4b6 | 8838 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
822f312d | 8839 | ~XFEATURE_MASK_PKRU); |
5f409e20 RR |
8840 | |
8841 | fpregs_mark_activate(); | |
8842 | fpregs_unlock(); | |
8843 | ||
822f312d SAS |
8844 | trace_kvm_fpu(1); |
8845 | } | |
8846 | ||
8847 | /* When vcpu_run ends, restore user space FPU context. */ | |
8848 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
8849 | { | |
5f409e20 RR |
8850 | fpregs_lock(); |
8851 | ||
c9aef3b8 SC |
8852 | kvm_save_current_fpu(vcpu->arch.guest_fpu); |
8853 | ||
d9a710e5 | 8854 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
5f409e20 RR |
8855 | |
8856 | fpregs_mark_activate(); | |
8857 | fpregs_unlock(); | |
8858 | ||
822f312d SAS |
8859 | ++vcpu->stat.fpu_reload; |
8860 | trace_kvm_fpu(0); | |
8861 | } | |
8862 | ||
1b94f6f8 | 8863 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 8864 | { |
1b94f6f8 | 8865 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 8866 | int r; |
b6c7a5dc | 8867 | |
accb757d | 8868 | vcpu_load(vcpu); |
20b7035c | 8869 | kvm_sigset_activate(vcpu); |
5663d8f9 PX |
8870 | kvm_load_guest_fpu(vcpu); |
8871 | ||
a4535290 | 8872 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
8873 | if (kvm_run->immediate_exit) { |
8874 | r = -EINTR; | |
8875 | goto out; | |
8876 | } | |
b6c7a5dc | 8877 | kvm_vcpu_block(vcpu); |
66450a21 | 8878 | kvm_apic_accept_events(vcpu); |
72875d8a | 8879 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 8880 | r = -EAGAIN; |
a0595000 JS |
8881 | if (signal_pending(current)) { |
8882 | r = -EINTR; | |
1b94f6f8 | 8883 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
8884 | ++vcpu->stat.signal_exits; |
8885 | } | |
ac9f6dc0 | 8886 | goto out; |
b6c7a5dc HB |
8887 | } |
8888 | ||
1b94f6f8 | 8889 | if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { |
01643c51 KH |
8890 | r = -EINVAL; |
8891 | goto out; | |
8892 | } | |
8893 | ||
1b94f6f8 | 8894 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
8895 | r = sync_regs(vcpu); |
8896 | if (r != 0) | |
8897 | goto out; | |
8898 | } | |
8899 | ||
b6c7a5dc | 8900 | /* re-sync apic's tpr */ |
35754c98 | 8901 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
8902 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
8903 | r = -EINVAL; | |
8904 | goto out; | |
8905 | } | |
8906 | } | |
b6c7a5dc | 8907 | |
716d51ab GN |
8908 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
8909 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
8910 | vcpu->arch.complete_userspace_io = NULL; | |
8911 | r = cui(vcpu); | |
8912 | if (r <= 0) | |
5663d8f9 | 8913 | goto out; |
716d51ab GN |
8914 | } else |
8915 | WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); | |
5287f194 | 8916 | |
460df4c1 PB |
8917 | if (kvm_run->immediate_exit) |
8918 | r = -EINTR; | |
8919 | else | |
8920 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
8921 | |
8922 | out: | |
5663d8f9 | 8923 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 8924 | if (kvm_run->kvm_valid_regs) |
01643c51 | 8925 | store_regs(vcpu); |
f1d86e46 | 8926 | post_kvm_run_save(vcpu); |
20b7035c | 8927 | kvm_sigset_deactivate(vcpu); |
b6c7a5dc | 8928 | |
accb757d | 8929 | vcpu_put(vcpu); |
b6c7a5dc HB |
8930 | return r; |
8931 | } | |
8932 | ||
01643c51 | 8933 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8934 | { |
7ae441ea GN |
8935 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
8936 | /* | |
8937 | * We are here if userspace calls get_regs() in the middle of | |
8938 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 8939 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
8940 | * that usually, but some bad designed PV devices (vmware |
8941 | * backdoor interface) need this to work | |
8942 | */ | |
c9b8b07c | 8943 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
8944 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
8945 | } | |
de3cd117 SC |
8946 | regs->rax = kvm_rax_read(vcpu); |
8947 | regs->rbx = kvm_rbx_read(vcpu); | |
8948 | regs->rcx = kvm_rcx_read(vcpu); | |
8949 | regs->rdx = kvm_rdx_read(vcpu); | |
8950 | regs->rsi = kvm_rsi_read(vcpu); | |
8951 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 8952 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 8953 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 8954 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8955 | regs->r8 = kvm_r8_read(vcpu); |
8956 | regs->r9 = kvm_r9_read(vcpu); | |
8957 | regs->r10 = kvm_r10_read(vcpu); | |
8958 | regs->r11 = kvm_r11_read(vcpu); | |
8959 | regs->r12 = kvm_r12_read(vcpu); | |
8960 | regs->r13 = kvm_r13_read(vcpu); | |
8961 | regs->r14 = kvm_r14_read(vcpu); | |
8962 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
8963 | #endif |
8964 | ||
5fdbf976 | 8965 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 8966 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 8967 | } |
b6c7a5dc | 8968 | |
01643c51 KH |
8969 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
8970 | { | |
8971 | vcpu_load(vcpu); | |
8972 | __get_regs(vcpu, regs); | |
1fc9b76b | 8973 | vcpu_put(vcpu); |
b6c7a5dc HB |
8974 | return 0; |
8975 | } | |
8976 | ||
01643c51 | 8977 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 8978 | { |
7ae441ea GN |
8979 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
8980 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
8981 | ||
de3cd117 SC |
8982 | kvm_rax_write(vcpu, regs->rax); |
8983 | kvm_rbx_write(vcpu, regs->rbx); | |
8984 | kvm_rcx_write(vcpu, regs->rcx); | |
8985 | kvm_rdx_write(vcpu, regs->rdx); | |
8986 | kvm_rsi_write(vcpu, regs->rsi); | |
8987 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 8988 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 8989 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 8990 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
8991 | kvm_r8_write(vcpu, regs->r8); |
8992 | kvm_r9_write(vcpu, regs->r9); | |
8993 | kvm_r10_write(vcpu, regs->r10); | |
8994 | kvm_r11_write(vcpu, regs->r11); | |
8995 | kvm_r12_write(vcpu, regs->r12); | |
8996 | kvm_r13_write(vcpu, regs->r13); | |
8997 | kvm_r14_write(vcpu, regs->r14); | |
8998 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
8999 | #endif |
9000 | ||
5fdbf976 | 9001 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 9002 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 9003 | |
b4f14abd JK |
9004 | vcpu->arch.exception.pending = false; |
9005 | ||
3842d135 | 9006 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 9007 | } |
3842d135 | 9008 | |
01643c51 KH |
9009 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
9010 | { | |
9011 | vcpu_load(vcpu); | |
9012 | __set_regs(vcpu, regs); | |
875656fe | 9013 | vcpu_put(vcpu); |
b6c7a5dc HB |
9014 | return 0; |
9015 | } | |
9016 | ||
b6c7a5dc HB |
9017 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
9018 | { | |
9019 | struct kvm_segment cs; | |
9020 | ||
3e6e0aab | 9021 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
9022 | *db = cs.db; |
9023 | *l = cs.l; | |
9024 | } | |
9025 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
9026 | ||
01643c51 | 9027 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9028 | { |
89a27f4d | 9029 | struct desc_ptr dt; |
b6c7a5dc | 9030 | |
3e6e0aab GT |
9031 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9032 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9033 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9034 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9035 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9036 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9037 | |
3e6e0aab GT |
9038 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9039 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9040 | |
afaf0b2f | 9041 | kvm_x86_ops.get_idt(vcpu, &dt); |
89a27f4d GN |
9042 | sregs->idt.limit = dt.size; |
9043 | sregs->idt.base = dt.address; | |
afaf0b2f | 9044 | kvm_x86_ops.get_gdt(vcpu, &dt); |
89a27f4d GN |
9045 | sregs->gdt.limit = dt.size; |
9046 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 9047 | |
4d4ec087 | 9048 | sregs->cr0 = kvm_read_cr0(vcpu); |
ad312c7c | 9049 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 9050 | sregs->cr3 = kvm_read_cr3(vcpu); |
fc78f519 | 9051 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 9052 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 9053 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc HB |
9054 | sregs->apic_base = kvm_get_apic_base(vcpu); |
9055 | ||
0e96f31e | 9056 | memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); |
b6c7a5dc | 9057 | |
04140b41 | 9058 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
9059 | set_bit(vcpu->arch.interrupt.nr, |
9060 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 9061 | } |
16d7a191 | 9062 | |
01643c51 KH |
9063 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
9064 | struct kvm_sregs *sregs) | |
9065 | { | |
9066 | vcpu_load(vcpu); | |
9067 | __get_sregs(vcpu, sregs); | |
bcdec41c | 9068 | vcpu_put(vcpu); |
b6c7a5dc HB |
9069 | return 0; |
9070 | } | |
9071 | ||
62d9f0db MT |
9072 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
9073 | struct kvm_mp_state *mp_state) | |
9074 | { | |
fd232561 | 9075 | vcpu_load(vcpu); |
f958bd23 SC |
9076 | if (kvm_mpx_supported()) |
9077 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 9078 | |
66450a21 | 9079 | kvm_apic_accept_events(vcpu); |
6aef266c SV |
9080 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && |
9081 | vcpu->arch.pv.pv_unhalted) | |
9082 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; | |
9083 | else | |
9084 | mp_state->mp_state = vcpu->arch.mp_state; | |
9085 | ||
f958bd23 SC |
9086 | if (kvm_mpx_supported()) |
9087 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 9088 | vcpu_put(vcpu); |
62d9f0db MT |
9089 | return 0; |
9090 | } | |
9091 | ||
9092 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
9093 | struct kvm_mp_state *mp_state) | |
9094 | { | |
e83dff5e CD |
9095 | int ret = -EINVAL; |
9096 | ||
9097 | vcpu_load(vcpu); | |
9098 | ||
bce87cce | 9099 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 9100 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 9101 | goto out; |
66450a21 | 9102 | |
27cbe7d6 LA |
9103 | /* |
9104 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
9105 | * INIT state; latched init should be reported using | |
9106 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
9107 | */ | |
9108 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
9109 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
9110 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 9111 | goto out; |
28bf2888 | 9112 | |
66450a21 JK |
9113 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
9114 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
9115 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
9116 | } else | |
9117 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 9118 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
9119 | |
9120 | ret = 0; | |
9121 | out: | |
9122 | vcpu_put(vcpu); | |
9123 | return ret; | |
62d9f0db MT |
9124 | } |
9125 | ||
7f3d35fd KW |
9126 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
9127 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 9128 | { |
c9b8b07c | 9129 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 9130 | int ret; |
e01c2426 | 9131 | |
8ec4722d | 9132 | init_emulate_ctxt(vcpu); |
c697518a | 9133 | |
7f3d35fd | 9134 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 9135 | has_error_code, error_code); |
1051778f SC |
9136 | if (ret) { |
9137 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
9138 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
9139 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 9140 | return 0; |
1051778f | 9141 | } |
37817f29 | 9142 | |
9d74191a TY |
9143 | kvm_rip_write(vcpu, ctxt->eip); |
9144 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 9145 | return 1; |
37817f29 IE |
9146 | } |
9147 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
9148 | ||
3140c156 | 9149 | static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 9150 | { |
37b95951 | 9151 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
9152 | /* |
9153 | * When EFER.LME and CR0.PG are set, the processor is in | |
9154 | * 64-bit mode (though maybe in a 32-bit code segment). | |
9155 | * CR4.PAE and EFER.LMA must be set. | |
9156 | */ | |
37b95951 | 9157 | if (!(sregs->cr4 & X86_CR4_PAE) |
f2981033 LT |
9158 | || !(sregs->efer & EFER_LMA)) |
9159 | return -EINVAL; | |
9160 | } else { | |
9161 | /* | |
9162 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
9163 | * segment cannot be 64-bit. | |
9164 | */ | |
9165 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
9166 | return -EINVAL; | |
9167 | } | |
9168 | ||
3ca94192 | 9169 | return kvm_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
9170 | } |
9171 | ||
01643c51 | 9172 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 9173 | { |
58cb628d | 9174 | struct msr_data apic_base_msr; |
b6c7a5dc | 9175 | int mmu_reset_needed = 0; |
c4d21882 | 9176 | int cpuid_update_needed = 0; |
63f42e02 | 9177 | int pending_vec, max_bits, idx; |
89a27f4d | 9178 | struct desc_ptr dt; |
b4ef9d4e CD |
9179 | int ret = -EINVAL; |
9180 | ||
f2981033 | 9181 | if (kvm_valid_sregs(vcpu, sregs)) |
8dbfb2bf | 9182 | goto out; |
f2981033 | 9183 | |
d3802286 JM |
9184 | apic_base_msr.data = sregs->apic_base; |
9185 | apic_base_msr.host_initiated = true; | |
9186 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
b4ef9d4e | 9187 | goto out; |
6d1068b3 | 9188 | |
89a27f4d GN |
9189 | dt.size = sregs->idt.limit; |
9190 | dt.address = sregs->idt.base; | |
afaf0b2f | 9191 | kvm_x86_ops.set_idt(vcpu, &dt); |
89a27f4d GN |
9192 | dt.size = sregs->gdt.limit; |
9193 | dt.address = sregs->gdt.base; | |
afaf0b2f | 9194 | kvm_x86_ops.set_gdt(vcpu, &dt); |
b6c7a5dc | 9195 | |
ad312c7c | 9196 | vcpu->arch.cr2 = sregs->cr2; |
9f8fe504 | 9197 | mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 9198 | vcpu->arch.cr3 = sregs->cr3; |
cb3c1e2f | 9199 | kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); |
b6c7a5dc | 9200 | |
2d3ad1f4 | 9201 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 9202 | |
f6801dff | 9203 | mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
afaf0b2f | 9204 | kvm_x86_ops.set_efer(vcpu, sregs->efer); |
b6c7a5dc | 9205 | |
4d4ec087 | 9206 | mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
afaf0b2f | 9207 | kvm_x86_ops.set_cr0(vcpu, sregs->cr0); |
d7306163 | 9208 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 9209 | |
fc78f519 | 9210 | mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
c4d21882 WH |
9211 | cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & |
9212 | (X86_CR4_OSXSAVE | X86_CR4_PKE)); | |
afaf0b2f | 9213 | kvm_x86_ops.set_cr4(vcpu, sregs->cr4); |
c4d21882 | 9214 | if (cpuid_update_needed) |
aedbaf4f | 9215 | kvm_update_cpuid_runtime(vcpu); |
63f42e02 XG |
9216 | |
9217 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
bf03d4f9 | 9218 | if (is_pae_paging(vcpu)) { |
9f8fe504 | 9219 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); |
7c93be44 MT |
9220 | mmu_reset_needed = 1; |
9221 | } | |
63f42e02 | 9222 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b6c7a5dc HB |
9223 | |
9224 | if (mmu_reset_needed) | |
9225 | kvm_mmu_reset_context(vcpu); | |
9226 | ||
a50abc3b | 9227 | max_bits = KVM_NR_INTERRUPTS; |
923c61bb GN |
9228 | pending_vec = find_first_bit( |
9229 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
9230 | if (pending_vec < max_bits) { | |
66fd3f7f | 9231 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb | 9232 | pr_debug("Set back pending irq %d\n", pending_vec); |
b6c7a5dc HB |
9233 | } |
9234 | ||
3e6e0aab GT |
9235 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
9236 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
9237 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
9238 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
9239 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
9240 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 9241 | |
3e6e0aab GT |
9242 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
9243 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 9244 | |
5f0269f5 ME |
9245 | update_cr8_intercept(vcpu); |
9246 | ||
9c3e4aab | 9247 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 9248 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 9249 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 9250 | !is_protmode(vcpu)) |
9c3e4aab MT |
9251 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
9252 | ||
3842d135 AK |
9253 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
9254 | ||
b4ef9d4e CD |
9255 | ret = 0; |
9256 | out: | |
01643c51 KH |
9257 | return ret; |
9258 | } | |
9259 | ||
9260 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
9261 | struct kvm_sregs *sregs) | |
9262 | { | |
9263 | int ret; | |
9264 | ||
9265 | vcpu_load(vcpu); | |
9266 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
9267 | vcpu_put(vcpu); |
9268 | return ret; | |
b6c7a5dc HB |
9269 | } |
9270 | ||
d0bfb940 JK |
9271 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
9272 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 9273 | { |
355be0b9 | 9274 | unsigned long rflags; |
ae675ef0 | 9275 | int i, r; |
b6c7a5dc | 9276 | |
66b56562 CD |
9277 | vcpu_load(vcpu); |
9278 | ||
4f926bf2 JK |
9279 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
9280 | r = -EBUSY; | |
9281 | if (vcpu->arch.exception.pending) | |
2122ff5e | 9282 | goto out; |
4f926bf2 JK |
9283 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
9284 | kvm_queue_exception(vcpu, DB_VECTOR); | |
9285 | else | |
9286 | kvm_queue_exception(vcpu, BP_VECTOR); | |
9287 | } | |
9288 | ||
91586a3b JK |
9289 | /* |
9290 | * Read rflags as long as potentially injected trace flags are still | |
9291 | * filtered out. | |
9292 | */ | |
9293 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
9294 | |
9295 | vcpu->guest_debug = dbg->control; | |
9296 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
9297 | vcpu->guest_debug = 0; | |
9298 | ||
9299 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
9300 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
9301 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 9302 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
9303 | } else { |
9304 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
9305 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 9306 | } |
c8639010 | 9307 | kvm_update_dr7(vcpu); |
ae675ef0 | 9308 | |
f92653ee JK |
9309 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
9310 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + | |
9311 | get_segment_base(vcpu, VCPU_SREG_CS); | |
94fe45da | 9312 | |
91586a3b JK |
9313 | /* |
9314 | * Trigger an rflags update that will inject or remove the trace | |
9315 | * flags. | |
9316 | */ | |
9317 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 9318 | |
afaf0b2f | 9319 | kvm_x86_ops.update_bp_intercept(vcpu); |
b6c7a5dc | 9320 | |
4f926bf2 | 9321 | r = 0; |
d0bfb940 | 9322 | |
2122ff5e | 9323 | out: |
66b56562 | 9324 | vcpu_put(vcpu); |
b6c7a5dc HB |
9325 | return r; |
9326 | } | |
9327 | ||
8b006791 ZX |
9328 | /* |
9329 | * Translate a guest virtual address to a guest physical address. | |
9330 | */ | |
9331 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
9332 | struct kvm_translation *tr) | |
9333 | { | |
9334 | unsigned long vaddr = tr->linear_address; | |
9335 | gpa_t gpa; | |
f656ce01 | 9336 | int idx; |
8b006791 | 9337 | |
1da5b61d CD |
9338 | vcpu_load(vcpu); |
9339 | ||
f656ce01 | 9340 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 9341 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 9342 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 ZX |
9343 | tr->physical_address = gpa; |
9344 | tr->valid = gpa != UNMAPPED_GVA; | |
9345 | tr->writeable = 1; | |
9346 | tr->usermode = 0; | |
8b006791 | 9347 | |
1da5b61d | 9348 | vcpu_put(vcpu); |
8b006791 ZX |
9349 | return 0; |
9350 | } | |
9351 | ||
d0752060 HB |
9352 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
9353 | { | |
1393123e | 9354 | struct fxregs_state *fxsave; |
d0752060 | 9355 | |
1393123e | 9356 | vcpu_load(vcpu); |
d0752060 | 9357 | |
b666a4b6 | 9358 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 HB |
9359 | memcpy(fpu->fpr, fxsave->st_space, 128); |
9360 | fpu->fcw = fxsave->cwd; | |
9361 | fpu->fsw = fxsave->swd; | |
9362 | fpu->ftwx = fxsave->twd; | |
9363 | fpu->last_opcode = fxsave->fop; | |
9364 | fpu->last_ip = fxsave->rip; | |
9365 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 9366 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 9367 | |
1393123e | 9368 | vcpu_put(vcpu); |
d0752060 HB |
9369 | return 0; |
9370 | } | |
9371 | ||
9372 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
9373 | { | |
6a96bc7f CD |
9374 | struct fxregs_state *fxsave; |
9375 | ||
9376 | vcpu_load(vcpu); | |
9377 | ||
b666a4b6 | 9378 | fxsave = &vcpu->arch.guest_fpu->state.fxsave; |
d0752060 | 9379 | |
d0752060 HB |
9380 | memcpy(fxsave->st_space, fpu->fpr, 128); |
9381 | fxsave->cwd = fpu->fcw; | |
9382 | fxsave->swd = fpu->fsw; | |
9383 | fxsave->twd = fpu->ftwx; | |
9384 | fxsave->fop = fpu->last_opcode; | |
9385 | fxsave->rip = fpu->last_ip; | |
9386 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 9387 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 9388 | |
6a96bc7f | 9389 | vcpu_put(vcpu); |
d0752060 HB |
9390 | return 0; |
9391 | } | |
9392 | ||
01643c51 KH |
9393 | static void store_regs(struct kvm_vcpu *vcpu) |
9394 | { | |
9395 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
9396 | ||
9397 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
9398 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
9399 | ||
9400 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
9401 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
9402 | ||
9403 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
9404 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
9405 | vcpu, &vcpu->run->s.regs.events); | |
9406 | } | |
9407 | ||
9408 | static int sync_regs(struct kvm_vcpu *vcpu) | |
9409 | { | |
9410 | if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) | |
9411 | return -EINVAL; | |
9412 | ||
9413 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { | |
9414 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
9415 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
9416 | } | |
9417 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
9418 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
9419 | return -EINVAL; | |
9420 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
9421 | } | |
9422 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
9423 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
9424 | vcpu, &vcpu->run->s.regs.events)) | |
9425 | return -EINVAL; | |
9426 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
9427 | } | |
9428 | ||
9429 | return 0; | |
9430 | } | |
9431 | ||
0ee6a517 | 9432 | static void fx_init(struct kvm_vcpu *vcpu) |
d0752060 | 9433 | { |
b666a4b6 | 9434 | fpstate_init(&vcpu->arch.guest_fpu->state); |
782511b0 | 9435 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
b666a4b6 | 9436 | vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = |
df1daba7 | 9437 | host_xcr0 | XSTATE_COMPACTION_ENABLED; |
d0752060 | 9438 | |
2acf923e DC |
9439 | /* |
9440 | * Ensure guest xcr0 is valid for loading | |
9441 | */ | |
d91cab78 | 9442 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; |
2acf923e | 9443 | |
ad312c7c | 9444 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 9445 | } |
d0752060 | 9446 | |
897cc38e | 9447 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 9448 | { |
897cc38e SC |
9449 | if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) |
9450 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " | |
9451 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 9452 | |
897cc38e | 9453 | return 0; |
e9b11c17 ZX |
9454 | } |
9455 | ||
e529ef66 | 9456 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 9457 | { |
95a0d01e SC |
9458 | struct page *page; |
9459 | int r; | |
c447e76b | 9460 | |
95a0d01e SC |
9461 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
9462 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
9463 | else | |
9464 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 9465 | |
95a0d01e | 9466 | kvm_set_tsc_khz(vcpu, max_tsc_khz); |
c447e76b | 9467 | |
95a0d01e SC |
9468 | r = kvm_mmu_create(vcpu); |
9469 | if (r < 0) | |
9470 | return r; | |
9471 | ||
9472 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
9473 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
9474 | if (r < 0) | |
9475 | goto fail_mmu_destroy; | |
4e19c36f SS |
9476 | if (kvm_apicv_activated(vcpu->kvm)) |
9477 | vcpu->arch.apicv_active = true; | |
95a0d01e SC |
9478 | } else |
9479 | static_key_slow_inc(&kvm_no_apic_vcpu); | |
9480 | ||
9481 | r = -ENOMEM; | |
9482 | ||
9483 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
9484 | if (!page) | |
9485 | goto fail_free_lapic; | |
9486 | vcpu->arch.pio_data = page_address(page); | |
9487 | ||
9488 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, | |
9489 | GFP_KERNEL_ACCOUNT); | |
9490 | if (!vcpu->arch.mce_banks) | |
9491 | goto fail_free_pio_data; | |
9492 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
9493 | ||
9494 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
9495 | GFP_KERNEL_ACCOUNT)) | |
9496 | goto fail_free_mce_banks; | |
9497 | ||
c9b8b07c SC |
9498 | if (!alloc_emulate_ctxt(vcpu)) |
9499 | goto free_wbinvd_dirty_mask; | |
9500 | ||
95a0d01e SC |
9501 | vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, |
9502 | GFP_KERNEL_ACCOUNT); | |
9503 | if (!vcpu->arch.user_fpu) { | |
9504 | pr_err("kvm: failed to allocate userspace's fpu\n"); | |
c9b8b07c | 9505 | goto free_emulate_ctxt; |
95a0d01e SC |
9506 | } |
9507 | ||
9508 | vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | |
9509 | GFP_KERNEL_ACCOUNT); | |
9510 | if (!vcpu->arch.guest_fpu) { | |
9511 | pr_err("kvm: failed to allocate vcpu's fpu\n"); | |
9512 | goto free_user_fpu; | |
9513 | } | |
9514 | fx_init(vcpu); | |
9515 | ||
95a0d01e | 9516 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
7d2e8748 | 9517 | vcpu->arch.tdp_level = kvm_x86_ops.get_tdp_level(vcpu); |
95a0d01e SC |
9518 | |
9519 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
9520 | ||
9521 | kvm_async_pf_hash_reset(vcpu); | |
9522 | kvm_pmu_init(vcpu); | |
9523 | ||
9524 | vcpu->arch.pending_external_vector = -1; | |
9525 | vcpu->arch.preempted_in_kernel = false; | |
9526 | ||
9527 | kvm_hv_vcpu_init(vcpu); | |
9528 | ||
afaf0b2f | 9529 | r = kvm_x86_ops.vcpu_create(vcpu); |
95a0d01e SC |
9530 | if (r) |
9531 | goto free_guest_fpu; | |
e9b11c17 | 9532 | |
0cf9135b | 9533 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 9534 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
19efffa2 | 9535 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 9536 | vcpu_load(vcpu); |
d28bc9dd | 9537 | kvm_vcpu_reset(vcpu, false); |
e1732991 | 9538 | kvm_init_mmu(vcpu, false); |
e9b11c17 | 9539 | vcpu_put(vcpu); |
ec7660cc | 9540 | return 0; |
95a0d01e SC |
9541 | |
9542 | free_guest_fpu: | |
9543 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
9544 | free_user_fpu: | |
9545 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
c9b8b07c SC |
9546 | free_emulate_ctxt: |
9547 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
9548 | free_wbinvd_dirty_mask: |
9549 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
9550 | fail_free_mce_banks: | |
9551 | kfree(vcpu->arch.mce_banks); | |
9552 | fail_free_pio_data: | |
9553 | free_page((unsigned long)vcpu->arch.pio_data); | |
9554 | fail_free_lapic: | |
9555 | kvm_free_lapic(vcpu); | |
9556 | fail_mmu_destroy: | |
9557 | kvm_mmu_destroy(vcpu); | |
9558 | return r; | |
e9b11c17 ZX |
9559 | } |
9560 | ||
31928aa5 | 9561 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 9562 | { |
8fe8ab46 | 9563 | struct msr_data msr; |
332967a3 | 9564 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 9565 | |
d3457c87 RK |
9566 | kvm_hv_vcpu_postcreate(vcpu); |
9567 | ||
ec7660cc | 9568 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 9569 | return; |
ec7660cc | 9570 | vcpu_load(vcpu); |
8fe8ab46 WA |
9571 | msr.data = 0x0; |
9572 | msr.index = MSR_IA32_TSC; | |
9573 | msr.host_initiated = true; | |
9574 | kvm_write_tsc(vcpu, &msr); | |
42897d86 | 9575 | vcpu_put(vcpu); |
2d5ba19b MT |
9576 | |
9577 | /* poll control enabled by default */ | |
9578 | vcpu->arch.msr_kvm_poll_control = 1; | |
9579 | ||
ec7660cc | 9580 | mutex_unlock(&vcpu->mutex); |
42897d86 | 9581 | |
b34de572 WL |
9582 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
9583 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
9584 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
9585 | } |
9586 | ||
d40ccc62 | 9587 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 9588 | { |
4cbc418a | 9589 | struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; |
95a0d01e | 9590 | int idx; |
344d9588 | 9591 | |
4cbc418a PB |
9592 | kvm_release_pfn(cache->pfn, cache->dirty, cache); |
9593 | ||
50b143e1 | 9594 | kvmclock_reset(vcpu); |
e9b11c17 | 9595 | |
afaf0b2f | 9596 | kvm_x86_ops.vcpu_free(vcpu); |
50b143e1 | 9597 | |
c9b8b07c | 9598 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 SC |
9599 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
9600 | kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); | |
9601 | kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); | |
95a0d01e SC |
9602 | |
9603 | kvm_hv_vcpu_uninit(vcpu); | |
9604 | kvm_pmu_destroy(vcpu); | |
9605 | kfree(vcpu->arch.mce_banks); | |
9606 | kvm_free_lapic(vcpu); | |
9607 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
9608 | kvm_mmu_destroy(vcpu); | |
9609 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
9610 | free_page((unsigned long)vcpu->arch.pio_data); | |
9611 | if (!lapic_in_kernel(vcpu)) | |
9612 | static_key_slow_dec(&kvm_no_apic_vcpu); | |
e9b11c17 ZX |
9613 | } |
9614 | ||
d28bc9dd | 9615 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 9616 | { |
b7e31be3 RK |
9617 | kvm_lapic_reset(vcpu, init_event); |
9618 | ||
e69fab5d PB |
9619 | vcpu->arch.hflags = 0; |
9620 | ||
c43203ca | 9621 | vcpu->arch.smi_pending = 0; |
52797bf9 | 9622 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
9623 | atomic_set(&vcpu->arch.nmi_queued, 0); |
9624 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 9625 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
9626 | kvm_clear_interrupt_queue(vcpu); |
9627 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 9628 | |
42dbaa5a | 9629 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 9630 | kvm_update_dr0123(vcpu); |
6f43ed01 | 9631 | vcpu->arch.dr6 = DR6_INIT; |
42dbaa5a | 9632 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 9633 | kvm_update_dr7(vcpu); |
42dbaa5a | 9634 | |
1119022c NA |
9635 | vcpu->arch.cr2 = 0; |
9636 | ||
3842d135 | 9637 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
9638 | vcpu->arch.apf.msr_en_val = 0; |
9639 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 9640 | vcpu->arch.st.msr_val = 0; |
3842d135 | 9641 | |
12f9a48f GC |
9642 | kvmclock_reset(vcpu); |
9643 | ||
af585b92 GN |
9644 | kvm_clear_async_pf_completion_queue(vcpu); |
9645 | kvm_async_pf_hash_reset(vcpu); | |
9646 | vcpu->arch.apf.halted = false; | |
3842d135 | 9647 | |
a554d207 WL |
9648 | if (kvm_mpx_supported()) { |
9649 | void *mpx_state_buffer; | |
9650 | ||
9651 | /* | |
9652 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
9653 | * called with loaded FPU and does not let userspace fix the state. | |
9654 | */ | |
f775b13e RR |
9655 | if (init_event) |
9656 | kvm_put_guest_fpu(vcpu); | |
b666a4b6 | 9657 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9658 | XFEATURE_BNDREGS); |
a554d207 WL |
9659 | if (mpx_state_buffer) |
9660 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); | |
b666a4b6 | 9661 | mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, |
abd16d68 | 9662 | XFEATURE_BNDCSR); |
a554d207 WL |
9663 | if (mpx_state_buffer) |
9664 | memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); | |
f775b13e RR |
9665 | if (init_event) |
9666 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
9667 | } |
9668 | ||
64d60670 | 9669 | if (!init_event) { |
d28bc9dd | 9670 | kvm_pmu_reset(vcpu); |
64d60670 | 9671 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 9672 | |
db2336a8 | 9673 | vcpu->arch.msr_misc_features_enables = 0; |
a554d207 WL |
9674 | |
9675 | vcpu->arch.xcr0 = XFEATURE_MASK_FP; | |
64d60670 | 9676 | } |
f5132b01 | 9677 | |
66f7b72e JS |
9678 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
9679 | vcpu->arch.regs_avail = ~0; | |
9680 | vcpu->arch.regs_dirty = ~0; | |
9681 | ||
a554d207 WL |
9682 | vcpu->arch.ia32_xss = 0; |
9683 | ||
afaf0b2f | 9684 | kvm_x86_ops.vcpu_reset(vcpu, init_event); |
e9b11c17 ZX |
9685 | } |
9686 | ||
2b4a273b | 9687 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
9688 | { |
9689 | struct kvm_segment cs; | |
9690 | ||
9691 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
9692 | cs.selector = vector << 8; | |
9693 | cs.base = vector << 12; | |
9694 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
9695 | kvm_rip_write(vcpu, 0); | |
e9b11c17 ZX |
9696 | } |
9697 | ||
13a34e06 | 9698 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 9699 | { |
ca84d1a2 ZA |
9700 | struct kvm *kvm; |
9701 | struct kvm_vcpu *vcpu; | |
9702 | int i; | |
0dd6a6ed ZA |
9703 | int ret; |
9704 | u64 local_tsc; | |
9705 | u64 max_tsc = 0; | |
9706 | bool stable, backwards_tsc = false; | |
18863bdd AK |
9707 | |
9708 | kvm_shared_msr_cpu_online(); | |
afaf0b2f | 9709 | ret = kvm_x86_ops.hardware_enable(); |
0dd6a6ed ZA |
9710 | if (ret != 0) |
9711 | return ret; | |
9712 | ||
4ea1636b | 9713 | local_tsc = rdtsc(); |
b0c39dc6 | 9714 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
9715 | list_for_each_entry(kvm, &vm_list, vm_list) { |
9716 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
9717 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 9718 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9719 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
9720 | backwards_tsc = true; | |
9721 | if (vcpu->arch.last_host_tsc > max_tsc) | |
9722 | max_tsc = vcpu->arch.last_host_tsc; | |
9723 | } | |
9724 | } | |
9725 | } | |
9726 | ||
9727 | /* | |
9728 | * Sometimes, even reliable TSCs go backwards. This happens on | |
9729 | * platforms that reset TSC during suspend or hibernate actions, but | |
9730 | * maintain synchronization. We must compensate. Fortunately, we can | |
9731 | * detect that condition here, which happens early in CPU bringup, | |
9732 | * before any KVM threads can be running. Unfortunately, we can't | |
9733 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
9734 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 9735 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
9736 | * variables that haven't been updated yet. |
9737 | * | |
9738 | * So we simply find the maximum observed TSC above, then record the | |
9739 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
9740 | * the adjustment will be applied. Note that we accumulate | |
9741 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
9742 | * gets a chance to run again. In the event that no KVM threads get a | |
9743 | * chance to run, we will miss the entire elapsed period, as we'll have | |
9744 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
9745 | * loose cycle time. This isn't too big a deal, since the loss will be | |
9746 | * uniform across all VCPUs (not to mention the scenario is extremely | |
9747 | * unlikely). It is possible that a second hibernate recovery happens | |
9748 | * much faster than a first, causing the observed TSC here to be | |
9749 | * smaller; this would require additional padding adjustment, which is | |
9750 | * why we set last_host_tsc to the local tsc observed here. | |
9751 | * | |
9752 | * N.B. - this code below runs only on platforms with reliable TSC, | |
9753 | * as that is the only way backwards_tsc is set above. Also note | |
9754 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
9755 | * have the same delta_cyc adjustment applied if backwards_tsc | |
9756 | * is detected. Note further, this adjustment is only done once, | |
9757 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
9758 | * called multiple times (one for each physical CPU bringup). | |
9759 | * | |
4a969980 | 9760 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
9761 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
9762 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
9763 | * guarantee that they stay in perfect synchronization. | |
9764 | */ | |
9765 | if (backwards_tsc) { | |
9766 | u64 delta_cyc = max_tsc - local_tsc; | |
9767 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 9768 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
9769 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9770 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
9771 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 9772 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
9773 | } |
9774 | ||
9775 | /* | |
9776 | * We have to disable TSC offset matching.. if you were | |
9777 | * booting a VM while issuing an S4 host suspend.... | |
9778 | * you may have some problem. Solving this issue is | |
9779 | * left as an exercise to the reader. | |
9780 | */ | |
9781 | kvm->arch.last_tsc_nsec = 0; | |
9782 | kvm->arch.last_tsc_write = 0; | |
9783 | } | |
9784 | ||
9785 | } | |
9786 | return 0; | |
e9b11c17 ZX |
9787 | } |
9788 | ||
13a34e06 | 9789 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 9790 | { |
afaf0b2f | 9791 | kvm_x86_ops.hardware_disable(); |
13a34e06 | 9792 | drop_user_return_notifiers(); |
e9b11c17 ZX |
9793 | } |
9794 | ||
b9904085 | 9795 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 9796 | { |
d008dfdb | 9797 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
9798 | int r; |
9799 | ||
91661989 SC |
9800 | rdmsrl_safe(MSR_EFER, &host_efer); |
9801 | ||
408e9a31 PB |
9802 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
9803 | rdmsrl(MSR_IA32_XSS, host_xss); | |
9804 | ||
d008dfdb | 9805 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
9806 | if (r != 0) |
9807 | return r; | |
9808 | ||
afaf0b2f | 9809 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); |
69c6f69a | 9810 | |
408e9a31 PB |
9811 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
9812 | supported_xss = 0; | |
9813 | ||
139f7425 PB |
9814 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
9815 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
9816 | #undef __kvm_cpu_cap_has | |
b11306b5 | 9817 | |
35181e86 HZ |
9818 | if (kvm_has_tsc_control) { |
9819 | /* | |
9820 | * Make sure the user can only configure tsc_khz values that | |
9821 | * fit into a signed integer. | |
273ba457 | 9822 | * A min value is not calculated because it will always |
35181e86 HZ |
9823 | * be 1 on all machines. |
9824 | */ | |
9825 | u64 max = min(0x7fffffffULL, | |
9826 | __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); | |
9827 | kvm_max_guest_tsc_khz = max; | |
9828 | ||
ad721883 | 9829 | kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; |
35181e86 | 9830 | } |
ad721883 | 9831 | |
9e9c3fe4 NA |
9832 | kvm_init_msr_list(); |
9833 | return 0; | |
e9b11c17 ZX |
9834 | } |
9835 | ||
9836 | void kvm_arch_hardware_unsetup(void) | |
9837 | { | |
afaf0b2f | 9838 | kvm_x86_ops.hardware_unsetup(); |
e9b11c17 ZX |
9839 | } |
9840 | ||
b9904085 | 9841 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 9842 | { |
f1cdecf5 | 9843 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 9844 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
9845 | |
9846 | WARN_ON(!irqs_disabled()); | |
9847 | ||
139f7425 PB |
9848 | if (__cr4_reserved_bits(cpu_has, c) != |
9849 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
9850 | return -EIO; |
9851 | ||
d008dfdb | 9852 | return ops->check_processor_compatibility(); |
d71ba788 PB |
9853 | } |
9854 | ||
9855 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
9856 | { | |
9857 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
9858 | } | |
9859 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
9860 | ||
9861 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
9862 | { | |
9863 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
9864 | } |
9865 | ||
54e9818f | 9866 | struct static_key kvm_no_apic_vcpu __read_mostly; |
bce87cce | 9867 | EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); |
54e9818f | 9868 | |
e790d9ef RK |
9869 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
9870 | { | |
b35e5548 LX |
9871 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
9872 | ||
c595ceee | 9873 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
9874 | if (pmu->version && unlikely(pmu->event_count)) { |
9875 | pmu->need_cleanup = true; | |
9876 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
9877 | } | |
afaf0b2f | 9878 | kvm_x86_ops.sched_in(vcpu, cpu); |
e790d9ef RK |
9879 | } |
9880 | ||
562b6b08 SC |
9881 | void kvm_arch_free_vm(struct kvm *kvm) |
9882 | { | |
9883 | kfree(kvm->arch.hyperv.hv_pa_pg); | |
9884 | vfree(kvm); | |
e790d9ef RK |
9885 | } |
9886 | ||
562b6b08 | 9887 | |
e08b9637 | 9888 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 9889 | { |
e08b9637 CO |
9890 | if (type) |
9891 | return -EINVAL; | |
9892 | ||
6ef768fa | 9893 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
f05e70ac | 9894 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
10605204 | 9895 | INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); |
1aa9b957 | 9896 | INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); |
4d5c5d0f | 9897 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 9898 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 9899 | |
5550af4d SY |
9900 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
9901 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
9902 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
9903 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
9904 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 9905 | |
038f8c11 | 9906 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 9907 | mutex_init(&kvm->arch.apic_map_lock); |
d828199e MT |
9908 | spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); |
9909 | ||
8171cd68 | 9910 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
d828199e | 9911 | pvclock_update_vm_gtod_copy(kvm); |
53f658b3 | 9912 | |
6fbbde9a DS |
9913 | kvm->arch.guest_can_read_msr_platform_info = true; |
9914 | ||
7e44e449 | 9915 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 9916 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 9917 | |
cbc0236a | 9918 | kvm_hv_init_vm(kvm); |
0eb05bf2 | 9919 | kvm_page_track_init(kvm); |
13d268ca | 9920 | kvm_mmu_init_vm(kvm); |
0eb05bf2 | 9921 | |
afaf0b2f | 9922 | return kvm_x86_ops.vm_init(kvm); |
d19a9cd2 ZX |
9923 | } |
9924 | ||
1aa9b957 JS |
9925 | int kvm_arch_post_init_vm(struct kvm *kvm) |
9926 | { | |
9927 | return kvm_mmu_post_init_vm(kvm); | |
9928 | } | |
9929 | ||
d19a9cd2 ZX |
9930 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
9931 | { | |
ec7660cc | 9932 | vcpu_load(vcpu); |
d19a9cd2 ZX |
9933 | kvm_mmu_unload(vcpu); |
9934 | vcpu_put(vcpu); | |
9935 | } | |
9936 | ||
9937 | static void kvm_free_vcpus(struct kvm *kvm) | |
9938 | { | |
9939 | unsigned int i; | |
988a2cae | 9940 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
9941 | |
9942 | /* | |
9943 | * Unpin any mmu pages first. | |
9944 | */ | |
af585b92 GN |
9945 | kvm_for_each_vcpu(i, vcpu, kvm) { |
9946 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 9947 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 9948 | } |
988a2cae | 9949 | kvm_for_each_vcpu(i, vcpu, kvm) |
4543bdc0 | 9950 | kvm_vcpu_destroy(vcpu); |
988a2cae GN |
9951 | |
9952 | mutex_lock(&kvm->lock); | |
9953 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
9954 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 9955 | |
988a2cae GN |
9956 | atomic_set(&kvm->online_vcpus, 0); |
9957 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
9958 | } |
9959 | ||
ad8ba2cd SY |
9960 | void kvm_arch_sync_events(struct kvm *kvm) |
9961 | { | |
332967a3 | 9962 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 9963 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 9964 | kvm_free_pit(kvm); |
ad8ba2cd SY |
9965 | } |
9966 | ||
1d8007bd | 9967 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) |
9da0e4d5 PB |
9968 | { |
9969 | int i, r; | |
0577d1ab | 9970 | unsigned long hva, uninitialized_var(old_npages); |
f0d648bd | 9971 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 9972 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
9973 | |
9974 | /* Called with kvm->slots_lock held. */ | |
1d8007bd PB |
9975 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
9976 | return -EINVAL; | |
9da0e4d5 | 9977 | |
f0d648bd PB |
9978 | slot = id_to_memslot(slots, id); |
9979 | if (size) { | |
0577d1ab | 9980 | if (slot && slot->npages) |
f0d648bd PB |
9981 | return -EEXIST; |
9982 | ||
9983 | /* | |
9984 | * MAP_SHARED to prevent internal slot pages from being moved | |
9985 | * by fork()/COW. | |
9986 | */ | |
9987 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
9988 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
9989 | if (IS_ERR((void *)hva)) | |
9990 | return PTR_ERR((void *)hva); | |
9991 | } else { | |
0577d1ab | 9992 | if (!slot || !slot->npages) |
f0d648bd PB |
9993 | return 0; |
9994 | ||
0577d1ab | 9995 | old_npages = slot->npages; |
e0135a10 | 9996 | hva = 0; |
f0d648bd PB |
9997 | } |
9998 | ||
9da0e4d5 | 9999 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 10000 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 10001 | |
1d8007bd PB |
10002 | m.slot = id | (i << 16); |
10003 | m.flags = 0; | |
10004 | m.guest_phys_addr = gpa; | |
f0d648bd | 10005 | m.userspace_addr = hva; |
1d8007bd | 10006 | m.memory_size = size; |
9da0e4d5 PB |
10007 | r = __kvm_set_memory_region(kvm, &m); |
10008 | if (r < 0) | |
10009 | return r; | |
10010 | } | |
10011 | ||
103c763c | 10012 | if (!size) |
0577d1ab | 10013 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 10014 | |
9da0e4d5 PB |
10015 | return 0; |
10016 | } | |
10017 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
10018 | ||
1aa9b957 JS |
10019 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
10020 | { | |
10021 | kvm_mmu_pre_destroy_vm(kvm); | |
10022 | } | |
10023 | ||
d19a9cd2 ZX |
10024 | void kvm_arch_destroy_vm(struct kvm *kvm) |
10025 | { | |
27469d29 AH |
10026 | if (current->mm == kvm->mm) { |
10027 | /* | |
10028 | * Free memory regions allocated on behalf of userspace, | |
10029 | * unless the the memory map has changed due to process exit | |
10030 | * or fd copying. | |
10031 | */ | |
6a3c623b PX |
10032 | mutex_lock(&kvm->slots_lock); |
10033 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
10034 | 0, 0); | |
10035 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
10036 | 0, 0); | |
10037 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
10038 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 10039 | } |
afaf0b2f SC |
10040 | if (kvm_x86_ops.vm_destroy) |
10041 | kvm_x86_ops.vm_destroy(kvm); | |
c761159c PX |
10042 | kvm_pic_destroy(kvm); |
10043 | kvm_ioapic_destroy(kvm); | |
d19a9cd2 | 10044 | kvm_free_vcpus(kvm); |
af1bae54 | 10045 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 10046 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 10047 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 10048 | kvm_page_track_cleanup(kvm); |
cbc0236a | 10049 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 10050 | } |
0de10343 | 10051 | |
e96c81ee | 10052 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
db3fe4eb TY |
10053 | { |
10054 | int i; | |
10055 | ||
d89cc617 | 10056 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
10057 | kvfree(slot->arch.rmap[i]); |
10058 | slot->arch.rmap[i] = NULL; | |
10059 | ||
d89cc617 TY |
10060 | if (i == 0) |
10061 | continue; | |
10062 | ||
e96c81ee SC |
10063 | kvfree(slot->arch.lpage_info[i - 1]); |
10064 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 10065 | } |
21ebbeda | 10066 | |
e96c81ee | 10067 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
10068 | } |
10069 | ||
0dab98b7 SC |
10070 | static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, |
10071 | unsigned long npages) | |
db3fe4eb TY |
10072 | { |
10073 | int i; | |
10074 | ||
edd4fa37 SC |
10075 | /* |
10076 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
10077 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
10078 | * the new memslot is successful. | |
10079 | */ | |
10080 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
10081 | ||
d89cc617 | 10082 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
92f94f1e | 10083 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
10084 | unsigned long ugfn; |
10085 | int lpages; | |
d89cc617 | 10086 | int level = i + 1; |
db3fe4eb TY |
10087 | |
10088 | lpages = gfn_to_index(slot->base_gfn + npages - 1, | |
10089 | slot->base_gfn, level) + 1; | |
10090 | ||
d89cc617 | 10091 | slot->arch.rmap[i] = |
778e1cdd | 10092 | kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), |
254272ce | 10093 | GFP_KERNEL_ACCOUNT); |
d89cc617 | 10094 | if (!slot->arch.rmap[i]) |
77d11309 | 10095 | goto out_free; |
d89cc617 TY |
10096 | if (i == 0) |
10097 | continue; | |
77d11309 | 10098 | |
254272ce | 10099 | linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 10100 | if (!linfo) |
db3fe4eb TY |
10101 | goto out_free; |
10102 | ||
92f94f1e XG |
10103 | slot->arch.lpage_info[i - 1] = linfo; |
10104 | ||
db3fe4eb | 10105 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10106 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 10107 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 10108 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
10109 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
10110 | /* | |
10111 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 10112 | * other, disable large page support for this slot. |
db3fe4eb | 10113 | */ |
600087b6 | 10114 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
10115 | unsigned long j; |
10116 | ||
10117 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 10118 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
10119 | } |
10120 | } | |
10121 | ||
21ebbeda XG |
10122 | if (kvm_page_track_create_memslot(slot, npages)) |
10123 | goto out_free; | |
10124 | ||
db3fe4eb TY |
10125 | return 0; |
10126 | ||
10127 | out_free: | |
d89cc617 | 10128 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 10129 | kvfree(slot->arch.rmap[i]); |
d89cc617 TY |
10130 | slot->arch.rmap[i] = NULL; |
10131 | if (i == 0) | |
10132 | continue; | |
10133 | ||
548ef284 | 10134 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 10135 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
10136 | } |
10137 | return -ENOMEM; | |
10138 | } | |
10139 | ||
15248258 | 10140 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 10141 | { |
91724814 BO |
10142 | struct kvm_vcpu *vcpu; |
10143 | int i; | |
10144 | ||
e6dff7d1 TY |
10145 | /* |
10146 | * memslots->generation has been incremented. | |
10147 | * mmio generation may have reached its maximum value. | |
10148 | */ | |
15248258 | 10149 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
10150 | |
10151 | /* Force re-initialization of steal_time cache */ | |
10152 | kvm_for_each_vcpu(i, vcpu, kvm) | |
10153 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
10154 | } |
10155 | ||
f7784b8e MT |
10156 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
10157 | struct kvm_memory_slot *memslot, | |
09170a49 | 10158 | const struct kvm_userspace_memory_region *mem, |
7b6195a9 | 10159 | enum kvm_mr_change change) |
0de10343 | 10160 | { |
0dab98b7 SC |
10161 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) |
10162 | return kvm_alloc_memslot_metadata(memslot, | |
10163 | mem->memory_size >> PAGE_SHIFT); | |
f7784b8e MT |
10164 | return 0; |
10165 | } | |
10166 | ||
88178fd4 | 10167 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b AY |
10168 | struct kvm_memory_slot *old, |
10169 | struct kvm_memory_slot *new, | |
10170 | enum kvm_mr_change change) | |
88178fd4 | 10171 | { |
3741679b AY |
10172 | /* |
10173 | * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. | |
10174 | * See comments below. | |
10175 | */ | |
10176 | if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) | |
88178fd4 | 10177 | return; |
88178fd4 KH |
10178 | |
10179 | /* | |
3741679b AY |
10180 | * Dirty logging tracks sptes in 4k granularity, meaning that large |
10181 | * sptes have to be split. If live migration is successful, the guest | |
10182 | * in the source machine will be destroyed and large sptes will be | |
10183 | * created in the destination. However, if the guest continues to run | |
10184 | * in the source machine (for example if live migration fails), small | |
10185 | * sptes will remain around and cause bad performance. | |
88178fd4 | 10186 | * |
3741679b AY |
10187 | * Scan sptes if dirty logging has been stopped, dropping those |
10188 | * which can be collapsed into a single large-page spte. Later | |
10189 | * page faults will create the large-page sptes. | |
88178fd4 | 10190 | * |
3741679b AY |
10191 | * There is no need to do this in any of the following cases: |
10192 | * CREATE: No dirty mappings will already exist. | |
10193 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
10194 | * kvm_arch_flush_shadow_memslot() | |
10195 | */ | |
10196 | if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
10197 | !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) | |
10198 | kvm_mmu_zap_collapsible_sptes(kvm, new); | |
10199 | ||
10200 | /* | |
10201 | * Enable or disable dirty logging for the slot. | |
88178fd4 | 10202 | * |
3741679b AY |
10203 | * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old |
10204 | * slot have been zapped so no dirty logging updates are needed for | |
10205 | * the old slot. | |
10206 | * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible | |
10207 | * any mappings that might be created in it will consume the | |
10208 | * properties of the new slot and do not need to be updated here. | |
88178fd4 | 10209 | * |
3741679b AY |
10210 | * When PML is enabled, the kvm_x86_ops dirty logging hooks are |
10211 | * called to enable/disable dirty logging. | |
88178fd4 | 10212 | * |
3741679b AY |
10213 | * When disabling dirty logging with PML enabled, the D-bit is set |
10214 | * for sptes in the slot in order to prevent unnecessary GPA | |
10215 | * logging in the PML buffer (and potential PML buffer full VMEXIT). | |
10216 | * This guarantees leaving PML enabled for the guest's lifetime | |
10217 | * won't have any additional overhead from PML when the guest is | |
10218 | * running with dirty logging disabled. | |
88178fd4 | 10219 | * |
3741679b AY |
10220 | * When enabling dirty logging, large sptes are write-protected |
10221 | * so they can be split on first write. New large sptes cannot | |
10222 | * be created for this slot until the end of the logging. | |
88178fd4 | 10223 | * See the comments in fast_page_fault(). |
3741679b AY |
10224 | * For small sptes, nothing is done if the dirty log is in the |
10225 | * initial-all-set state. Otherwise, depending on whether pml | |
10226 | * is enabled the D-bit or the W-bit will be cleared. | |
88178fd4 KH |
10227 | */ |
10228 | if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { | |
afaf0b2f SC |
10229 | if (kvm_x86_ops.slot_enable_log_dirty) { |
10230 | kvm_x86_ops.slot_enable_log_dirty(kvm, new); | |
3c9bd400 JZ |
10231 | } else { |
10232 | int level = | |
10233 | kvm_dirty_log_manual_protect_and_init_set(kvm) ? | |
3bae0459 | 10234 | PG_LEVEL_2M : PG_LEVEL_4K; |
3c9bd400 JZ |
10235 | |
10236 | /* | |
10237 | * If we're with initial-all-set, we don't need | |
10238 | * to write protect any small page because | |
10239 | * they're reported as dirty already. However | |
10240 | * we still need to write-protect huge pages | |
10241 | * so that the page split can happen lazily on | |
10242 | * the first write to the huge page. | |
10243 | */ | |
10244 | kvm_mmu_slot_remove_write_access(kvm, new, level); | |
10245 | } | |
88178fd4 | 10246 | } else { |
afaf0b2f SC |
10247 | if (kvm_x86_ops.slot_disable_log_dirty) |
10248 | kvm_x86_ops.slot_disable_log_dirty(kvm, new); | |
88178fd4 KH |
10249 | } |
10250 | } | |
10251 | ||
f7784b8e | 10252 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
09170a49 | 10253 | const struct kvm_userspace_memory_region *mem, |
9d4c197c | 10254 | struct kvm_memory_slot *old, |
f36f3f28 | 10255 | const struct kvm_memory_slot *new, |
8482644a | 10256 | enum kvm_mr_change change) |
f7784b8e | 10257 | { |
48c0e4e9 | 10258 | if (!kvm->arch.n_requested_mmu_pages) |
4d66623c WY |
10259 | kvm_mmu_change_mmu_pages(kvm, |
10260 | kvm_mmu_calculate_default_mmu_pages(kvm)); | |
1c91cad4 | 10261 | |
3ea3b7fa | 10262 | /* |
f36f3f28 | 10263 | * FIXME: const-ify all uses of struct kvm_memory_slot. |
c972f3b1 | 10264 | */ |
3741679b | 10265 | kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); |
21198846 SC |
10266 | |
10267 | /* Free the arrays associated with the old memslot. */ | |
10268 | if (change == KVM_MR_MOVE) | |
e96c81ee | 10269 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 10270 | } |
1d737c8a | 10271 | |
2df72e9b | 10272 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 10273 | { |
7390de1e | 10274 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
10275 | } |
10276 | ||
2df72e9b MT |
10277 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
10278 | struct kvm_memory_slot *slot) | |
10279 | { | |
ae7cd873 | 10280 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
10281 | } |
10282 | ||
e6c67d8c LA |
10283 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
10284 | { | |
10285 | return (is_guest_mode(vcpu) && | |
afaf0b2f SC |
10286 | kvm_x86_ops.guest_apic_has_interrupt && |
10287 | kvm_x86_ops.guest_apic_has_interrupt(vcpu)); | |
e6c67d8c LA |
10288 | } |
10289 | ||
5d9bc648 PB |
10290 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
10291 | { | |
10292 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
10293 | return true; | |
10294 | ||
10295 | if (kvm_apic_has_events(vcpu)) | |
10296 | return true; | |
10297 | ||
10298 | if (vcpu->arch.pv.pv_unhalted) | |
10299 | return true; | |
10300 | ||
a5f01f8e WL |
10301 | if (vcpu->arch.exception.pending) |
10302 | return true; | |
10303 | ||
47a66eed Z |
10304 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
10305 | (vcpu->arch.nmi_pending && | |
c300ab9f | 10306 | kvm_x86_ops.nmi_allowed(vcpu, false))) |
5d9bc648 PB |
10307 | return true; |
10308 | ||
47a66eed | 10309 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 10310 | (vcpu->arch.smi_pending && |
c300ab9f | 10311 | kvm_x86_ops.smi_allowed(vcpu, false))) |
73917739 PB |
10312 | return true; |
10313 | ||
5d9bc648 | 10314 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
10315 | (kvm_cpu_has_interrupt(vcpu) || |
10316 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
10317 | return true; |
10318 | ||
1f4b34f8 AS |
10319 | if (kvm_hv_has_stimer_pending(vcpu)) |
10320 | return true; | |
10321 | ||
d2060bd4 SC |
10322 | if (is_guest_mode(vcpu) && |
10323 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
10324 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
10325 | return true; | |
10326 | ||
5d9bc648 PB |
10327 | return false; |
10328 | } | |
10329 | ||
1d737c8a ZX |
10330 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
10331 | { | |
5d9bc648 | 10332 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 10333 | } |
5736199a | 10334 | |
17e433b5 WL |
10335 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
10336 | { | |
10337 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
10338 | return true; | |
10339 | ||
10340 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
10341 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
10342 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
10343 | return true; | |
10344 | ||
afaf0b2f | 10345 | if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) |
17e433b5 WL |
10346 | return true; |
10347 | ||
10348 | return false; | |
10349 | } | |
10350 | ||
199b5763 LM |
10351 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
10352 | { | |
de63ad4c | 10353 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
10354 | } |
10355 | ||
b6d33834 | 10356 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 10357 | { |
b6d33834 | 10358 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 10359 | } |
78646121 GN |
10360 | |
10361 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
10362 | { | |
c300ab9f | 10363 | return kvm_x86_ops.interrupt_allowed(vcpu, false); |
78646121 | 10364 | } |
229456fc | 10365 | |
82b32774 | 10366 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 10367 | { |
82b32774 NA |
10368 | if (is_64_bit_mode(vcpu)) |
10369 | return kvm_rip_read(vcpu); | |
10370 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
10371 | kvm_rip_read(vcpu)); | |
10372 | } | |
10373 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 10374 | |
82b32774 NA |
10375 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
10376 | { | |
10377 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
10378 | } |
10379 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
10380 | ||
94fe45da JK |
10381 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
10382 | { | |
10383 | unsigned long rflags; | |
10384 | ||
afaf0b2f | 10385 | rflags = kvm_x86_ops.get_rflags(vcpu); |
94fe45da | 10386 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 10387 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
10388 | return rflags; |
10389 | } | |
10390 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
10391 | ||
6addfc42 | 10392 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
10393 | { |
10394 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 10395 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 10396 | rflags |= X86_EFLAGS_TF; |
afaf0b2f | 10397 | kvm_x86_ops.set_rflags(vcpu, rflags); |
6addfc42 PB |
10398 | } |
10399 | ||
10400 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
10401 | { | |
10402 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 10403 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
10404 | } |
10405 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
10406 | ||
56028d08 GN |
10407 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) |
10408 | { | |
10409 | int r; | |
10410 | ||
44dd3ffa | 10411 | if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || |
f2e10669 | 10412 | work->wakeup_all) |
56028d08 GN |
10413 | return; |
10414 | ||
10415 | r = kvm_mmu_reload(vcpu); | |
10416 | if (unlikely(r)) | |
10417 | return; | |
10418 | ||
44dd3ffa | 10419 | if (!vcpu->arch.mmu->direct_map && |
d8dd54e0 | 10420 | work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) |
fb67e14f XG |
10421 | return; |
10422 | ||
7a02674d | 10423 | kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); |
56028d08 GN |
10424 | } |
10425 | ||
af585b92 GN |
10426 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
10427 | { | |
dd03bcaa PX |
10428 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
10429 | ||
af585b92 GN |
10430 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
10431 | } | |
10432 | ||
10433 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
10434 | { | |
dd03bcaa | 10435 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
10436 | } |
10437 | ||
10438 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10439 | { | |
10440 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10441 | ||
10442 | while (vcpu->arch.apf.gfns[key] != ~0) | |
10443 | key = kvm_async_pf_next_probe(key); | |
10444 | ||
10445 | vcpu->arch.apf.gfns[key] = gfn; | |
10446 | } | |
10447 | ||
10448 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10449 | { | |
10450 | int i; | |
10451 | u32 key = kvm_async_pf_hash_fn(gfn); | |
10452 | ||
dd03bcaa | 10453 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
10454 | (vcpu->arch.apf.gfns[key] != gfn && |
10455 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
10456 | key = kvm_async_pf_next_probe(key); |
10457 | ||
10458 | return key; | |
10459 | } | |
10460 | ||
10461 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10462 | { | |
10463 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
10464 | } | |
10465 | ||
10466 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
10467 | { | |
10468 | u32 i, j, k; | |
10469 | ||
10470 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
10471 | |
10472 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
10473 | return; | |
10474 | ||
af585b92 GN |
10475 | while (true) { |
10476 | vcpu->arch.apf.gfns[i] = ~0; | |
10477 | do { | |
10478 | j = kvm_async_pf_next_probe(j); | |
10479 | if (vcpu->arch.apf.gfns[j] == ~0) | |
10480 | return; | |
10481 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
10482 | /* | |
10483 | * k lies cyclically in ]i,j] | |
10484 | * | i.k.j | | |
10485 | * |....j i.k.| or |.k..j i...| | |
10486 | */ | |
10487 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
10488 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
10489 | i = j; | |
10490 | } | |
10491 | } | |
10492 | ||
68fd66f1 | 10493 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 10494 | { |
68fd66f1 VK |
10495 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
10496 | ||
10497 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
10498 | sizeof(reason)); | |
10499 | } | |
10500 | ||
10501 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
10502 | { | |
2635b5c4 | 10503 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 10504 | |
2635b5c4 VK |
10505 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
10506 | &token, offset, sizeof(token)); | |
10507 | } | |
10508 | ||
10509 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
10510 | { | |
10511 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
10512 | u32 val; | |
10513 | ||
10514 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
10515 | &val, offset, sizeof(val))) | |
10516 | return false; | |
10517 | ||
10518 | return !val; | |
7c90705b GN |
10519 | } |
10520 | ||
1dfdb45e PB |
10521 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
10522 | { | |
10523 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) | |
10524 | return false; | |
10525 | ||
2635b5c4 VK |
10526 | if (!kvm_pv_async_pf_enabled(vcpu) || |
10527 | (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) | |
1dfdb45e PB |
10528 | return false; |
10529 | ||
10530 | return true; | |
10531 | } | |
10532 | ||
10533 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
10534 | { | |
10535 | if (unlikely(!lapic_in_kernel(vcpu) || | |
10536 | kvm_event_needs_reinjection(vcpu) || | |
10537 | vcpu->arch.exception.pending)) | |
10538 | return false; | |
10539 | ||
10540 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
10541 | return false; | |
10542 | ||
10543 | /* | |
10544 | * If interrupts are off we cannot even use an artificial | |
10545 | * halt state. | |
10546 | */ | |
c300ab9f | 10547 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
10548 | } |
10549 | ||
2a18b7e7 | 10550 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
10551 | struct kvm_async_pf *work) |
10552 | { | |
6389ee94 AK |
10553 | struct x86_exception fault; |
10554 | ||
736c291c | 10555 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 10556 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 10557 | |
1dfdb45e | 10558 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 10559 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
10560 | fault.vector = PF_VECTOR; |
10561 | fault.error_code_valid = true; | |
10562 | fault.error_code = 0; | |
10563 | fault.nested_page_fault = false; | |
10564 | fault.address = work->arch.token; | |
adfe20fb | 10565 | fault.async_page_fault = true; |
6389ee94 | 10566 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 10567 | return true; |
1dfdb45e PB |
10568 | } else { |
10569 | /* | |
10570 | * It is not possible to deliver a paravirtualized asynchronous | |
10571 | * page fault, but putting the guest in an artificial halt state | |
10572 | * can be beneficial nevertheless: if an interrupt arrives, we | |
10573 | * can deliver it timely and perhaps the guest will schedule | |
10574 | * another process. When the instruction that triggered a page | |
10575 | * fault is retried, hopefully the page will be ready in the host. | |
10576 | */ | |
10577 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 10578 | return false; |
7c90705b | 10579 | } |
af585b92 GN |
10580 | } |
10581 | ||
10582 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
10583 | struct kvm_async_pf *work) | |
10584 | { | |
2635b5c4 VK |
10585 | struct kvm_lapic_irq irq = { |
10586 | .delivery_mode = APIC_DM_FIXED, | |
10587 | .vector = vcpu->arch.apf.vec | |
10588 | }; | |
6389ee94 | 10589 | |
f2e10669 | 10590 | if (work->wakeup_all) |
7c90705b GN |
10591 | work->arch.token = ~0; /* broadcast wakeup */ |
10592 | else | |
10593 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 10594 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 10595 | |
2a18b7e7 VK |
10596 | if ((work->wakeup_all || work->notpresent_injected) && |
10597 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
10598 | !apf_put_user_ready(vcpu, work->arch.token)) { |
10599 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 10600 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 10601 | } |
2635b5c4 | 10602 | |
e6d53e3b | 10603 | vcpu->arch.apf.halted = false; |
a4fa1635 | 10604 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
10605 | } |
10606 | ||
557a961a VK |
10607 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
10608 | { | |
10609 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
10610 | if (!vcpu->arch.apf.pageready_pending) | |
10611 | kvm_vcpu_kick(vcpu); | |
10612 | } | |
10613 | ||
7c0ade6c | 10614 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 10615 | { |
2635b5c4 | 10616 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
10617 | return true; |
10618 | else | |
2635b5c4 | 10619 | return apf_pageready_slot_free(vcpu); |
af585b92 GN |
10620 | } |
10621 | ||
5544eb9b PB |
10622 | void kvm_arch_start_assignment(struct kvm *kvm) |
10623 | { | |
10624 | atomic_inc(&kvm->arch.assigned_device_count); | |
10625 | } | |
10626 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
10627 | ||
10628 | void kvm_arch_end_assignment(struct kvm *kvm) | |
10629 | { | |
10630 | atomic_dec(&kvm->arch.assigned_device_count); | |
10631 | } | |
10632 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
10633 | ||
10634 | bool kvm_arch_has_assigned_device(struct kvm *kvm) | |
10635 | { | |
10636 | return atomic_read(&kvm->arch.assigned_device_count); | |
10637 | } | |
10638 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
10639 | ||
e0f0bbc5 AW |
10640 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
10641 | { | |
10642 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
10643 | } | |
10644 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
10645 | ||
10646 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
10647 | { | |
10648 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
10649 | } | |
10650 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
10651 | ||
10652 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
10653 | { | |
10654 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
10655 | } | |
10656 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
10657 | ||
14717e20 AW |
10658 | bool kvm_arch_has_irq_bypass(void) |
10659 | { | |
92735b1b | 10660 | return true; |
14717e20 AW |
10661 | } |
10662 | ||
87276880 FW |
10663 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
10664 | struct irq_bypass_producer *prod) | |
10665 | { | |
10666 | struct kvm_kernel_irqfd *irqfd = | |
10667 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10668 | ||
14717e20 | 10669 | irqfd->producer = prod; |
87276880 | 10670 | |
afaf0b2f | 10671 | return kvm_x86_ops.update_pi_irte(irqfd->kvm, |
14717e20 | 10672 | prod->irq, irqfd->gsi, 1); |
87276880 FW |
10673 | } |
10674 | ||
10675 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
10676 | struct irq_bypass_producer *prod) | |
10677 | { | |
10678 | int ret; | |
10679 | struct kvm_kernel_irqfd *irqfd = | |
10680 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
10681 | ||
87276880 FW |
10682 | WARN_ON(irqfd->producer != prod); |
10683 | irqfd->producer = NULL; | |
10684 | ||
10685 | /* | |
10686 | * When producer of consumer is unregistered, we change back to | |
10687 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 10688 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
10689 | * int this case doesn't want to receive the interrupts. |
10690 | */ | |
afaf0b2f | 10691 | ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
10692 | if (ret) |
10693 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
10694 | " fails: %d\n", irqfd->consumer.token, ret); | |
10695 | } | |
10696 | ||
10697 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
10698 | uint32_t guest_irq, bool set) | |
10699 | { | |
afaf0b2f | 10700 | return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); |
87276880 FW |
10701 | } |
10702 | ||
52004014 FW |
10703 | bool kvm_vector_hashing_enabled(void) |
10704 | { | |
10705 | return vector_hashing; | |
10706 | } | |
52004014 | 10707 | |
2d5ba19b MT |
10708 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
10709 | { | |
10710 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
10711 | } | |
10712 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
10713 | ||
841c2be0 ML |
10714 | |
10715 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 10716 | { |
841c2be0 ML |
10717 | /* |
10718 | * test that setting IA32_SPEC_CTRL to given value | |
10719 | * is allowed by the host processor | |
10720 | */ | |
10721 | ||
10722 | u64 saved_value; | |
10723 | unsigned long flags; | |
10724 | int ret = 0; | |
6441fa61 | 10725 | |
841c2be0 | 10726 | local_irq_save(flags); |
6441fa61 | 10727 | |
841c2be0 ML |
10728 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
10729 | ret = 1; | |
10730 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
10731 | ret = 1; | |
10732 | else | |
10733 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 10734 | |
841c2be0 ML |
10735 | local_irq_restore(flags); |
10736 | ||
10737 | return ret; | |
6441fa61 | 10738 | } |
841c2be0 | 10739 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 10740 | |
229456fc | 10741 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 10742 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
10743 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
10744 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
10745 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
10746 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 10747 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 10748 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 10749 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 10750 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 10751 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 10752 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 10753 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 10754 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 10755 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 10756 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 10757 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 10758 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
10759 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
10760 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 10761 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
24bbf74c | 10762 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); |