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6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
50#define DstMask (3<<1)
51/* Source operand type. */
52#define SrcNone (0<<3) /* No source operand. */
53#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
54#define SrcReg (1<<3) /* Register operand. */
55#define SrcMem (2<<3) /* Memory operand. */
56#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
58#define SrcImm (5<<3) /* Immediate operand. */
59#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
60#define SrcMask (7<<3)
61/* Generic ModRM decode. */
62#define ModRM (1<<6)
63/* Destination is only written; never read. */
64#define Mov (1<<7)
038e51de 65#define BitOp (1<<8)
c7e75a3d 66#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 67#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 68#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 69#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
70#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
71#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 72
43bb19cd 73enum {
1d6ad207 74 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 75 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 76};
77
c7e75a3d 78static u16 opcode_table[256] = {
6aa8b732
AK		 79 /* 0x00 - 0x07 */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x08 - 0x0F */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 0, 0, 0, 0,
87 /* 0x10 - 0x17 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x18 - 0x1F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x20 - 0x27 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 98 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 99 /* 0x28 - 0x2F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x30 - 0x37 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 0, 0, 0, 0,
107 /* 0x38 - 0x3F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
d77a2507 111 /* 0x40 - 0x47 */
33615aa9 112 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 113 /* 0x48 - 0x4F */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 115 /* 0x50 - 0x57 */
6e3d5dfb
AK		 116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 118 /* 0x58 - 0x5F */
6e3d5dfb
AK		 119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 121 /* 0x60 - 0x67 */
6aa8b732 122 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 123 0, 0, 0, 0,
124 /* 0x68 - 0x6F */
91ed7a0e 125 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
127 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 128 /* 0x70 - 0x77 */
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 /* 0x78 - 0x7F */
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 134 /* 0x80 - 0x87 */
1d6ad207
AK		 135 Group | Group1_80, Group | Group1_81,
136 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
139 /* 0x88 - 0x8F */
140 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
141 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 142 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 143 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 144 /* 0x90 - 0x97 */
145 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
146 /* 0x98 - 0x9F */
6e3d5dfb 147 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 148 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 149 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
150 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 151 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 153 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 154 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
156 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 157 /* 0xB0 - 0xB7 */
158 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
159 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 /* 0xB8 - 0xBF */
163 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
164 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 167 /* 0xC0 - 0xC7 */
d9413cd7 168 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 169 0, ImplicitOps | Stack, 0, 0,
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 171 /* 0xC8 - 0xCF */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xD0 - 0xD7 */
174 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
175 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
176 0, 0, 0, 0,
177 /* 0xD8 - 0xDF */
178 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 179 /* 0xE0 - 0xE7 */
a6a3034c
MG		 180 0, 0, 0, 0,
181 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
182 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 183 /* 0xE8 - 0xEF */
954cd36f
GT		 184 ImplicitOps | Stack, SrcImm | ImplicitOps,
185 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 186 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
187 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 188 /* 0xF0 - 0xF7 */
189 0, 0, 0, 0,
7d858a19 190 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 191 /* 0xF8 - 0xFF */
b284be57 192 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 193 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 194};
195
038e51de 196static u16 twobyte_table[256] = {
6aa8b732 197 /* 0x00 - 0x0F */
d95058a1 198 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 199 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 200 /* 0x10 - 0x1F */
201 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
202 /* 0x20 - 0x2F */
203 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
204 0, 0, 0, 0, 0, 0, 0, 0,
205 /* 0x30 - 0x3F */
35f3f286 206 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 207 /* 0x40 - 0x47 */
208 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 /* 0x48 - 0x4F */
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 /* 0x50 - 0x5F */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0x60 - 0x6F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x70 - 0x7F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x80 - 0x8F */
bbe9abbd
NK		 224 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
225 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 228 /* 0x90 - 0x9F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0xA0 - 0xA7 */
038e51de 231 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 232 /* 0xA8 - 0xAF */
2a7c5b8b 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 234 /* 0xB0 - 0xB7 */
235 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 236 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 237 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
238 DstReg | SrcMem16 | ModRM | Mov,
239 /* 0xB8 - 0xBF */
038e51de 240 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 241 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem16 | ModRM | Mov,
243 /* 0xC0 - 0xCF */
a012e65a
SY		 244 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
245 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 246 /* 0xD0 - 0xDF */
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
248 /* 0xE0 - 0xEF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xF0 - 0xFF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
252};
253
e09d082c 254static u16 group_table[] = {
1d6ad207
AK		 255 [Group1_80*8] =
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 [Group1_81*8] =
261 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
262 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 [Group1_82*8] =
266 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
267 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 [Group1_83*8] =
271 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
272 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 275 [Group1A*8] =
276 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 277 [Group3_Byte*8] =
278 ByteOp | SrcImm | DstMem | ModRM, 0,
279 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
280 0, 0, 0, 0,
281 [Group3*8] =
41afa025 282 DstMem | SrcImm | ModRM, 0,
6eb06cb2 283 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 284 0, 0, 0, 0,
fd60754e
AK		 285 [Group4*8] =
286 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
287 0, 0, 0, 0, 0, 0,
288 [Group5*8] =
d19292e4
MG		 289 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
290 SrcMem | ModRM | Stack, 0,
fd60754e 291 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 292 [Group7*8] =
293 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 294 SrcNone | ModRM | DstMem | Mov, 0,
295 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 296};
297
298static u16 group2_table[] = {
d95058a1 299 [Group7*8] =
16286d08
AK		 300 SrcNone | ModRM, 0, 0, 0,
301 SrcNone | ModRM | DstMem | Mov, 0,
302 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 303};
304
6aa8b732
AK		 305/* EFLAGS bit definitions. */
306#define EFLG_OF (1<<11)
307#define EFLG_DF (1<<10)
308#define EFLG_SF (1<<7)
309#define EFLG_ZF (1<<6)
310#define EFLG_AF (1<<4)
311#define EFLG_PF (1<<2)
312#define EFLG_CF (1<<0)
313
314/*
315 * Instruction emulation:
316 * Most instructions are emulated directly via a fragment of inline assembly
317 * code. This allows us to save/restore EFLAGS and thus very easily pick up
318 * any modified flags.
319 */
320
05b3e0c2 321#if defined(CONFIG_X86_64)
6aa8b732
AK		 322#define _LO32 "k" /* force 32-bit operand */
323#define _STK "%%rsp" /* stack pointer */
324#elif defined(__i386__)
325#define _LO32 "" /* force 32-bit operand */
326#define _STK "%%esp" /* stack pointer */
327#endif
328
329/*
330 * These EFLAGS bits are restored from saved value during emulation, and
331 * any changes are written back to the saved value after emulation.
332 */
333#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
334
335/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 336#define _PRE_EFLAGS(_sav, _msk, _tmp) \
337 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
338 "movl %"_sav",%"_LO32 _tmp"; " \
339 "push %"_tmp"; " \
340 "push %"_tmp"; " \
341 "movl %"_msk",%"_LO32 _tmp"; " \
342 "andl %"_LO32 _tmp",("_STK"); " \
343 "pushf; " \
344 "notl %"_LO32 _tmp"; " \
345 "andl %"_LO32 _tmp",("_STK"); " \
346 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
347 "pop %"_tmp"; " \
348 "orl %"_LO32 _tmp",("_STK"); " \
349 "popf; " \
350 "pop %"_sav"; "
6aa8b732
AK		 351
352/* After executing instruction: write-back necessary bits in EFLAGS. */
353#define _POST_EFLAGS(_sav, _msk, _tmp) \
354 /* _sav |= EFLAGS & _msk; */ \
355 "pushf; " \
356 "pop %"_tmp"; " \
357 "andl %"_msk",%"_LO32 _tmp"; " \
358 "orl %"_LO32 _tmp",%"_sav"; "
359
360/* Raw emulation: instruction has two explicit operands. */
361#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
362 do { \
363 unsigned long _tmp; \
364 \
365 switch ((_dst).bytes) { \
366 case 2: \
367 __asm__ __volatile__ ( \
d77c26fc 368 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 369 _op"w %"_wx"3,%1; " \
d77c26fc 370 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 371 : "=m" (_eflags), "=m" ((_dst).val), \
372 "=&r" (_tmp) \
d77c26fc 373 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 374 break; \
375 case 4: \
376 __asm__ __volatile__ ( \
d77c26fc 377 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 378 _op"l %"_lx"3,%1; " \
d77c26fc 379 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 380 : "=m" (_eflags), "=m" ((_dst).val), \
381 "=&r" (_tmp) \
d77c26fc 382 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 383 break; \
384 case 8: \
385 __emulate_2op_8byte(_op, _src, _dst, \
386 _eflags, _qx, _qy); \
387 break; \
388 } \
389 } while (0)
390
391#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
392 do { \
77cd337f 393 unsigned long __tmp; \
d77c26fc 394 switch ((_dst).bytes) { \
6aa8b732
AK		 395 case 1: \
396 __asm__ __volatile__ ( \
d77c26fc 397 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 398 _op"b %"_bx"3,%1; " \
d77c26fc 399 _POST_EFLAGS("0", "4", "2") \
6aa8b732 400 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 401 "=&r" (__tmp) \
d77c26fc 402 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 403 break; \
404 default: \
405 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
406 _wx, _wy, _lx, _ly, _qx, _qy); \
407 break; \
408 } \
409 } while (0)
410
411/* Source operand is byte-sized and may be restricted to just %cl. */
412#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
413 __emulate_2op(_op, _src, _dst, _eflags, \
414 "b", "c", "b", "c", "b", "c", "b", "c")
415
416/* Source operand is byte, word, long or quad sized. */
417#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
418 __emulate_2op(_op, _src, _dst, _eflags, \
419 "b", "q", "w", "r", _LO32, "r", "", "r")
420
421/* Source operand is word, long or quad sized. */
422#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
423 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
424 "w", "r", _LO32, "r", "", "r")
425
426/* Instruction has only one explicit operand (no source operand). */
427#define emulate_1op(_op, _dst, _eflags) \
428 do { \
429 unsigned long _tmp; \
430 \
d77c26fc 431 switch ((_dst).bytes) { \
6aa8b732
AK		 432 case 1: \
433 __asm__ __volatile__ ( \
d77c26fc 434 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 435 _op"b %1; " \
d77c26fc 436 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 437 : "=m" (_eflags), "=m" ((_dst).val), \
438 "=&r" (_tmp) \
d77c26fc 439 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 440 break; \
441 case 2: \
442 __asm__ __volatile__ ( \
d77c26fc 443 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 444 _op"w %1; " \
d77c26fc 445 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 446 : "=m" (_eflags), "=m" ((_dst).val), \
447 "=&r" (_tmp) \
d77c26fc 448 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 449 break; \
450 case 4: \
451 __asm__ __volatile__ ( \
d77c26fc 452 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 453 _op"l %1; " \
d77c26fc 454 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 455 : "=m" (_eflags), "=m" ((_dst).val), \
456 "=&r" (_tmp) \
d77c26fc 457 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 458 break; \
459 case 8: \
460 __emulate_1op_8byte(_op, _dst, _eflags); \
461 break; \
462 } \
463 } while (0)
464
465/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 466#if defined(CONFIG_X86_64)
6aa8b732
AK		 467#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
468 do { \
469 __asm__ __volatile__ ( \
d77c26fc 470 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 471 _op"q %"_qx"3,%1; " \
d77c26fc 472 _POST_EFLAGS("0", "4", "2") \
6aa8b732 473 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 474 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 475 } while (0)
476
477#define __emulate_1op_8byte(_op, _dst, _eflags) \
478 do { \
479 __asm__ __volatile__ ( \
d77c26fc 480 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 481 _op"q %1; " \
d77c26fc 482 _POST_EFLAGS("0", "3", "2") \
6aa8b732 483 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 484 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 485 } while (0)
486
487#elif defined(__i386__)
488#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
489#define __emulate_1op_8byte(_op, _dst, _eflags)
490#endif /* __i386__ */
491
492/* Fetch next part of the instruction being emulated. */
493#define insn_fetch(_type, _size, _eip) \
494({ unsigned long _x; \
62266869 495 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 496 if (rc != 0) \
6aa8b732
AK		 497 goto done; \
498 (_eip) += (_size); \
499 (_type)_x; \
500})
501
ddcb2885
HH		 502static inline unsigned long ad_mask(struct decode_cache *c)
503{
504 return (1UL << (c->ad_bytes << 3)) - 1;
505}
506
6aa8b732 507/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 508static inline unsigned long
509address_mask(struct decode_cache *c, unsigned long reg)
510{
511 if (c->ad_bytes == sizeof(unsigned long))
512 return reg;
513 else
514 return reg & ad_mask(c);
515}
516
517static inline unsigned long
518register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
519{
520 return base + address_mask(c, reg);
521}
522
7a957275
HH		 523static inline void
524register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
525{
526 if (c->ad_bytes == sizeof(unsigned long))
527 *reg += inc;
528 else
529 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
530}
6aa8b732 531
7a957275
HH		 532static inline void jmp_rel(struct decode_cache *c, int rel)
533{
534 register_address_increment(c, &c->eip, rel);
535}
098c937b 536
7a5b56df
AK		 537static void set_seg_override(struct decode_cache *c, int seg)
538{
539 c->has_seg_override = true;
540 c->seg_override = seg;
541}
542
543static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
544{
545 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
546 return 0;
547
548 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
549}
550
551static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
552 struct decode_cache *c)
553{
554 if (!c->has_seg_override)
555 return 0;
556
557 return seg_base(ctxt, c->seg_override);
558}
559
560static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
561{
562 return seg_base(ctxt, VCPU_SREG_ES);
563}
564
565static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
566{
567 return seg_base(ctxt, VCPU_SREG_SS);
568}
569
62266869
AK		 570static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
571 struct x86_emulate_ops *ops,
572 unsigned long linear, u8 *dest)
573{
574 struct fetch_cache *fc = &ctxt->decode.fetch;
575 int rc;
576 int size;
577
578 if (linear < fc->start || linear >= fc->end) {
579 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
580 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
581 if (rc)
582 return rc;
583 fc->start = linear;
584 fc->end = linear + size;
585 }
586 *dest = fc->data[linear - fc->start];
587 return 0;
588}
589
590static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
591 struct x86_emulate_ops *ops,
592 unsigned long eip, void *dest, unsigned size)
593{
594 int rc = 0;
595
596 eip += ctxt->cs_base;
597 while (size--) {
598 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
599 if (rc)
600 return rc;
601 }
602 return 0;
603}
604
1e3c5cb0
RR		 605/*
606 * Given the 'reg' portion of a ModRM byte, and a register block, return a
607 * pointer into the block that addresses the relevant register.
608 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
609 */
610static void *decode_register(u8 modrm_reg, unsigned long *regs,
611 int highbyte_regs)
6aa8b732
AK		 612{
613 void *p;
614
615 p = &regs[modrm_reg];
616 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
617 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
618 return p;
619}
620
621static int read_descriptor(struct x86_emulate_ctxt *ctxt,
622 struct x86_emulate_ops *ops,
623 void *ptr,
624 u16 *size, unsigned long *address, int op_bytes)
625{
626 int rc;
627
628 if (op_bytes == 2)
629 op_bytes = 3;
630 *address = 0;
cebff02b
LV		 631 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
632 ctxt->vcpu);
6aa8b732
AK		 633 if (rc)
634 return rc;
cebff02b
LV		 635 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
636 ctxt->vcpu);
6aa8b732
AK		 637 return rc;
638}
639
bbe9abbd
NK		 640static int test_cc(unsigned int condition, unsigned int flags)
641{
642 int rc = 0;
643
644 switch ((condition & 15) >> 1) {
645 case 0: /* o */
646 rc |= (flags & EFLG_OF);
647 break;
648 case 1: /* b/c/nae */
649 rc |= (flags & EFLG_CF);
650 break;
651 case 2: /* z/e */
652 rc |= (flags & EFLG_ZF);
653 break;
654 case 3: /* be/na */
655 rc |= (flags & (EFLG_CF|EFLG_ZF));
656 break;
657 case 4: /* s */
658 rc |= (flags & EFLG_SF);
659 break;
660 case 5: /* p/pe */
661 rc |= (flags & EFLG_PF);
662 break;
663 case 7: /* le/ng */
664 rc |= (flags & EFLG_ZF);
665 /* fall through */
666 case 6: /* l/nge */
667 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
668 break;
669 }
670
671 /* Odd condition identifiers (lsb == 1) have inverted sense. */
672 return (!!rc ^ (condition & 1));
673}
674
3c118e24
AK		 675static void decode_register_operand(struct operand *op,
676 struct decode_cache *c,
3c118e24
AK		 677 int inhibit_bytereg)
678{
33615aa9 679 unsigned reg = c->modrm_reg;
9f1ef3f8 680 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 681
682 if (!(c->d & ModRM))
683 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 684 op->type = OP_REG;
685 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 686 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 687 op->val = *(u8 *)op->ptr;
688 op->bytes = 1;
689 } else {
33615aa9 690 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 691 op->bytes = c->op_bytes;
692 switch (op->bytes) {
693 case 2:
694 op->val = *(u16 *)op->ptr;
695 break;
696 case 4:
697 op->val = *(u32 *)op->ptr;
698 break;
699 case 8:
700 op->val = *(u64 *) op->ptr;
701 break;
702 }
703 }
704 op->orig_val = op->val;
705}
706
1c73ef66
AK		 707static int decode_modrm(struct x86_emulate_ctxt *ctxt,
708 struct x86_emulate_ops *ops)
709{
710 struct decode_cache *c = &ctxt->decode;
711 u8 sib;
f5b4edcd 712 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 713 int rc = 0;
714
715 if (c->rex_prefix) {
716 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
717 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
718 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
719 }
720
721 c->modrm = insn_fetch(u8, 1, c->eip);
722 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
723 c->modrm_reg |= (c->modrm & 0x38) >> 3;
724 c->modrm_rm |= (c->modrm & 0x07);
725 c->modrm_ea = 0;
726 c->use_modrm_ea = 1;
727
728 if (c->modrm_mod == 3) {
107d6d2e
AK		 729 c->modrm_ptr = decode_register(c->modrm_rm,
730 c->regs, c->d & ByteOp);
731 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 732 return rc;
733 }
734
735 if (c->ad_bytes == 2) {
736 unsigned bx = c->regs[VCPU_REGS_RBX];
737 unsigned bp = c->regs[VCPU_REGS_RBP];
738 unsigned si = c->regs[VCPU_REGS_RSI];
739 unsigned di = c->regs[VCPU_REGS_RDI];
740
741 /* 16-bit ModR/M decode. */
742 switch (c->modrm_mod) {
743 case 0:
744 if (c->modrm_rm == 6)
745 c->modrm_ea += insn_fetch(u16, 2, c->eip);
746 break;
747 case 1:
748 c->modrm_ea += insn_fetch(s8, 1, c->eip);
749 break;
750 case 2:
751 c->modrm_ea += insn_fetch(u16, 2, c->eip);
752 break;
753 }
754 switch (c->modrm_rm) {
755 case 0:
756 c->modrm_ea += bx + si;
757 break;
758 case 1:
759 c->modrm_ea += bx + di;
760 break;
761 case 2:
762 c->modrm_ea += bp + si;
763 break;
764 case 3:
765 c->modrm_ea += bp + di;
766 break;
767 case 4:
768 c->modrm_ea += si;
769 break;
770 case 5:
771 c->modrm_ea += di;
772 break;
773 case 6:
774 if (c->modrm_mod != 0)
775 c->modrm_ea += bp;
776 break;
777 case 7:
778 c->modrm_ea += bx;
779 break;
780 }
781 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
782 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 783 if (!c->has_seg_override)
784 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 785 c->modrm_ea = (u16)c->modrm_ea;
786 } else {
787 /* 32/64-bit ModR/M decode. */
84411d85 788 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 789 sib = insn_fetch(u8, 1, c->eip);
790 index_reg |= (sib >> 3) & 7;
791 base_reg |= sib & 7;
792 scale = sib >> 6;
793
dc71d0f1
AK		 794 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
795 c->modrm_ea += insn_fetch(s32, 4, c->eip);
796 else
1c73ef66 797 c->modrm_ea += c->regs[base_reg];
dc71d0f1 798 if (index_reg != 4)
1c73ef66 799 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 800 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
801 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 802 c->rip_relative = 1;
84411d85 803 } else
1c73ef66 804 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 805 switch (c->modrm_mod) {
806 case 0:
807 if (c->modrm_rm == 5)
808 c->modrm_ea += insn_fetch(s32, 4, c->eip);
809 break;
810 case 1:
811 c->modrm_ea += insn_fetch(s8, 1, c->eip);
812 break;
813 case 2:
814 c->modrm_ea += insn_fetch(s32, 4, c->eip);
815 break;
816 }
817 }
1c73ef66
AK		 818done:
819 return rc;
820}
821
822static int decode_abs(struct x86_emulate_ctxt *ctxt,
823 struct x86_emulate_ops *ops)
824{
825 struct decode_cache *c = &ctxt->decode;
826 int rc = 0;
827
828 switch (c->ad_bytes) {
829 case 2:
830 c->modrm_ea = insn_fetch(u16, 2, c->eip);
831 break;
832 case 4:
833 c->modrm_ea = insn_fetch(u32, 4, c->eip);
834 break;
835 case 8:
836 c->modrm_ea = insn_fetch(u64, 8, c->eip);
837 break;
838 }
839done:
840 return rc;
841}
842
6aa8b732 843int
8b4caf66 844x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 845{
e4e03ded 846 struct decode_cache *c = &ctxt->decode;
6aa8b732 847 int rc = 0;
6aa8b732 848 int mode = ctxt->mode;
e09d082c 849 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 850
851 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 852
e4e03ded 853 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 854 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 855 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 856 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 857
858 switch (mode) {
859 case X86EMUL_MODE_REAL:
860 case X86EMUL_MODE_PROT16:
f21b8bf4 861 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 862 break;
863 case X86EMUL_MODE_PROT32:
f21b8bf4 864 def_op_bytes = def_ad_bytes = 4;
6aa8b732 865 break;
05b3e0c2 866#ifdef CONFIG_X86_64
6aa8b732 867 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 868 def_op_bytes = 4;
869 def_ad_bytes = 8;
6aa8b732
AK		 870 break;
871#endif
872 default:
873 return -1;
874 }
875
f21b8bf4
AK		 876 c->op_bytes = def_op_bytes;
877 c->ad_bytes = def_ad_bytes;
878
6aa8b732 879 /* Legacy prefixes. */
b4c6abfe 880 for (;;) {
e4e03ded 881 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 882 case 0x66: /* operand-size override */
f21b8bf4
AK		 883 /* switch between 2/4 bytes */
884 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 885 break;
886 case 0x67: /* address-size override */
887 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 888 /* switch between 4/8 bytes */
f21b8bf4 889 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 890 else
e4e03ded 891 /* switch between 2/4 bytes */
f21b8bf4 892 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 893 break;
7a5b56df 894 case 0x26: /* ES override */
6aa8b732 895 case 0x2e: /* CS override */
7a5b56df 896 case 0x36: /* SS override */
6aa8b732 897 case 0x3e: /* DS override */
7a5b56df 898 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 899 break;
900 case 0x64: /* FS override */
6aa8b732 901 case 0x65: /* GS override */
7a5b56df 902 set_seg_override(c, c->b & 7);
6aa8b732 903 break;
b4c6abfe
LV		 904 case 0x40 ... 0x4f: /* REX */
905 if (mode != X86EMUL_MODE_PROT64)
906 goto done_prefixes;
33615aa9 907 c->rex_prefix = c->b;
b4c6abfe 908 continue;
6aa8b732 909 case 0xf0: /* LOCK */
e4e03ded 910 c->lock_prefix = 1;
6aa8b732 911 break;
ae6200ba 912 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 913 c->rep_prefix = REPNE_PREFIX;
914 break;
6aa8b732 915 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 916 c->rep_prefix = REPE_PREFIX;
6aa8b732 917 break;
6aa8b732
AK		 918 default:
919 goto done_prefixes;
920 }
b4c6abfe
LV		 921
922 /* Any legacy prefix after a REX prefix nullifies its effect. */
923
33615aa9 924 c->rex_prefix = 0;
6aa8b732
AK		 925 }
926
927done_prefixes:
928
929 /* REX prefix. */
1c73ef66 930 if (c->rex_prefix)
33615aa9 931 if (c->rex_prefix & 8)
e4e03ded 932 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 933
934 /* Opcode byte(s). */
e4e03ded
LV		 935 c->d = opcode_table[c->b];
936 if (c->d == 0) {
6aa8b732 937 /* Two-byte opcode? */
e4e03ded
LV		 938 if (c->b == 0x0f) {
939 c->twobyte = 1;
940 c->b = insn_fetch(u8, 1, c->eip);
941 c->d = twobyte_table[c->b];
6aa8b732 942 }
e09d082c 943 }
6aa8b732 944
e09d082c
AK		 945 if (c->d & Group) {
946 group = c->d & GroupMask;
947 c->modrm = insn_fetch(u8, 1, c->eip);
948 --c->eip;
949
950 group = (group << 3) + ((c->modrm >> 3) & 7);
951 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
952 c->d = group2_table[group];
953 else
954 c->d = group_table[group];
955 }
956
957 /* Unrecognised? */
958 if (c->d == 0) {
959 DPRINTF("Cannot emulate %02x\n", c->b);
960 return -1;
6aa8b732
AK		 961 }
962
6e3d5dfb
AK		 963 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
964 c->op_bytes = 8;
965
6aa8b732 966 /* ModRM and SIB bytes. */
1c73ef66
AK		 967 if (c->d & ModRM)
968 rc = decode_modrm(ctxt, ops);
969 else if (c->d & MemAbs)
970 rc = decode_abs(ctxt, ops);
971 if (rc)
972 goto done;
6aa8b732 973
7a5b56df
AK		 974 if (!c->has_seg_override)
975 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 976
7a5b56df
AK		 977 if (!(!c->twobyte && c->b == 0x8d))
978 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 979
980 if (c->ad_bytes != 8)
981 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 982 /*
983 * Decode and fetch the source operand: register, memory
984 * or immediate.
985 */
e4e03ded 986 switch (c->d & SrcMask) {
6aa8b732
AK		 987 case SrcNone:
988 break;
989 case SrcReg:
9f1ef3f8 990 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 991 break;
992 case SrcMem16:
e4e03ded 993 c->src.bytes = 2;
6aa8b732
AK		 994 goto srcmem_common;
995 case SrcMem32:
e4e03ded 996 c->src.bytes = 4;
6aa8b732
AK		 997 goto srcmem_common;
998 case SrcMem:
e4e03ded
LV		 999 c->src.bytes = (c->d & ByteOp) ? 1 :
1000 c->op_bytes;
b85b9ee9 1001 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1002 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1003 break;
d77c26fc 1004 srcmem_common:
4e62417b
AJ		 1005 /*
1006 * For instructions with a ModR/M byte, switch to register
1007 * access if Mod = 3.
1008 */
e4e03ded
LV		 1009 if ((c->d & ModRM) && c->modrm_mod == 3) {
1010 c->src.type = OP_REG;
66b85505 1011 c->src.val = c->modrm_val;
107d6d2e 1012 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1013 break;
1014 }
e4e03ded 1015 c->src.type = OP_MEM;
6aa8b732
AK		 1016 break;
1017 case SrcImm:
e4e03ded
LV		 1018 c->src.type = OP_IMM;
1019 c->src.ptr = (unsigned long *)c->eip;
1020 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1021 if (c->src.bytes == 8)
1022 c->src.bytes = 4;
6aa8b732 1023 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1024 switch (c->src.bytes) {
6aa8b732 1025 case 1:
e4e03ded 1026 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1027 break;
1028 case 2:
e4e03ded 1029 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1030 break;
1031 case 4:
e4e03ded 1032 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1033 break;
1034 }
1035 break;
1036 case SrcImmByte:
e4e03ded
LV		 1037 c->src.type = OP_IMM;
1038 c->src.ptr = (unsigned long *)c->eip;
1039 c->src.bytes = 1;
1040 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1041 break;
1042 }
1043
038e51de 1044 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1045 switch (c->d & DstMask) {
038e51de
AK		 1046 case ImplicitOps:
1047 /* Special instructions do their own operand decoding. */
8b4caf66 1048 return 0;
038e51de 1049 case DstReg:
9f1ef3f8 1050 decode_register_operand(&c->dst, c,
3c118e24 1051 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1052 break;
1053 case DstMem:
e4e03ded 1054 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1055 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1056 c->dst.type = OP_REG;
66b85505 1057 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1058 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1059 break;
1060 }
8b4caf66
LV		 1061 c->dst.type = OP_MEM;
1062 break;
1063 }
1064
f5b4edcd
AK		 1065 if (c->rip_relative)
1066 c->modrm_ea += c->eip;
1067
8b4caf66
LV		 1068done:
1069 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1070}
1071
8cdbd2c9
LV		 1072static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1073{
1074 struct decode_cache *c = &ctxt->decode;
1075
1076 c->dst.type = OP_MEM;
1077 c->dst.bytes = c->op_bytes;
1078 c->dst.val = c->src.val;
7a957275 1079 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1080 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1081 c->regs[VCPU_REGS_RSP]);
1082}
1083
1084static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1085 struct x86_emulate_ops *ops)
1086{
1087 struct decode_cache *c = &ctxt->decode;
1088 int rc;
1089
7a5b56df 1090 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1091 c->regs[VCPU_REGS_RSP]),
1092 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1093 if (rc != 0)
1094 return rc;
1095
7a957275 1096 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1097
1098 return 0;
1099}
1100
05f086f8 1101static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1102{
05f086f8 1103 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1104 switch (c->modrm_reg) {
1105 case 0: /* rol */
05f086f8 1106 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1107 break;
1108 case 1: /* ror */
05f086f8 1109 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1110 break;
1111 case 2: /* rcl */
05f086f8 1112 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1113 break;
1114 case 3: /* rcr */
05f086f8 1115 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1116 break;
1117 case 4: /* sal/shl */
1118 case 6: /* sal/shl */
05f086f8 1119 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1120 break;
1121 case 5: /* shr */
05f086f8 1122 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1123 break;
1124 case 7: /* sar */
05f086f8 1125 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1126 break;
1127 }
1128}
1129
1130static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1131 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1132{
1133 struct decode_cache *c = &ctxt->decode;
1134 int rc = 0;
1135
1136 switch (c->modrm_reg) {
1137 case 0 ... 1: /* test */
05f086f8 1138 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1139 break;
1140 case 2: /* not */
1141 c->dst.val = ~c->dst.val;
1142 break;
1143 case 3: /* neg */
05f086f8 1144 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1145 break;
1146 default:
1147 DPRINTF("Cannot emulate %02x\n", c->b);
1148 rc = X86EMUL_UNHANDLEABLE;
1149 break;
1150 }
8cdbd2c9
LV		 1151 return rc;
1152}
1153
1154static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1155 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1156{
1157 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1158
1159 switch (c->modrm_reg) {
1160 case 0: /* inc */
05f086f8 1161 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1162 break;
1163 case 1: /* dec */
05f086f8 1164 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1165 break;
d19292e4
MG		 1166 case 2: /* call near abs */ {
1167 long int old_eip;
1168 old_eip = c->eip;
1169 c->eip = c->src.val;
1170 c->src.val = old_eip;
1171 emulate_push(ctxt);
1172 break;
1173 }
8cdbd2c9 1174 case 4: /* jmp abs */
fd60754e 1175 c->eip = c->src.val;
8cdbd2c9
LV		 1176 break;
1177 case 6: /* push */
fd60754e 1178 emulate_push(ctxt);
8cdbd2c9 1179 break;
8cdbd2c9
LV		 1180 }
1181 return 0;
1182}
1183
1184static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1185 struct x86_emulate_ops *ops,
e8d8d7fe 1186 unsigned long memop)
8cdbd2c9
LV		 1187{
1188 struct decode_cache *c = &ctxt->decode;
1189 u64 old, new;
1190 int rc;
1191
e8d8d7fe 1192 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1193 if (rc != 0)
1194 return rc;
1195
1196 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1197 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1198
1199 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1200 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1201 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1202
1203 } else {
1204 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1205 (u32) c->regs[VCPU_REGS_RBX];
1206
e8d8d7fe 1207 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1208 if (rc != 0)
1209 return rc;
05f086f8 1210 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1211 }
1212 return 0;
1213}
1214
1215static inline int writeback(struct x86_emulate_ctxt *ctxt,
1216 struct x86_emulate_ops *ops)
1217{
1218 int rc;
1219 struct decode_cache *c = &ctxt->decode;
1220
1221 switch (c->dst.type) {
1222 case OP_REG:
1223 /* The 4-byte case *is* correct:
1224 * in 64-bit mode we zero-extend.
1225 */
1226 switch (c->dst.bytes) {
1227 case 1:
1228 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1229 break;
1230 case 2:
1231 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1232 break;
1233 case 4:
1234 *c->dst.ptr = (u32)c->dst.val;
1235 break; /* 64b: zero-ext */
1236 case 8:
1237 *c->dst.ptr = c->dst.val;
1238 break;
1239 }
1240 break;
1241 case OP_MEM:
1242 if (c->lock_prefix)
1243 rc = ops->cmpxchg_emulated(
1244 (unsigned long)c->dst.ptr,
1245 &c->dst.orig_val,
1246 &c->dst.val,
1247 c->dst.bytes,
1248 ctxt->vcpu);
1249 else
1250 rc = ops->write_emulated(
1251 (unsigned long)c->dst.ptr,
1252 &c->dst.val,
1253 c->dst.bytes,
1254 ctxt->vcpu);
1255 if (rc != 0)
1256 return rc;
a01af5ec
LV		 1257 break;
1258 case OP_NONE:
1259 /* no writeback */
1260 break;
8cdbd2c9
LV		 1261 default:
1262 break;
1263 }
1264 return 0;
1265}
1266
8b4caf66 1267int
1be3aa47 1268x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1269{
e8d8d7fe 1270 unsigned long memop = 0;
8b4caf66 1271 u64 msr_data;
3427318f 1272 unsigned long saved_eip = 0;
8b4caf66 1273 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1274 unsigned int port;
1275 int io_dir_in;
1be3aa47 1276 int rc = 0;
8b4caf66 1277
3427318f
LV		 1278 /* Shadow copy of register state. Committed on successful emulation.
1279 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1280 * modify them.
1281 */
1282
ad312c7c 1283 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1284 saved_eip = c->eip;
1285
c7e75a3d 1286 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1287 memop = c->modrm_ea;
8b4caf66 1288
b9fa9d6b
AK		 1289 if (c->rep_prefix && (c->d & String)) {
1290 /* All REP prefixes have the same first termination condition */
1291 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1292 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1293 goto done;
1294 }
1295 /* The second termination condition only applies for REPE
1296 * and REPNE. Test if the repeat string operation prefix is
1297 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1298 * corresponding termination condition according to:
1299 * - if REPE/REPZ and ZF = 0 then done
1300 * - if REPNE/REPNZ and ZF = 1 then done
1301 */
1302 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1303 (c->b == 0xae) || (c->b == 0xaf)) {
1304 if ((c->rep_prefix == REPE_PREFIX) &&
1305 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1306 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1307 goto done;
1308 }
1309 if ((c->rep_prefix == REPNE_PREFIX) &&
1310 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1311 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1312 goto done;
1313 }
1314 }
1315 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1316 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1317 }
1318
8b4caf66 1319 if (c->src.type == OP_MEM) {
e8d8d7fe 1320 c->src.ptr = (unsigned long *)memop;
8b4caf66 1321 c->src.val = 0;
d77c26fc
MD		 1322 rc = ops->read_emulated((unsigned long)c->src.ptr,
1323 &c->src.val,
1324 c->src.bytes,
1325 ctxt->vcpu);
1326 if (rc != 0)
8b4caf66
LV		 1327 goto done;
1328 c->src.orig_val = c->src.val;
1329 }
1330
1331 if ((c->d & DstMask) == ImplicitOps)
1332 goto special_insn;
1333
1334
1335 if (c->dst.type == OP_MEM) {
e8d8d7fe 1336 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1337 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1338 c->dst.val = 0;
e4e03ded
LV		 1339 if (c->d & BitOp) {
1340 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1341
e4e03ded
LV		 1342 c->dst.ptr = (void *)c->dst.ptr +
1343 (c->src.val & mask) / 8;
038e51de 1344 }
e4e03ded
LV		 1345 if (!(c->d & Mov) &&
1346 /* optimisation - avoid slow emulated read */
1347 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1348 &c->dst.val,
1349 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1350 goto done;
038e51de 1351 }
e4e03ded 1352 c->dst.orig_val = c->dst.val;
038e51de 1353
018a98db
AK		 1354special_insn:
1355
e4e03ded 1356 if (c->twobyte)
6aa8b732
AK		 1357 goto twobyte_insn;
1358
e4e03ded 1359 switch (c->b) {
6aa8b732
AK		 1360 case 0x00 ... 0x05:
1361 add: /* add */
05f086f8 1362 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1363 break;
1364 case 0x08 ... 0x0d:
1365 or: /* or */
05f086f8 1366 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1367 break;
1368 case 0x10 ... 0x15:
1369 adc: /* adc */
05f086f8 1370 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1371 break;
1372 case 0x18 ... 0x1d:
1373 sbb: /* sbb */
05f086f8 1374 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1375 break;
19eb938e 1376 case 0x20 ... 0x23:
6aa8b732 1377 and: /* and */
05f086f8 1378 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1379 break;
19eb938e 1380 case 0x24: /* and al imm8 */
e4e03ded
LV		 1381 c->dst.type = OP_REG;
1382 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1383 c->dst.val = *(u8 *)c->dst.ptr;
1384 c->dst.bytes = 1;
1385 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1386 goto and;
1387 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1388 c->dst.type = OP_REG;
1389 c->dst.bytes = c->op_bytes;
1390 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1391 if (c->op_bytes == 2)
1392 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1393 else
e4e03ded
LV		 1394 c->dst.val = *(u32 *)c->dst.ptr;
1395 c->dst.orig_val = c->dst.val;
19eb938e 1396 goto and;
6aa8b732
AK		 1397 case 0x28 ... 0x2d:
1398 sub: /* sub */
05f086f8 1399 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1400 break;
1401 case 0x30 ... 0x35:
1402 xor: /* xor */
05f086f8 1403 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1404 break;
1405 case 0x38 ... 0x3d:
1406 cmp: /* cmp */
05f086f8 1407 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1408 break;
33615aa9
AK		 1409 case 0x40 ... 0x47: /* inc r16/r32 */
1410 emulate_1op("inc", c->dst, ctxt->eflags);
1411 break;
1412 case 0x48 ... 0x4f: /* dec r16/r32 */
1413 emulate_1op("dec", c->dst, ctxt->eflags);
1414 break;
1415 case 0x50 ... 0x57: /* push reg */
1416 c->dst.type = OP_MEM;
1417 c->dst.bytes = c->op_bytes;
1418 c->dst.val = c->src.val;
7a957275 1419 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1420 -c->op_bytes);
1421 c->dst.ptr = (void *) register_address(
7a5b56df 1422 c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1423 break;
1424 case 0x58 ... 0x5f: /* pop reg */
1425 pop_instruction:
7a5b56df 1426 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1427 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1428 c->op_bytes, ctxt->vcpu)) != 0)
1429 goto done;
1430
7a957275 1431 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1432 c->op_bytes);
1433 c->dst.type = OP_NONE; /* Disable writeback. */
1434 break;
6aa8b732 1435 case 0x63: /* movsxd */
8b4caf66 1436 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1437 goto cannot_emulate;
e4e03ded 1438 c->dst.val = (s32) c->src.val;
6aa8b732 1439 break;
91ed7a0e 1440 case 0x68: /* push imm */
018a98db 1441 case 0x6a: /* push imm8 */
018a98db
AK		 1442 emulate_push(ctxt);
1443 break;
1444 case 0x6c: /* insb */
1445 case 0x6d: /* insw/insd */
1446 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1447 1,
1448 (c->d & ByteOp) ? 1 : c->op_bytes,
1449 c->rep_prefix ?
e4706772 1450 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1451 (ctxt->eflags & EFLG_DF),
7a5b56df 1452 register_address(c, es_base(ctxt),
018a98db
AK		 1453 c->regs[VCPU_REGS_RDI]),
1454 c->rep_prefix,
1455 c->regs[VCPU_REGS_RDX]) == 0) {
1456 c->eip = saved_eip;
1457 return -1;
1458 }
1459 return 0;
1460 case 0x6e: /* outsb */
1461 case 0x6f: /* outsw/outsd */
1462 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1463 0,
1464 (c->d & ByteOp) ? 1 : c->op_bytes,
1465 c->rep_prefix ?
e4706772 1466 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1467 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1468 register_address(c,
1469 seg_override_base(ctxt, c),
018a98db
AK		 1470 c->regs[VCPU_REGS_RSI]),
1471 c->rep_prefix,
1472 c->regs[VCPU_REGS_RDX]) == 0) {
1473 c->eip = saved_eip;
1474 return -1;
1475 }
1476 return 0;
1477 case 0x70 ... 0x7f: /* jcc (short) */ {
1478 int rel = insn_fetch(s8, 1, c->eip);
1479
1480 if (test_cc(c->b, ctxt->eflags))
7a957275 1481 jmp_rel(c, rel);
018a98db
AK		 1482 break;
1483 }
6aa8b732 1484 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1485 switch (c->modrm_reg) {
6aa8b732
AK		 1486 case 0:
1487 goto add;
1488 case 1:
1489 goto or;
1490 case 2:
1491 goto adc;
1492 case 3:
1493 goto sbb;
1494 case 4:
1495 goto and;
1496 case 5:
1497 goto sub;
1498 case 6:
1499 goto xor;
1500 case 7:
1501 goto cmp;
1502 }
1503 break;
1504 case 0x84 ... 0x85:
05f086f8 1505 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1506 break;
1507 case 0x86 ... 0x87: /* xchg */
b13354f8 1508 xchg:
6aa8b732 1509 /* Write back the register source. */
e4e03ded 1510 switch (c->dst.bytes) {
6aa8b732 1511 case 1:
e4e03ded 1512 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1513 break;
1514 case 2:
e4e03ded 1515 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1516 break;
1517 case 4:
e4e03ded 1518 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1519 break; /* 64b reg: zero-extend */
1520 case 8:
e4e03ded 1521 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1522 break;
1523 }
1524 /*
1525 * Write back the memory destination with implicit LOCK
1526 * prefix.
1527 */
e4e03ded
LV		 1528 c->dst.val = c->src.val;
1529 c->lock_prefix = 1;
6aa8b732 1530 break;
6aa8b732 1531 case 0x88 ... 0x8b: /* mov */
7de75248 1532 goto mov;
38d5bc6d
GT		 1533 case 0x8c: { /* mov r/m, sreg */
1534 struct kvm_segment segreg;
1535
1536 if (c->modrm_reg <= 5)
1537 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1538 else {
1539 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1540 c->modrm);
1541 goto cannot_emulate;
1542 }
1543 c->dst.val = segreg.selector;
1544 break;
1545 }
7e0b54b1 1546 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1547 c->dst.val = c->modrm_ea;
7e0b54b1 1548 break;
4257198a
GT		 1549 case 0x8e: { /* mov seg, r/m16 */
1550 uint16_t sel;
1551 int type_bits;
1552 int err;
1553
1554 sel = c->src.val;
1555 if (c->modrm_reg <= 5) {
1556 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1557 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1558 type_bits, c->modrm_reg);
1559 } else {
1560 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1561 c->modrm);
1562 goto cannot_emulate;
1563 }
1564
1565 if (err < 0)
1566 goto cannot_emulate;
1567
1568 c->dst.type = OP_NONE; /* Disable writeback. */
1569 break;
1570 }
6aa8b732 1571 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1572 rc = emulate_grp1a(ctxt, ops);
1573 if (rc != 0)
6aa8b732 1574 goto done;
6aa8b732 1575 break;
b13354f8
MG		 1576 case 0x90: /* nop / xchg r8,rax */
1577 if (!(c->rex_prefix & 1)) { /* nop */
1578 c->dst.type = OP_NONE;
1579 break;
1580 }
1581 case 0x91 ... 0x97: /* xchg reg,rax */
1582 c->src.type = c->dst.type = OP_REG;
1583 c->src.bytes = c->dst.bytes = c->op_bytes;
1584 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1585 c->src.val = *(c->src.ptr);
1586 goto xchg;
fd2a7608 1587 case 0x9c: /* pushf */
05f086f8 1588 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1589 emulate_push(ctxt);
1590 break;
535eabcf 1591 case 0x9d: /* popf */
05f086f8 1592 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1593 goto pop_instruction;
018a98db
AK		 1594 case 0xa0 ... 0xa1: /* mov */
1595 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1596 c->dst.val = c->src.val;
1597 break;
1598 case 0xa2 ... 0xa3: /* mov */
1599 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1600 break;
6aa8b732 1601 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1602 c->dst.type = OP_MEM;
1603 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1604 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1605 es_base(ctxt),
e4e03ded 1606 c->regs[VCPU_REGS_RDI]);
e4706772 1607 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1608 seg_override_base(ctxt, c),
e4e03ded
LV		 1609 c->regs[VCPU_REGS_RSI]),
1610 &c->dst.val,
1611 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1612 goto done;
7a957275 1613 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1614 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1615 : c->dst.bytes);
7a957275 1616 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1617 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1618 : c->dst.bytes);
6aa8b732
AK		 1619 break;
1620 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1621 c->src.type = OP_NONE; /* Disable writeback. */
1622 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1623 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1624 seg_override_base(ctxt, c),
d7e5117a
GT		 1625 c->regs[VCPU_REGS_RSI]);
1626 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1627 &c->src.val,
1628 c->src.bytes,
1629 ctxt->vcpu)) != 0)
1630 goto done;
1631
1632 c->dst.type = OP_NONE; /* Disable writeback. */
1633 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1634 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1635 es_base(ctxt),
d7e5117a
GT		 1636 c->regs[VCPU_REGS_RDI]);
1637 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1638 &c->dst.val,
1639 c->dst.bytes,
1640 ctxt->vcpu)) != 0)
1641 goto done;
1642
1643 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1644
1645 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1646
7a957275 1647 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1648 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1649 : c->src.bytes);
7a957275 1650 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1651 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1652 : c->dst.bytes);
1653
1654 break;
6aa8b732 1655 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1656 c->dst.type = OP_MEM;
1657 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1658 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1659 es_base(ctxt),
a7e6c88a 1660 c->regs[VCPU_REGS_RDI]);
e4e03ded 1661 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1662 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1663 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1664 : c->dst.bytes);
6aa8b732
AK		 1665 break;
1666 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1667 c->dst.type = OP_REG;
1668 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1669 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1670 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1671 seg_override_base(ctxt, c),
a7e6c88a
SY		 1672 c->regs[VCPU_REGS_RSI]),
1673 &c->dst.val,
1674 c->dst.bytes,
1675 ctxt->vcpu)) != 0)
6aa8b732 1676 goto done;
7a957275 1677 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1678 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1679 : c->dst.bytes);
6aa8b732
AK		 1680 break;
1681 case 0xae ... 0xaf: /* scas */
1682 DPRINTF("Urk! I don't handle SCAS.\n");
1683 goto cannot_emulate;
a5e2e82b 1684 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1685 goto mov;
018a98db
AK		 1686 case 0xc0 ... 0xc1:
1687 emulate_grp2(ctxt);
1688 break;
111de5d6
AK		 1689 case 0xc3: /* ret */
1690 c->dst.ptr = &c->eip;
1691 goto pop_instruction;
018a98db
AK		 1692 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1693 mov:
1694 c->dst.val = c->src.val;
1695 break;
1696 case 0xd0 ... 0xd1: /* Grp2 */
1697 c->src.val = 1;
1698 emulate_grp2(ctxt);
1699 break;
1700 case 0xd2 ... 0xd3: /* Grp2 */
1701 c->src.val = c->regs[VCPU_REGS_RCX];
1702 emulate_grp2(ctxt);
1703 break;
a6a3034c
MG		 1704 case 0xe4: /* inb */
1705 case 0xe5: /* in */
1706 port = insn_fetch(u8, 1, c->eip);
1707 io_dir_in = 1;
1708 goto do_io;
1709 case 0xe6: /* outb */
1710 case 0xe7: /* out */
1711 port = insn_fetch(u8, 1, c->eip);
1712 io_dir_in = 0;
1713 goto do_io;
1a52e051
NK		 1714 case 0xe8: /* call (near) */ {
1715 long int rel;
e4e03ded 1716 switch (c->op_bytes) {
1a52e051 1717 case 2:
e4e03ded 1718 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1719 break;
1720 case 4:
e4e03ded 1721 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1722 break;
1a52e051
NK		 1723 default:
1724 DPRINTF("Call: Invalid op_bytes\n");
1725 goto cannot_emulate;
1726 }
e4e03ded 1727 c->src.val = (unsigned long) c->eip;
7a957275 1728 jmp_rel(c, rel);
e4e03ded 1729 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1730 emulate_push(ctxt);
1731 break;
1a52e051
NK		 1732 }
1733 case 0xe9: /* jmp rel */
954cd36f
GT		 1734 goto jmp;
1735 case 0xea: /* jmp far */ {
1736 uint32_t eip;
1737 uint16_t sel;
1738
1739 switch (c->op_bytes) {
1740 case 2:
1741 eip = insn_fetch(u16, 2, c->eip);
1742 break;
1743 case 4:
1744 eip = insn_fetch(u32, 4, c->eip);
1745 break;
1746 default:
1747 DPRINTF("jmp far: Invalid op_bytes\n");
1748 goto cannot_emulate;
1749 }
1750 sel = insn_fetch(u16, 2, c->eip);
1751 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1752 DPRINTF("jmp far: Failed to load CS descriptor\n");
1753 goto cannot_emulate;
1754 }
1755
1756 c->eip = eip;
1757 break;
1758 }
1759 case 0xeb:
1760 jmp: /* jmp rel short */
7a957275 1761 jmp_rel(c, c->src.val);
a01af5ec 1762 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1763 break;
a6a3034c
MG		 1764 case 0xec: /* in al,dx */
1765 case 0xed: /* in (e/r)ax,dx */
1766 port = c->regs[VCPU_REGS_RDX];
1767 io_dir_in = 1;
1768 goto do_io;
1769 case 0xee: /* out al,dx */
1770 case 0xef: /* out (e/r)ax,dx */
1771 port = c->regs[VCPU_REGS_RDX];
1772 io_dir_in = 0;
1773 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1774 (c->d & ByteOp) ? 1 : c->op_bytes,
1775 port) != 0) {
1776 c->eip = saved_eip;
1777 goto cannot_emulate;
1778 }
1779 return 0;
111de5d6 1780 case 0xf4: /* hlt */
ad312c7c 1781 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1782 break;
111de5d6
AK		 1783 case 0xf5: /* cmc */
1784 /* complement carry flag from eflags reg */
1785 ctxt->eflags ^= EFLG_CF;
1786 c->dst.type = OP_NONE; /* Disable writeback. */
1787 break;
018a98db
AK		 1788 case 0xf6 ... 0xf7: /* Grp3 */
1789 rc = emulate_grp3(ctxt, ops);
1790 if (rc != 0)
1791 goto done;
1792 break;
111de5d6
AK		 1793 case 0xf8: /* clc */
1794 ctxt->eflags &= ~EFLG_CF;
1795 c->dst.type = OP_NONE; /* Disable writeback. */
1796 break;
1797 case 0xfa: /* cli */
1798 ctxt->eflags &= ~X86_EFLAGS_IF;
1799 c->dst.type = OP_NONE; /* Disable writeback. */
1800 break;
1801 case 0xfb: /* sti */
1802 ctxt->eflags |= X86_EFLAGS_IF;
1803 c->dst.type = OP_NONE; /* Disable writeback. */
1804 break;
fb4616f4
MG		 1805 case 0xfc: /* cld */
1806 ctxt->eflags &= ~EFLG_DF;
1807 c->dst.type = OP_NONE; /* Disable writeback. */
1808 break;
1809 case 0xfd: /* std */
1810 ctxt->eflags |= EFLG_DF;
1811 c->dst.type = OP_NONE; /* Disable writeback. */
1812 break;
018a98db
AK		 1813 case 0xfe ... 0xff: /* Grp4/Grp5 */
1814 rc = emulate_grp45(ctxt, ops);
1815 if (rc != 0)
1816 goto done;
1817 break;
6aa8b732 1818 }
018a98db
AK		 1819
1820writeback:
1821 rc = writeback(ctxt, ops);
1822 if (rc != 0)
1823 goto done;
1824
1825 /* Commit shadow register state. */
ad312c7c 1826 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1827 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1828
1829done:
1830 if (rc == X86EMUL_UNHANDLEABLE) {
1831 c->eip = saved_eip;
1832 return -1;
1833 }
1834 return 0;
6aa8b732
AK		 1835
1836twobyte_insn:
e4e03ded 1837 switch (c->b) {
6aa8b732 1838 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1839 switch (c->modrm_reg) {
6aa8b732
AK		 1840 u16 size;
1841 unsigned long address;
1842
aca7f966 1843 case 0: /* vmcall */
e4e03ded 1844 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1845 goto cannot_emulate;
1846
7aa81cc0
AL		 1847 rc = kvm_fix_hypercall(ctxt->vcpu);
1848 if (rc)
1849 goto done;
1850
33e3885d 1851 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1852 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1853 /* Disable writeback. */
1854 c->dst.type = OP_NONE;
aca7f966 1855 break;
6aa8b732 1856 case 2: /* lgdt */
e4e03ded
LV		 1857 rc = read_descriptor(ctxt, ops, c->src.ptr,
1858 &size, &address, c->op_bytes);
6aa8b732
AK		 1859 if (rc)
1860 goto done;
1861 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1862 /* Disable writeback. */
1863 c->dst.type = OP_NONE;
6aa8b732 1864 break;
aca7f966 1865 case 3: /* lidt/vmmcall */
e4e03ded 1866 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1867 rc = kvm_fix_hypercall(ctxt->vcpu);
1868 if (rc)
1869 goto done;
1870 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1871 } else {
e4e03ded 1872 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1873 &size, &address,
e4e03ded 1874 c->op_bytes);
aca7f966
AL		 1875 if (rc)
1876 goto done;
1877 realmode_lidt(ctxt->vcpu, size, address);
1878 }
16286d08
AK		 1879 /* Disable writeback. */
1880 c->dst.type = OP_NONE;
6aa8b732
AK		 1881 break;
1882 case 4: /* smsw */
16286d08
AK		 1883 c->dst.bytes = 2;
1884 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1885 break;
1886 case 6: /* lmsw */
16286d08
AK		 1887 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1888 &ctxt->eflags);
dc7457ea 1889 c->dst.type = OP_NONE;
6aa8b732
AK		 1890 break;
1891 case 7: /* invlpg*/
e8d8d7fe 1892 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1893 /* Disable writeback. */
1894 c->dst.type = OP_NONE;
6aa8b732
AK		 1895 break;
1896 default:
1897 goto cannot_emulate;
1898 }
1899 break;
018a98db
AK		 1900 case 0x06:
1901 emulate_clts(ctxt->vcpu);
1902 c->dst.type = OP_NONE;
1903 break;
1904 case 0x08: /* invd */
1905 case 0x09: /* wbinvd */
1906 case 0x0d: /* GrpP (prefetch) */
1907 case 0x18: /* Grp16 (prefetch/nop) */
1908 c->dst.type = OP_NONE;
1909 break;
1910 case 0x20: /* mov cr, reg */
1911 if (c->modrm_mod != 3)
1912 goto cannot_emulate;
1913 c->regs[c->modrm_rm] =
1914 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1915 c->dst.type = OP_NONE; /* no writeback */
1916 break;
6aa8b732 1917 case 0x21: /* mov from dr to reg */
e4e03ded 1918 if (c->modrm_mod != 3)
6aa8b732 1919 goto cannot_emulate;
8cdbd2c9 1920 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1921 if (rc)
1922 goto cannot_emulate;
1923 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1924 break;
018a98db
AK		 1925 case 0x22: /* mov reg, cr */
1926 if (c->modrm_mod != 3)
1927 goto cannot_emulate;
1928 realmode_set_cr(ctxt->vcpu,
1929 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1930 c->dst.type = OP_NONE;
1931 break;
6aa8b732 1932 case 0x23: /* mov from reg to dr */
e4e03ded 1933 if (c->modrm_mod != 3)
6aa8b732 1934 goto cannot_emulate;
e4e03ded
LV		 1935 rc = emulator_set_dr(ctxt, c->modrm_reg,
1936 c->regs[c->modrm_rm]);
a01af5ec
LV		 1937 if (rc)
1938 goto cannot_emulate;
1939 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1940 break;
018a98db
AK		 1941 case 0x30:
1942 /* wrmsr */
1943 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1944 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1945 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1946 if (rc) {
c1a5d4f9 1947 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1948 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1949 }
1950 rc = X86EMUL_CONTINUE;
1951 c->dst.type = OP_NONE;
1952 break;
1953 case 0x32:
1954 /* rdmsr */
1955 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1956 if (rc) {
c1a5d4f9 1957 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1958 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1959 } else {
1960 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1961 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1962 }
1963 rc = X86EMUL_CONTINUE;
1964 c->dst.type = OP_NONE;
1965 break;
6aa8b732 1966 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1967 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1968 if (!test_cc(c->b, ctxt->eflags))
1969 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1970 break;
018a98db
AK		 1971 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1972 long int rel;
1973
1974 switch (c->op_bytes) {
1975 case 2:
1976 rel = insn_fetch(s16, 2, c->eip);
1977 break;
1978 case 4:
1979 rel = insn_fetch(s32, 4, c->eip);
1980 break;
1981 case 8:
1982 rel = insn_fetch(s64, 8, c->eip);
1983 break;
1984 default:
1985 DPRINTF("jnz: Invalid op_bytes\n");
1986 goto cannot_emulate;
1987 }
1988 if (test_cc(c->b, ctxt->eflags))
7a957275 1989 jmp_rel(c, rel);
018a98db
AK		 1990 c->dst.type = OP_NONE;
1991 break;
1992 }
7de75248
NK		 1993 case 0xa3:
1994 bt: /* bt */
e4f8e039 1995 c->dst.type = OP_NONE;
e4e03ded
LV		 1996 /* only subword offset */
1997 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1998 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1999 break;
2000 case 0xab:
2001 bts: /* bts */
e4e03ded
LV		 2002 /* only subword offset */
2003 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2004 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2005 break;
2a7c5b8b
GC		 2006 case 0xae: /* clflush */
2007 break;
6aa8b732
AK		 2008 case 0xb0 ... 0xb1: /* cmpxchg */
2009 /*
2010 * Save real source value, then compare EAX against
2011 * destination.
2012 */
e4e03ded
LV		 2013 c->src.orig_val = c->src.val;
2014 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2015 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2016 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2017 /* Success: write back to memory. */
e4e03ded 2018 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2019 } else {
2020 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2021 c->dst.type = OP_REG;
2022 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2023 }
2024 break;
6aa8b732
AK		 2025 case 0xb3:
2026 btr: /* btr */
e4e03ded
LV		 2027 /* only subword offset */
2028 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2029 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2030 break;
6aa8b732 2031 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2032 c->dst.bytes = c->op_bytes;
2033 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2034 : (u16) c->src.val;
6aa8b732 2035 break;
6aa8b732 2036 case 0xba: /* Grp8 */
e4e03ded 2037 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2038 case 0:
2039 goto bt;
2040 case 1:
2041 goto bts;
2042 case 2:
2043 goto btr;
2044 case 3:
2045 goto btc;
2046 }
2047 break;
7de75248
NK		 2048 case 0xbb:
2049 btc: /* btc */
e4e03ded
LV		 2050 /* only subword offset */
2051 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2052 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2053 break;
6aa8b732 2054 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2055 c->dst.bytes = c->op_bytes;
2056 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2057 (s16) c->src.val;
6aa8b732 2058 break;
a012e65a 2059 case 0xc3: /* movnti */
e4e03ded
LV		 2060 c->dst.bytes = c->op_bytes;
2061 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2062 (u64) c->src.val;
a012e65a 2063 break;
6aa8b732 2064 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2065 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2066 if (rc != 0)
2067 goto done;
018a98db 2068 c->dst.type = OP_NONE;
8cdbd2c9 2069 break;
6aa8b732
AK		 2070 }
2071 goto writeback;
2072
2073cannot_emulate:
e4e03ded 2074 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2075 c->eip = saved_eip;
6aa8b732
AK		 2076 return -1;
2077}
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