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KVM: x86 emulator: allow pop from mmio
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61#define SrcMask (7<<4)
6aa8b732 62/* Generic ModRM decode. */
9c9fddd0 63#define ModRM (1<<7)
6aa8b732 64/* Destination is only written; never read. */
9c9fddd0
GT		 65#define Mov (1<<8)
66#define BitOp (1<<9)
67#define MemAbs (1<<10) /* Memory operand is absolute displacement */
68#define String (1<<12) /* String instruction (rep capable) */
69#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 70#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
71#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
72#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 73
43bb19cd 74enum {
1d6ad207 75 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 76 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 77};
78
c7e75a3d 79static u16 opcode_table[256] = {
6aa8b732
AK		 80 /* 0x00 - 0x07 */
81 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
82 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 83 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 84 /* 0x08 - 0x0F */
85 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
86 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
87 0, 0, 0, 0,
88 /* 0x10 - 0x17 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
91 0, 0, 0, 0,
92 /* 0x18 - 0x1F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x20 - 0x27 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 99 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 100 /* 0x28 - 0x2F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x30 - 0x37 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 0, 0, 0, 0,
108 /* 0x38 - 0x3F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
112 0, 0,
d77a2507 113 /* 0x40 - 0x47 */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 115 /* 0x48 - 0x4F */
33615aa9 116 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 117 /* 0x50 - 0x57 */
6e3d5dfb
AK		 118 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
119 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 120 /* 0x58 - 0x5F */
6e3d5dfb
AK		 121 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
122 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 123 /* 0x60 - 0x67 */
6aa8b732 124 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 125 0, 0, 0, 0,
126 /* 0x68 - 0x6F */
91ed7a0e 127 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 128 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
129 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 130 /* 0x70 - 0x77 */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x78 - 0x7F */
134 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
135 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 136 /* 0x80 - 0x87 */
1d6ad207
AK		 137 Group | Group1_80, Group | Group1_81,
138 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 139 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
140 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
141 /* 0x88 - 0x8F */
142 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
143 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 144 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 145 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 146 /* 0x90 - 0x97 */
147 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
148 /* 0x98 - 0x9F */
6e3d5dfb 149 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 150 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 151 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
152 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 153 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 155 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 156 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
157 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
158 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 159 /* 0xB0 - 0xB7 */
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
163 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
164 /* 0xB8 - 0xBF */
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
167 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
168 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 169 /* 0xC0 - 0xC7 */
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 171 0, ImplicitOps | Stack, 0, 0,
d9413cd7 172 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 173 /* 0xC8 - 0xCF */
174 0, 0, 0, 0, 0, 0, 0, 0,
175 /* 0xD0 - 0xD7 */
176 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
177 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
178 0, 0, 0, 0,
179 /* 0xD8 - 0xDF */
180 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 181 /* 0xE0 - 0xE7 */
a6a3034c
MG		 182 0, 0, 0, 0,
183 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
184 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 185 /* 0xE8 - 0xEF */
954cd36f
GT		 186 ImplicitOps | Stack, SrcImm | ImplicitOps,
187 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 188 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
189 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 190 /* 0xF0 - 0xF7 */
191 0, 0, 0, 0,
7d858a19 192 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 193 /* 0xF8 - 0xFF */
b284be57 194 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 195 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 196};
197
038e51de 198static u16 twobyte_table[256] = {
6aa8b732 199 /* 0x00 - 0x0F */
d95058a1 200 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 201 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 202 /* 0x10 - 0x1F */
203 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x20 - 0x2F */
205 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x30 - 0x3F */
35f3f286 208 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 209 /* 0x40 - 0x47 */
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 /* 0x48 - 0x4F */
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 /* 0x50 - 0x5F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x60 - 0x6F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x70 - 0x7F */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x80 - 0x8F */
bbe9abbd
NK		 226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
228 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
229 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 230 /* 0x90 - 0x9F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0xA0 - 0xA7 */
038e51de 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 234 /* 0xA8 - 0xAF */
2a7c5b8b 235 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 236 /* 0xB0 - 0xB7 */
237 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 238 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 239 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem16 | ModRM | Mov,
241 /* 0xB8 - 0xBF */
038e51de 242 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 243 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
244 DstReg | SrcMem16 | ModRM | Mov,
245 /* 0xC0 - 0xCF */
a012e65a
SY		 246 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
247 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 248 /* 0xD0 - 0xDF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xE0 - 0xEF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0xF0 - 0xFF */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
254};
255
e09d082c 256static u16 group_table[] = {
1d6ad207
AK		 257 [Group1_80*8] =
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
261 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
262 [Group1_81*8] =
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
266 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
267 [Group1_82*8] =
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 [Group1_83*8] =
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
275 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
276 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 277 [Group1A*8] =
278 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 279 [Group3_Byte*8] =
280 ByteOp | SrcImm | DstMem | ModRM, 0,
281 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
282 0, 0, 0, 0,
283 [Group3*8] =
41afa025 284 DstMem | SrcImm | ModRM, 0,
6eb06cb2 285 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 286 0, 0, 0, 0,
fd60754e
AK		 287 [Group4*8] =
288 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
289 0, 0, 0, 0, 0, 0,
290 [Group5*8] =
d19292e4
MG		 291 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
292 SrcMem | ModRM | Stack, 0,
ef46f18e 293 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 294 [Group7*8] =
295 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 296 SrcNone | ModRM | DstMem | Mov, 0,
297 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 298};
299
300static u16 group2_table[] = {
d95058a1 301 [Group7*8] =
16286d08
AK		 302 SrcNone | ModRM, 0, 0, 0,
303 SrcNone | ModRM | DstMem | Mov, 0,
304 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 305};
306
6aa8b732
AK		 307/* EFLAGS bit definitions. */
308#define EFLG_OF (1<<11)
309#define EFLG_DF (1<<10)
310#define EFLG_SF (1<<7)
311#define EFLG_ZF (1<<6)
312#define EFLG_AF (1<<4)
313#define EFLG_PF (1<<2)
314#define EFLG_CF (1<<0)
315
316/*
317 * Instruction emulation:
318 * Most instructions are emulated directly via a fragment of inline assembly
319 * code. This allows us to save/restore EFLAGS and thus very easily pick up
320 * any modified flags.
321 */
322
05b3e0c2 323#if defined(CONFIG_X86_64)
6aa8b732
AK		 324#define _LO32 "k" /* force 32-bit operand */
325#define _STK "%%rsp" /* stack pointer */
326#elif defined(__i386__)
327#define _LO32 "" /* force 32-bit operand */
328#define _STK "%%esp" /* stack pointer */
329#endif
330
331/*
332 * These EFLAGS bits are restored from saved value during emulation, and
333 * any changes are written back to the saved value after emulation.
334 */
335#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
336
337/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 338#define _PRE_EFLAGS(_sav, _msk, _tmp) \
339 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
340 "movl %"_sav",%"_LO32 _tmp"; " \
341 "push %"_tmp"; " \
342 "push %"_tmp"; " \
343 "movl %"_msk",%"_LO32 _tmp"; " \
344 "andl %"_LO32 _tmp",("_STK"); " \
345 "pushf; " \
346 "notl %"_LO32 _tmp"; " \
347 "andl %"_LO32 _tmp",("_STK"); " \
348 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
349 "pop %"_tmp"; " \
350 "orl %"_LO32 _tmp",("_STK"); " \
351 "popf; " \
352 "pop %"_sav"; "
6aa8b732
AK		 353
354/* After executing instruction: write-back necessary bits in EFLAGS. */
355#define _POST_EFLAGS(_sav, _msk, _tmp) \
356 /* _sav |= EFLAGS & _msk; */ \
357 "pushf; " \
358 "pop %"_tmp"; " \
359 "andl %"_msk",%"_LO32 _tmp"; " \
360 "orl %"_LO32 _tmp",%"_sav"; "
361
dda96d8f
AK		 362#ifdef CONFIG_X86_64
363#define ON64(x) x
364#else
365#define ON64(x)
366#endif
367
6b7ad61f
AK		 368#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
369 do { \
370 __asm__ __volatile__ ( \
371 _PRE_EFLAGS("0", "4", "2") \
372 _op _suffix " %"_x"3,%1; " \
373 _POST_EFLAGS("0", "4", "2") \
374 : "=m" (_eflags), "=m" ((_dst).val), \
375 "=&r" (_tmp) \
376 : _y ((_src).val), "i" (EFLAGS_MASK)); \
377 } while (0);
378
379
6aa8b732
AK		 380/* Raw emulation: instruction has two explicit operands. */
381#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 382 do { \
383 unsigned long _tmp; \
384 \
385 switch ((_dst).bytes) { \
386 case 2: \
387 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
388 break; \
389 case 4: \
390 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
391 break; \
392 case 8: \
393 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
394 break; \
395 } \
6aa8b732
AK		 396 } while (0)
397
398#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
399 do { \
6b7ad61f 400 unsigned long _tmp; \
d77c26fc 401 switch ((_dst).bytes) { \
6aa8b732 402 case 1: \
6b7ad61f 403 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 404 break; \
405 default: \
406 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
407 _wx, _wy, _lx, _ly, _qx, _qy); \
408 break; \
409 } \
410 } while (0)
411
412/* Source operand is byte-sized and may be restricted to just %cl. */
413#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
414 __emulate_2op(_op, _src, _dst, _eflags, \
415 "b", "c", "b", "c", "b", "c", "b", "c")
416
417/* Source operand is byte, word, long or quad sized. */
418#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
419 __emulate_2op(_op, _src, _dst, _eflags, \
420 "b", "q", "w", "r", _LO32, "r", "", "r")
421
422/* Source operand is word, long or quad sized. */
423#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
424 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
425 "w", "r", _LO32, "r", "", "r")
426
dda96d8f 427#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 428 do { \
429 unsigned long _tmp; \
430 \
dda96d8f
AK		 431 __asm__ __volatile__ ( \
432 _PRE_EFLAGS("0", "3", "2") \
433 _op _suffix " %1; " \
434 _POST_EFLAGS("0", "3", "2") \
435 : "=m" (_eflags), "+m" ((_dst).val), \
436 "=&r" (_tmp) \
437 : "i" (EFLAGS_MASK)); \
438 } while (0)
439
440/* Instruction has only one explicit operand (no source operand). */
441#define emulate_1op(_op, _dst, _eflags) \
442 do { \
d77c26fc 443 switch ((_dst).bytes) { \
dda96d8f
AK		 444 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
445 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
446 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
447 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 448 } \
449 } while (0)
450
6aa8b732
AK		 451/* Fetch next part of the instruction being emulated. */
452#define insn_fetch(_type, _size, _eip) \
453({ unsigned long _x; \
62266869 454 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 455 if (rc != 0) \
6aa8b732
AK		 456 goto done; \
457 (_eip) += (_size); \
458 (_type)_x; \
459})
460
ddcb2885
HH		 461static inline unsigned long ad_mask(struct decode_cache *c)
462{
463 return (1UL << (c->ad_bytes << 3)) - 1;
464}
465
6aa8b732 466/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 467static inline unsigned long
468address_mask(struct decode_cache *c, unsigned long reg)
469{
470 if (c->ad_bytes == sizeof(unsigned long))
471 return reg;
472 else
473 return reg & ad_mask(c);
474}
475
476static inline unsigned long
477register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
478{
479 return base + address_mask(c, reg);
480}
481
7a957275
HH		 482static inline void
483register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
484{
485 if (c->ad_bytes == sizeof(unsigned long))
486 *reg += inc;
487 else
488 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
489}
6aa8b732 490
7a957275
HH		 491static inline void jmp_rel(struct decode_cache *c, int rel)
492{
493 register_address_increment(c, &c->eip, rel);
494}
098c937b 495
7a5b56df
AK		 496static void set_seg_override(struct decode_cache *c, int seg)
497{
498 c->has_seg_override = true;
499 c->seg_override = seg;
500}
501
502static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
503{
504 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
505 return 0;
506
507 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
508}
509
510static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
511 struct decode_cache *c)
512{
513 if (!c->has_seg_override)
514 return 0;
515
516 return seg_base(ctxt, c->seg_override);
517}
518
519static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
520{
521 return seg_base(ctxt, VCPU_SREG_ES);
522}
523
524static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
525{
526 return seg_base(ctxt, VCPU_SREG_SS);
527}
528
62266869
AK		 529static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
530 struct x86_emulate_ops *ops,
531 unsigned long linear, u8 *dest)
532{
533 struct fetch_cache *fc = &ctxt->decode.fetch;
534 int rc;
535 int size;
536
537 if (linear < fc->start || linear >= fc->end) {
538 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
539 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
540 if (rc)
541 return rc;
542 fc->start = linear;
543 fc->end = linear + size;
544 }
545 *dest = fc->data[linear - fc->start];
546 return 0;
547}
548
549static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
550 struct x86_emulate_ops *ops,
551 unsigned long eip, void *dest, unsigned size)
552{
553 int rc = 0;
554
555 eip += ctxt->cs_base;
556 while (size--) {
557 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
558 if (rc)
559 return rc;
560 }
561 return 0;
562}
563
1e3c5cb0
RR		 564/*
565 * Given the 'reg' portion of a ModRM byte, and a register block, return a
566 * pointer into the block that addresses the relevant register.
567 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
568 */
569static void *decode_register(u8 modrm_reg, unsigned long *regs,
570 int highbyte_regs)
6aa8b732
AK		 571{
572 void *p;
573
574 p = &regs[modrm_reg];
575 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
576 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
577 return p;
578}
579
580static int read_descriptor(struct x86_emulate_ctxt *ctxt,
581 struct x86_emulate_ops *ops,
582 void *ptr,
583 u16 *size, unsigned long *address, int op_bytes)
584{
585 int rc;
586
587 if (op_bytes == 2)
588 op_bytes = 3;
589 *address = 0;
cebff02b
LV		 590 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
591 ctxt->vcpu);
6aa8b732
AK		 592 if (rc)
593 return rc;
cebff02b
LV		 594 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
595 ctxt->vcpu);
6aa8b732
AK		 596 return rc;
597}
598
bbe9abbd
NK		 599static int test_cc(unsigned int condition, unsigned int flags)
600{
601 int rc = 0;
602
603 switch ((condition & 15) >> 1) {
604 case 0: /* o */
605 rc |= (flags & EFLG_OF);
606 break;
607 case 1: /* b/c/nae */
608 rc |= (flags & EFLG_CF);
609 break;
610 case 2: /* z/e */
611 rc |= (flags & EFLG_ZF);
612 break;
613 case 3: /* be/na */
614 rc |= (flags & (EFLG_CF|EFLG_ZF));
615 break;
616 case 4: /* s */
617 rc |= (flags & EFLG_SF);
618 break;
619 case 5: /* p/pe */
620 rc |= (flags & EFLG_PF);
621 break;
622 case 7: /* le/ng */
623 rc |= (flags & EFLG_ZF);
624 /* fall through */
625 case 6: /* l/nge */
626 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
627 break;
628 }
629
630 /* Odd condition identifiers (lsb == 1) have inverted sense. */
631 return (!!rc ^ (condition & 1));
632}
633
3c118e24
AK		 634static void decode_register_operand(struct operand *op,
635 struct decode_cache *c,
3c118e24
AK		 636 int inhibit_bytereg)
637{
33615aa9 638 unsigned reg = c->modrm_reg;
9f1ef3f8 639 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 640
641 if (!(c->d & ModRM))
642 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 643 op->type = OP_REG;
644 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 645 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 646 op->val = *(u8 *)op->ptr;
647 op->bytes = 1;
648 } else {
33615aa9 649 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 650 op->bytes = c->op_bytes;
651 switch (op->bytes) {
652 case 2:
653 op->val = *(u16 *)op->ptr;
654 break;
655 case 4:
656 op->val = *(u32 *)op->ptr;
657 break;
658 case 8:
659 op->val = *(u64 *) op->ptr;
660 break;
661 }
662 }
663 op->orig_val = op->val;
664}
665
1c73ef66
AK		 666static int decode_modrm(struct x86_emulate_ctxt *ctxt,
667 struct x86_emulate_ops *ops)
668{
669 struct decode_cache *c = &ctxt->decode;
670 u8 sib;
f5b4edcd 671 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 672 int rc = 0;
673
674 if (c->rex_prefix) {
675 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
676 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
677 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
678 }
679
680 c->modrm = insn_fetch(u8, 1, c->eip);
681 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
682 c->modrm_reg |= (c->modrm & 0x38) >> 3;
683 c->modrm_rm |= (c->modrm & 0x07);
684 c->modrm_ea = 0;
685 c->use_modrm_ea = 1;
686
687 if (c->modrm_mod == 3) {
107d6d2e
AK		 688 c->modrm_ptr = decode_register(c->modrm_rm,
689 c->regs, c->d & ByteOp);
690 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 691 return rc;
692 }
693
694 if (c->ad_bytes == 2) {
695 unsigned bx = c->regs[VCPU_REGS_RBX];
696 unsigned bp = c->regs[VCPU_REGS_RBP];
697 unsigned si = c->regs[VCPU_REGS_RSI];
698 unsigned di = c->regs[VCPU_REGS_RDI];
699
700 /* 16-bit ModR/M decode. */
701 switch (c->modrm_mod) {
702 case 0:
703 if (c->modrm_rm == 6)
704 c->modrm_ea += insn_fetch(u16, 2, c->eip);
705 break;
706 case 1:
707 c->modrm_ea += insn_fetch(s8, 1, c->eip);
708 break;
709 case 2:
710 c->modrm_ea += insn_fetch(u16, 2, c->eip);
711 break;
712 }
713 switch (c->modrm_rm) {
714 case 0:
715 c->modrm_ea += bx + si;
716 break;
717 case 1:
718 c->modrm_ea += bx + di;
719 break;
720 case 2:
721 c->modrm_ea += bp + si;
722 break;
723 case 3:
724 c->modrm_ea += bp + di;
725 break;
726 case 4:
727 c->modrm_ea += si;
728 break;
729 case 5:
730 c->modrm_ea += di;
731 break;
732 case 6:
733 if (c->modrm_mod != 0)
734 c->modrm_ea += bp;
735 break;
736 case 7:
737 c->modrm_ea += bx;
738 break;
739 }
740 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
741 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 742 if (!c->has_seg_override)
743 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 744 c->modrm_ea = (u16)c->modrm_ea;
745 } else {
746 /* 32/64-bit ModR/M decode. */
84411d85 747 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 748 sib = insn_fetch(u8, 1, c->eip);
749 index_reg |= (sib >> 3) & 7;
750 base_reg |= sib & 7;
751 scale = sib >> 6;
752
dc71d0f1
AK		 753 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
754 c->modrm_ea += insn_fetch(s32, 4, c->eip);
755 else
1c73ef66 756 c->modrm_ea += c->regs[base_reg];
dc71d0f1 757 if (index_reg != 4)
1c73ef66 758 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 759 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
760 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 761 c->rip_relative = 1;
84411d85 762 } else
1c73ef66 763 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 764 switch (c->modrm_mod) {
765 case 0:
766 if (c->modrm_rm == 5)
767 c->modrm_ea += insn_fetch(s32, 4, c->eip);
768 break;
769 case 1:
770 c->modrm_ea += insn_fetch(s8, 1, c->eip);
771 break;
772 case 2:
773 c->modrm_ea += insn_fetch(s32, 4, c->eip);
774 break;
775 }
776 }
1c73ef66
AK		 777done:
778 return rc;
779}
780
781static int decode_abs(struct x86_emulate_ctxt *ctxt,
782 struct x86_emulate_ops *ops)
783{
784 struct decode_cache *c = &ctxt->decode;
785 int rc = 0;
786
787 switch (c->ad_bytes) {
788 case 2:
789 c->modrm_ea = insn_fetch(u16, 2, c->eip);
790 break;
791 case 4:
792 c->modrm_ea = insn_fetch(u32, 4, c->eip);
793 break;
794 case 8:
795 c->modrm_ea = insn_fetch(u64, 8, c->eip);
796 break;
797 }
798done:
799 return rc;
800}
801
6aa8b732 802int
8b4caf66 803x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 804{
e4e03ded 805 struct decode_cache *c = &ctxt->decode;
6aa8b732 806 int rc = 0;
6aa8b732 807 int mode = ctxt->mode;
e09d082c 808 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 809
810 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 811
e4e03ded 812 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 813 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 814 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 815 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 816
817 switch (mode) {
818 case X86EMUL_MODE_REAL:
819 case X86EMUL_MODE_PROT16:
f21b8bf4 820 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 821 break;
822 case X86EMUL_MODE_PROT32:
f21b8bf4 823 def_op_bytes = def_ad_bytes = 4;
6aa8b732 824 break;
05b3e0c2 825#ifdef CONFIG_X86_64
6aa8b732 826 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 827 def_op_bytes = 4;
828 def_ad_bytes = 8;
6aa8b732
AK		 829 break;
830#endif
831 default:
832 return -1;
833 }
834
f21b8bf4
AK		 835 c->op_bytes = def_op_bytes;
836 c->ad_bytes = def_ad_bytes;
837
6aa8b732 838 /* Legacy prefixes. */
b4c6abfe 839 for (;;) {
e4e03ded 840 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 841 case 0x66: /* operand-size override */
f21b8bf4
AK		 842 /* switch between 2/4 bytes */
843 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 844 break;
845 case 0x67: /* address-size override */
846 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 847 /* switch between 4/8 bytes */
f21b8bf4 848 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 849 else
e4e03ded 850 /* switch between 2/4 bytes */
f21b8bf4 851 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 852 break;
7a5b56df 853 case 0x26: /* ES override */
6aa8b732 854 case 0x2e: /* CS override */
7a5b56df 855 case 0x36: /* SS override */
6aa8b732 856 case 0x3e: /* DS override */
7a5b56df 857 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 858 break;
859 case 0x64: /* FS override */
6aa8b732 860 case 0x65: /* GS override */
7a5b56df 861 set_seg_override(c, c->b & 7);
6aa8b732 862 break;
b4c6abfe
LV		 863 case 0x40 ... 0x4f: /* REX */
864 if (mode != X86EMUL_MODE_PROT64)
865 goto done_prefixes;
33615aa9 866 c->rex_prefix = c->b;
b4c6abfe 867 continue;
6aa8b732 868 case 0xf0: /* LOCK */
e4e03ded 869 c->lock_prefix = 1;
6aa8b732 870 break;
ae6200ba 871 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 872 c->rep_prefix = REPNE_PREFIX;
873 break;
6aa8b732 874 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 875 c->rep_prefix = REPE_PREFIX;
6aa8b732 876 break;
6aa8b732
AK		 877 default:
878 goto done_prefixes;
879 }
b4c6abfe
LV		 880
881 /* Any legacy prefix after a REX prefix nullifies its effect. */
882
33615aa9 883 c->rex_prefix = 0;
6aa8b732
AK		 884 }
885
886done_prefixes:
887
888 /* REX prefix. */
1c73ef66 889 if (c->rex_prefix)
33615aa9 890 if (c->rex_prefix & 8)
e4e03ded 891 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 892
893 /* Opcode byte(s). */
e4e03ded
LV		 894 c->d = opcode_table[c->b];
895 if (c->d == 0) {
6aa8b732 896 /* Two-byte opcode? */
e4e03ded
LV		 897 if (c->b == 0x0f) {
898 c->twobyte = 1;
899 c->b = insn_fetch(u8, 1, c->eip);
900 c->d = twobyte_table[c->b];
6aa8b732 901 }
e09d082c 902 }
6aa8b732 903
e09d082c
AK		 904 if (c->d & Group) {
905 group = c->d & GroupMask;
906 c->modrm = insn_fetch(u8, 1, c->eip);
907 --c->eip;
908
909 group = (group << 3) + ((c->modrm >> 3) & 7);
910 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
911 c->d = group2_table[group];
912 else
913 c->d = group_table[group];
914 }
915
916 /* Unrecognised? */
917 if (c->d == 0) {
918 DPRINTF("Cannot emulate %02x\n", c->b);
919 return -1;
6aa8b732
AK		 920 }
921
6e3d5dfb
AK		 922 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
923 c->op_bytes = 8;
924
6aa8b732 925 /* ModRM and SIB bytes. */
1c73ef66
AK		 926 if (c->d & ModRM)
927 rc = decode_modrm(ctxt, ops);
928 else if (c->d & MemAbs)
929 rc = decode_abs(ctxt, ops);
930 if (rc)
931 goto done;
6aa8b732 932
7a5b56df
AK		 933 if (!c->has_seg_override)
934 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 935
7a5b56df
AK		 936 if (!(!c->twobyte && c->b == 0x8d))
937 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 938
939 if (c->ad_bytes != 8)
940 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 941 /*
942 * Decode and fetch the source operand: register, memory
943 * or immediate.
944 */
e4e03ded 945 switch (c->d & SrcMask) {
6aa8b732
AK		 946 case SrcNone:
947 break;
948 case SrcReg:
9f1ef3f8 949 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 950 break;
951 case SrcMem16:
e4e03ded 952 c->src.bytes = 2;
6aa8b732
AK		 953 goto srcmem_common;
954 case SrcMem32:
e4e03ded 955 c->src.bytes = 4;
6aa8b732
AK		 956 goto srcmem_common;
957 case SrcMem:
e4e03ded
LV		 958 c->src.bytes = (c->d & ByteOp) ? 1 :
959 c->op_bytes;
b85b9ee9 960 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 961 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 962 break;
d77c26fc 963 srcmem_common:
4e62417b
AJ		 964 /*
965 * For instructions with a ModR/M byte, switch to register
966 * access if Mod = 3.
967 */
e4e03ded
LV		 968 if ((c->d & ModRM) && c->modrm_mod == 3) {
969 c->src.type = OP_REG;
66b85505 970 c->src.val = c->modrm_val;
107d6d2e 971 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 972 break;
973 }
e4e03ded 974 c->src.type = OP_MEM;
6aa8b732
AK		 975 break;
976 case SrcImm:
e4e03ded
LV		 977 c->src.type = OP_IMM;
978 c->src.ptr = (unsigned long *)c->eip;
979 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
980 if (c->src.bytes == 8)
981 c->src.bytes = 4;
6aa8b732 982 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 983 switch (c->src.bytes) {
6aa8b732 984 case 1:
e4e03ded 985 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 986 break;
987 case 2:
e4e03ded 988 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 989 break;
990 case 4:
e4e03ded 991 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 992 break;
993 }
994 break;
995 case SrcImmByte:
e4e03ded
LV		 996 c->src.type = OP_IMM;
997 c->src.ptr = (unsigned long *)c->eip;
998 c->src.bytes = 1;
999 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1000 break;
1001 }
1002
038e51de 1003 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1004 switch (c->d & DstMask) {
038e51de
AK		 1005 case ImplicitOps:
1006 /* Special instructions do their own operand decoding. */
8b4caf66 1007 return 0;
038e51de 1008 case DstReg:
9f1ef3f8 1009 decode_register_operand(&c->dst, c,
3c118e24 1010 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1011 break;
1012 case DstMem:
e4e03ded 1013 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1014 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1015 c->dst.type = OP_REG;
66b85505 1016 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1017 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1018 break;
1019 }
8b4caf66
LV		 1020 c->dst.type = OP_MEM;
1021 break;
9c9fddd0
GT		 1022 case DstAcc:
1023 c->dst.type = OP_REG;
1024 c->dst.bytes = c->op_bytes;
1025 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1026 switch (c->op_bytes) {
1027 case 1:
1028 c->dst.val = *(u8 *)c->dst.ptr;
1029 break;
1030 case 2:
1031 c->dst.val = *(u16 *)c->dst.ptr;
1032 break;
1033 case 4:
1034 c->dst.val = *(u32 *)c->dst.ptr;
1035 break;
1036 }
1037 c->dst.orig_val = c->dst.val;
1038 break;
8b4caf66
LV		 1039 }
1040
f5b4edcd
AK		 1041 if (c->rip_relative)
1042 c->modrm_ea += c->eip;
1043
8b4caf66
LV		 1044done:
1045 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1046}
1047
8cdbd2c9
LV		 1048static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1049{
1050 struct decode_cache *c = &ctxt->decode;
1051
1052 c->dst.type = OP_MEM;
1053 c->dst.bytes = c->op_bytes;
1054 c->dst.val = c->src.val;
7a957275 1055 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1056 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1057 c->regs[VCPU_REGS_RSP]);
1058}
1059
faa5a3ae
AK		 1060static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1061 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1062{
1063 struct decode_cache *c = &ctxt->decode;
1064 int rc;
1065
781d0edc
AK		 1066 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1067 c->regs[VCPU_REGS_RSP]),
1068 &c->src.val, c->src.bytes, ctxt->vcpu);
8cdbd2c9
LV		 1069 if (rc != 0)
1070 return rc;
1071
faa5a3ae
AK		 1072 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.bytes);
1073 return rc;
1074}
8cdbd2c9 1075
faa5a3ae
AK		 1076static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1077 struct x86_emulate_ops *ops)
1078{
1079 struct decode_cache *c = &ctxt->decode;
1080 int rc;
1081
1082 c->src.bytes = c->dst.bytes;
1083 rc = emulate_pop(ctxt, ops);
1084 if (rc != 0)
1085 return rc;
1086 c->dst.val = c->src.val;
8cdbd2c9
LV		 1087 return 0;
1088}
1089
05f086f8 1090static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1091{
05f086f8 1092 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1093 switch (c->modrm_reg) {
1094 case 0: /* rol */
05f086f8 1095 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1096 break;
1097 case 1: /* ror */
05f086f8 1098 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1099 break;
1100 case 2: /* rcl */
05f086f8 1101 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1102 break;
1103 case 3: /* rcr */
05f086f8 1104 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1105 break;
1106 case 4: /* sal/shl */
1107 case 6: /* sal/shl */
05f086f8 1108 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1109 break;
1110 case 5: /* shr */
05f086f8 1111 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1112 break;
1113 case 7: /* sar */
05f086f8 1114 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 }
1117}
1118
1119static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1120 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1121{
1122 struct decode_cache *c = &ctxt->decode;
1123 int rc = 0;
1124
1125 switch (c->modrm_reg) {
1126 case 0 ... 1: /* test */
05f086f8 1127 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1128 break;
1129 case 2: /* not */
1130 c->dst.val = ~c->dst.val;
1131 break;
1132 case 3: /* neg */
05f086f8 1133 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1134 break;
1135 default:
1136 DPRINTF("Cannot emulate %02x\n", c->b);
1137 rc = X86EMUL_UNHANDLEABLE;
1138 break;
1139 }
8cdbd2c9
LV		 1140 return rc;
1141}
1142
1143static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1144 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1145{
1146 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1147
1148 switch (c->modrm_reg) {
1149 case 0: /* inc */
05f086f8 1150 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1151 break;
1152 case 1: /* dec */
05f086f8 1153 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1154 break;
d19292e4
MG		 1155 case 2: /* call near abs */ {
1156 long int old_eip;
1157 old_eip = c->eip;
1158 c->eip = c->src.val;
1159 c->src.val = old_eip;
1160 emulate_push(ctxt);
1161 break;
1162 }
8cdbd2c9 1163 case 4: /* jmp abs */
fd60754e 1164 c->eip = c->src.val;
8cdbd2c9
LV		 1165 break;
1166 case 6: /* push */
fd60754e 1167 emulate_push(ctxt);
8cdbd2c9 1168 break;
8cdbd2c9
LV		 1169 }
1170 return 0;
1171}
1172
1173static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1174 struct x86_emulate_ops *ops,
e8d8d7fe 1175 unsigned long memop)
8cdbd2c9
LV		 1176{
1177 struct decode_cache *c = &ctxt->decode;
1178 u64 old, new;
1179 int rc;
1180
e8d8d7fe 1181 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1182 if (rc != 0)
1183 return rc;
1184
1185 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1186 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1187
1188 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1189 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1190 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1191
1192 } else {
1193 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1194 (u32) c->regs[VCPU_REGS_RBX];
1195
e8d8d7fe 1196 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1197 if (rc != 0)
1198 return rc;
05f086f8 1199 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1200 }
1201 return 0;
1202}
1203
1204static inline int writeback(struct x86_emulate_ctxt *ctxt,
1205 struct x86_emulate_ops *ops)
1206{
1207 int rc;
1208 struct decode_cache *c = &ctxt->decode;
1209
1210 switch (c->dst.type) {
1211 case OP_REG:
1212 /* The 4-byte case *is* correct:
1213 * in 64-bit mode we zero-extend.
1214 */
1215 switch (c->dst.bytes) {
1216 case 1:
1217 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1218 break;
1219 case 2:
1220 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1221 break;
1222 case 4:
1223 *c->dst.ptr = (u32)c->dst.val;
1224 break; /* 64b: zero-ext */
1225 case 8:
1226 *c->dst.ptr = c->dst.val;
1227 break;
1228 }
1229 break;
1230 case OP_MEM:
1231 if (c->lock_prefix)
1232 rc = ops->cmpxchg_emulated(
1233 (unsigned long)c->dst.ptr,
1234 &c->dst.orig_val,
1235 &c->dst.val,
1236 c->dst.bytes,
1237 ctxt->vcpu);
1238 else
1239 rc = ops->write_emulated(
1240 (unsigned long)c->dst.ptr,
1241 &c->dst.val,
1242 c->dst.bytes,
1243 ctxt->vcpu);
1244 if (rc != 0)
1245 return rc;
a01af5ec
LV		 1246 break;
1247 case OP_NONE:
1248 /* no writeback */
1249 break;
8cdbd2c9
LV		 1250 default:
1251 break;
1252 }
1253 return 0;
1254}
1255
8b4caf66 1256int
1be3aa47 1257x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1258{
e8d8d7fe 1259 unsigned long memop = 0;
8b4caf66 1260 u64 msr_data;
3427318f 1261 unsigned long saved_eip = 0;
8b4caf66 1262 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1263 unsigned int port;
1264 int io_dir_in;
1be3aa47 1265 int rc = 0;
8b4caf66 1266
3427318f
LV		 1267 /* Shadow copy of register state. Committed on successful emulation.
1268 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1269 * modify them.
1270 */
1271
ad312c7c 1272 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1273 saved_eip = c->eip;
1274
c7e75a3d 1275 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1276 memop = c->modrm_ea;
8b4caf66 1277
b9fa9d6b
AK		 1278 if (c->rep_prefix && (c->d & String)) {
1279 /* All REP prefixes have the same first termination condition */
1280 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1281 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1282 goto done;
1283 }
1284 /* The second termination condition only applies for REPE
1285 * and REPNE. Test if the repeat string operation prefix is
1286 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1287 * corresponding termination condition according to:
1288 * - if REPE/REPZ and ZF = 0 then done
1289 * - if REPNE/REPNZ and ZF = 1 then done
1290 */
1291 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1292 (c->b == 0xae) || (c->b == 0xaf)) {
1293 if ((c->rep_prefix == REPE_PREFIX) &&
1294 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1295 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1296 goto done;
1297 }
1298 if ((c->rep_prefix == REPNE_PREFIX) &&
1299 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1300 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1301 goto done;
1302 }
1303 }
1304 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1305 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1306 }
1307
8b4caf66 1308 if (c->src.type == OP_MEM) {
e8d8d7fe 1309 c->src.ptr = (unsigned long *)memop;
8b4caf66 1310 c->src.val = 0;
d77c26fc
MD		 1311 rc = ops->read_emulated((unsigned long)c->src.ptr,
1312 &c->src.val,
1313 c->src.bytes,
1314 ctxt->vcpu);
1315 if (rc != 0)
8b4caf66
LV		 1316 goto done;
1317 c->src.orig_val = c->src.val;
1318 }
1319
1320 if ((c->d & DstMask) == ImplicitOps)
1321 goto special_insn;
1322
1323
1324 if (c->dst.type == OP_MEM) {
e8d8d7fe 1325 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1326 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1327 c->dst.val = 0;
e4e03ded
LV		 1328 if (c->d & BitOp) {
1329 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1330
e4e03ded
LV		 1331 c->dst.ptr = (void *)c->dst.ptr +
1332 (c->src.val & mask) / 8;
038e51de 1333 }
e4e03ded
LV		 1334 if (!(c->d & Mov) &&
1335 /* optimisation - avoid slow emulated read */
1336 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1337 &c->dst.val,
1338 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1339 goto done;
038e51de 1340 }
e4e03ded 1341 c->dst.orig_val = c->dst.val;
038e51de 1342
018a98db
AK		 1343special_insn:
1344
e4e03ded 1345 if (c->twobyte)
6aa8b732
AK		 1346 goto twobyte_insn;
1347
e4e03ded 1348 switch (c->b) {
6aa8b732
AK		 1349 case 0x00 ... 0x05:
1350 add: /* add */
05f086f8 1351 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1352 break;
1353 case 0x08 ... 0x0d:
1354 or: /* or */
05f086f8 1355 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1356 break;
1357 case 0x10 ... 0x15:
1358 adc: /* adc */
05f086f8 1359 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1360 break;
1361 case 0x18 ... 0x1d:
1362 sbb: /* sbb */
05f086f8 1363 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1364 break;
aa3a816b 1365 case 0x20 ... 0x25:
6aa8b732 1366 and: /* and */
05f086f8 1367 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1368 break;
1369 case 0x28 ... 0x2d:
1370 sub: /* sub */
05f086f8 1371 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1372 break;
1373 case 0x30 ... 0x35:
1374 xor: /* xor */
05f086f8 1375 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1376 break;
1377 case 0x38 ... 0x3d:
1378 cmp: /* cmp */
05f086f8 1379 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1380 break;
33615aa9
AK		 1381 case 0x40 ... 0x47: /* inc r16/r32 */
1382 emulate_1op("inc", c->dst, ctxt->eflags);
1383 break;
1384 case 0x48 ... 0x4f: /* dec r16/r32 */
1385 emulate_1op("dec", c->dst, ctxt->eflags);
1386 break;
1387 case 0x50 ... 0x57: /* push reg */
2786b014 1388 emulate_push(ctxt);
33615aa9
AK		 1389 break;
1390 case 0x58 ... 0x5f: /* pop reg */
1391 pop_instruction:
7a5b56df 1392 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1393 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1394 c->op_bytes, ctxt->vcpu)) != 0)
1395 goto done;
1396
7a957275 1397 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1398 c->op_bytes);
1399 c->dst.type = OP_NONE; /* Disable writeback. */
1400 break;
6aa8b732 1401 case 0x63: /* movsxd */
8b4caf66 1402 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1403 goto cannot_emulate;
e4e03ded 1404 c->dst.val = (s32) c->src.val;
6aa8b732 1405 break;
91ed7a0e 1406 case 0x68: /* push imm */
018a98db 1407 case 0x6a: /* push imm8 */
018a98db
AK		 1408 emulate_push(ctxt);
1409 break;
1410 case 0x6c: /* insb */
1411 case 0x6d: /* insw/insd */
1412 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1413 1,
1414 (c->d & ByteOp) ? 1 : c->op_bytes,
1415 c->rep_prefix ?
e4706772 1416 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1417 (ctxt->eflags & EFLG_DF),
7a5b56df 1418 register_address(c, es_base(ctxt),
018a98db
AK		 1419 c->regs[VCPU_REGS_RDI]),
1420 c->rep_prefix,
1421 c->regs[VCPU_REGS_RDX]) == 0) {
1422 c->eip = saved_eip;
1423 return -1;
1424 }
1425 return 0;
1426 case 0x6e: /* outsb */
1427 case 0x6f: /* outsw/outsd */
1428 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1429 0,
1430 (c->d & ByteOp) ? 1 : c->op_bytes,
1431 c->rep_prefix ?
e4706772 1432 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1433 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1434 register_address(c,
1435 seg_override_base(ctxt, c),
018a98db
AK		 1436 c->regs[VCPU_REGS_RSI]),
1437 c->rep_prefix,
1438 c->regs[VCPU_REGS_RDX]) == 0) {
1439 c->eip = saved_eip;
1440 return -1;
1441 }
1442 return 0;
1443 case 0x70 ... 0x7f: /* jcc (short) */ {
1444 int rel = insn_fetch(s8, 1, c->eip);
1445
1446 if (test_cc(c->b, ctxt->eflags))
7a957275 1447 jmp_rel(c, rel);
018a98db
AK		 1448 break;
1449 }
6aa8b732 1450 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1451 switch (c->modrm_reg) {
6aa8b732
AK		 1452 case 0:
1453 goto add;
1454 case 1:
1455 goto or;
1456 case 2:
1457 goto adc;
1458 case 3:
1459 goto sbb;
1460 case 4:
1461 goto and;
1462 case 5:
1463 goto sub;
1464 case 6:
1465 goto xor;
1466 case 7:
1467 goto cmp;
1468 }
1469 break;
1470 case 0x84 ... 0x85:
05f086f8 1471 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1472 break;
1473 case 0x86 ... 0x87: /* xchg */
b13354f8 1474 xchg:
6aa8b732 1475 /* Write back the register source. */
e4e03ded 1476 switch (c->dst.bytes) {
6aa8b732 1477 case 1:
e4e03ded 1478 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1479 break;
1480 case 2:
e4e03ded 1481 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1482 break;
1483 case 4:
e4e03ded 1484 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1485 break; /* 64b reg: zero-extend */
1486 case 8:
e4e03ded 1487 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1488 break;
1489 }
1490 /*
1491 * Write back the memory destination with implicit LOCK
1492 * prefix.
1493 */
e4e03ded
LV		 1494 c->dst.val = c->src.val;
1495 c->lock_prefix = 1;
6aa8b732 1496 break;
6aa8b732 1497 case 0x88 ... 0x8b: /* mov */
7de75248 1498 goto mov;
38d5bc6d
GT		 1499 case 0x8c: { /* mov r/m, sreg */
1500 struct kvm_segment segreg;
1501
1502 if (c->modrm_reg <= 5)
1503 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1504 else {
1505 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1506 c->modrm);
1507 goto cannot_emulate;
1508 }
1509 c->dst.val = segreg.selector;
1510 break;
1511 }
7e0b54b1 1512 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1513 c->dst.val = c->modrm_ea;
7e0b54b1 1514 break;
4257198a
GT		 1515 case 0x8e: { /* mov seg, r/m16 */
1516 uint16_t sel;
1517 int type_bits;
1518 int err;
1519
1520 sel = c->src.val;
1521 if (c->modrm_reg <= 5) {
1522 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1523 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1524 type_bits, c->modrm_reg);
1525 } else {
1526 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1527 c->modrm);
1528 goto cannot_emulate;
1529 }
1530
1531 if (err < 0)
1532 goto cannot_emulate;
1533
1534 c->dst.type = OP_NONE; /* Disable writeback. */
1535 break;
1536 }
6aa8b732 1537 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1538 rc = emulate_grp1a(ctxt, ops);
1539 if (rc != 0)
6aa8b732 1540 goto done;
6aa8b732 1541 break;
b13354f8
MG		 1542 case 0x90: /* nop / xchg r8,rax */
1543 if (!(c->rex_prefix & 1)) { /* nop */
1544 c->dst.type = OP_NONE;
1545 break;
1546 }
1547 case 0x91 ... 0x97: /* xchg reg,rax */
1548 c->src.type = c->dst.type = OP_REG;
1549 c->src.bytes = c->dst.bytes = c->op_bytes;
1550 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1551 c->src.val = *(c->src.ptr);
1552 goto xchg;
fd2a7608 1553 case 0x9c: /* pushf */
05f086f8 1554 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1555 emulate_push(ctxt);
1556 break;
535eabcf 1557 case 0x9d: /* popf */
05f086f8 1558 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1559 goto pop_instruction;
018a98db
AK		 1560 case 0xa0 ... 0xa1: /* mov */
1561 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1562 c->dst.val = c->src.val;
1563 break;
1564 case 0xa2 ... 0xa3: /* mov */
1565 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1566 break;
6aa8b732 1567 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1568 c->dst.type = OP_MEM;
1569 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1570 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1571 es_base(ctxt),
e4e03ded 1572 c->regs[VCPU_REGS_RDI]);
e4706772 1573 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1574 seg_override_base(ctxt, c),
e4e03ded
LV		 1575 c->regs[VCPU_REGS_RSI]),
1576 &c->dst.val,
1577 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1578 goto done;
7a957275 1579 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1580 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1581 : c->dst.bytes);
7a957275 1582 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1583 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1584 : c->dst.bytes);
6aa8b732
AK		 1585 break;
1586 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1587 c->src.type = OP_NONE; /* Disable writeback. */
1588 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1589 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1590 seg_override_base(ctxt, c),
d7e5117a
GT		 1591 c->regs[VCPU_REGS_RSI]);
1592 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1593 &c->src.val,
1594 c->src.bytes,
1595 ctxt->vcpu)) != 0)
1596 goto done;
1597
1598 c->dst.type = OP_NONE; /* Disable writeback. */
1599 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1600 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1601 es_base(ctxt),
d7e5117a
GT		 1602 c->regs[VCPU_REGS_RDI]);
1603 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1604 &c->dst.val,
1605 c->dst.bytes,
1606 ctxt->vcpu)) != 0)
1607 goto done;
1608
1609 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1610
1611 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1612
7a957275 1613 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1614 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1615 : c->src.bytes);
7a957275 1616 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1617 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1618 : c->dst.bytes);
1619
1620 break;
6aa8b732 1621 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1622 c->dst.type = OP_MEM;
1623 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1624 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1625 es_base(ctxt),
a7e6c88a 1626 c->regs[VCPU_REGS_RDI]);
e4e03ded 1627 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1628 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1629 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1630 : c->dst.bytes);
6aa8b732
AK		 1631 break;
1632 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1633 c->dst.type = OP_REG;
1634 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1635 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1636 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1637 seg_override_base(ctxt, c),
a7e6c88a
SY		 1638 c->regs[VCPU_REGS_RSI]),
1639 &c->dst.val,
1640 c->dst.bytes,
1641 ctxt->vcpu)) != 0)
6aa8b732 1642 goto done;
7a957275 1643 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1644 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1645 : c->dst.bytes);
6aa8b732
AK		 1646 break;
1647 case 0xae ... 0xaf: /* scas */
1648 DPRINTF("Urk! I don't handle SCAS.\n");
1649 goto cannot_emulate;
a5e2e82b 1650 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1651 goto mov;
018a98db
AK		 1652 case 0xc0 ... 0xc1:
1653 emulate_grp2(ctxt);
1654 break;
111de5d6
AK		 1655 case 0xc3: /* ret */
1656 c->dst.ptr = &c->eip;
1657 goto pop_instruction;
018a98db
AK		 1658 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1659 mov:
1660 c->dst.val = c->src.val;
1661 break;
1662 case 0xd0 ... 0xd1: /* Grp2 */
1663 c->src.val = 1;
1664 emulate_grp2(ctxt);
1665 break;
1666 case 0xd2 ... 0xd3: /* Grp2 */
1667 c->src.val = c->regs[VCPU_REGS_RCX];
1668 emulate_grp2(ctxt);
1669 break;
a6a3034c
MG		 1670 case 0xe4: /* inb */
1671 case 0xe5: /* in */
1672 port = insn_fetch(u8, 1, c->eip);
1673 io_dir_in = 1;
1674 goto do_io;
1675 case 0xe6: /* outb */
1676 case 0xe7: /* out */
1677 port = insn_fetch(u8, 1, c->eip);
1678 io_dir_in = 0;
1679 goto do_io;
1a52e051
NK		 1680 case 0xe8: /* call (near) */ {
1681 long int rel;
e4e03ded 1682 switch (c->op_bytes) {
1a52e051 1683 case 2:
e4e03ded 1684 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1685 break;
1686 case 4:
e4e03ded 1687 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1688 break;
1a52e051
NK		 1689 default:
1690 DPRINTF("Call: Invalid op_bytes\n");
1691 goto cannot_emulate;
1692 }
e4e03ded 1693 c->src.val = (unsigned long) c->eip;
7a957275 1694 jmp_rel(c, rel);
e4e03ded 1695 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1696 emulate_push(ctxt);
1697 break;
1a52e051
NK		 1698 }
1699 case 0xe9: /* jmp rel */
954cd36f
GT		 1700 goto jmp;
1701 case 0xea: /* jmp far */ {
1702 uint32_t eip;
1703 uint16_t sel;
1704
1705 switch (c->op_bytes) {
1706 case 2:
1707 eip = insn_fetch(u16, 2, c->eip);
1708 break;
1709 case 4:
1710 eip = insn_fetch(u32, 4, c->eip);
1711 break;
1712 default:
1713 DPRINTF("jmp far: Invalid op_bytes\n");
1714 goto cannot_emulate;
1715 }
1716 sel = insn_fetch(u16, 2, c->eip);
1717 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1718 DPRINTF("jmp far: Failed to load CS descriptor\n");
1719 goto cannot_emulate;
1720 }
1721
1722 c->eip = eip;
1723 break;
1724 }
1725 case 0xeb:
1726 jmp: /* jmp rel short */
7a957275 1727 jmp_rel(c, c->src.val);
a01af5ec 1728 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1729 break;
a6a3034c
MG		 1730 case 0xec: /* in al,dx */
1731 case 0xed: /* in (e/r)ax,dx */
1732 port = c->regs[VCPU_REGS_RDX];
1733 io_dir_in = 1;
1734 goto do_io;
1735 case 0xee: /* out al,dx */
1736 case 0xef: /* out (e/r)ax,dx */
1737 port = c->regs[VCPU_REGS_RDX];
1738 io_dir_in = 0;
1739 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1740 (c->d & ByteOp) ? 1 : c->op_bytes,
1741 port) != 0) {
1742 c->eip = saved_eip;
1743 goto cannot_emulate;
1744 }
e93f36bc 1745 break;
111de5d6 1746 case 0xf4: /* hlt */
ad312c7c 1747 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1748 break;
111de5d6
AK		 1749 case 0xf5: /* cmc */
1750 /* complement carry flag from eflags reg */
1751 ctxt->eflags ^= EFLG_CF;
1752 c->dst.type = OP_NONE; /* Disable writeback. */
1753 break;
018a98db
AK		 1754 case 0xf6 ... 0xf7: /* Grp3 */
1755 rc = emulate_grp3(ctxt, ops);
1756 if (rc != 0)
1757 goto done;
1758 break;
111de5d6
AK		 1759 case 0xf8: /* clc */
1760 ctxt->eflags &= ~EFLG_CF;
1761 c->dst.type = OP_NONE; /* Disable writeback. */
1762 break;
1763 case 0xfa: /* cli */
1764 ctxt->eflags &= ~X86_EFLAGS_IF;
1765 c->dst.type = OP_NONE; /* Disable writeback. */
1766 break;
1767 case 0xfb: /* sti */
1768 ctxt->eflags |= X86_EFLAGS_IF;
1769 c->dst.type = OP_NONE; /* Disable writeback. */
1770 break;
fb4616f4
MG		 1771 case 0xfc: /* cld */
1772 ctxt->eflags &= ~EFLG_DF;
1773 c->dst.type = OP_NONE; /* Disable writeback. */
1774 break;
1775 case 0xfd: /* std */
1776 ctxt->eflags |= EFLG_DF;
1777 c->dst.type = OP_NONE; /* Disable writeback. */
1778 break;
018a98db
AK		 1779 case 0xfe ... 0xff: /* Grp4/Grp5 */
1780 rc = emulate_grp45(ctxt, ops);
1781 if (rc != 0)
1782 goto done;
1783 break;
6aa8b732 1784 }
018a98db
AK		 1785
1786writeback:
1787 rc = writeback(ctxt, ops);
1788 if (rc != 0)
1789 goto done;
1790
1791 /* Commit shadow register state. */
ad312c7c 1792 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1793 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1794
1795done:
1796 if (rc == X86EMUL_UNHANDLEABLE) {
1797 c->eip = saved_eip;
1798 return -1;
1799 }
1800 return 0;
6aa8b732
AK		 1801
1802twobyte_insn:
e4e03ded 1803 switch (c->b) {
6aa8b732 1804 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1805 switch (c->modrm_reg) {
6aa8b732
AK		 1806 u16 size;
1807 unsigned long address;
1808
aca7f966 1809 case 0: /* vmcall */
e4e03ded 1810 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1811 goto cannot_emulate;
1812
7aa81cc0
AL		 1813 rc = kvm_fix_hypercall(ctxt->vcpu);
1814 if (rc)
1815 goto done;
1816
33e3885d 1817 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1818 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1819 /* Disable writeback. */
1820 c->dst.type = OP_NONE;
aca7f966 1821 break;
6aa8b732 1822 case 2: /* lgdt */
e4e03ded
LV		 1823 rc = read_descriptor(ctxt, ops, c->src.ptr,
1824 &size, &address, c->op_bytes);
6aa8b732
AK		 1825 if (rc)
1826 goto done;
1827 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1828 /* Disable writeback. */
1829 c->dst.type = OP_NONE;
6aa8b732 1830 break;
aca7f966 1831 case 3: /* lidt/vmmcall */
e4e03ded 1832 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1833 rc = kvm_fix_hypercall(ctxt->vcpu);
1834 if (rc)
1835 goto done;
1836 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1837 } else {
e4e03ded 1838 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1839 &size, &address,
e4e03ded 1840 c->op_bytes);
aca7f966
AL		 1841 if (rc)
1842 goto done;
1843 realmode_lidt(ctxt->vcpu, size, address);
1844 }
16286d08
AK		 1845 /* Disable writeback. */
1846 c->dst.type = OP_NONE;
6aa8b732
AK		 1847 break;
1848 case 4: /* smsw */
16286d08
AK		 1849 c->dst.bytes = 2;
1850 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1851 break;
1852 case 6: /* lmsw */
16286d08
AK		 1853 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1854 &ctxt->eflags);
dc7457ea 1855 c->dst.type = OP_NONE;
6aa8b732
AK		 1856 break;
1857 case 7: /* invlpg*/
e8d8d7fe 1858 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1859 /* Disable writeback. */
1860 c->dst.type = OP_NONE;
6aa8b732
AK		 1861 break;
1862 default:
1863 goto cannot_emulate;
1864 }
1865 break;
018a98db
AK		 1866 case 0x06:
1867 emulate_clts(ctxt->vcpu);
1868 c->dst.type = OP_NONE;
1869 break;
1870 case 0x08: /* invd */
1871 case 0x09: /* wbinvd */
1872 case 0x0d: /* GrpP (prefetch) */
1873 case 0x18: /* Grp16 (prefetch/nop) */
1874 c->dst.type = OP_NONE;
1875 break;
1876 case 0x20: /* mov cr, reg */
1877 if (c->modrm_mod != 3)
1878 goto cannot_emulate;
1879 c->regs[c->modrm_rm] =
1880 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1881 c->dst.type = OP_NONE; /* no writeback */
1882 break;
6aa8b732 1883 case 0x21: /* mov from dr to reg */
e4e03ded 1884 if (c->modrm_mod != 3)
6aa8b732 1885 goto cannot_emulate;
8cdbd2c9 1886 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1887 if (rc)
1888 goto cannot_emulate;
1889 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1890 break;
018a98db
AK		 1891 case 0x22: /* mov reg, cr */
1892 if (c->modrm_mod != 3)
1893 goto cannot_emulate;
1894 realmode_set_cr(ctxt->vcpu,
1895 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1896 c->dst.type = OP_NONE;
1897 break;
6aa8b732 1898 case 0x23: /* mov from reg to dr */
e4e03ded 1899 if (c->modrm_mod != 3)
6aa8b732 1900 goto cannot_emulate;
e4e03ded
LV		 1901 rc = emulator_set_dr(ctxt, c->modrm_reg,
1902 c->regs[c->modrm_rm]);
a01af5ec
LV		 1903 if (rc)
1904 goto cannot_emulate;
1905 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1906 break;
018a98db
AK		 1907 case 0x30:
1908 /* wrmsr */
1909 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1910 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1911 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1912 if (rc) {
c1a5d4f9 1913 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1914 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1915 }
1916 rc = X86EMUL_CONTINUE;
1917 c->dst.type = OP_NONE;
1918 break;
1919 case 0x32:
1920 /* rdmsr */
1921 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1922 if (rc) {
c1a5d4f9 1923 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1924 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1925 } else {
1926 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1927 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1928 }
1929 rc = X86EMUL_CONTINUE;
1930 c->dst.type = OP_NONE;
1931 break;
6aa8b732 1932 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1933 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1934 if (!test_cc(c->b, ctxt->eflags))
1935 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1936 break;
018a98db
AK		 1937 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1938 long int rel;
1939
1940 switch (c->op_bytes) {
1941 case 2:
1942 rel = insn_fetch(s16, 2, c->eip);
1943 break;
1944 case 4:
1945 rel = insn_fetch(s32, 4, c->eip);
1946 break;
1947 case 8:
1948 rel = insn_fetch(s64, 8, c->eip);
1949 break;
1950 default:
1951 DPRINTF("jnz: Invalid op_bytes\n");
1952 goto cannot_emulate;
1953 }
1954 if (test_cc(c->b, ctxt->eflags))
7a957275 1955 jmp_rel(c, rel);
018a98db
AK		 1956 c->dst.type = OP_NONE;
1957 break;
1958 }
7de75248
NK		 1959 case 0xa3:
1960 bt: /* bt */
e4f8e039 1961 c->dst.type = OP_NONE;
e4e03ded
LV		 1962 /* only subword offset */
1963 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1964 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1965 break;
1966 case 0xab:
1967 bts: /* bts */
e4e03ded
LV		 1968 /* only subword offset */
1969 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1970 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1971 break;
2a7c5b8b
GC		 1972 case 0xae: /* clflush */
1973 break;
6aa8b732
AK		 1974 case 0xb0 ... 0xb1: /* cmpxchg */
1975 /*
1976 * Save real source value, then compare EAX against
1977 * destination.
1978 */
e4e03ded
LV		 1979 c->src.orig_val = c->src.val;
1980 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1981 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1982 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1983 /* Success: write back to memory. */
e4e03ded 1984 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1985 } else {
1986 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1987 c->dst.type = OP_REG;
1988 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1989 }
1990 break;
6aa8b732
AK		 1991 case 0xb3:
1992 btr: /* btr */
e4e03ded
LV		 1993 /* only subword offset */
1994 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1995 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1996 break;
6aa8b732 1997 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1998 c->dst.bytes = c->op_bytes;
1999 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2000 : (u16) c->src.val;
6aa8b732 2001 break;
6aa8b732 2002 case 0xba: /* Grp8 */
e4e03ded 2003 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2004 case 0:
2005 goto bt;
2006 case 1:
2007 goto bts;
2008 case 2:
2009 goto btr;
2010 case 3:
2011 goto btc;
2012 }
2013 break;
7de75248
NK		 2014 case 0xbb:
2015 btc: /* btc */
e4e03ded
LV		 2016 /* only subword offset */
2017 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2018 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2019 break;
6aa8b732 2020 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2021 c->dst.bytes = c->op_bytes;
2022 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2023 (s16) c->src.val;
6aa8b732 2024 break;
a012e65a 2025 case 0xc3: /* movnti */
e4e03ded
LV		 2026 c->dst.bytes = c->op_bytes;
2027 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2028 (u64) c->src.val;
a012e65a 2029 break;
6aa8b732 2030 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2031 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2032 if (rc != 0)
2033 goto done;
018a98db 2034 c->dst.type = OP_NONE;
8cdbd2c9 2035 break;
6aa8b732
AK		 2036 }
2037 goto writeback;
2038
2039cannot_emulate:
e4e03ded 2040 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2041 c->eip = saved_eip;
6aa8b732
AK		 2042 return -1;
2043}
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