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KVM: x86 emulator: Completely decode in/out at decoding stage
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 61#define SrcOne (7<<4) /* Implied '1' */
341de7e3
GN		 62#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
63#define SrcMask (0xf<<4)
6aa8b732 64/* Generic ModRM decode. */
341de7e3 65#define ModRM (1<<8)
6aa8b732 66/* Destination is only written; never read. */
341de7e3
GN		 67#define Mov (1<<9)
68#define BitOp (1<<10)
69#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 70#define String (1<<12) /* String instruction (rep capable) */
71#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 72#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
73#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
74#define GroupMask 0xff /* Group number stored in bits 0:7 */
0dc8d10f
GT		 75/* Source 2 operand type */
76#define Src2None (0<<29)
77#define Src2CL (1<<29)
78#define Src2ImmByte (2<<29)
79#define Src2One (3<<29)
a5f868bd 80#define Src2Imm16 (4<<29)
0dc8d10f 81#define Src2Mask (7<<29)
6aa8b732 82
43bb19cd 83enum {
1d6ad207 84 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 85 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 86};
87
45ed60b3 88static u32 opcode_table[256] = {
6aa8b732
AK		 89 /* 0x00 - 0x07 */
90 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
91 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 92 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 93 /* 0x08 - 0x0F */
94 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
95 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
96 0, 0, 0, 0,
97 /* 0x10 - 0x17 */
98 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
99 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
100 0, 0, 0, 0,
101 /* 0x18 - 0x1F */
102 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
103 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
104 0, 0, 0, 0,
105 /* 0x20 - 0x27 */
106 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
107 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 108 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 109 /* 0x28 - 0x2F */
110 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
112 0, 0, 0, 0,
113 /* 0x30 - 0x37 */
114 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
115 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
116 0, 0, 0, 0,
117 /* 0x38 - 0x3F */
118 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 120 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
121 0, 0,
d77a2507 122 /* 0x40 - 0x47 */
33615aa9 123 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 124 /* 0x48 - 0x4F */
33615aa9 125 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 126 /* 0x50 - 0x57 */
6e3d5dfb
AK		 127 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
128 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 129 /* 0x58 - 0x5F */
6e3d5dfb
AK		 130 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
131 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 132 /* 0x60 - 0x67 */
6aa8b732 133 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 134 0, 0, 0, 0,
135 /* 0x68 - 0x6F */
91ed7a0e 136 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 137 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
138 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 139 /* 0x70 - 0x77 */
b2833e3c
GN		 140 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
141 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 142 /* 0x78 - 0x7F */
b2833e3c
GN		 143 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
144 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 145 /* 0x80 - 0x87 */
1d6ad207
AK		 146 Group | Group1_80, Group | Group1_81,
147 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 148 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
149 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
150 /* 0x88 - 0x8F */
151 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
152 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 153 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 154 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 155 /* 0x90 - 0x97 */
156 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
157 /* 0x98 - 0x9F */
0654169e
GN		 158 0, 0, SrcImm | Src2Imm16, 0,
159 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 160 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 161 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
162 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 163 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
164 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 165 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 166 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
167 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
168 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 169 /* 0xB0 - 0xB7 */
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
172 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
173 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
174 /* 0xB8 - 0xBF */
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
177 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
178 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 179 /* 0xC0 - 0xC7 */
d9413cd7 180 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 181 0, ImplicitOps | Stack, 0, 0,
d9413cd7 182 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 183 /* 0xC8 - 0xCF */
a77ab5ea 184 0, 0, 0, ImplicitOps | Stack, 0, 0, 0, 0,
6aa8b732
AK		 185 /* 0xD0 - 0xD7 */
186 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
187 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
188 0, 0, 0, 0,
189 /* 0xD8 - 0xDF */
190 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 191 /* 0xE0 - 0xE7 */
a6a3034c 192 0, 0, 0, 0,
84ce66a6
GN		 193 ByteOp | SrcImmUByte, SrcImmUByte,
194 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 195 /* 0xE8 - 0xEF */
d53c4777 196 SrcImm | Stack, SrcImm | ImplicitOps,
782b877c 197 SrcImm | Src2Imm16, SrcImmByte | ImplicitOps,
a6a3034c
MG		 198 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
199 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 200 /* 0xF0 - 0xF7 */
201 0, 0, 0, 0,
7d858a19 202 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 203 /* 0xF8 - 0xFF */
b284be57 204 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 205 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 206};
207
45ed60b3 208static u32 twobyte_table[256] = {
6aa8b732 209 /* 0x00 - 0x0F */
d95058a1 210 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 211 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 212 /* 0x10 - 0x1F */
213 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
214 /* 0x20 - 0x2F */
215 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
216 0, 0, 0, 0, 0, 0, 0, 0,
217 /* 0x30 - 0x3F */
35f3f286 218 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 219 /* 0x40 - 0x47 */
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 /* 0x48 - 0x4F */
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
228 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
229 /* 0x50 - 0x5F */
230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
231 /* 0x60 - 0x6F */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0x70 - 0x7F */
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x80 - 0x8F */
b2833e3c
GN		 236 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
237 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 238 /* 0x90 - 0x9F */
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0xA0 - 0xA7 */
9bf8ea42
GT		 241 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
242 DstMem | SrcReg | Src2ImmByte | ModRM,
243 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 244 /* 0xA8 - 0xAF */
9bf8ea42
GT		 245 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
246 DstMem | SrcReg | Src2ImmByte | ModRM,
247 DstMem | SrcReg | Src2CL | ModRM,
248 ModRM, 0,
6aa8b732
AK		 249 /* 0xB0 - 0xB7 */
250 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 251 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 252 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem16 | ModRM | Mov,
254 /* 0xB8 - 0xBF */
038e51de 255 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 256 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
257 DstReg | SrcMem16 | ModRM | Mov,
258 /* 0xC0 - 0xCF */
a012e65a
SY		 259 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
260 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 261 /* 0xD0 - 0xDF */
262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
263 /* 0xE0 - 0xEF */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xF0 - 0xFF */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
267};
268
45ed60b3 269static u32 group_table[] = {
1d6ad207
AK		 270 [Group1_80*8] =
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
275 [Group1_81*8] =
276 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
280 [Group1_82*8] =
281 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
285 [Group1_83*8] =
286 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 290 [Group1A*8] =
291 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 292 [Group3_Byte*8] =
293 ByteOp | SrcImm | DstMem | ModRM, 0,
294 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
295 0, 0, 0, 0,
296 [Group3*8] =
41afa025 297 DstMem | SrcImm | ModRM, 0,
6eb06cb2 298 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 299 0, 0, 0, 0,
fd60754e
AK		 300 [Group4*8] =
301 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
302 0, 0, 0, 0, 0, 0,
303 [Group5*8] =
d19292e4
MG		 304 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
305 SrcMem | ModRM | Stack, 0,
ef46f18e 306 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 307 [Group7*8] =
308 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 309 SrcNone | ModRM | DstMem | Mov, 0,
310 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 311};
312
45ed60b3 313static u32 group2_table[] = {
d95058a1 314 [Group7*8] =
fbce554e 315 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 316 SrcNone | ModRM | DstMem | Mov, 0,
317 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 318};
319
6aa8b732
AK		 320/* EFLAGS bit definitions. */
321#define EFLG_OF (1<<11)
322#define EFLG_DF (1<<10)
323#define EFLG_SF (1<<7)
324#define EFLG_ZF (1<<6)
325#define EFLG_AF (1<<4)
326#define EFLG_PF (1<<2)
327#define EFLG_CF (1<<0)
328
329/*
330 * Instruction emulation:
331 * Most instructions are emulated directly via a fragment of inline assembly
332 * code. This allows us to save/restore EFLAGS and thus very easily pick up
333 * any modified flags.
334 */
335
05b3e0c2 336#if defined(CONFIG_X86_64)
6aa8b732
AK		 337#define _LO32 "k" /* force 32-bit operand */
338#define _STK "%%rsp" /* stack pointer */
339#elif defined(__i386__)
340#define _LO32 "" /* force 32-bit operand */
341#define _STK "%%esp" /* stack pointer */
342#endif
343
344/*
345 * These EFLAGS bits are restored from saved value during emulation, and
346 * any changes are written back to the saved value after emulation.
347 */
348#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
349
350/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 351#define _PRE_EFLAGS(_sav, _msk, _tmp) \
352 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
353 "movl %"_sav",%"_LO32 _tmp"; " \
354 "push %"_tmp"; " \
355 "push %"_tmp"; " \
356 "movl %"_msk",%"_LO32 _tmp"; " \
357 "andl %"_LO32 _tmp",("_STK"); " \
358 "pushf; " \
359 "notl %"_LO32 _tmp"; " \
360 "andl %"_LO32 _tmp",("_STK"); " \
361 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
362 "pop %"_tmp"; " \
363 "orl %"_LO32 _tmp",("_STK"); " \
364 "popf; " \
365 "pop %"_sav"; "
6aa8b732
AK		 366
367/* After executing instruction: write-back necessary bits in EFLAGS. */
368#define _POST_EFLAGS(_sav, _msk, _tmp) \
369 /* _sav |= EFLAGS & _msk; */ \
370 "pushf; " \
371 "pop %"_tmp"; " \
372 "andl %"_msk",%"_LO32 _tmp"; " \
373 "orl %"_LO32 _tmp",%"_sav"; "
374
dda96d8f
AK		 375#ifdef CONFIG_X86_64
376#define ON64(x) x
377#else
378#define ON64(x)
379#endif
380
6b7ad61f
AK		 381#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
382 do { \
383 __asm__ __volatile__ ( \
384 _PRE_EFLAGS("0", "4", "2") \
385 _op _suffix " %"_x"3,%1; " \
386 _POST_EFLAGS("0", "4", "2") \
387 : "=m" (_eflags), "=m" ((_dst).val), \
388 "=&r" (_tmp) \
389 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 390 } while (0)
6b7ad61f
AK		 391
392
6aa8b732
AK		 393/* Raw emulation: instruction has two explicit operands. */
394#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 395 do { \
396 unsigned long _tmp; \
397 \
398 switch ((_dst).bytes) { \
399 case 2: \
400 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
401 break; \
402 case 4: \
403 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
404 break; \
405 case 8: \
406 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
407 break; \
408 } \
6aa8b732
AK		 409 } while (0)
410
411#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
412 do { \
6b7ad61f 413 unsigned long _tmp; \
d77c26fc 414 switch ((_dst).bytes) { \
6aa8b732 415 case 1: \
6b7ad61f 416 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 417 break; \
418 default: \
419 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
420 _wx, _wy, _lx, _ly, _qx, _qy); \
421 break; \
422 } \
423 } while (0)
424
425/* Source operand is byte-sized and may be restricted to just %cl. */
426#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
427 __emulate_2op(_op, _src, _dst, _eflags, \
428 "b", "c", "b", "c", "b", "c", "b", "c")
429
430/* Source operand is byte, word, long or quad sized. */
431#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
432 __emulate_2op(_op, _src, _dst, _eflags, \
433 "b", "q", "w", "r", _LO32, "r", "", "r")
434
435/* Source operand is word, long or quad sized. */
436#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
437 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
438 "w", "r", _LO32, "r", "", "r")
439
d175226a
GT		 440/* Instruction has three operands and one operand is stored in ECX register */
441#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
442 do { \
443 unsigned long _tmp; \
444 _type _clv = (_cl).val; \
445 _type _srcv = (_src).val; \
446 _type _dstv = (_dst).val; \
447 \
448 __asm__ __volatile__ ( \
449 _PRE_EFLAGS("0", "5", "2") \
450 _op _suffix " %4,%1 \n" \
451 _POST_EFLAGS("0", "5", "2") \
452 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
453 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
454 ); \
455 \
456 (_cl).val = (unsigned long) _clv; \
457 (_src).val = (unsigned long) _srcv; \
458 (_dst).val = (unsigned long) _dstv; \
459 } while (0)
460
461#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
462 do { \
463 switch ((_dst).bytes) { \
464 case 2: \
465 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
466 "w", unsigned short); \
467 break; \
468 case 4: \
469 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
470 "l", unsigned int); \
471 break; \
472 case 8: \
473 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
474 "q", unsigned long)); \
475 break; \
476 } \
477 } while (0)
478
dda96d8f 479#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 480 do { \
481 unsigned long _tmp; \
482 \
dda96d8f
AK		 483 __asm__ __volatile__ ( \
484 _PRE_EFLAGS("0", "3", "2") \
485 _op _suffix " %1; " \
486 _POST_EFLAGS("0", "3", "2") \
487 : "=m" (_eflags), "+m" ((_dst).val), \
488 "=&r" (_tmp) \
489 : "i" (EFLAGS_MASK)); \
490 } while (0)
491
492/* Instruction has only one explicit operand (no source operand). */
493#define emulate_1op(_op, _dst, _eflags) \
494 do { \
d77c26fc 495 switch ((_dst).bytes) { \
dda96d8f
AK		 496 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
497 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
498 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
499 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 500 } \
501 } while (0)
502
6aa8b732
AK		 503/* Fetch next part of the instruction being emulated. */
504#define insn_fetch(_type, _size, _eip) \
505({ unsigned long _x; \
62266869 506 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 507 if (rc != 0) \
6aa8b732
AK		 508 goto done; \
509 (_eip) += (_size); \
510 (_type)_x; \
511})
512
ddcb2885
HH		 513static inline unsigned long ad_mask(struct decode_cache *c)
514{
515 return (1UL << (c->ad_bytes << 3)) - 1;
516}
517
6aa8b732 518/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 519static inline unsigned long
520address_mask(struct decode_cache *c, unsigned long reg)
521{
522 if (c->ad_bytes == sizeof(unsigned long))
523 return reg;
524 else
525 return reg & ad_mask(c);
526}
527
528static inline unsigned long
529register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
530{
531 return base + address_mask(c, reg);
532}
533
7a957275
HH		 534static inline void
535register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
536{
537 if (c->ad_bytes == sizeof(unsigned long))
538 *reg += inc;
539 else
540 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
541}
6aa8b732 542
7a957275
HH		 543static inline void jmp_rel(struct decode_cache *c, int rel)
544{
545 register_address_increment(c, &c->eip, rel);
546}
098c937b 547
7a5b56df
AK		 548static void set_seg_override(struct decode_cache *c, int seg)
549{
550 c->has_seg_override = true;
551 c->seg_override = seg;
552}
553
554static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
555{
556 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
557 return 0;
558
559 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
560}
561
562static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
563 struct decode_cache *c)
564{
565 if (!c->has_seg_override)
566 return 0;
567
568 return seg_base(ctxt, c->seg_override);
569}
570
571static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
572{
573 return seg_base(ctxt, VCPU_SREG_ES);
574}
575
576static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
577{
578 return seg_base(ctxt, VCPU_SREG_SS);
579}
580
62266869
AK		 581static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
582 struct x86_emulate_ops *ops,
583 unsigned long linear, u8 *dest)
584{
585 struct fetch_cache *fc = &ctxt->decode.fetch;
586 int rc;
587 int size;
588
589 if (linear < fc->start || linear >= fc->end) {
590 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
591 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
592 if (rc)
593 return rc;
594 fc->start = linear;
595 fc->end = linear + size;
596 }
597 *dest = fc->data[linear - fc->start];
598 return 0;
599}
600
601static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
602 struct x86_emulate_ops *ops,
603 unsigned long eip, void *dest, unsigned size)
604{
605 int rc = 0;
606
607 eip += ctxt->cs_base;
608 while (size--) {
609 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
610 if (rc)
611 return rc;
612 }
613 return 0;
614}
615
1e3c5cb0
RR		 616/*
617 * Given the 'reg' portion of a ModRM byte, and a register block, return a
618 * pointer into the block that addresses the relevant register.
619 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
620 */
621static void *decode_register(u8 modrm_reg, unsigned long *regs,
622 int highbyte_regs)
6aa8b732
AK		 623{
624 void *p;
625
626 p = &regs[modrm_reg];
627 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
628 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
629 return p;
630}
631
632static int read_descriptor(struct x86_emulate_ctxt *ctxt,
633 struct x86_emulate_ops *ops,
634 void *ptr,
635 u16 *size, unsigned long *address, int op_bytes)
636{
637 int rc;
638
639 if (op_bytes == 2)
640 op_bytes = 3;
641 *address = 0;
cebff02b
LV		 642 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
643 ctxt->vcpu);
6aa8b732
AK		 644 if (rc)
645 return rc;
cebff02b
LV		 646 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
647 ctxt->vcpu);
6aa8b732
AK		 648 return rc;
649}
650
bbe9abbd
NK		 651static int test_cc(unsigned int condition, unsigned int flags)
652{
653 int rc = 0;
654
655 switch ((condition & 15) >> 1) {
656 case 0: /* o */
657 rc |= (flags & EFLG_OF);
658 break;
659 case 1: /* b/c/nae */
660 rc |= (flags & EFLG_CF);
661 break;
662 case 2: /* z/e */
663 rc |= (flags & EFLG_ZF);
664 break;
665 case 3: /* be/na */
666 rc |= (flags & (EFLG_CF|EFLG_ZF));
667 break;
668 case 4: /* s */
669 rc |= (flags & EFLG_SF);
670 break;
671 case 5: /* p/pe */
672 rc |= (flags & EFLG_PF);
673 break;
674 case 7: /* le/ng */
675 rc |= (flags & EFLG_ZF);
676 /* fall through */
677 case 6: /* l/nge */
678 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
679 break;
680 }
681
682 /* Odd condition identifiers (lsb == 1) have inverted sense. */
683 return (!!rc ^ (condition & 1));
684}
685
3c118e24
AK		 686static void decode_register_operand(struct operand *op,
687 struct decode_cache *c,
3c118e24
AK		 688 int inhibit_bytereg)
689{
33615aa9 690 unsigned reg = c->modrm_reg;
9f1ef3f8 691 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 692
693 if (!(c->d & ModRM))
694 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 695 op->type = OP_REG;
696 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 697 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 698 op->val = *(u8 *)op->ptr;
699 op->bytes = 1;
700 } else {
33615aa9 701 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 702 op->bytes = c->op_bytes;
703 switch (op->bytes) {
704 case 2:
705 op->val = *(u16 *)op->ptr;
706 break;
707 case 4:
708 op->val = *(u32 *)op->ptr;
709 break;
710 case 8:
711 op->val = *(u64 *) op->ptr;
712 break;
713 }
714 }
715 op->orig_val = op->val;
716}
717
1c73ef66
AK		 718static int decode_modrm(struct x86_emulate_ctxt *ctxt,
719 struct x86_emulate_ops *ops)
720{
721 struct decode_cache *c = &ctxt->decode;
722 u8 sib;
f5b4edcd 723 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 724 int rc = 0;
725
726 if (c->rex_prefix) {
727 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
728 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
729 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
730 }
731
732 c->modrm = insn_fetch(u8, 1, c->eip);
733 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
734 c->modrm_reg |= (c->modrm & 0x38) >> 3;
735 c->modrm_rm |= (c->modrm & 0x07);
736 c->modrm_ea = 0;
737 c->use_modrm_ea = 1;
738
739 if (c->modrm_mod == 3) {
107d6d2e
AK		 740 c->modrm_ptr = decode_register(c->modrm_rm,
741 c->regs, c->d & ByteOp);
742 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 743 return rc;
744 }
745
746 if (c->ad_bytes == 2) {
747 unsigned bx = c->regs[VCPU_REGS_RBX];
748 unsigned bp = c->regs[VCPU_REGS_RBP];
749 unsigned si = c->regs[VCPU_REGS_RSI];
750 unsigned di = c->regs[VCPU_REGS_RDI];
751
752 /* 16-bit ModR/M decode. */
753 switch (c->modrm_mod) {
754 case 0:
755 if (c->modrm_rm == 6)
756 c->modrm_ea += insn_fetch(u16, 2, c->eip);
757 break;
758 case 1:
759 c->modrm_ea += insn_fetch(s8, 1, c->eip);
760 break;
761 case 2:
762 c->modrm_ea += insn_fetch(u16, 2, c->eip);
763 break;
764 }
765 switch (c->modrm_rm) {
766 case 0:
767 c->modrm_ea += bx + si;
768 break;
769 case 1:
770 c->modrm_ea += bx + di;
771 break;
772 case 2:
773 c->modrm_ea += bp + si;
774 break;
775 case 3:
776 c->modrm_ea += bp + di;
777 break;
778 case 4:
779 c->modrm_ea += si;
780 break;
781 case 5:
782 c->modrm_ea += di;
783 break;
784 case 6:
785 if (c->modrm_mod != 0)
786 c->modrm_ea += bp;
787 break;
788 case 7:
789 c->modrm_ea += bx;
790 break;
791 }
792 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
793 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 794 if (!c->has_seg_override)
795 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 796 c->modrm_ea = (u16)c->modrm_ea;
797 } else {
798 /* 32/64-bit ModR/M decode. */
84411d85 799 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 800 sib = insn_fetch(u8, 1, c->eip);
801 index_reg |= (sib >> 3) & 7;
802 base_reg |= sib & 7;
803 scale = sib >> 6;
804
dc71d0f1
AK		 805 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
806 c->modrm_ea += insn_fetch(s32, 4, c->eip);
807 else
1c73ef66 808 c->modrm_ea += c->regs[base_reg];
dc71d0f1 809 if (index_reg != 4)
1c73ef66 810 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 811 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
812 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 813 c->rip_relative = 1;
84411d85 814 } else
1c73ef66 815 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 816 switch (c->modrm_mod) {
817 case 0:
818 if (c->modrm_rm == 5)
819 c->modrm_ea += insn_fetch(s32, 4, c->eip);
820 break;
821 case 1:
822 c->modrm_ea += insn_fetch(s8, 1, c->eip);
823 break;
824 case 2:
825 c->modrm_ea += insn_fetch(s32, 4, c->eip);
826 break;
827 }
828 }
1c73ef66
AK		 829done:
830 return rc;
831}
832
833static int decode_abs(struct x86_emulate_ctxt *ctxt,
834 struct x86_emulate_ops *ops)
835{
836 struct decode_cache *c = &ctxt->decode;
837 int rc = 0;
838
839 switch (c->ad_bytes) {
840 case 2:
841 c->modrm_ea = insn_fetch(u16, 2, c->eip);
842 break;
843 case 4:
844 c->modrm_ea = insn_fetch(u32, 4, c->eip);
845 break;
846 case 8:
847 c->modrm_ea = insn_fetch(u64, 8, c->eip);
848 break;
849 }
850done:
851 return rc;
852}
853
6aa8b732 854int
8b4caf66 855x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 856{
e4e03ded 857 struct decode_cache *c = &ctxt->decode;
6aa8b732 858 int rc = 0;
6aa8b732 859 int mode = ctxt->mode;
e09d082c 860 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 861
862 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 863
e4e03ded 864 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 865 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 866 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 867 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 868
869 switch (mode) {
870 case X86EMUL_MODE_REAL:
871 case X86EMUL_MODE_PROT16:
f21b8bf4 872 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 873 break;
874 case X86EMUL_MODE_PROT32:
f21b8bf4 875 def_op_bytes = def_ad_bytes = 4;
6aa8b732 876 break;
05b3e0c2 877#ifdef CONFIG_X86_64
6aa8b732 878 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 879 def_op_bytes = 4;
880 def_ad_bytes = 8;
6aa8b732
AK		 881 break;
882#endif
883 default:
884 return -1;
885 }
886
f21b8bf4
AK		 887 c->op_bytes = def_op_bytes;
888 c->ad_bytes = def_ad_bytes;
889
6aa8b732 890 /* Legacy prefixes. */
b4c6abfe 891 for (;;) {
e4e03ded 892 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 893 case 0x66: /* operand-size override */
f21b8bf4
AK		 894 /* switch between 2/4 bytes */
895 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 896 break;
897 case 0x67: /* address-size override */
898 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 899 /* switch between 4/8 bytes */
f21b8bf4 900 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 901 else
e4e03ded 902 /* switch between 2/4 bytes */
f21b8bf4 903 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 904 break;
7a5b56df 905 case 0x26: /* ES override */
6aa8b732 906 case 0x2e: /* CS override */
7a5b56df 907 case 0x36: /* SS override */
6aa8b732 908 case 0x3e: /* DS override */
7a5b56df 909 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 910 break;
911 case 0x64: /* FS override */
6aa8b732 912 case 0x65: /* GS override */
7a5b56df 913 set_seg_override(c, c->b & 7);
6aa8b732 914 break;
b4c6abfe
LV		 915 case 0x40 ... 0x4f: /* REX */
916 if (mode != X86EMUL_MODE_PROT64)
917 goto done_prefixes;
33615aa9 918 c->rex_prefix = c->b;
b4c6abfe 919 continue;
6aa8b732 920 case 0xf0: /* LOCK */
e4e03ded 921 c->lock_prefix = 1;
6aa8b732 922 break;
ae6200ba 923 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 924 c->rep_prefix = REPNE_PREFIX;
925 break;
6aa8b732 926 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 927 c->rep_prefix = REPE_PREFIX;
6aa8b732 928 break;
6aa8b732
AK		 929 default:
930 goto done_prefixes;
931 }
b4c6abfe
LV		 932
933 /* Any legacy prefix after a REX prefix nullifies its effect. */
934
33615aa9 935 c->rex_prefix = 0;
6aa8b732
AK		 936 }
937
938done_prefixes:
939
940 /* REX prefix. */
1c73ef66 941 if (c->rex_prefix)
33615aa9 942 if (c->rex_prefix & 8)
e4e03ded 943 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 944
945 /* Opcode byte(s). */
e4e03ded
LV		 946 c->d = opcode_table[c->b];
947 if (c->d == 0) {
6aa8b732 948 /* Two-byte opcode? */
e4e03ded
LV		 949 if (c->b == 0x0f) {
950 c->twobyte = 1;
951 c->b = insn_fetch(u8, 1, c->eip);
952 c->d = twobyte_table[c->b];
6aa8b732 953 }
e09d082c 954 }
6aa8b732 955
e09d082c
AK		 956 if (c->d & Group) {
957 group = c->d & GroupMask;
958 c->modrm = insn_fetch(u8, 1, c->eip);
959 --c->eip;
960
961 group = (group << 3) + ((c->modrm >> 3) & 7);
962 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
963 c->d = group2_table[group];
964 else
965 c->d = group_table[group];
966 }
967
968 /* Unrecognised? */
969 if (c->d == 0) {
970 DPRINTF("Cannot emulate %02x\n", c->b);
971 return -1;
6aa8b732
AK		 972 }
973
6e3d5dfb
AK		 974 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
975 c->op_bytes = 8;
976
6aa8b732 977 /* ModRM and SIB bytes. */
1c73ef66
AK		 978 if (c->d & ModRM)
979 rc = decode_modrm(ctxt, ops);
980 else if (c->d & MemAbs)
981 rc = decode_abs(ctxt, ops);
982 if (rc)
983 goto done;
6aa8b732 984
7a5b56df
AK		 985 if (!c->has_seg_override)
986 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 987
7a5b56df
AK		 988 if (!(!c->twobyte && c->b == 0x8d))
989 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 990
991 if (c->ad_bytes != 8)
992 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 993 /*
994 * Decode and fetch the source operand: register, memory
995 * or immediate.
996 */
e4e03ded 997 switch (c->d & SrcMask) {
6aa8b732
AK		 998 case SrcNone:
999 break;
1000 case SrcReg:
9f1ef3f8 1001 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1002 break;
1003 case SrcMem16:
e4e03ded 1004 c->src.bytes = 2;
6aa8b732
AK		 1005 goto srcmem_common;
1006 case SrcMem32:
e4e03ded 1007 c->src.bytes = 4;
6aa8b732
AK		 1008 goto srcmem_common;
1009 case SrcMem:
e4e03ded
LV		 1010 c->src.bytes = (c->d & ByteOp) ? 1 :
1011 c->op_bytes;
b85b9ee9 1012 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1013 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1014 break;
d77c26fc 1015 srcmem_common:
4e62417b
AJ		 1016 /*
1017 * For instructions with a ModR/M byte, switch to register
1018 * access if Mod = 3.
1019 */
e4e03ded
LV		 1020 if ((c->d & ModRM) && c->modrm_mod == 3) {
1021 c->src.type = OP_REG;
66b85505 1022 c->src.val = c->modrm_val;
107d6d2e 1023 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1024 break;
1025 }
e4e03ded 1026 c->src.type = OP_MEM;
6aa8b732
AK		 1027 break;
1028 case SrcImm:
e4e03ded
LV		 1029 c->src.type = OP_IMM;
1030 c->src.ptr = (unsigned long *)c->eip;
1031 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1032 if (c->src.bytes == 8)
1033 c->src.bytes = 4;
6aa8b732 1034 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1035 switch (c->src.bytes) {
6aa8b732 1036 case 1:
e4e03ded 1037 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1038 break;
1039 case 2:
e4e03ded 1040 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1041 break;
1042 case 4:
e4e03ded 1043 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1044 break;
1045 }
1046 break;
1047 case SrcImmByte:
341de7e3 1048 case SrcImmUByte:
e4e03ded
LV		 1049 c->src.type = OP_IMM;
1050 c->src.ptr = (unsigned long *)c->eip;
1051 c->src.bytes = 1;
341de7e3
GN		 1052 if ((c->d & SrcMask) == SrcImmByte)
1053 c->src.val = insn_fetch(s8, 1, c->eip);
1054 else
1055 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1056 break;
bfcadf83
GT		 1057 case SrcOne:
1058 c->src.bytes = 1;
1059 c->src.val = 1;
1060 break;
6aa8b732
AK		 1061 }
1062
0dc8d10f
GT		 1063 /*
1064 * Decode and fetch the second source operand: register, memory
1065 * or immediate.
1066 */
1067 switch (c->d & Src2Mask) {
1068 case Src2None:
1069 break;
1070 case Src2CL:
1071 c->src2.bytes = 1;
1072 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1073 break;
1074 case Src2ImmByte:
1075 c->src2.type = OP_IMM;
1076 c->src2.ptr = (unsigned long *)c->eip;
1077 c->src2.bytes = 1;
1078 c->src2.val = insn_fetch(u8, 1, c->eip);
1079 break;
a5f868bd
GN		 1080 case Src2Imm16:
1081 c->src2.type = OP_IMM;
1082 c->src2.ptr = (unsigned long *)c->eip;
1083 c->src2.bytes = 2;
1084 c->src2.val = insn_fetch(u16, 2, c->eip);
1085 break;
0dc8d10f
GT		 1086 case Src2One:
1087 c->src2.bytes = 1;
1088 c->src2.val = 1;
1089 break;
1090 }
1091
038e51de 1092 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1093 switch (c->d & DstMask) {
038e51de
AK		 1094 case ImplicitOps:
1095 /* Special instructions do their own operand decoding. */
8b4caf66 1096 return 0;
038e51de 1097 case DstReg:
9f1ef3f8 1098 decode_register_operand(&c->dst, c,
3c118e24 1099 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1100 break;
1101 case DstMem:
e4e03ded 1102 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1103 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1104 c->dst.type = OP_REG;
66b85505 1105 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1106 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1107 break;
1108 }
8b4caf66
LV		 1109 c->dst.type = OP_MEM;
1110 break;
9c9fddd0
GT		 1111 case DstAcc:
1112 c->dst.type = OP_REG;
1113 c->dst.bytes = c->op_bytes;
1114 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1115 switch (c->op_bytes) {
1116 case 1:
1117 c->dst.val = *(u8 *)c->dst.ptr;
1118 break;
1119 case 2:
1120 c->dst.val = *(u16 *)c->dst.ptr;
1121 break;
1122 case 4:
1123 c->dst.val = *(u32 *)c->dst.ptr;
1124 break;
1125 }
1126 c->dst.orig_val = c->dst.val;
1127 break;
8b4caf66
LV		 1128 }
1129
f5b4edcd
AK		 1130 if (c->rip_relative)
1131 c->modrm_ea += c->eip;
1132
8b4caf66
LV		 1133done:
1134 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1135}
1136
8cdbd2c9
LV		 1137static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1138{
1139 struct decode_cache *c = &ctxt->decode;
1140
1141 c->dst.type = OP_MEM;
1142 c->dst.bytes = c->op_bytes;
1143 c->dst.val = c->src.val;
7a957275 1144 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1145 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1146 c->regs[VCPU_REGS_RSP]);
1147}
1148
faa5a3ae 1149static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1150 struct x86_emulate_ops *ops,
1151 void *dest, int len)
8cdbd2c9
LV		 1152{
1153 struct decode_cache *c = &ctxt->decode;
1154 int rc;
1155
781d0edc
AK		 1156 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1157 c->regs[VCPU_REGS_RSP]),
350f69dc 1158 dest, len, ctxt->vcpu);
8cdbd2c9
LV		 1159 if (rc != 0)
1160 return rc;
1161
350f69dc 1162 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1163 return rc;
1164}
8cdbd2c9 1165
faa5a3ae
AK		 1166static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1167 struct x86_emulate_ops *ops)
1168{
1169 struct decode_cache *c = &ctxt->decode;
1170 int rc;
1171
350f69dc 1172 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1173 if (rc != 0)
1174 return rc;
8cdbd2c9
LV		 1175 return 0;
1176}
1177
05f086f8 1178static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1179{
05f086f8 1180 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1181 switch (c->modrm_reg) {
1182 case 0: /* rol */
05f086f8 1183 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1184 break;
1185 case 1: /* ror */
05f086f8 1186 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1187 break;
1188 case 2: /* rcl */
05f086f8 1189 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1190 break;
1191 case 3: /* rcr */
05f086f8 1192 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1193 break;
1194 case 4: /* sal/shl */
1195 case 6: /* sal/shl */
05f086f8 1196 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1197 break;
1198 case 5: /* shr */
05f086f8 1199 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1200 break;
1201 case 7: /* sar */
05f086f8 1202 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1203 break;
1204 }
1205}
1206
1207static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1208 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1209{
1210 struct decode_cache *c = &ctxt->decode;
1211 int rc = 0;
1212
1213 switch (c->modrm_reg) {
1214 case 0 ... 1: /* test */
05f086f8 1215 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1216 break;
1217 case 2: /* not */
1218 c->dst.val = ~c->dst.val;
1219 break;
1220 case 3: /* neg */
05f086f8 1221 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1222 break;
1223 default:
1224 DPRINTF("Cannot emulate %02x\n", c->b);
1225 rc = X86EMUL_UNHANDLEABLE;
1226 break;
1227 }
8cdbd2c9
LV		 1228 return rc;
1229}
1230
1231static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1232 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1233{
1234 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1235
1236 switch (c->modrm_reg) {
1237 case 0: /* inc */
05f086f8 1238 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1239 break;
1240 case 1: /* dec */
05f086f8 1241 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1242 break;
d19292e4
MG		 1243 case 2: /* call near abs */ {
1244 long int old_eip;
1245 old_eip = c->eip;
1246 c->eip = c->src.val;
1247 c->src.val = old_eip;
1248 emulate_push(ctxt);
1249 break;
1250 }
8cdbd2c9 1251 case 4: /* jmp abs */
fd60754e 1252 c->eip = c->src.val;
8cdbd2c9
LV		 1253 break;
1254 case 6: /* push */
fd60754e 1255 emulate_push(ctxt);
8cdbd2c9 1256 break;
8cdbd2c9
LV		 1257 }
1258 return 0;
1259}
1260
1261static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1262 struct x86_emulate_ops *ops,
e8d8d7fe 1263 unsigned long memop)
8cdbd2c9
LV		 1264{
1265 struct decode_cache *c = &ctxt->decode;
1266 u64 old, new;
1267 int rc;
1268
e8d8d7fe 1269 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1270 if (rc != 0)
1271 return rc;
1272
1273 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1274 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1275
1276 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1277 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1278 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1279
1280 } else {
1281 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1282 (u32) c->regs[VCPU_REGS_RBX];
1283
e8d8d7fe 1284 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1285 if (rc != 0)
1286 return rc;
05f086f8 1287 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1288 }
1289 return 0;
1290}
1291
a77ab5ea
AK		 1292static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1293 struct x86_emulate_ops *ops)
1294{
1295 struct decode_cache *c = &ctxt->decode;
1296 int rc;
1297 unsigned long cs;
1298
1299 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1300 if (rc)
1301 return rc;
1302 if (c->op_bytes == 4)
1303 c->eip = (u32)c->eip;
1304 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1305 if (rc)
1306 return rc;
1307 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1308 return rc;
1309}
1310
8cdbd2c9
LV		 1311static inline int writeback(struct x86_emulate_ctxt *ctxt,
1312 struct x86_emulate_ops *ops)
1313{
1314 int rc;
1315 struct decode_cache *c = &ctxt->decode;
1316
1317 switch (c->dst.type) {
1318 case OP_REG:
1319 /* The 4-byte case *is* correct:
1320 * in 64-bit mode we zero-extend.
1321 */
1322 switch (c->dst.bytes) {
1323 case 1:
1324 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1325 break;
1326 case 2:
1327 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1328 break;
1329 case 4:
1330 *c->dst.ptr = (u32)c->dst.val;
1331 break; /* 64b: zero-ext */
1332 case 8:
1333 *c->dst.ptr = c->dst.val;
1334 break;
1335 }
1336 break;
1337 case OP_MEM:
1338 if (c->lock_prefix)
1339 rc = ops->cmpxchg_emulated(
1340 (unsigned long)c->dst.ptr,
1341 &c->dst.orig_val,
1342 &c->dst.val,
1343 c->dst.bytes,
1344 ctxt->vcpu);
1345 else
1346 rc = ops->write_emulated(
1347 (unsigned long)c->dst.ptr,
1348 &c->dst.val,
1349 c->dst.bytes,
1350 ctxt->vcpu);
1351 if (rc != 0)
1352 return rc;
a01af5ec
LV		 1353 break;
1354 case OP_NONE:
1355 /* no writeback */
1356 break;
8cdbd2c9
LV		 1357 default:
1358 break;
1359 }
1360 return 0;
1361}
1362
8b4caf66 1363int
1be3aa47 1364x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1365{
e8d8d7fe 1366 unsigned long memop = 0;
8b4caf66 1367 u64 msr_data;
3427318f 1368 unsigned long saved_eip = 0;
8b4caf66 1369 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1370 unsigned int port;
1371 int io_dir_in;
1be3aa47 1372 int rc = 0;
8b4caf66 1373
3427318f
LV		 1374 /* Shadow copy of register state. Committed on successful emulation.
1375 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1376 * modify them.
1377 */
1378
ad312c7c 1379 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1380 saved_eip = c->eip;
1381
c7e75a3d 1382 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1383 memop = c->modrm_ea;
8b4caf66 1384
b9fa9d6b
AK		 1385 if (c->rep_prefix && (c->d & String)) {
1386 /* All REP prefixes have the same first termination condition */
1387 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1388 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1389 goto done;
1390 }
1391 /* The second termination condition only applies for REPE
1392 * and REPNE. Test if the repeat string operation prefix is
1393 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1394 * corresponding termination condition according to:
1395 * - if REPE/REPZ and ZF = 0 then done
1396 * - if REPNE/REPNZ and ZF = 1 then done
1397 */
1398 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1399 (c->b == 0xae) || (c->b == 0xaf)) {
1400 if ((c->rep_prefix == REPE_PREFIX) &&
1401 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1402 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1403 goto done;
1404 }
1405 if ((c->rep_prefix == REPNE_PREFIX) &&
1406 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1407 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1408 goto done;
1409 }
1410 }
1411 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1412 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1413 }
1414
8b4caf66 1415 if (c->src.type == OP_MEM) {
e8d8d7fe 1416 c->src.ptr = (unsigned long *)memop;
8b4caf66 1417 c->src.val = 0;
d77c26fc
MD		 1418 rc = ops->read_emulated((unsigned long)c->src.ptr,
1419 &c->src.val,
1420 c->src.bytes,
1421 ctxt->vcpu);
1422 if (rc != 0)
8b4caf66
LV		 1423 goto done;
1424 c->src.orig_val = c->src.val;
1425 }
1426
1427 if ((c->d & DstMask) == ImplicitOps)
1428 goto special_insn;
1429
1430
1431 if (c->dst.type == OP_MEM) {
e8d8d7fe 1432 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1433 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1434 c->dst.val = 0;
e4e03ded
LV		 1435 if (c->d & BitOp) {
1436 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1437
e4e03ded
LV		 1438 c->dst.ptr = (void *)c->dst.ptr +
1439 (c->src.val & mask) / 8;
038e51de 1440 }
e4e03ded
LV		 1441 if (!(c->d & Mov) &&
1442 /* optimisation - avoid slow emulated read */
1443 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1444 &c->dst.val,
1445 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1446 goto done;
038e51de 1447 }
e4e03ded 1448 c->dst.orig_val = c->dst.val;
038e51de 1449
018a98db
AK		 1450special_insn:
1451
e4e03ded 1452 if (c->twobyte)
6aa8b732
AK		 1453 goto twobyte_insn;
1454
e4e03ded 1455 switch (c->b) {
6aa8b732
AK		 1456 case 0x00 ... 0x05:
1457 add: /* add */
05f086f8 1458 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1459 break;
1460 case 0x08 ... 0x0d:
1461 or: /* or */
05f086f8 1462 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1463 break;
1464 case 0x10 ... 0x15:
1465 adc: /* adc */
05f086f8 1466 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1467 break;
1468 case 0x18 ... 0x1d:
1469 sbb: /* sbb */
05f086f8 1470 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1471 break;
aa3a816b 1472 case 0x20 ... 0x25:
6aa8b732 1473 and: /* and */
05f086f8 1474 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1475 break;
1476 case 0x28 ... 0x2d:
1477 sub: /* sub */
05f086f8 1478 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1479 break;
1480 case 0x30 ... 0x35:
1481 xor: /* xor */
05f086f8 1482 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1483 break;
1484 case 0x38 ... 0x3d:
1485 cmp: /* cmp */
05f086f8 1486 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1487 break;
33615aa9
AK		 1488 case 0x40 ... 0x47: /* inc r16/r32 */
1489 emulate_1op("inc", c->dst, ctxt->eflags);
1490 break;
1491 case 0x48 ... 0x4f: /* dec r16/r32 */
1492 emulate_1op("dec", c->dst, ctxt->eflags);
1493 break;
1494 case 0x50 ... 0x57: /* push reg */
2786b014 1495 emulate_push(ctxt);
33615aa9
AK		 1496 break;
1497 case 0x58 ... 0x5f: /* pop reg */
1498 pop_instruction:
350f69dc 1499 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1500 if (rc != 0)
33615aa9 1501 goto done;
33615aa9 1502 break;
6aa8b732 1503 case 0x63: /* movsxd */
8b4caf66 1504 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1505 goto cannot_emulate;
e4e03ded 1506 c->dst.val = (s32) c->src.val;
6aa8b732 1507 break;
91ed7a0e 1508 case 0x68: /* push imm */
018a98db 1509 case 0x6a: /* push imm8 */
018a98db
AK		 1510 emulate_push(ctxt);
1511 break;
1512 case 0x6c: /* insb */
1513 case 0x6d: /* insw/insd */
1514 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1515 1,
1516 (c->d & ByteOp) ? 1 : c->op_bytes,
1517 c->rep_prefix ?
e4706772 1518 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1519 (ctxt->eflags & EFLG_DF),
7a5b56df 1520 register_address(c, es_base(ctxt),
018a98db
AK		 1521 c->regs[VCPU_REGS_RDI]),
1522 c->rep_prefix,
1523 c->regs[VCPU_REGS_RDX]) == 0) {
1524 c->eip = saved_eip;
1525 return -1;
1526 }
1527 return 0;
1528 case 0x6e: /* outsb */
1529 case 0x6f: /* outsw/outsd */
1530 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1531 0,
1532 (c->d & ByteOp) ? 1 : c->op_bytes,
1533 c->rep_prefix ?
e4706772 1534 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1535 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1536 register_address(c,
1537 seg_override_base(ctxt, c),
018a98db
AK		 1538 c->regs[VCPU_REGS_RSI]),
1539 c->rep_prefix,
1540 c->regs[VCPU_REGS_RDX]) == 0) {
1541 c->eip = saved_eip;
1542 return -1;
1543 }
1544 return 0;
b2833e3c 1545 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1546 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1547 jmp_rel(c, c->src.val);
018a98db 1548 break;
6aa8b732 1549 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1550 switch (c->modrm_reg) {
6aa8b732
AK		 1551 case 0:
1552 goto add;
1553 case 1:
1554 goto or;
1555 case 2:
1556 goto adc;
1557 case 3:
1558 goto sbb;
1559 case 4:
1560 goto and;
1561 case 5:
1562 goto sub;
1563 case 6:
1564 goto xor;
1565 case 7:
1566 goto cmp;
1567 }
1568 break;
1569 case 0x84 ... 0x85:
05f086f8 1570 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1571 break;
1572 case 0x86 ... 0x87: /* xchg */
b13354f8 1573 xchg:
6aa8b732 1574 /* Write back the register source. */
e4e03ded 1575 switch (c->dst.bytes) {
6aa8b732 1576 case 1:
e4e03ded 1577 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1578 break;
1579 case 2:
e4e03ded 1580 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1581 break;
1582 case 4:
e4e03ded 1583 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1584 break; /* 64b reg: zero-extend */
1585 case 8:
e4e03ded 1586 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1587 break;
1588 }
1589 /*
1590 * Write back the memory destination with implicit LOCK
1591 * prefix.
1592 */
e4e03ded
LV		 1593 c->dst.val = c->src.val;
1594 c->lock_prefix = 1;
6aa8b732 1595 break;
6aa8b732 1596 case 0x88 ... 0x8b: /* mov */
7de75248 1597 goto mov;
38d5bc6d
GT		 1598 case 0x8c: { /* mov r/m, sreg */
1599 struct kvm_segment segreg;
1600
1601 if (c->modrm_reg <= 5)
1602 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1603 else {
1604 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1605 c->modrm);
1606 goto cannot_emulate;
1607 }
1608 c->dst.val = segreg.selector;
1609 break;
1610 }
7e0b54b1 1611 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1612 c->dst.val = c->modrm_ea;
7e0b54b1 1613 break;
4257198a
GT		 1614 case 0x8e: { /* mov seg, r/m16 */
1615 uint16_t sel;
1616 int type_bits;
1617 int err;
1618
1619 sel = c->src.val;
1620 if (c->modrm_reg <= 5) {
1621 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1622 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1623 type_bits, c->modrm_reg);
1624 } else {
1625 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1626 c->modrm);
1627 goto cannot_emulate;
1628 }
1629
1630 if (err < 0)
1631 goto cannot_emulate;
1632
1633 c->dst.type = OP_NONE; /* Disable writeback. */
1634 break;
1635 }
6aa8b732 1636 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1637 rc = emulate_grp1a(ctxt, ops);
1638 if (rc != 0)
6aa8b732 1639 goto done;
6aa8b732 1640 break;
b13354f8
MG		 1641 case 0x90: /* nop / xchg r8,rax */
1642 if (!(c->rex_prefix & 1)) { /* nop */
1643 c->dst.type = OP_NONE;
1644 break;
1645 }
1646 case 0x91 ... 0x97: /* xchg reg,rax */
1647 c->src.type = c->dst.type = OP_REG;
1648 c->src.bytes = c->dst.bytes = c->op_bytes;
1649 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1650 c->src.val = *(c->src.ptr);
1651 goto xchg;
fd2a7608 1652 case 0x9c: /* pushf */
05f086f8 1653 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1654 emulate_push(ctxt);
1655 break;
535eabcf 1656 case 0x9d: /* popf */
2b48cc75 1657 c->dst.type = OP_REG;
05f086f8 1658 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1659 c->dst.bytes = c->op_bytes;
535eabcf 1660 goto pop_instruction;
018a98db
AK		 1661 case 0xa0 ... 0xa1: /* mov */
1662 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1663 c->dst.val = c->src.val;
1664 break;
1665 case 0xa2 ... 0xa3: /* mov */
1666 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1667 break;
6aa8b732 1668 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1669 c->dst.type = OP_MEM;
1670 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1671 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1672 es_base(ctxt),
e4e03ded 1673 c->regs[VCPU_REGS_RDI]);
e4706772 1674 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1675 seg_override_base(ctxt, c),
e4e03ded
LV		 1676 c->regs[VCPU_REGS_RSI]),
1677 &c->dst.val,
1678 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1679 goto done;
7a957275 1680 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1681 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1682 : c->dst.bytes);
7a957275 1683 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1684 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1685 : c->dst.bytes);
6aa8b732
AK		 1686 break;
1687 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1688 c->src.type = OP_NONE; /* Disable writeback. */
1689 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1690 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1691 seg_override_base(ctxt, c),
d7e5117a
GT		 1692 c->regs[VCPU_REGS_RSI]);
1693 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1694 &c->src.val,
1695 c->src.bytes,
1696 ctxt->vcpu)) != 0)
1697 goto done;
1698
1699 c->dst.type = OP_NONE; /* Disable writeback. */
1700 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1701 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1702 es_base(ctxt),
d7e5117a
GT		 1703 c->regs[VCPU_REGS_RDI]);
1704 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1705 &c->dst.val,
1706 c->dst.bytes,
1707 ctxt->vcpu)) != 0)
1708 goto done;
1709
1710 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1711
1712 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1713
7a957275 1714 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1715 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1716 : c->src.bytes);
7a957275 1717 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1718 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1719 : c->dst.bytes);
1720
1721 break;
6aa8b732 1722 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1723 c->dst.type = OP_MEM;
1724 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1725 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1726 es_base(ctxt),
a7e6c88a 1727 c->regs[VCPU_REGS_RDI]);
e4e03ded 1728 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1729 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1730 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1731 : c->dst.bytes);
6aa8b732
AK		 1732 break;
1733 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1734 c->dst.type = OP_REG;
1735 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1736 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1737 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1738 seg_override_base(ctxt, c),
a7e6c88a
SY		 1739 c->regs[VCPU_REGS_RSI]),
1740 &c->dst.val,
1741 c->dst.bytes,
1742 ctxt->vcpu)) != 0)
6aa8b732 1743 goto done;
7a957275 1744 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1745 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1746 : c->dst.bytes);
6aa8b732
AK		 1747 break;
1748 case 0xae ... 0xaf: /* scas */
1749 DPRINTF("Urk! I don't handle SCAS.\n");
1750 goto cannot_emulate;
a5e2e82b 1751 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1752 goto mov;
018a98db
AK		 1753 case 0xc0 ... 0xc1:
1754 emulate_grp2(ctxt);
1755 break;
111de5d6 1756 case 0xc3: /* ret */
cf5de4f8 1757 c->dst.type = OP_REG;
111de5d6 1758 c->dst.ptr = &c->eip;
cf5de4f8 1759 c->dst.bytes = c->op_bytes;
111de5d6 1760 goto pop_instruction;
018a98db
AK		 1761 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1762 mov:
1763 c->dst.val = c->src.val;
1764 break;
a77ab5ea
AK		 1765 case 0xcb: /* ret far */
1766 rc = emulate_ret_far(ctxt, ops);
1767 if (rc)
1768 goto done;
1769 break;
018a98db
AK		 1770 case 0xd0 ... 0xd1: /* Grp2 */
1771 c->src.val = 1;
1772 emulate_grp2(ctxt);
1773 break;
1774 case 0xd2 ... 0xd3: /* Grp2 */
1775 c->src.val = c->regs[VCPU_REGS_RCX];
1776 emulate_grp2(ctxt);
1777 break;
a6a3034c
MG		 1778 case 0xe4: /* inb */
1779 case 0xe5: /* in */
84ce66a6 1780 port = c->src.val;
a6a3034c
MG		 1781 io_dir_in = 1;
1782 goto do_io;
1783 case 0xe6: /* outb */
1784 case 0xe7: /* out */
84ce66a6 1785 port = c->src.val;
a6a3034c
MG		 1786 io_dir_in = 0;
1787 goto do_io;
1a52e051 1788 case 0xe8: /* call (near) */ {
d53c4777 1789 long int rel = c->src.val;
e4e03ded 1790 c->src.val = (unsigned long) c->eip;
7a957275 1791 jmp_rel(c, rel);
8cdbd2c9
LV		 1792 emulate_push(ctxt);
1793 break;
1a52e051
NK		 1794 }
1795 case 0xe9: /* jmp rel */
954cd36f 1796 goto jmp;
782b877c
GN		 1797 case 0xea: /* jmp far */
1798 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
1799 VCPU_SREG_CS) < 0) {
954cd36f
GT		 1800 DPRINTF("jmp far: Failed to load CS descriptor\n");
1801 goto cannot_emulate;
1802 }
1803
782b877c 1804 c->eip = c->src.val;
954cd36f 1805 break;
954cd36f
GT		 1806 case 0xeb:
1807 jmp: /* jmp rel short */
7a957275 1808 jmp_rel(c, c->src.val);
a01af5ec 1809 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1810 break;
a6a3034c
MG		 1811 case 0xec: /* in al,dx */
1812 case 0xed: /* in (e/r)ax,dx */
1813 port = c->regs[VCPU_REGS_RDX];
1814 io_dir_in = 1;
1815 goto do_io;
1816 case 0xee: /* out al,dx */
1817 case 0xef: /* out (e/r)ax,dx */
1818 port = c->regs[VCPU_REGS_RDX];
1819 io_dir_in = 0;
1820 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1821 (c->d & ByteOp) ? 1 : c->op_bytes,
1822 port) != 0) {
1823 c->eip = saved_eip;
1824 goto cannot_emulate;
1825 }
e93f36bc 1826 break;
111de5d6 1827 case 0xf4: /* hlt */
ad312c7c 1828 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1829 break;
111de5d6
AK		 1830 case 0xf5: /* cmc */
1831 /* complement carry flag from eflags reg */
1832 ctxt->eflags ^= EFLG_CF;
1833 c->dst.type = OP_NONE; /* Disable writeback. */
1834 break;
018a98db
AK		 1835 case 0xf6 ... 0xf7: /* Grp3 */
1836 rc = emulate_grp3(ctxt, ops);
1837 if (rc != 0)
1838 goto done;
1839 break;
111de5d6
AK		 1840 case 0xf8: /* clc */
1841 ctxt->eflags &= ~EFLG_CF;
1842 c->dst.type = OP_NONE; /* Disable writeback. */
1843 break;
1844 case 0xfa: /* cli */
1845 ctxt->eflags &= ~X86_EFLAGS_IF;
1846 c->dst.type = OP_NONE; /* Disable writeback. */
1847 break;
1848 case 0xfb: /* sti */
1849 ctxt->eflags |= X86_EFLAGS_IF;
1850 c->dst.type = OP_NONE; /* Disable writeback. */
1851 break;
fb4616f4
MG		 1852 case 0xfc: /* cld */
1853 ctxt->eflags &= ~EFLG_DF;
1854 c->dst.type = OP_NONE; /* Disable writeback. */
1855 break;
1856 case 0xfd: /* std */
1857 ctxt->eflags |= EFLG_DF;
1858 c->dst.type = OP_NONE; /* Disable writeback. */
1859 break;
018a98db
AK		 1860 case 0xfe ... 0xff: /* Grp4/Grp5 */
1861 rc = emulate_grp45(ctxt, ops);
1862 if (rc != 0)
1863 goto done;
1864 break;
6aa8b732 1865 }
018a98db
AK		 1866
1867writeback:
1868 rc = writeback(ctxt, ops);
1869 if (rc != 0)
1870 goto done;
1871
1872 /* Commit shadow register state. */
ad312c7c 1873 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1874 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1875
1876done:
1877 if (rc == X86EMUL_UNHANDLEABLE) {
1878 c->eip = saved_eip;
1879 return -1;
1880 }
1881 return 0;
6aa8b732
AK		 1882
1883twobyte_insn:
e4e03ded 1884 switch (c->b) {
6aa8b732 1885 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1886 switch (c->modrm_reg) {
6aa8b732
AK		 1887 u16 size;
1888 unsigned long address;
1889
aca7f966 1890 case 0: /* vmcall */
e4e03ded 1891 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1892 goto cannot_emulate;
1893
7aa81cc0
AL		 1894 rc = kvm_fix_hypercall(ctxt->vcpu);
1895 if (rc)
1896 goto done;
1897
33e3885d 1898 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1899 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1900 /* Disable writeback. */
1901 c->dst.type = OP_NONE;
aca7f966 1902 break;
6aa8b732 1903 case 2: /* lgdt */
e4e03ded
LV		 1904 rc = read_descriptor(ctxt, ops, c->src.ptr,
1905 &size, &address, c->op_bytes);
6aa8b732
AK		 1906 if (rc)
1907 goto done;
1908 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1909 /* Disable writeback. */
1910 c->dst.type = OP_NONE;
6aa8b732 1911 break;
aca7f966 1912 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 1913 if (c->modrm_mod == 3) {
1914 switch (c->modrm_rm) {
1915 case 1:
1916 rc = kvm_fix_hypercall(ctxt->vcpu);
1917 if (rc)
1918 goto done;
1919 break;
1920 default:
1921 goto cannot_emulate;
1922 }
aca7f966 1923 } else {
e4e03ded 1924 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1925 &size, &address,
e4e03ded 1926 c->op_bytes);
aca7f966
AL		 1927 if (rc)
1928 goto done;
1929 realmode_lidt(ctxt->vcpu, size, address);
1930 }
16286d08
AK		 1931 /* Disable writeback. */
1932 c->dst.type = OP_NONE;
6aa8b732
AK		 1933 break;
1934 case 4: /* smsw */
16286d08
AK		 1935 c->dst.bytes = 2;
1936 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1937 break;
1938 case 6: /* lmsw */
16286d08
AK		 1939 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1940 &ctxt->eflags);
dc7457ea 1941 c->dst.type = OP_NONE;
6aa8b732
AK		 1942 break;
1943 case 7: /* invlpg*/
e8d8d7fe 1944 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1945 /* Disable writeback. */
1946 c->dst.type = OP_NONE;
6aa8b732
AK		 1947 break;
1948 default:
1949 goto cannot_emulate;
1950 }
1951 break;
018a98db
AK		 1952 case 0x06:
1953 emulate_clts(ctxt->vcpu);
1954 c->dst.type = OP_NONE;
1955 break;
1956 case 0x08: /* invd */
1957 case 0x09: /* wbinvd */
1958 case 0x0d: /* GrpP (prefetch) */
1959 case 0x18: /* Grp16 (prefetch/nop) */
1960 c->dst.type = OP_NONE;
1961 break;
1962 case 0x20: /* mov cr, reg */
1963 if (c->modrm_mod != 3)
1964 goto cannot_emulate;
1965 c->regs[c->modrm_rm] =
1966 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1967 c->dst.type = OP_NONE; /* no writeback */
1968 break;
6aa8b732 1969 case 0x21: /* mov from dr to reg */
e4e03ded 1970 if (c->modrm_mod != 3)
6aa8b732 1971 goto cannot_emulate;
8cdbd2c9 1972 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1973 if (rc)
1974 goto cannot_emulate;
1975 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1976 break;
018a98db
AK		 1977 case 0x22: /* mov reg, cr */
1978 if (c->modrm_mod != 3)
1979 goto cannot_emulate;
1980 realmode_set_cr(ctxt->vcpu,
1981 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1982 c->dst.type = OP_NONE;
1983 break;
6aa8b732 1984 case 0x23: /* mov from reg to dr */
e4e03ded 1985 if (c->modrm_mod != 3)
6aa8b732 1986 goto cannot_emulate;
e4e03ded
LV		 1987 rc = emulator_set_dr(ctxt, c->modrm_reg,
1988 c->regs[c->modrm_rm]);
a01af5ec
LV		 1989 if (rc)
1990 goto cannot_emulate;
1991 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1992 break;
018a98db
AK		 1993 case 0x30:
1994 /* wrmsr */
1995 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1996 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1997 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1998 if (rc) {
c1a5d4f9 1999 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2000 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2001 }
2002 rc = X86EMUL_CONTINUE;
2003 c->dst.type = OP_NONE;
2004 break;
2005 case 0x32:
2006 /* rdmsr */
2007 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2008 if (rc) {
c1a5d4f9 2009 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2010 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2011 } else {
2012 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2013 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2014 }
2015 rc = X86EMUL_CONTINUE;
2016 c->dst.type = OP_NONE;
2017 break;
6aa8b732 2018 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2019 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2020 if (!test_cc(c->b, ctxt->eflags))
2021 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2022 break;
b2833e3c 2023 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2024 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2025 jmp_rel(c, c->src.val);
018a98db
AK		 2026 c->dst.type = OP_NONE;
2027 break;
7de75248
NK		 2028 case 0xa3:
2029 bt: /* bt */
e4f8e039 2030 c->dst.type = OP_NONE;
e4e03ded
LV		 2031 /* only subword offset */
2032 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2033 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2034 break;
9bf8ea42
GT		 2035 case 0xa4: /* shld imm8, r, r/m */
2036 case 0xa5: /* shld cl, r, r/m */
2037 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2038 break;
7de75248
NK		 2039 case 0xab:
2040 bts: /* bts */
e4e03ded
LV		 2041 /* only subword offset */
2042 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2043 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2044 break;
9bf8ea42
GT		 2045 case 0xac: /* shrd imm8, r, r/m */
2046 case 0xad: /* shrd cl, r, r/m */
2047 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2048 break;
2a7c5b8b
GC		 2049 case 0xae: /* clflush */
2050 break;
6aa8b732
AK		 2051 case 0xb0 ... 0xb1: /* cmpxchg */
2052 /*
2053 * Save real source value, then compare EAX against
2054 * destination.
2055 */
e4e03ded
LV		 2056 c->src.orig_val = c->src.val;
2057 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2058 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2059 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2060 /* Success: write back to memory. */
e4e03ded 2061 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2062 } else {
2063 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2064 c->dst.type = OP_REG;
2065 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2066 }
2067 break;
6aa8b732
AK		 2068 case 0xb3:
2069 btr: /* btr */
e4e03ded
LV		 2070 /* only subword offset */
2071 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2072 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2073 break;
6aa8b732 2074 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2075 c->dst.bytes = c->op_bytes;
2076 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2077 : (u16) c->src.val;
6aa8b732 2078 break;
6aa8b732 2079 case 0xba: /* Grp8 */
e4e03ded 2080 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2081 case 0:
2082 goto bt;
2083 case 1:
2084 goto bts;
2085 case 2:
2086 goto btr;
2087 case 3:
2088 goto btc;
2089 }
2090 break;
7de75248
NK		 2091 case 0xbb:
2092 btc: /* btc */
e4e03ded
LV		 2093 /* only subword offset */
2094 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2095 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2096 break;
6aa8b732 2097 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2098 c->dst.bytes = c->op_bytes;
2099 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2100 (s16) c->src.val;
6aa8b732 2101 break;
a012e65a 2102 case 0xc3: /* movnti */
e4e03ded
LV		 2103 c->dst.bytes = c->op_bytes;
2104 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2105 (u64) c->src.val;
a012e65a 2106 break;
6aa8b732 2107 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2108 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2109 if (rc != 0)
2110 goto done;
018a98db 2111 c->dst.type = OP_NONE;
8cdbd2c9 2112 break;
6aa8b732
AK		 2113 }
2114 goto writeback;
2115
2116cannot_emulate:
e4e03ded 2117 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2118 c->eip = saved_eip;
6aa8b732
AK		 2119 return -1;
2120}
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