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KVM: x86 emulator: add ad_mask static inline
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
6aa8b732
AK		 29#define DPRINTF(x...) do {} while (0)
30#endif
6aa8b732 31#include <linux/module.h>
edf88417 32#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
c7e75a3d 65#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 66#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 67#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 68#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 71
43bb19cd 72enum {
1d6ad207 73 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 75};
76
c7e75a3d 77static u16 opcode_table[256] = {
6aa8b732
AK		 78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 97 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
d77a2507 110 /* 0x40 - 0x47 */
33615aa9 111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 112 /* 0x48 - 0x4F */
33615aa9 113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 114 /* 0x50 - 0x57 */
6e3d5dfb
AK		 115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 117 /* 0x58 - 0x5F */
6e3d5dfb
AK		 118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 120 /* 0x60 - 0x67 */
6aa8b732 121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
6e3d5dfb 124 0, 0, ImplicitOps | Mov | Stack, 0,
e70669ab
LV		 125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 133 /* 0x80 - 0x87 */
1d6ad207
AK		 134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
43bb19cd 141 0, ModRM | DstReg, 0, Group | Group1A,
6aa8b732 142 /* 0x90 - 0x9F */
6e3d5dfb
AK		 143 0, 0, 0, 0, 0, 0, 0, 0,
144 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 145 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 146 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
147 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 148 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
149 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 150 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 151 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
153 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732
AK		 154 /* 0xB0 - 0xBF */
155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xC0 - 0xC7 */
d9413cd7 157 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 158 0, ImplicitOps | Stack, 0, 0,
d9413cd7 159 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 160 /* 0xC8 - 0xCF */
161 0, 0, 0, 0, 0, 0, 0, 0,
162 /* 0xD0 - 0xD7 */
163 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
164 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
165 0, 0, 0, 0,
166 /* 0xD8 - 0xDF */
167 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 168 /* 0xE0 - 0xE7 */
169 0, 0, 0, 0, 0, 0, 0, 0,
170 /* 0xE8 - 0xEF */
6e3d5dfb
AK		 171 ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
172 0, 0, 0, 0,
6aa8b732
AK		 173 /* 0xF0 - 0xF7 */
174 0, 0, 0, 0,
7d858a19 175 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 176 /* 0xF8 - 0xFF */
b284be57 177 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fd60754e 178 0, 0, Group | Group4, Group | Group5,
6aa8b732
AK		 179};
180
038e51de 181static u16 twobyte_table[256] = {
6aa8b732 182 /* 0x00 - 0x0F */
d95058a1 183 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 184 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 185 /* 0x10 - 0x1F */
186 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
187 /* 0x20 - 0x2F */
188 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
189 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x30 - 0x3F */
35f3f286 191 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 192 /* 0x40 - 0x47 */
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
195 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
196 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
197 /* 0x48 - 0x4F */
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
202 /* 0x50 - 0x5F */
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x60 - 0x6F */
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
206 /* 0x70 - 0x7F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x80 - 0x8F */
bbe9abbd
NK		 209 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
210 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
211 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
212 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 213 /* 0x90 - 0x9F */
214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
215 /* 0xA0 - 0xA7 */
038e51de 216 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 217 /* 0xA8 - 0xAF */
038e51de 218 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 219 /* 0xB0 - 0xB7 */
220 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 221 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 222 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem16 | ModRM | Mov,
224 /* 0xB8 - 0xBF */
038e51de 225 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xC0 - 0xCF */
a012e65a
SY		 229 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
230 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 231 /* 0xD0 - 0xDF */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0xE0 - 0xEF */
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0xF0 - 0xFF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
237};
238
e09d082c 239static u16 group_table[] = {
1d6ad207
AK		 240 [Group1_80*8] =
241 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
242 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
243 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
244 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
245 [Group1_81*8] =
246 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
247 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
248 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
249 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
250 [Group1_82*8] =
251 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
252 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
253 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
255 [Group1_83*8] =
256 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
257 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
258 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
259 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 260 [Group1A*8] =
261 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 262 [Group3_Byte*8] =
263 ByteOp | SrcImm | DstMem | ModRM, 0,
264 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
265 0, 0, 0, 0,
266 [Group3*8] =
267 DstMem | SrcImm | ModRM | SrcImm, 0,
268 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
fd60754e
AK		 270 [Group4*8] =
271 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
272 0, 0, 0, 0, 0, 0,
273 [Group5*8] =
274 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
275 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 276 [Group7*8] =
277 0, 0, ModRM | SrcMem, ModRM | SrcMem,
278 SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, SrcMem | ModRM | ByteOp,
e09d082c
AK		 279};
280
281static u16 group2_table[] = {
d95058a1
AK		 282 [Group7*8] =
283 SrcNone | ModRM, 0, 0, 0, SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, 0,
e09d082c
AK		 284};
285
6aa8b732
AK		 286/* EFLAGS bit definitions. */
287#define EFLG_OF (1<<11)
288#define EFLG_DF (1<<10)
289#define EFLG_SF (1<<7)
290#define EFLG_ZF (1<<6)
291#define EFLG_AF (1<<4)
292#define EFLG_PF (1<<2)
293#define EFLG_CF (1<<0)
294
295/*
296 * Instruction emulation:
297 * Most instructions are emulated directly via a fragment of inline assembly
298 * code. This allows us to save/restore EFLAGS and thus very easily pick up
299 * any modified flags.
300 */
301
05b3e0c2 302#if defined(CONFIG_X86_64)
6aa8b732
AK		 303#define _LO32 "k" /* force 32-bit operand */
304#define _STK "%%rsp" /* stack pointer */
305#elif defined(__i386__)
306#define _LO32 "" /* force 32-bit operand */
307#define _STK "%%esp" /* stack pointer */
308#endif
309
310/*
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
313 */
314#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
315
316/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 317#define _PRE_EFLAGS(_sav, _msk, _tmp) \
318 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
319 "movl %"_sav",%"_LO32 _tmp"; " \
320 "push %"_tmp"; " \
321 "push %"_tmp"; " \
322 "movl %"_msk",%"_LO32 _tmp"; " \
323 "andl %"_LO32 _tmp",("_STK"); " \
324 "pushf; " \
325 "notl %"_LO32 _tmp"; " \
326 "andl %"_LO32 _tmp",("_STK"); " \
327 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
328 "pop %"_tmp"; " \
329 "orl %"_LO32 _tmp",("_STK"); " \
330 "popf; " \
331 "pop %"_sav"; "
6aa8b732
AK		 332
333/* After executing instruction: write-back necessary bits in EFLAGS. */
334#define _POST_EFLAGS(_sav, _msk, _tmp) \
335 /* _sav |= EFLAGS & _msk; */ \
336 "pushf; " \
337 "pop %"_tmp"; " \
338 "andl %"_msk",%"_LO32 _tmp"; " \
339 "orl %"_LO32 _tmp",%"_sav"; "
340
341/* Raw emulation: instruction has two explicit operands. */
342#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
343 do { \
344 unsigned long _tmp; \
345 \
346 switch ((_dst).bytes) { \
347 case 2: \
348 __asm__ __volatile__ ( \
d77c26fc 349 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 350 _op"w %"_wx"3,%1; " \
d77c26fc 351 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 352 : "=m" (_eflags), "=m" ((_dst).val), \
353 "=&r" (_tmp) \
d77c26fc 354 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 355 break; \
356 case 4: \
357 __asm__ __volatile__ ( \
d77c26fc 358 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 359 _op"l %"_lx"3,%1; " \
d77c26fc 360 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 361 : "=m" (_eflags), "=m" ((_dst).val), \
362 "=&r" (_tmp) \
d77c26fc 363 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 364 break; \
365 case 8: \
366 __emulate_2op_8byte(_op, _src, _dst, \
367 _eflags, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
373 do { \
374 unsigned long _tmp; \
d77c26fc 375 switch ((_dst).bytes) { \
6aa8b732
AK		 376 case 1: \
377 __asm__ __volatile__ ( \
d77c26fc 378 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 379 _op"b %"_bx"3,%1; " \
d77c26fc 380 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 381 : "=m" (_eflags), "=m" ((_dst).val), \
382 "=&r" (_tmp) \
d77c26fc 383 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 384 break; \
385 default: \
386 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
387 _wx, _wy, _lx, _ly, _qx, _qy); \
388 break; \
389 } \
390 } while (0)
391
392/* Source operand is byte-sized and may be restricted to just %cl. */
393#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
394 __emulate_2op(_op, _src, _dst, _eflags, \
395 "b", "c", "b", "c", "b", "c", "b", "c")
396
397/* Source operand is byte, word, long or quad sized. */
398#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
399 __emulate_2op(_op, _src, _dst, _eflags, \
400 "b", "q", "w", "r", _LO32, "r", "", "r")
401
402/* Source operand is word, long or quad sized. */
403#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
404 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
405 "w", "r", _LO32, "r", "", "r")
406
407/* Instruction has only one explicit operand (no source operand). */
408#define emulate_1op(_op, _dst, _eflags) \
409 do { \
410 unsigned long _tmp; \
411 \
d77c26fc 412 switch ((_dst).bytes) { \
6aa8b732
AK		 413 case 1: \
414 __asm__ __volatile__ ( \
d77c26fc 415 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 416 _op"b %1; " \
d77c26fc 417 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 418 : "=m" (_eflags), "=m" ((_dst).val), \
419 "=&r" (_tmp) \
d77c26fc 420 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 421 break; \
422 case 2: \
423 __asm__ __volatile__ ( \
d77c26fc 424 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 425 _op"w %1; " \
d77c26fc 426 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 427 : "=m" (_eflags), "=m" ((_dst).val), \
428 "=&r" (_tmp) \
d77c26fc 429 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 430 break; \
431 case 4: \
432 __asm__ __volatile__ ( \
d77c26fc 433 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 434 _op"l %1; " \
d77c26fc 435 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 436 : "=m" (_eflags), "=m" ((_dst).val), \
437 "=&r" (_tmp) \
d77c26fc 438 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 439 break; \
440 case 8: \
441 __emulate_1op_8byte(_op, _dst, _eflags); \
442 break; \
443 } \
444 } while (0)
445
446/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 447#if defined(CONFIG_X86_64)
6aa8b732
AK		 448#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
449 do { \
450 __asm__ __volatile__ ( \
d77c26fc 451 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 452 _op"q %"_qx"3,%1; " \
d77c26fc 453 _POST_EFLAGS("0", "4", "2") \
6aa8b732 454 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 455 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 456 } while (0)
457
458#define __emulate_1op_8byte(_op, _dst, _eflags) \
459 do { \
460 __asm__ __volatile__ ( \
d77c26fc 461 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 462 _op"q %1; " \
d77c26fc 463 _POST_EFLAGS("0", "3", "2") \
6aa8b732 464 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 465 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 466 } while (0)
467
468#elif defined(__i386__)
469#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
470#define __emulate_1op_8byte(_op, _dst, _eflags)
471#endif /* __i386__ */
472
473/* Fetch next part of the instruction being emulated. */
474#define insn_fetch(_type, _size, _eip) \
475({ unsigned long _x; \
62266869 476 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 477 if (rc != 0) \
6aa8b732
AK		 478 goto done; \
479 (_eip) += (_size); \
480 (_type)_x; \
481})
482
ddcb2885
HH		 483static inline unsigned long ad_mask(struct decode_cache *c)
484{
485 return (1UL << (c->ad_bytes << 3)) - 1;
486}
487
6aa8b732 488/* Access/update address held in a register, based on addressing mode. */
e70669ab 489#define address_mask(reg) \
e4e03ded 490 ((c->ad_bytes == sizeof(unsigned long)) ? \
ddcb2885 491 (reg) : ((reg) & ad_mask(c)))
6aa8b732 492#define register_address(base, reg) \
e70669ab 493 ((base) + address_mask(reg))
6aa8b732
AK		 494#define register_address_increment(reg, inc) \
495 do { \
496 /* signed type ensures sign extension to long */ \
497 int _inc = (inc); \
e4e03ded 498 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 499 (reg) += _inc; \
500 else \
e4e03ded 501 (reg) = ((reg) & \
ddcb2885 502 ~ad_mask(c)) | \
e4e03ded 503 (((reg) + _inc) & \
ddcb2885 504 ad_mask(c)); \
6aa8b732
AK		 505 } while (0)
506
098c937b
NK		 507#define JMP_REL(rel) \
508 do { \
e4e03ded 509 register_address_increment(c->eip, rel); \
098c937b
NK		 510 } while (0)
511
62266869
AK		 512static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
513 struct x86_emulate_ops *ops,
514 unsigned long linear, u8 *dest)
515{
516 struct fetch_cache *fc = &ctxt->decode.fetch;
517 int rc;
518 int size;
519
520 if (linear < fc->start || linear >= fc->end) {
521 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
522 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
523 if (rc)
524 return rc;
525 fc->start = linear;
526 fc->end = linear + size;
527 }
528 *dest = fc->data[linear - fc->start];
529 return 0;
530}
531
532static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
533 struct x86_emulate_ops *ops,
534 unsigned long eip, void *dest, unsigned size)
535{
536 int rc = 0;
537
538 eip += ctxt->cs_base;
539 while (size--) {
540 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
541 if (rc)
542 return rc;
543 }
544 return 0;
545}
546
1e3c5cb0
RR		 547/*
548 * Given the 'reg' portion of a ModRM byte, and a register block, return a
549 * pointer into the block that addresses the relevant register.
550 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
551 */
552static void *decode_register(u8 modrm_reg, unsigned long *regs,
553 int highbyte_regs)
6aa8b732
AK		 554{
555 void *p;
556
557 p = &regs[modrm_reg];
558 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
559 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
560 return p;
561}
562
563static int read_descriptor(struct x86_emulate_ctxt *ctxt,
564 struct x86_emulate_ops *ops,
565 void *ptr,
566 u16 *size, unsigned long *address, int op_bytes)
567{
568 int rc;
569
570 if (op_bytes == 2)
571 op_bytes = 3;
572 *address = 0;
cebff02b
LV		 573 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
574 ctxt->vcpu);
6aa8b732
AK		 575 if (rc)
576 return rc;
cebff02b
LV		 577 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
578 ctxt->vcpu);
6aa8b732
AK		 579 return rc;
580}
581
bbe9abbd
NK		 582static int test_cc(unsigned int condition, unsigned int flags)
583{
584 int rc = 0;
585
586 switch ((condition & 15) >> 1) {
587 case 0: /* o */
588 rc |= (flags & EFLG_OF);
589 break;
590 case 1: /* b/c/nae */
591 rc |= (flags & EFLG_CF);
592 break;
593 case 2: /* z/e */
594 rc |= (flags & EFLG_ZF);
595 break;
596 case 3: /* be/na */
597 rc |= (flags & (EFLG_CF|EFLG_ZF));
598 break;
599 case 4: /* s */
600 rc |= (flags & EFLG_SF);
601 break;
602 case 5: /* p/pe */
603 rc |= (flags & EFLG_PF);
604 break;
605 case 7: /* le/ng */
606 rc |= (flags & EFLG_ZF);
607 /* fall through */
608 case 6: /* l/nge */
609 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
610 break;
611 }
612
613 /* Odd condition identifiers (lsb == 1) have inverted sense. */
614 return (!!rc ^ (condition & 1));
615}
616
3c118e24
AK		 617static void decode_register_operand(struct operand *op,
618 struct decode_cache *c,
3c118e24
AK		 619 int inhibit_bytereg)
620{
33615aa9 621 unsigned reg = c->modrm_reg;
9f1ef3f8 622 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 623
624 if (!(c->d & ModRM))
625 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 626 op->type = OP_REG;
627 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 628 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 629 op->val = *(u8 *)op->ptr;
630 op->bytes = 1;
631 } else {
33615aa9 632 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 633 op->bytes = c->op_bytes;
634 switch (op->bytes) {
635 case 2:
636 op->val = *(u16 *)op->ptr;
637 break;
638 case 4:
639 op->val = *(u32 *)op->ptr;
640 break;
641 case 8:
642 op->val = *(u64 *) op->ptr;
643 break;
644 }
645 }
646 op->orig_val = op->val;
647}
648
1c73ef66
AK		 649static int decode_modrm(struct x86_emulate_ctxt *ctxt,
650 struct x86_emulate_ops *ops)
651{
652 struct decode_cache *c = &ctxt->decode;
653 u8 sib;
654 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
655 int rc = 0;
656
657 if (c->rex_prefix) {
658 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
659 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
660 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
661 }
662
663 c->modrm = insn_fetch(u8, 1, c->eip);
664 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
665 c->modrm_reg |= (c->modrm & 0x38) >> 3;
666 c->modrm_rm |= (c->modrm & 0x07);
667 c->modrm_ea = 0;
668 c->use_modrm_ea = 1;
669
670 if (c->modrm_mod == 3) {
671 c->modrm_val = *(unsigned long *)
672 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
673 return rc;
674 }
675
676 if (c->ad_bytes == 2) {
677 unsigned bx = c->regs[VCPU_REGS_RBX];
678 unsigned bp = c->regs[VCPU_REGS_RBP];
679 unsigned si = c->regs[VCPU_REGS_RSI];
680 unsigned di = c->regs[VCPU_REGS_RDI];
681
682 /* 16-bit ModR/M decode. */
683 switch (c->modrm_mod) {
684 case 0:
685 if (c->modrm_rm == 6)
686 c->modrm_ea += insn_fetch(u16, 2, c->eip);
687 break;
688 case 1:
689 c->modrm_ea += insn_fetch(s8, 1, c->eip);
690 break;
691 case 2:
692 c->modrm_ea += insn_fetch(u16, 2, c->eip);
693 break;
694 }
695 switch (c->modrm_rm) {
696 case 0:
697 c->modrm_ea += bx + si;
698 break;
699 case 1:
700 c->modrm_ea += bx + di;
701 break;
702 case 2:
703 c->modrm_ea += bp + si;
704 break;
705 case 3:
706 c->modrm_ea += bp + di;
707 break;
708 case 4:
709 c->modrm_ea += si;
710 break;
711 case 5:
712 c->modrm_ea += di;
713 break;
714 case 6:
715 if (c->modrm_mod != 0)
716 c->modrm_ea += bp;
717 break;
718 case 7:
719 c->modrm_ea += bx;
720 break;
721 }
722 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
723 (c->modrm_rm == 6 && c->modrm_mod != 0))
724 if (!c->override_base)
725 c->override_base = &ctxt->ss_base;
726 c->modrm_ea = (u16)c->modrm_ea;
727 } else {
728 /* 32/64-bit ModR/M decode. */
729 switch (c->modrm_rm) {
730 case 4:
731 case 12:
732 sib = insn_fetch(u8, 1, c->eip);
733 index_reg |= (sib >> 3) & 7;
734 base_reg |= sib & 7;
735 scale = sib >> 6;
736
737 switch (base_reg) {
738 case 5:
739 if (c->modrm_mod != 0)
740 c->modrm_ea += c->regs[base_reg];
741 else
742 c->modrm_ea +=
743 insn_fetch(s32, 4, c->eip);
744 break;
745 default:
746 c->modrm_ea += c->regs[base_reg];
747 }
748 switch (index_reg) {
749 case 4:
750 break;
751 default:
752 c->modrm_ea += c->regs[index_reg] << scale;
753 }
754 break;
755 case 5:
756 if (c->modrm_mod != 0)
757 c->modrm_ea += c->regs[c->modrm_rm];
758 else if (ctxt->mode == X86EMUL_MODE_PROT64)
759 rip_relative = 1;
760 break;
761 default:
762 c->modrm_ea += c->regs[c->modrm_rm];
763 break;
764 }
765 switch (c->modrm_mod) {
766 case 0:
767 if (c->modrm_rm == 5)
768 c->modrm_ea += insn_fetch(s32, 4, c->eip);
769 break;
770 case 1:
771 c->modrm_ea += insn_fetch(s8, 1, c->eip);
772 break;
773 case 2:
774 c->modrm_ea += insn_fetch(s32, 4, c->eip);
775 break;
776 }
777 }
778 if (rip_relative) {
779 c->modrm_ea += c->eip;
780 switch (c->d & SrcMask) {
781 case SrcImmByte:
782 c->modrm_ea += 1;
783 break;
784 case SrcImm:
785 if (c->d & ByteOp)
786 c->modrm_ea += 1;
787 else
788 if (c->op_bytes == 8)
789 c->modrm_ea += 4;
790 else
791 c->modrm_ea += c->op_bytes;
792 }
793 }
794done:
795 return rc;
796}
797
798static int decode_abs(struct x86_emulate_ctxt *ctxt,
799 struct x86_emulate_ops *ops)
800{
801 struct decode_cache *c = &ctxt->decode;
802 int rc = 0;
803
804 switch (c->ad_bytes) {
805 case 2:
806 c->modrm_ea = insn_fetch(u16, 2, c->eip);
807 break;
808 case 4:
809 c->modrm_ea = insn_fetch(u32, 4, c->eip);
810 break;
811 case 8:
812 c->modrm_ea = insn_fetch(u64, 8, c->eip);
813 break;
814 }
815done:
816 return rc;
817}
818
6aa8b732 819int
8b4caf66 820x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 821{
e4e03ded 822 struct decode_cache *c = &ctxt->decode;
6aa8b732 823 int rc = 0;
6aa8b732 824 int mode = ctxt->mode;
e09d082c 825 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 826
827 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 828
e4e03ded 829 memset(c, 0, sizeof(struct decode_cache));
ad312c7c
ZX		 830 c->eip = ctxt->vcpu->arch.rip;
831 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 832
833 switch (mode) {
834 case X86EMUL_MODE_REAL:
835 case X86EMUL_MODE_PROT16:
f21b8bf4 836 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 837 break;
838 case X86EMUL_MODE_PROT32:
f21b8bf4 839 def_op_bytes = def_ad_bytes = 4;
6aa8b732 840 break;
05b3e0c2 841#ifdef CONFIG_X86_64
6aa8b732 842 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 843 def_op_bytes = 4;
844 def_ad_bytes = 8;
6aa8b732
AK		 845 break;
846#endif
847 default:
848 return -1;
849 }
850
f21b8bf4
AK		 851 c->op_bytes = def_op_bytes;
852 c->ad_bytes = def_ad_bytes;
853
6aa8b732 854 /* Legacy prefixes. */
b4c6abfe 855 for (;;) {
e4e03ded 856 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 857 case 0x66: /* operand-size override */
f21b8bf4
AK		 858 /* switch between 2/4 bytes */
859 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 860 break;
861 case 0x67: /* address-size override */
862 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 863 /* switch between 4/8 bytes */
f21b8bf4 864 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 865 else
e4e03ded 866 /* switch between 2/4 bytes */
f21b8bf4 867 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 868 break;
869 case 0x2e: /* CS override */
e4e03ded 870 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 871 break;
872 case 0x3e: /* DS override */
e4e03ded 873 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 874 break;
875 case 0x26: /* ES override */
e4e03ded 876 c->override_base = &ctxt->es_base;
6aa8b732
AK		 877 break;
878 case 0x64: /* FS override */
e4e03ded 879 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 880 break;
881 case 0x65: /* GS override */
e4e03ded 882 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 883 break;
884 case 0x36: /* SS override */
e4e03ded 885 c->override_base = &ctxt->ss_base;
6aa8b732 886 break;
b4c6abfe
LV		 887 case 0x40 ... 0x4f: /* REX */
888 if (mode != X86EMUL_MODE_PROT64)
889 goto done_prefixes;
33615aa9 890 c->rex_prefix = c->b;
b4c6abfe 891 continue;
6aa8b732 892 case 0xf0: /* LOCK */
e4e03ded 893 c->lock_prefix = 1;
6aa8b732 894 break;
ae6200ba 895 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 896 c->rep_prefix = REPNE_PREFIX;
897 break;
6aa8b732 898 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 899 c->rep_prefix = REPE_PREFIX;
6aa8b732 900 break;
6aa8b732
AK		 901 default:
902 goto done_prefixes;
903 }
b4c6abfe
LV		 904
905 /* Any legacy prefix after a REX prefix nullifies its effect. */
906
33615aa9 907 c->rex_prefix = 0;
6aa8b732
AK		 908 }
909
910done_prefixes:
911
912 /* REX prefix. */
1c73ef66 913 if (c->rex_prefix)
33615aa9 914 if (c->rex_prefix & 8)
e4e03ded 915 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 916
917 /* Opcode byte(s). */
e4e03ded
LV		 918 c->d = opcode_table[c->b];
919 if (c->d == 0) {
6aa8b732 920 /* Two-byte opcode? */
e4e03ded
LV		 921 if (c->b == 0x0f) {
922 c->twobyte = 1;
923 c->b = insn_fetch(u8, 1, c->eip);
924 c->d = twobyte_table[c->b];
6aa8b732 925 }
e09d082c 926 }
6aa8b732 927
e09d082c
AK		 928 if (c->d & Group) {
929 group = c->d & GroupMask;
930 c->modrm = insn_fetch(u8, 1, c->eip);
931 --c->eip;
932
933 group = (group << 3) + ((c->modrm >> 3) & 7);
934 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
935 c->d = group2_table[group];
936 else
937 c->d = group_table[group];
938 }
939
940 /* Unrecognised? */
941 if (c->d == 0) {
942 DPRINTF("Cannot emulate %02x\n", c->b);
943 return -1;
6aa8b732
AK		 944 }
945
6e3d5dfb
AK		 946 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
947 c->op_bytes = 8;
948
6aa8b732 949 /* ModRM and SIB bytes. */
1c73ef66
AK		 950 if (c->d & ModRM)
951 rc = decode_modrm(ctxt, ops);
952 else if (c->d & MemAbs)
953 rc = decode_abs(ctxt, ops);
954 if (rc)
955 goto done;
6aa8b732 956
c7e75a3d
AK		 957 if (!c->override_base)
958 c->override_base = &ctxt->ds_base;
959 if (mode == X86EMUL_MODE_PROT64 &&
960 c->override_base != &ctxt->fs_base &&
961 c->override_base != &ctxt->gs_base)
962 c->override_base = NULL;
963
964 if (c->override_base)
965 c->modrm_ea += *c->override_base;
966
967 if (c->ad_bytes != 8)
968 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 969 /*
970 * Decode and fetch the source operand: register, memory
971 * or immediate.
972 */
e4e03ded 973 switch (c->d & SrcMask) {
6aa8b732
AK		 974 case SrcNone:
975 break;
976 case SrcReg:
9f1ef3f8 977 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 978 break;
979 case SrcMem16:
e4e03ded 980 c->src.bytes = 2;
6aa8b732
AK		 981 goto srcmem_common;
982 case SrcMem32:
e4e03ded 983 c->src.bytes = 4;
6aa8b732
AK		 984 goto srcmem_common;
985 case SrcMem:
e4e03ded
LV		 986 c->src.bytes = (c->d & ByteOp) ? 1 :
987 c->op_bytes;
b85b9ee9 988 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 989 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 990 break;
d77c26fc 991 srcmem_common:
4e62417b
AJ		 992 /*
993 * For instructions with a ModR/M byte, switch to register
994 * access if Mod = 3.
995 */
e4e03ded
LV		 996 if ((c->d & ModRM) && c->modrm_mod == 3) {
997 c->src.type = OP_REG;
4e62417b
AJ		 998 break;
999 }
e4e03ded 1000 c->src.type = OP_MEM;
6aa8b732
AK		 1001 break;
1002 case SrcImm:
e4e03ded
LV		 1003 c->src.type = OP_IMM;
1004 c->src.ptr = (unsigned long *)c->eip;
1005 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1006 if (c->src.bytes == 8)
1007 c->src.bytes = 4;
6aa8b732 1008 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1009 switch (c->src.bytes) {
6aa8b732 1010 case 1:
e4e03ded 1011 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1012 break;
1013 case 2:
e4e03ded 1014 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1015 break;
1016 case 4:
e4e03ded 1017 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1018 break;
1019 }
1020 break;
1021 case SrcImmByte:
e4e03ded
LV		 1022 c->src.type = OP_IMM;
1023 c->src.ptr = (unsigned long *)c->eip;
1024 c->src.bytes = 1;
1025 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1026 break;
1027 }
1028
038e51de 1029 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1030 switch (c->d & DstMask) {
038e51de
AK		 1031 case ImplicitOps:
1032 /* Special instructions do their own operand decoding. */
8b4caf66 1033 return 0;
038e51de 1034 case DstReg:
9f1ef3f8 1035 decode_register_operand(&c->dst, c,
3c118e24 1036 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1037 break;
1038 case DstMem:
e4e03ded
LV		 1039 if ((c->d & ModRM) && c->modrm_mod == 3) {
1040 c->dst.type = OP_REG;
4e62417b
AJ		 1041 break;
1042 }
8b4caf66
LV		 1043 c->dst.type = OP_MEM;
1044 break;
1045 }
1046
1047done:
1048 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1049}
1050
8cdbd2c9
LV		 1051static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1052{
1053 struct decode_cache *c = &ctxt->decode;
1054
1055 c->dst.type = OP_MEM;
1056 c->dst.bytes = c->op_bytes;
1057 c->dst.val = c->src.val;
1058 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
1059 c->dst.ptr = (void *) register_address(ctxt->ss_base,
1060 c->regs[VCPU_REGS_RSP]);
1061}
1062
1063static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1064 struct x86_emulate_ops *ops)
1065{
1066 struct decode_cache *c = &ctxt->decode;
1067 int rc;
1068
8cdbd2c9
LV		 1069 rc = ops->read_std(register_address(ctxt->ss_base,
1070 c->regs[VCPU_REGS_RSP]),
1071 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1072 if (rc != 0)
1073 return rc;
1074
1075 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
1076
1077 return 0;
1078}
1079
05f086f8 1080static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1081{
05f086f8 1082 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1083 switch (c->modrm_reg) {
1084 case 0: /* rol */
05f086f8 1085 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1086 break;
1087 case 1: /* ror */
05f086f8 1088 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1089 break;
1090 case 2: /* rcl */
05f086f8 1091 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1092 break;
1093 case 3: /* rcr */
05f086f8 1094 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1095 break;
1096 case 4: /* sal/shl */
1097 case 6: /* sal/shl */
05f086f8 1098 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1099 break;
1100 case 5: /* shr */
05f086f8 1101 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1102 break;
1103 case 7: /* sar */
05f086f8 1104 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1105 break;
1106 }
1107}
1108
1109static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1110 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1111{
1112 struct decode_cache *c = &ctxt->decode;
1113 int rc = 0;
1114
1115 switch (c->modrm_reg) {
1116 case 0 ... 1: /* test */
05f086f8 1117 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1118 break;
1119 case 2: /* not */
1120 c->dst.val = ~c->dst.val;
1121 break;
1122 case 3: /* neg */
05f086f8 1123 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1124 break;
1125 default:
1126 DPRINTF("Cannot emulate %02x\n", c->b);
1127 rc = X86EMUL_UNHANDLEABLE;
1128 break;
1129 }
8cdbd2c9
LV		 1130 return rc;
1131}
1132
1133static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1134 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1135{
1136 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1137
1138 switch (c->modrm_reg) {
1139 case 0: /* inc */
05f086f8 1140 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1141 break;
1142 case 1: /* dec */
05f086f8 1143 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1144 break;
1145 case 4: /* jmp abs */
fd60754e 1146 c->eip = c->src.val;
8cdbd2c9
LV		 1147 break;
1148 case 6: /* push */
fd60754e 1149 emulate_push(ctxt);
8cdbd2c9 1150 break;
8cdbd2c9
LV		 1151 }
1152 return 0;
1153}
1154
1155static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1156 struct x86_emulate_ops *ops,
e8d8d7fe 1157 unsigned long memop)
8cdbd2c9
LV		 1158{
1159 struct decode_cache *c = &ctxt->decode;
1160 u64 old, new;
1161 int rc;
1162
e8d8d7fe 1163 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1164 if (rc != 0)
1165 return rc;
1166
1167 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1168 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1169
1170 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1171 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1172 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1173
1174 } else {
1175 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1176 (u32) c->regs[VCPU_REGS_RBX];
1177
e8d8d7fe 1178 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1179 if (rc != 0)
1180 return rc;
05f086f8 1181 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1182 }
1183 return 0;
1184}
1185
1186static inline int writeback(struct x86_emulate_ctxt *ctxt,
1187 struct x86_emulate_ops *ops)
1188{
1189 int rc;
1190 struct decode_cache *c = &ctxt->decode;
1191
1192 switch (c->dst.type) {
1193 case OP_REG:
1194 /* The 4-byte case *is* correct:
1195 * in 64-bit mode we zero-extend.
1196 */
1197 switch (c->dst.bytes) {
1198 case 1:
1199 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1200 break;
1201 case 2:
1202 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1203 break;
1204 case 4:
1205 *c->dst.ptr = (u32)c->dst.val;
1206 break; /* 64b: zero-ext */
1207 case 8:
1208 *c->dst.ptr = c->dst.val;
1209 break;
1210 }
1211 break;
1212 case OP_MEM:
1213 if (c->lock_prefix)
1214 rc = ops->cmpxchg_emulated(
1215 (unsigned long)c->dst.ptr,
1216 &c->dst.orig_val,
1217 &c->dst.val,
1218 c->dst.bytes,
1219 ctxt->vcpu);
1220 else
1221 rc = ops->write_emulated(
1222 (unsigned long)c->dst.ptr,
1223 &c->dst.val,
1224 c->dst.bytes,
1225 ctxt->vcpu);
1226 if (rc != 0)
1227 return rc;
a01af5ec
LV		 1228 break;
1229 case OP_NONE:
1230 /* no writeback */
1231 break;
8cdbd2c9
LV		 1232 default:
1233 break;
1234 }
1235 return 0;
1236}
1237
8b4caf66 1238int
1be3aa47 1239x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1240{
e8d8d7fe 1241 unsigned long memop = 0;
8b4caf66 1242 u64 msr_data;
3427318f 1243 unsigned long saved_eip = 0;
8b4caf66 1244 struct decode_cache *c = &ctxt->decode;
1be3aa47 1245 int rc = 0;
8b4caf66 1246
3427318f
LV		 1247 /* Shadow copy of register state. Committed on successful emulation.
1248 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1249 * modify them.
1250 */
1251
ad312c7c 1252 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1253 saved_eip = c->eip;
1254
c7e75a3d 1255 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1256 memop = c->modrm_ea;
8b4caf66 1257
b9fa9d6b
AK		 1258 if (c->rep_prefix && (c->d & String)) {
1259 /* All REP prefixes have the same first termination condition */
1260 if (c->regs[VCPU_REGS_RCX] == 0) {
ad312c7c 1261 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1262 goto done;
1263 }
1264 /* The second termination condition only applies for REPE
1265 * and REPNE. Test if the repeat string operation prefix is
1266 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1267 * corresponding termination condition according to:
1268 * - if REPE/REPZ and ZF = 0 then done
1269 * - if REPNE/REPNZ and ZF = 1 then done
1270 */
1271 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1272 (c->b == 0xae) || (c->b == 0xaf)) {
1273 if ((c->rep_prefix == REPE_PREFIX) &&
1274 ((ctxt->eflags & EFLG_ZF) == 0)) {
ad312c7c 1275 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1276 goto done;
1277 }
1278 if ((c->rep_prefix == REPNE_PREFIX) &&
1279 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
ad312c7c 1280 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1281 goto done;
1282 }
1283 }
1284 c->regs[VCPU_REGS_RCX]--;
ad312c7c 1285 c->eip = ctxt->vcpu->arch.rip;
b9fa9d6b
AK		 1286 }
1287
8b4caf66 1288 if (c->src.type == OP_MEM) {
e8d8d7fe 1289 c->src.ptr = (unsigned long *)memop;
8b4caf66 1290 c->src.val = 0;
d77c26fc
MD		 1291 rc = ops->read_emulated((unsigned long)c->src.ptr,
1292 &c->src.val,
1293 c->src.bytes,
1294 ctxt->vcpu);
1295 if (rc != 0)
8b4caf66
LV		 1296 goto done;
1297 c->src.orig_val = c->src.val;
1298 }
1299
1300 if ((c->d & DstMask) == ImplicitOps)
1301 goto special_insn;
1302
1303
1304 if (c->dst.type == OP_MEM) {
e8d8d7fe 1305 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1306 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1307 c->dst.val = 0;
e4e03ded
LV		 1308 if (c->d & BitOp) {
1309 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1310
e4e03ded
LV		 1311 c->dst.ptr = (void *)c->dst.ptr +
1312 (c->src.val & mask) / 8;
038e51de 1313 }
e4e03ded
LV		 1314 if (!(c->d & Mov) &&
1315 /* optimisation - avoid slow emulated read */
1316 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1317 &c->dst.val,
1318 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1319 goto done;
038e51de 1320 }
e4e03ded 1321 c->dst.orig_val = c->dst.val;
038e51de 1322
018a98db
AK		 1323special_insn:
1324
e4e03ded 1325 if (c->twobyte)
6aa8b732
AK		 1326 goto twobyte_insn;
1327
e4e03ded 1328 switch (c->b) {
6aa8b732
AK		 1329 case 0x00 ... 0x05:
1330 add: /* add */
05f086f8 1331 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1332 break;
1333 case 0x08 ... 0x0d:
1334 or: /* or */
05f086f8 1335 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1336 break;
1337 case 0x10 ... 0x15:
1338 adc: /* adc */
05f086f8 1339 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1340 break;
1341 case 0x18 ... 0x1d:
1342 sbb: /* sbb */
05f086f8 1343 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1344 break;
19eb938e 1345 case 0x20 ... 0x23:
6aa8b732 1346 and: /* and */
05f086f8 1347 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1348 break;
19eb938e 1349 case 0x24: /* and al imm8 */
e4e03ded
LV		 1350 c->dst.type = OP_REG;
1351 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1352 c->dst.val = *(u8 *)c->dst.ptr;
1353 c->dst.bytes = 1;
1354 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1355 goto and;
1356 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1357 c->dst.type = OP_REG;
1358 c->dst.bytes = c->op_bytes;
1359 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1360 if (c->op_bytes == 2)
1361 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1362 else
e4e03ded
LV		 1363 c->dst.val = *(u32 *)c->dst.ptr;
1364 c->dst.orig_val = c->dst.val;
19eb938e 1365 goto and;
6aa8b732
AK		 1366 case 0x28 ... 0x2d:
1367 sub: /* sub */
05f086f8 1368 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1369 break;
1370 case 0x30 ... 0x35:
1371 xor: /* xor */
05f086f8 1372 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1373 break;
1374 case 0x38 ... 0x3d:
1375 cmp: /* cmp */
05f086f8 1376 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1377 break;
33615aa9
AK		 1378 case 0x40 ... 0x47: /* inc r16/r32 */
1379 emulate_1op("inc", c->dst, ctxt->eflags);
1380 break;
1381 case 0x48 ... 0x4f: /* dec r16/r32 */
1382 emulate_1op("dec", c->dst, ctxt->eflags);
1383 break;
1384 case 0x50 ... 0x57: /* push reg */
1385 c->dst.type = OP_MEM;
1386 c->dst.bytes = c->op_bytes;
1387 c->dst.val = c->src.val;
1388 register_address_increment(c->regs[VCPU_REGS_RSP],
1389 -c->op_bytes);
1390 c->dst.ptr = (void *) register_address(
1391 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
1392 break;
1393 case 0x58 ... 0x5f: /* pop reg */
1394 pop_instruction:
1395 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1396 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1397 c->op_bytes, ctxt->vcpu)) != 0)
1398 goto done;
1399
1400 register_address_increment(c->regs[VCPU_REGS_RSP],
1401 c->op_bytes);
1402 c->dst.type = OP_NONE; /* Disable writeback. */
1403 break;
6aa8b732 1404 case 0x63: /* movsxd */
8b4caf66 1405 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1406 goto cannot_emulate;
e4e03ded 1407 c->dst.val = (s32) c->src.val;
6aa8b732 1408 break;
018a98db
AK		 1409 case 0x6a: /* push imm8 */
1410 c->src.val = 0L;
1411 c->src.val = insn_fetch(s8, 1, c->eip);
1412 emulate_push(ctxt);
1413 break;
1414 case 0x6c: /* insb */
1415 case 0x6d: /* insw/insd */
1416 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1417 1,
1418 (c->d & ByteOp) ? 1 : c->op_bytes,
1419 c->rep_prefix ?
1420 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1421 (ctxt->eflags & EFLG_DF),
1422 register_address(ctxt->es_base,
1423 c->regs[VCPU_REGS_RDI]),
1424 c->rep_prefix,
1425 c->regs[VCPU_REGS_RDX]) == 0) {
1426 c->eip = saved_eip;
1427 return -1;
1428 }
1429 return 0;
1430 case 0x6e: /* outsb */
1431 case 0x6f: /* outsw/outsd */
1432 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1433 0,
1434 (c->d & ByteOp) ? 1 : c->op_bytes,
1435 c->rep_prefix ?
1436 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1437 (ctxt->eflags & EFLG_DF),
1438 register_address(c->override_base ?
1439 *c->override_base :
1440 ctxt->ds_base,
1441 c->regs[VCPU_REGS_RSI]),
1442 c->rep_prefix,
1443 c->regs[VCPU_REGS_RDX]) == 0) {
1444 c->eip = saved_eip;
1445 return -1;
1446 }
1447 return 0;
1448 case 0x70 ... 0x7f: /* jcc (short) */ {
1449 int rel = insn_fetch(s8, 1, c->eip);
1450
1451 if (test_cc(c->b, ctxt->eflags))
1452 JMP_REL(rel);
1453 break;
1454 }
6aa8b732 1455 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1456 switch (c->modrm_reg) {
6aa8b732
AK		 1457 case 0:
1458 goto add;
1459 case 1:
1460 goto or;
1461 case 2:
1462 goto adc;
1463 case 3:
1464 goto sbb;
1465 case 4:
1466 goto and;
1467 case 5:
1468 goto sub;
1469 case 6:
1470 goto xor;
1471 case 7:
1472 goto cmp;
1473 }
1474 break;
1475 case 0x84 ... 0x85:
05f086f8 1476 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1477 break;
1478 case 0x86 ... 0x87: /* xchg */
1479 /* Write back the register source. */
e4e03ded 1480 switch (c->dst.bytes) {
6aa8b732 1481 case 1:
e4e03ded 1482 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1483 break;
1484 case 2:
e4e03ded 1485 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1486 break;
1487 case 4:
e4e03ded 1488 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1489 break; /* 64b reg: zero-extend */
1490 case 8:
e4e03ded 1491 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1492 break;
1493 }
1494 /*
1495 * Write back the memory destination with implicit LOCK
1496 * prefix.
1497 */
e4e03ded
LV		 1498 c->dst.val = c->src.val;
1499 c->lock_prefix = 1;
6aa8b732 1500 break;
6aa8b732 1501 case 0x88 ... 0x8b: /* mov */
7de75248 1502 goto mov;
7e0b54b1 1503 case 0x8d: /* lea r16/r32, m */
e4e03ded 1504 c->dst.val = c->modrm_val;
7e0b54b1 1505 break;
6aa8b732 1506 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1507 rc = emulate_grp1a(ctxt, ops);
1508 if (rc != 0)
6aa8b732 1509 goto done;
6aa8b732 1510 break;
fd2a7608 1511 case 0x9c: /* pushf */
05f086f8 1512 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1513 emulate_push(ctxt);
1514 break;
535eabcf 1515 case 0x9d: /* popf */
05f086f8 1516 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1517 goto pop_instruction;
018a98db
AK		 1518 case 0xa0 ... 0xa1: /* mov */
1519 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1520 c->dst.val = c->src.val;
1521 break;
1522 case 0xa2 ... 0xa3: /* mov */
1523 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1524 break;
6aa8b732 1525 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1526 c->dst.type = OP_MEM;
1527 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1528 c->dst.ptr = (unsigned long *)register_address(
1529 ctxt->es_base,
1530 c->regs[VCPU_REGS_RDI]);
6aa8b732 1531 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1532 c->override_base ? *c->override_base :
1533 ctxt->ds_base,
1534 c->regs[VCPU_REGS_RSI]),
1535 &c->dst.val,
1536 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1537 goto done;
e4e03ded 1538 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1539 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1540 : c->dst.bytes);
1541 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1542 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1543 : c->dst.bytes);
6aa8b732
AK		 1544 break;
1545 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1546 c->src.type = OP_NONE; /* Disable writeback. */
1547 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1548 c->src.ptr = (unsigned long *)register_address(
1549 c->override_base ? *c->override_base :
1550 ctxt->ds_base,
1551 c->regs[VCPU_REGS_RSI]);
1552 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1553 &c->src.val,
1554 c->src.bytes,
1555 ctxt->vcpu)) != 0)
1556 goto done;
1557
1558 c->dst.type = OP_NONE; /* Disable writeback. */
1559 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1560 c->dst.ptr = (unsigned long *)register_address(
1561 ctxt->es_base,
1562 c->regs[VCPU_REGS_RDI]);
1563 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1564 &c->dst.val,
1565 c->dst.bytes,
1566 ctxt->vcpu)) != 0)
1567 goto done;
1568
1569 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1570
1571 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1572
1573 register_address_increment(c->regs[VCPU_REGS_RSI],
1574 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1575 : c->src.bytes);
1576 register_address_increment(c->regs[VCPU_REGS_RDI],
1577 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1578 : c->dst.bytes);
1579
1580 break;
6aa8b732 1581 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1582 c->dst.type = OP_MEM;
1583 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
a7e6c88a
SY		 1584 c->dst.ptr = (unsigned long *)register_address(
1585 ctxt->es_base,
1586 c->regs[VCPU_REGS_RDI]);
e4e03ded
LV		 1587 c->dst.val = c->regs[VCPU_REGS_RAX];
1588 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1589 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1590 : c->dst.bytes);
6aa8b732
AK		 1591 break;
1592 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1593 c->dst.type = OP_REG;
1594 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1595 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
a7e6c88a
SY		 1596 if ((rc = ops->read_emulated(register_address(
1597 c->override_base ? *c->override_base :
1598 ctxt->ds_base,
1599 c->regs[VCPU_REGS_RSI]),
1600 &c->dst.val,
1601 c->dst.bytes,
1602 ctxt->vcpu)) != 0)
6aa8b732 1603 goto done;
e4e03ded 1604 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1605 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1606 : c->dst.bytes);
6aa8b732
AK		 1607 break;
1608 case 0xae ... 0xaf: /* scas */
1609 DPRINTF("Urk! I don't handle SCAS.\n");
1610 goto cannot_emulate;
018a98db
AK		 1611 case 0xc0 ... 0xc1:
1612 emulate_grp2(ctxt);
1613 break;
111de5d6
AK		 1614 case 0xc3: /* ret */
1615 c->dst.ptr = &c->eip;
1616 goto pop_instruction;
018a98db
AK		 1617 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1618 mov:
1619 c->dst.val = c->src.val;
1620 break;
1621 case 0xd0 ... 0xd1: /* Grp2 */
1622 c->src.val = 1;
1623 emulate_grp2(ctxt);
1624 break;
1625 case 0xd2 ... 0xd3: /* Grp2 */
1626 c->src.val = c->regs[VCPU_REGS_RCX];
1627 emulate_grp2(ctxt);
1628 break;
1a52e051
NK		 1629 case 0xe8: /* call (near) */ {
1630 long int rel;
e4e03ded 1631 switch (c->op_bytes) {
1a52e051 1632 case 2:
e4e03ded 1633 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1634 break;
1635 case 4:
e4e03ded 1636 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1637 break;
1a52e051
NK		 1638 default:
1639 DPRINTF("Call: Invalid op_bytes\n");
1640 goto cannot_emulate;
1641 }
e4e03ded 1642 c->src.val = (unsigned long) c->eip;
1a52e051 1643 JMP_REL(rel);
e4e03ded 1644 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1645 emulate_push(ctxt);
1646 break;
1a52e051
NK		 1647 }
1648 case 0xe9: /* jmp rel */
1649 case 0xeb: /* jmp rel short */
e4e03ded 1650 JMP_REL(c->src.val);
a01af5ec 1651 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1652 break;
111de5d6 1653 case 0xf4: /* hlt */
ad312c7c 1654 ctxt->vcpu->arch.halt_request = 1;
111de5d6
AK		 1655 goto done;
1656 case 0xf5: /* cmc */
1657 /* complement carry flag from eflags reg */
1658 ctxt->eflags ^= EFLG_CF;
1659 c->dst.type = OP_NONE; /* Disable writeback. */
1660 break;
018a98db
AK		 1661 case 0xf6 ... 0xf7: /* Grp3 */
1662 rc = emulate_grp3(ctxt, ops);
1663 if (rc != 0)
1664 goto done;
1665 break;
111de5d6
AK		 1666 case 0xf8: /* clc */
1667 ctxt->eflags &= ~EFLG_CF;
1668 c->dst.type = OP_NONE; /* Disable writeback. */
1669 break;
1670 case 0xfa: /* cli */
1671 ctxt->eflags &= ~X86_EFLAGS_IF;
1672 c->dst.type = OP_NONE; /* Disable writeback. */
1673 break;
1674 case 0xfb: /* sti */
1675 ctxt->eflags |= X86_EFLAGS_IF;
1676 c->dst.type = OP_NONE; /* Disable writeback. */
1677 break;
018a98db
AK		 1678 case 0xfe ... 0xff: /* Grp4/Grp5 */
1679 rc = emulate_grp45(ctxt, ops);
1680 if (rc != 0)
1681 goto done;
1682 break;
6aa8b732 1683 }
018a98db
AK		 1684
1685writeback:
1686 rc = writeback(ctxt, ops);
1687 if (rc != 0)
1688 goto done;
1689
1690 /* Commit shadow register state. */
ad312c7c
ZX		 1691 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1692 ctxt->vcpu->arch.rip = c->eip;
018a98db
AK		 1693
1694done:
1695 if (rc == X86EMUL_UNHANDLEABLE) {
1696 c->eip = saved_eip;
1697 return -1;
1698 }
1699 return 0;
6aa8b732
AK		 1700
1701twobyte_insn:
e4e03ded 1702 switch (c->b) {
6aa8b732 1703 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1704 switch (c->modrm_reg) {
6aa8b732
AK		 1705 u16 size;
1706 unsigned long address;
1707
aca7f966 1708 case 0: /* vmcall */
e4e03ded 1709 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1710 goto cannot_emulate;
1711
7aa81cc0
AL		 1712 rc = kvm_fix_hypercall(ctxt->vcpu);
1713 if (rc)
1714 goto done;
1715
1716 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1717 break;
6aa8b732 1718 case 2: /* lgdt */
e4e03ded
LV		 1719 rc = read_descriptor(ctxt, ops, c->src.ptr,
1720 &size, &address, c->op_bytes);
6aa8b732
AK		 1721 if (rc)
1722 goto done;
1723 realmode_lgdt(ctxt->vcpu, size, address);
1724 break;
aca7f966 1725 case 3: /* lidt/vmmcall */
e4e03ded 1726 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1727 rc = kvm_fix_hypercall(ctxt->vcpu);
1728 if (rc)
1729 goto done;
1730 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1731 } else {
e4e03ded 1732 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1733 &size, &address,
e4e03ded 1734 c->op_bytes);
aca7f966
AL		 1735 if (rc)
1736 goto done;
1737 realmode_lidt(ctxt->vcpu, size, address);
1738 }
6aa8b732
AK		 1739 break;
1740 case 4: /* smsw */
e4e03ded 1741 if (c->modrm_mod != 3)
6aa8b732 1742 goto cannot_emulate;
e4e03ded 1743 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1744 = realmode_get_cr(ctxt->vcpu, 0);
1745 break;
1746 case 6: /* lmsw */
e4e03ded 1747 if (c->modrm_mod != 3)
6aa8b732 1748 goto cannot_emulate;
05f086f8
LV		 1749 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1750 &ctxt->eflags);
6aa8b732
AK		 1751 break;
1752 case 7: /* invlpg*/
e8d8d7fe 1753 emulate_invlpg(ctxt->vcpu, memop);
6aa8b732
AK		 1754 break;
1755 default:
1756 goto cannot_emulate;
1757 }
a01af5ec
LV		 1758 /* Disable writeback. */
1759 c->dst.type = OP_NONE;
6aa8b732 1760 break;
018a98db
AK		 1761 case 0x06:
1762 emulate_clts(ctxt->vcpu);
1763 c->dst.type = OP_NONE;
1764 break;
1765 case 0x08: /* invd */
1766 case 0x09: /* wbinvd */
1767 case 0x0d: /* GrpP (prefetch) */
1768 case 0x18: /* Grp16 (prefetch/nop) */
1769 c->dst.type = OP_NONE;
1770 break;
1771 case 0x20: /* mov cr, reg */
1772 if (c->modrm_mod != 3)
1773 goto cannot_emulate;
1774 c->regs[c->modrm_rm] =
1775 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1776 c->dst.type = OP_NONE; /* no writeback */
1777 break;
6aa8b732 1778 case 0x21: /* mov from dr to reg */
e4e03ded 1779 if (c->modrm_mod != 3)
6aa8b732 1780 goto cannot_emulate;
8cdbd2c9 1781 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1782 if (rc)
1783 goto cannot_emulate;
1784 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1785 break;
018a98db
AK		 1786 case 0x22: /* mov reg, cr */
1787 if (c->modrm_mod != 3)
1788 goto cannot_emulate;
1789 realmode_set_cr(ctxt->vcpu,
1790 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1791 c->dst.type = OP_NONE;
1792 break;
6aa8b732 1793 case 0x23: /* mov from reg to dr */
e4e03ded 1794 if (c->modrm_mod != 3)
6aa8b732 1795 goto cannot_emulate;
e4e03ded
LV		 1796 rc = emulator_set_dr(ctxt, c->modrm_reg,
1797 c->regs[c->modrm_rm]);
a01af5ec
LV		 1798 if (rc)
1799 goto cannot_emulate;
1800 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1801 break;
018a98db
AK		 1802 case 0x30:
1803 /* wrmsr */
1804 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1805 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1806 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1807 if (rc) {
c1a5d4f9 1808 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1809 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1810 }
1811 rc = X86EMUL_CONTINUE;
1812 c->dst.type = OP_NONE;
1813 break;
1814 case 0x32:
1815 /* rdmsr */
1816 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1817 if (rc) {
c1a5d4f9 1818 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1819 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1820 } else {
1821 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1822 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1823 }
1824 rc = X86EMUL_CONTINUE;
1825 c->dst.type = OP_NONE;
1826 break;
6aa8b732 1827 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1828 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1829 if (!test_cc(c->b, ctxt->eflags))
1830 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1831 break;
018a98db
AK		 1832 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1833 long int rel;
1834
1835 switch (c->op_bytes) {
1836 case 2:
1837 rel = insn_fetch(s16, 2, c->eip);
1838 break;
1839 case 4:
1840 rel = insn_fetch(s32, 4, c->eip);
1841 break;
1842 case 8:
1843 rel = insn_fetch(s64, 8, c->eip);
1844 break;
1845 default:
1846 DPRINTF("jnz: Invalid op_bytes\n");
1847 goto cannot_emulate;
1848 }
1849 if (test_cc(c->b, ctxt->eflags))
1850 JMP_REL(rel);
1851 c->dst.type = OP_NONE;
1852 break;
1853 }
7de75248
NK		 1854 case 0xa3:
1855 bt: /* bt */
e4f8e039 1856 c->dst.type = OP_NONE;
e4e03ded
LV		 1857 /* only subword offset */
1858 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1859 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1860 break;
1861 case 0xab:
1862 bts: /* bts */
e4e03ded
LV		 1863 /* only subword offset */
1864 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1865 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1866 break;
6aa8b732
AK		 1867 case 0xb0 ... 0xb1: /* cmpxchg */
1868 /*
1869 * Save real source value, then compare EAX against
1870 * destination.
1871 */
e4e03ded
LV		 1872 c->src.orig_val = c->src.val;
1873 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1874 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1875 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1876 /* Success: write back to memory. */
e4e03ded 1877 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1878 } else {
1879 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1880 c->dst.type = OP_REG;
1881 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1882 }
1883 break;
6aa8b732
AK		 1884 case 0xb3:
1885 btr: /* btr */
e4e03ded
LV		 1886 /* only subword offset */
1887 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1888 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1889 break;
6aa8b732 1890 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1891 c->dst.bytes = c->op_bytes;
1892 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1893 : (u16) c->src.val;
6aa8b732 1894 break;
6aa8b732 1895 case 0xba: /* Grp8 */
e4e03ded 1896 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1897 case 0:
1898 goto bt;
1899 case 1:
1900 goto bts;
1901 case 2:
1902 goto btr;
1903 case 3:
1904 goto btc;
1905 }
1906 break;
7de75248
NK		 1907 case 0xbb:
1908 btc: /* btc */
e4e03ded
LV		 1909 /* only subword offset */
1910 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1911 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1912 break;
6aa8b732 1913 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1914 c->dst.bytes = c->op_bytes;
1915 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1916 (s16) c->src.val;
6aa8b732 1917 break;
a012e65a 1918 case 0xc3: /* movnti */
e4e03ded
LV		 1919 c->dst.bytes = c->op_bytes;
1920 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1921 (u64) c->src.val;
a012e65a 1922 break;
6aa8b732 1923 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 1924 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 1925 if (rc != 0)
1926 goto done;
018a98db 1927 c->dst.type = OP_NONE;
8cdbd2c9 1928 break;
6aa8b732
AK		 1929 }
1930 goto writeback;
1931
1932cannot_emulate:
e4e03ded 1933 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1934 c->eip = saved_eip;
6aa8b732
AK		 1935 return -1;
1936}
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