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1 | /****************************************************************************** |
2 | * x86_emulate.c | |
3 | * | |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 27 | #else |
edf88417 | 28 | #include <linux/kvm_host.h> |
6aa8b732 AK |
29 | #define DPRINTF(x...) do {} while (0) |
30 | #endif | |
6aa8b732 | 31 | #include <linux/module.h> |
edf88417 | 32 | #include <asm/kvm_x86_emulate.h> |
6aa8b732 AK |
33 | |
34 | /* | |
35 | * Opcode effective-address decode tables. | |
36 | * Note that we only emulate instructions that have at least one memory | |
37 | * operand (excluding implicit stack references). We assume that stack | |
38 | * references and instruction fetches will never occur in special memory | |
39 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
40 | * not be handled. | |
41 | */ | |
42 | ||
43 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
44 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
45 | /* Destination operand type. */ | |
46 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
47 | #define DstReg (2<<1) /* Register operand. */ | |
48 | #define DstMem (3<<1) /* Memory operand. */ | |
49 | #define DstMask (3<<1) | |
50 | /* Source operand type. */ | |
51 | #define SrcNone (0<<3) /* No source operand. */ | |
52 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ | |
53 | #define SrcReg (1<<3) /* Register operand. */ | |
54 | #define SrcMem (2<<3) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<3) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ | |
59 | #define SrcMask (7<<3) | |
60 | /* Generic ModRM decode. */ | |
61 | #define ModRM (1<<6) | |
62 | /* Destination is only written; never read. */ | |
63 | #define Mov (1<<7) | |
038e51de | 64 | #define BitOp (1<<8) |
c7e75a3d | 65 | #define MemAbs (1<<9) /* Memory operand is absolute displacement */ |
b9fa9d6b | 66 | #define String (1<<10) /* String instruction (rep capable) */ |
6e3d5dfb | 67 | #define Stack (1<<11) /* Stack instruction (push/pop) */ |
e09d082c AK |
68 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
69 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
70 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | |
6aa8b732 | 71 | |
43bb19cd | 72 | enum { |
1d6ad207 | 73 | Group1_80, Group1_81, Group1_82, Group1_83, |
d95058a1 | 74 | Group1A, Group3_Byte, Group3, Group4, Group5, Group7, |
43bb19cd AK |
75 | }; |
76 | ||
c7e75a3d | 77 | static u16 opcode_table[256] = { |
6aa8b732 AK |
78 | /* 0x00 - 0x07 */ |
79 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
80 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
81 | 0, 0, 0, 0, | |
82 | /* 0x08 - 0x0F */ | |
83 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
84 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
85 | 0, 0, 0, 0, | |
86 | /* 0x10 - 0x17 */ | |
87 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
88 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
89 | 0, 0, 0, 0, | |
90 | /* 0x18 - 0x1F */ | |
91 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
92 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
93 | 0, 0, 0, 0, | |
94 | /* 0x20 - 0x27 */ | |
95 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
96 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
19eb938e | 97 | SrcImmByte, SrcImm, 0, 0, |
6aa8b732 AK |
98 | /* 0x28 - 0x2F */ |
99 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
100 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
101 | 0, 0, 0, 0, | |
102 | /* 0x30 - 0x37 */ | |
103 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
104 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
105 | 0, 0, 0, 0, | |
106 | /* 0x38 - 0x3F */ | |
107 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
108 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
109 | 0, 0, 0, 0, | |
d77a2507 | 110 | /* 0x40 - 0x47 */ |
33615aa9 | 111 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 112 | /* 0x48 - 0x4F */ |
33615aa9 | 113 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 114 | /* 0x50 - 0x57 */ |
6e3d5dfb AK |
115 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, |
116 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, | |
7f0aaee0 | 117 | /* 0x58 - 0x5F */ |
6e3d5dfb AK |
118 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, |
119 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, | |
7d316911 | 120 | /* 0x60 - 0x67 */ |
6aa8b732 | 121 | 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , |
7d316911 NK |
122 | 0, 0, 0, 0, |
123 | /* 0x68 - 0x6F */ | |
6e3d5dfb | 124 | 0, 0, ImplicitOps | Mov | Stack, 0, |
e70669ab LV |
125 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
126 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 NK |
127 | /* 0x70 - 0x77 */ |
128 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
129 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
130 | /* 0x78 - 0x7F */ | |
131 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
132 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 | 133 | /* 0x80 - 0x87 */ |
1d6ad207 AK |
134 | Group | Group1_80, Group | Group1_81, |
135 | Group | Group1_82, Group | Group1_83, | |
6aa8b732 AK |
136 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
137 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
138 | /* 0x88 - 0x8F */ | |
139 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
140 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
43bb19cd | 141 | 0, ModRM | DstReg, 0, Group | Group1A, |
6aa8b732 | 142 | /* 0x90 - 0x9F */ |
6e3d5dfb AK |
143 | 0, 0, 0, 0, 0, 0, 0, 0, |
144 | 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, | |
6aa8b732 | 145 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
146 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
147 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
b9fa9d6b AK |
148 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
149 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
6aa8b732 | 150 | /* 0xA8 - 0xAF */ |
b9fa9d6b AK |
151 | 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
152 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, | |
153 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
6aa8b732 AK |
154 | /* 0xB0 - 0xBF */ |
155 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
156 | /* 0xC0 - 0xC7 */ | |
d9413cd7 | 157 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 158 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 159 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 AK |
160 | /* 0xC8 - 0xCF */ |
161 | 0, 0, 0, 0, 0, 0, 0, 0, | |
162 | /* 0xD0 - 0xD7 */ | |
163 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
164 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
165 | 0, 0, 0, 0, | |
166 | /* 0xD8 - 0xDF */ | |
167 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b NK |
168 | /* 0xE0 - 0xE7 */ |
169 | 0, 0, 0, 0, 0, 0, 0, 0, | |
170 | /* 0xE8 - 0xEF */ | |
6e3d5dfb AK |
171 | ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, |
172 | 0, 0, 0, 0, | |
6aa8b732 AK |
173 | /* 0xF0 - 0xF7 */ |
174 | 0, 0, 0, 0, | |
7d858a19 | 175 | ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3, |
6aa8b732 | 176 | /* 0xF8 - 0xFF */ |
b284be57 | 177 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fd60754e | 178 | 0, 0, Group | Group4, Group | Group5, |
6aa8b732 AK |
179 | }; |
180 | ||
038e51de | 181 | static u16 twobyte_table[256] = { |
6aa8b732 | 182 | /* 0x00 - 0x0F */ |
d95058a1 | 183 | 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0, |
651a3e29 | 184 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
6aa8b732 AK |
185 | /* 0x10 - 0x1F */ |
186 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
187 | /* 0x20 - 0x2F */ | |
188 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, | |
189 | 0, 0, 0, 0, 0, 0, 0, 0, | |
190 | /* 0x30 - 0x3F */ | |
35f3f286 | 191 | ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
192 | /* 0x40 - 0x47 */ |
193 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
194 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
195 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
196 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
197 | /* 0x48 - 0x4F */ | |
198 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
199 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
200 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
201 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
202 | /* 0x50 - 0x5F */ | |
203 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
204 | /* 0x60 - 0x6F */ | |
205 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
206 | /* 0x70 - 0x7F */ | |
207 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
208 | /* 0x80 - 0x8F */ | |
bbe9abbd NK |
209 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
210 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
211 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
212 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
213 | /* 0x90 - 0x9F */ |
214 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
215 | /* 0xA0 - 0xA7 */ | |
038e51de | 216 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 | 217 | /* 0xA8 - 0xAF */ |
038e51de | 218 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 AK |
219 | /* 0xB0 - 0xB7 */ |
220 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, | |
038e51de | 221 | DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
222 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
223 | DstReg | SrcMem16 | ModRM | Mov, | |
224 | /* 0xB8 - 0xBF */ | |
038e51de | 225 | 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
226 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
227 | DstReg | SrcMem16 | ModRM | Mov, | |
228 | /* 0xC0 - 0xCF */ | |
a012e65a SY |
229 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM, |
230 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6aa8b732 AK |
231 | /* 0xD0 - 0xDF */ |
232 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
233 | /* 0xE0 - 0xEF */ | |
234 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
235 | /* 0xF0 - 0xFF */ | |
236 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
237 | }; | |
238 | ||
e09d082c | 239 | static u16 group_table[] = { |
1d6ad207 AK |
240 | [Group1_80*8] = |
241 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
242 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
243 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
244 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
245 | [Group1_81*8] = | |
246 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
247 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
248 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
249 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
250 | [Group1_82*8] = | |
251 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
252 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
253 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
254 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
255 | [Group1_83*8] = | |
256 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
257 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
258 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
259 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
43bb19cd AK |
260 | [Group1A*8] = |
261 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 AK |
262 | [Group3_Byte*8] = |
263 | ByteOp | SrcImm | DstMem | ModRM, 0, | |
264 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
265 | 0, 0, 0, 0, | |
266 | [Group3*8] = | |
267 | DstMem | SrcImm | ModRM | SrcImm, 0, | |
268 | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
269 | 0, 0, 0, 0, | |
fd60754e AK |
270 | [Group4*8] = |
271 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
272 | 0, 0, 0, 0, 0, 0, | |
273 | [Group5*8] = | |
274 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0, | |
275 | SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0, | |
d95058a1 AK |
276 | [Group7*8] = |
277 | 0, 0, ModRM | SrcMem, ModRM | SrcMem, | |
278 | SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, SrcMem | ModRM | ByteOp, | |
e09d082c AK |
279 | }; |
280 | ||
281 | static u16 group2_table[] = { | |
d95058a1 AK |
282 | [Group7*8] = |
283 | SrcNone | ModRM, 0, 0, 0, SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, 0, | |
e09d082c AK |
284 | }; |
285 | ||
6aa8b732 AK |
286 | /* EFLAGS bit definitions. */ |
287 | #define EFLG_OF (1<<11) | |
288 | #define EFLG_DF (1<<10) | |
289 | #define EFLG_SF (1<<7) | |
290 | #define EFLG_ZF (1<<6) | |
291 | #define EFLG_AF (1<<4) | |
292 | #define EFLG_PF (1<<2) | |
293 | #define EFLG_CF (1<<0) | |
294 | ||
295 | /* | |
296 | * Instruction emulation: | |
297 | * Most instructions are emulated directly via a fragment of inline assembly | |
298 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
299 | * any modified flags. | |
300 | */ | |
301 | ||
05b3e0c2 | 302 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
303 | #define _LO32 "k" /* force 32-bit operand */ |
304 | #define _STK "%%rsp" /* stack pointer */ | |
305 | #elif defined(__i386__) | |
306 | #define _LO32 "" /* force 32-bit operand */ | |
307 | #define _STK "%%esp" /* stack pointer */ | |
308 | #endif | |
309 | ||
310 | /* | |
311 | * These EFLAGS bits are restored from saved value during emulation, and | |
312 | * any changes are written back to the saved value after emulation. | |
313 | */ | |
314 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
315 | ||
316 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
317 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
318 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
319 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
320 | "push %"_tmp"; " \ | |
321 | "push %"_tmp"; " \ | |
322 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
323 | "andl %"_LO32 _tmp",("_STK"); " \ | |
324 | "pushf; " \ | |
325 | "notl %"_LO32 _tmp"; " \ | |
326 | "andl %"_LO32 _tmp",("_STK"); " \ | |
327 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
328 | "pop %"_tmp"; " \ | |
329 | "orl %"_LO32 _tmp",("_STK"); " \ | |
330 | "popf; " \ | |
331 | "pop %"_sav"; " | |
6aa8b732 AK |
332 | |
333 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
334 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
335 | /* _sav |= EFLAGS & _msk; */ \ | |
336 | "pushf; " \ | |
337 | "pop %"_tmp"; " \ | |
338 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
339 | "orl %"_LO32 _tmp",%"_sav"; " | |
340 | ||
341 | /* Raw emulation: instruction has two explicit operands. */ | |
342 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
343 | do { \ | |
344 | unsigned long _tmp; \ | |
345 | \ | |
346 | switch ((_dst).bytes) { \ | |
347 | case 2: \ | |
348 | __asm__ __volatile__ ( \ | |
d77c26fc | 349 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 350 | _op"w %"_wx"3,%1; " \ |
d77c26fc | 351 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
352 | : "=m" (_eflags), "=m" ((_dst).val), \ |
353 | "=&r" (_tmp) \ | |
d77c26fc | 354 | : _wy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
355 | break; \ |
356 | case 4: \ | |
357 | __asm__ __volatile__ ( \ | |
d77c26fc | 358 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 359 | _op"l %"_lx"3,%1; " \ |
d77c26fc | 360 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
361 | : "=m" (_eflags), "=m" ((_dst).val), \ |
362 | "=&r" (_tmp) \ | |
d77c26fc | 363 | : _ly ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
364 | break; \ |
365 | case 8: \ | |
366 | __emulate_2op_8byte(_op, _src, _dst, \ | |
367 | _eflags, _qx, _qy); \ | |
368 | break; \ | |
369 | } \ | |
370 | } while (0) | |
371 | ||
372 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
373 | do { \ | |
374 | unsigned long _tmp; \ | |
d77c26fc | 375 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
376 | case 1: \ |
377 | __asm__ __volatile__ ( \ | |
d77c26fc | 378 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 379 | _op"b %"_bx"3,%1; " \ |
d77c26fc | 380 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
381 | : "=m" (_eflags), "=m" ((_dst).val), \ |
382 | "=&r" (_tmp) \ | |
d77c26fc | 383 | : _by ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
384 | break; \ |
385 | default: \ | |
386 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
387 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
388 | break; \ | |
389 | } \ | |
390 | } while (0) | |
391 | ||
392 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
393 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
394 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
395 | "b", "c", "b", "c", "b", "c", "b", "c") | |
396 | ||
397 | /* Source operand is byte, word, long or quad sized. */ | |
398 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
399 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
400 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
401 | ||
402 | /* Source operand is word, long or quad sized. */ | |
403 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
404 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
405 | "w", "r", _LO32, "r", "", "r") | |
406 | ||
407 | /* Instruction has only one explicit operand (no source operand). */ | |
408 | #define emulate_1op(_op, _dst, _eflags) \ | |
409 | do { \ | |
410 | unsigned long _tmp; \ | |
411 | \ | |
d77c26fc | 412 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
413 | case 1: \ |
414 | __asm__ __volatile__ ( \ | |
d77c26fc | 415 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 416 | _op"b %1; " \ |
d77c26fc | 417 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
418 | : "=m" (_eflags), "=m" ((_dst).val), \ |
419 | "=&r" (_tmp) \ | |
d77c26fc | 420 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
421 | break; \ |
422 | case 2: \ | |
423 | __asm__ __volatile__ ( \ | |
d77c26fc | 424 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 425 | _op"w %1; " \ |
d77c26fc | 426 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
427 | : "=m" (_eflags), "=m" ((_dst).val), \ |
428 | "=&r" (_tmp) \ | |
d77c26fc | 429 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
430 | break; \ |
431 | case 4: \ | |
432 | __asm__ __volatile__ ( \ | |
d77c26fc | 433 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 434 | _op"l %1; " \ |
d77c26fc | 435 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
436 | : "=m" (_eflags), "=m" ((_dst).val), \ |
437 | "=&r" (_tmp) \ | |
d77c26fc | 438 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
439 | break; \ |
440 | case 8: \ | |
441 | __emulate_1op_8byte(_op, _dst, _eflags); \ | |
442 | break; \ | |
443 | } \ | |
444 | } while (0) | |
445 | ||
446 | /* Emulate an instruction with quadword operands (x86/64 only). */ | |
05b3e0c2 | 447 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
448 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \ |
449 | do { \ | |
450 | __asm__ __volatile__ ( \ | |
d77c26fc | 451 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 452 | _op"q %"_qx"3,%1; " \ |
d77c26fc | 453 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 | 454 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 455 | : _qy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
456 | } while (0) |
457 | ||
458 | #define __emulate_1op_8byte(_op, _dst, _eflags) \ | |
459 | do { \ | |
460 | __asm__ __volatile__ ( \ | |
d77c26fc | 461 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 462 | _op"q %1; " \ |
d77c26fc | 463 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 | 464 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 465 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
466 | } while (0) |
467 | ||
468 | #elif defined(__i386__) | |
469 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) | |
470 | #define __emulate_1op_8byte(_op, _dst, _eflags) | |
471 | #endif /* __i386__ */ | |
472 | ||
473 | /* Fetch next part of the instruction being emulated. */ | |
474 | #define insn_fetch(_type, _size, _eip) \ | |
475 | ({ unsigned long _x; \ | |
62266869 | 476 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
d77c26fc | 477 | if (rc != 0) \ |
6aa8b732 AK |
478 | goto done; \ |
479 | (_eip) += (_size); \ | |
480 | (_type)_x; \ | |
481 | }) | |
482 | ||
ddcb2885 HH |
483 | static inline unsigned long ad_mask(struct decode_cache *c) |
484 | { | |
485 | return (1UL << (c->ad_bytes << 3)) - 1; | |
486 | } | |
487 | ||
6aa8b732 | 488 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
489 | static inline unsigned long |
490 | address_mask(struct decode_cache *c, unsigned long reg) | |
491 | { | |
492 | if (c->ad_bytes == sizeof(unsigned long)) | |
493 | return reg; | |
494 | else | |
495 | return reg & ad_mask(c); | |
496 | } | |
497 | ||
498 | static inline unsigned long | |
499 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
500 | { | |
501 | return base + address_mask(c, reg); | |
502 | } | |
503 | ||
7a957275 HH |
504 | static inline void |
505 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
506 | { | |
507 | if (c->ad_bytes == sizeof(unsigned long)) | |
508 | *reg += inc; | |
509 | else | |
510 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
511 | } | |
6aa8b732 | 512 | |
7a957275 HH |
513 | static inline void jmp_rel(struct decode_cache *c, int rel) |
514 | { | |
515 | register_address_increment(c, &c->eip, rel); | |
516 | } | |
098c937b | 517 | |
62266869 AK |
518 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
519 | struct x86_emulate_ops *ops, | |
520 | unsigned long linear, u8 *dest) | |
521 | { | |
522 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
523 | int rc; | |
524 | int size; | |
525 | ||
526 | if (linear < fc->start || linear >= fc->end) { | |
527 | size = min(15UL, PAGE_SIZE - offset_in_page(linear)); | |
528 | rc = ops->read_std(linear, fc->data, size, ctxt->vcpu); | |
529 | if (rc) | |
530 | return rc; | |
531 | fc->start = linear; | |
532 | fc->end = linear + size; | |
533 | } | |
534 | *dest = fc->data[linear - fc->start]; | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
539 | struct x86_emulate_ops *ops, | |
540 | unsigned long eip, void *dest, unsigned size) | |
541 | { | |
542 | int rc = 0; | |
543 | ||
544 | eip += ctxt->cs_base; | |
545 | while (size--) { | |
546 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
547 | if (rc) | |
548 | return rc; | |
549 | } | |
550 | return 0; | |
551 | } | |
552 | ||
1e3c5cb0 RR |
553 | /* |
554 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
555 | * pointer into the block that addresses the relevant register. | |
556 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
557 | */ | |
558 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
559 | int highbyte_regs) | |
6aa8b732 AK |
560 | { |
561 | void *p; | |
562 | ||
563 | p = ®s[modrm_reg]; | |
564 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
565 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
566 | return p; | |
567 | } | |
568 | ||
569 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
570 | struct x86_emulate_ops *ops, | |
571 | void *ptr, | |
572 | u16 *size, unsigned long *address, int op_bytes) | |
573 | { | |
574 | int rc; | |
575 | ||
576 | if (op_bytes == 2) | |
577 | op_bytes = 3; | |
578 | *address = 0; | |
cebff02b LV |
579 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
580 | ctxt->vcpu); | |
6aa8b732 AK |
581 | if (rc) |
582 | return rc; | |
cebff02b LV |
583 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
584 | ctxt->vcpu); | |
6aa8b732 AK |
585 | return rc; |
586 | } | |
587 | ||
bbe9abbd NK |
588 | static int test_cc(unsigned int condition, unsigned int flags) |
589 | { | |
590 | int rc = 0; | |
591 | ||
592 | switch ((condition & 15) >> 1) { | |
593 | case 0: /* o */ | |
594 | rc |= (flags & EFLG_OF); | |
595 | break; | |
596 | case 1: /* b/c/nae */ | |
597 | rc |= (flags & EFLG_CF); | |
598 | break; | |
599 | case 2: /* z/e */ | |
600 | rc |= (flags & EFLG_ZF); | |
601 | break; | |
602 | case 3: /* be/na */ | |
603 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
604 | break; | |
605 | case 4: /* s */ | |
606 | rc |= (flags & EFLG_SF); | |
607 | break; | |
608 | case 5: /* p/pe */ | |
609 | rc |= (flags & EFLG_PF); | |
610 | break; | |
611 | case 7: /* le/ng */ | |
612 | rc |= (flags & EFLG_ZF); | |
613 | /* fall through */ | |
614 | case 6: /* l/nge */ | |
615 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
616 | break; | |
617 | } | |
618 | ||
619 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
620 | return (!!rc ^ (condition & 1)); | |
621 | } | |
622 | ||
3c118e24 AK |
623 | static void decode_register_operand(struct operand *op, |
624 | struct decode_cache *c, | |
3c118e24 AK |
625 | int inhibit_bytereg) |
626 | { | |
33615aa9 | 627 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 628 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
629 | |
630 | if (!(c->d & ModRM)) | |
631 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
632 | op->type = OP_REG; |
633 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 634 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
635 | op->val = *(u8 *)op->ptr; |
636 | op->bytes = 1; | |
637 | } else { | |
33615aa9 | 638 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
639 | op->bytes = c->op_bytes; |
640 | switch (op->bytes) { | |
641 | case 2: | |
642 | op->val = *(u16 *)op->ptr; | |
643 | break; | |
644 | case 4: | |
645 | op->val = *(u32 *)op->ptr; | |
646 | break; | |
647 | case 8: | |
648 | op->val = *(u64 *) op->ptr; | |
649 | break; | |
650 | } | |
651 | } | |
652 | op->orig_val = op->val; | |
653 | } | |
654 | ||
1c73ef66 AK |
655 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
656 | struct x86_emulate_ops *ops) | |
657 | { | |
658 | struct decode_cache *c = &ctxt->decode; | |
659 | u8 sib; | |
660 | int index_reg = 0, base_reg = 0, scale, rip_relative = 0; | |
661 | int rc = 0; | |
662 | ||
663 | if (c->rex_prefix) { | |
664 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
665 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
666 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
667 | } | |
668 | ||
669 | c->modrm = insn_fetch(u8, 1, c->eip); | |
670 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
671 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
672 | c->modrm_rm |= (c->modrm & 0x07); | |
673 | c->modrm_ea = 0; | |
674 | c->use_modrm_ea = 1; | |
675 | ||
676 | if (c->modrm_mod == 3) { | |
677 | c->modrm_val = *(unsigned long *) | |
678 | decode_register(c->modrm_rm, c->regs, c->d & ByteOp); | |
679 | return rc; | |
680 | } | |
681 | ||
682 | if (c->ad_bytes == 2) { | |
683 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
684 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
685 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
686 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
687 | ||
688 | /* 16-bit ModR/M decode. */ | |
689 | switch (c->modrm_mod) { | |
690 | case 0: | |
691 | if (c->modrm_rm == 6) | |
692 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
693 | break; | |
694 | case 1: | |
695 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
696 | break; | |
697 | case 2: | |
698 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
699 | break; | |
700 | } | |
701 | switch (c->modrm_rm) { | |
702 | case 0: | |
703 | c->modrm_ea += bx + si; | |
704 | break; | |
705 | case 1: | |
706 | c->modrm_ea += bx + di; | |
707 | break; | |
708 | case 2: | |
709 | c->modrm_ea += bp + si; | |
710 | break; | |
711 | case 3: | |
712 | c->modrm_ea += bp + di; | |
713 | break; | |
714 | case 4: | |
715 | c->modrm_ea += si; | |
716 | break; | |
717 | case 5: | |
718 | c->modrm_ea += di; | |
719 | break; | |
720 | case 6: | |
721 | if (c->modrm_mod != 0) | |
722 | c->modrm_ea += bp; | |
723 | break; | |
724 | case 7: | |
725 | c->modrm_ea += bx; | |
726 | break; | |
727 | } | |
728 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
729 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
730 | if (!c->override_base) | |
731 | c->override_base = &ctxt->ss_base; | |
732 | c->modrm_ea = (u16)c->modrm_ea; | |
733 | } else { | |
734 | /* 32/64-bit ModR/M decode. */ | |
735 | switch (c->modrm_rm) { | |
736 | case 4: | |
737 | case 12: | |
738 | sib = insn_fetch(u8, 1, c->eip); | |
739 | index_reg |= (sib >> 3) & 7; | |
740 | base_reg |= sib & 7; | |
741 | scale = sib >> 6; | |
742 | ||
743 | switch (base_reg) { | |
744 | case 5: | |
745 | if (c->modrm_mod != 0) | |
746 | c->modrm_ea += c->regs[base_reg]; | |
747 | else | |
748 | c->modrm_ea += | |
749 | insn_fetch(s32, 4, c->eip); | |
750 | break; | |
751 | default: | |
752 | c->modrm_ea += c->regs[base_reg]; | |
753 | } | |
754 | switch (index_reg) { | |
755 | case 4: | |
756 | break; | |
757 | default: | |
758 | c->modrm_ea += c->regs[index_reg] << scale; | |
759 | } | |
760 | break; | |
761 | case 5: | |
762 | if (c->modrm_mod != 0) | |
763 | c->modrm_ea += c->regs[c->modrm_rm]; | |
764 | else if (ctxt->mode == X86EMUL_MODE_PROT64) | |
765 | rip_relative = 1; | |
766 | break; | |
767 | default: | |
768 | c->modrm_ea += c->regs[c->modrm_rm]; | |
769 | break; | |
770 | } | |
771 | switch (c->modrm_mod) { | |
772 | case 0: | |
773 | if (c->modrm_rm == 5) | |
774 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
775 | break; | |
776 | case 1: | |
777 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
778 | break; | |
779 | case 2: | |
780 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
781 | break; | |
782 | } | |
783 | } | |
784 | if (rip_relative) { | |
785 | c->modrm_ea += c->eip; | |
786 | switch (c->d & SrcMask) { | |
787 | case SrcImmByte: | |
788 | c->modrm_ea += 1; | |
789 | break; | |
790 | case SrcImm: | |
791 | if (c->d & ByteOp) | |
792 | c->modrm_ea += 1; | |
793 | else | |
794 | if (c->op_bytes == 8) | |
795 | c->modrm_ea += 4; | |
796 | else | |
797 | c->modrm_ea += c->op_bytes; | |
798 | } | |
799 | } | |
800 | done: | |
801 | return rc; | |
802 | } | |
803 | ||
804 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
805 | struct x86_emulate_ops *ops) | |
806 | { | |
807 | struct decode_cache *c = &ctxt->decode; | |
808 | int rc = 0; | |
809 | ||
810 | switch (c->ad_bytes) { | |
811 | case 2: | |
812 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
813 | break; | |
814 | case 4: | |
815 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
816 | break; | |
817 | case 8: | |
818 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
819 | break; | |
820 | } | |
821 | done: | |
822 | return rc; | |
823 | } | |
824 | ||
6aa8b732 | 825 | int |
8b4caf66 | 826 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 827 | { |
e4e03ded | 828 | struct decode_cache *c = &ctxt->decode; |
6aa8b732 | 829 | int rc = 0; |
6aa8b732 | 830 | int mode = ctxt->mode; |
e09d082c | 831 | int def_op_bytes, def_ad_bytes, group; |
6aa8b732 AK |
832 | |
833 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 834 | |
e4e03ded | 835 | memset(c, 0, sizeof(struct decode_cache)); |
ad312c7c ZX |
836 | c->eip = ctxt->vcpu->arch.rip; |
837 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); | |
6aa8b732 AK |
838 | |
839 | switch (mode) { | |
840 | case X86EMUL_MODE_REAL: | |
841 | case X86EMUL_MODE_PROT16: | |
f21b8bf4 | 842 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
843 | break; |
844 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 845 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 846 | break; |
05b3e0c2 | 847 | #ifdef CONFIG_X86_64 |
6aa8b732 | 848 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
849 | def_op_bytes = 4; |
850 | def_ad_bytes = 8; | |
6aa8b732 AK |
851 | break; |
852 | #endif | |
853 | default: | |
854 | return -1; | |
855 | } | |
856 | ||
f21b8bf4 AK |
857 | c->op_bytes = def_op_bytes; |
858 | c->ad_bytes = def_ad_bytes; | |
859 | ||
6aa8b732 | 860 | /* Legacy prefixes. */ |
b4c6abfe | 861 | for (;;) { |
e4e03ded | 862 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 863 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
864 | /* switch between 2/4 bytes */ |
865 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
866 | break; |
867 | case 0x67: /* address-size override */ | |
868 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 869 | /* switch between 4/8 bytes */ |
f21b8bf4 | 870 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 871 | else |
e4e03ded | 872 | /* switch between 2/4 bytes */ |
f21b8bf4 | 873 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 AK |
874 | break; |
875 | case 0x2e: /* CS override */ | |
e4e03ded | 876 | c->override_base = &ctxt->cs_base; |
6aa8b732 AK |
877 | break; |
878 | case 0x3e: /* DS override */ | |
e4e03ded | 879 | c->override_base = &ctxt->ds_base; |
6aa8b732 AK |
880 | break; |
881 | case 0x26: /* ES override */ | |
e4e03ded | 882 | c->override_base = &ctxt->es_base; |
6aa8b732 AK |
883 | break; |
884 | case 0x64: /* FS override */ | |
e4e03ded | 885 | c->override_base = &ctxt->fs_base; |
6aa8b732 AK |
886 | break; |
887 | case 0x65: /* GS override */ | |
e4e03ded | 888 | c->override_base = &ctxt->gs_base; |
6aa8b732 AK |
889 | break; |
890 | case 0x36: /* SS override */ | |
e4e03ded | 891 | c->override_base = &ctxt->ss_base; |
6aa8b732 | 892 | break; |
b4c6abfe LV |
893 | case 0x40 ... 0x4f: /* REX */ |
894 | if (mode != X86EMUL_MODE_PROT64) | |
895 | goto done_prefixes; | |
33615aa9 | 896 | c->rex_prefix = c->b; |
b4c6abfe | 897 | continue; |
6aa8b732 | 898 | case 0xf0: /* LOCK */ |
e4e03ded | 899 | c->lock_prefix = 1; |
6aa8b732 | 900 | break; |
ae6200ba | 901 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
902 | c->rep_prefix = REPNE_PREFIX; |
903 | break; | |
6aa8b732 | 904 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 905 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 906 | break; |
6aa8b732 AK |
907 | default: |
908 | goto done_prefixes; | |
909 | } | |
b4c6abfe LV |
910 | |
911 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
912 | ||
33615aa9 | 913 | c->rex_prefix = 0; |
6aa8b732 AK |
914 | } |
915 | ||
916 | done_prefixes: | |
917 | ||
918 | /* REX prefix. */ | |
1c73ef66 | 919 | if (c->rex_prefix) |
33615aa9 | 920 | if (c->rex_prefix & 8) |
e4e03ded | 921 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
922 | |
923 | /* Opcode byte(s). */ | |
e4e03ded LV |
924 | c->d = opcode_table[c->b]; |
925 | if (c->d == 0) { | |
6aa8b732 | 926 | /* Two-byte opcode? */ |
e4e03ded LV |
927 | if (c->b == 0x0f) { |
928 | c->twobyte = 1; | |
929 | c->b = insn_fetch(u8, 1, c->eip); | |
930 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 931 | } |
e09d082c | 932 | } |
6aa8b732 | 933 | |
e09d082c AK |
934 | if (c->d & Group) { |
935 | group = c->d & GroupMask; | |
936 | c->modrm = insn_fetch(u8, 1, c->eip); | |
937 | --c->eip; | |
938 | ||
939 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
940 | if ((c->d & GroupDual) && (c->modrm >> 6) == 3) | |
941 | c->d = group2_table[group]; | |
942 | else | |
943 | c->d = group_table[group]; | |
944 | } | |
945 | ||
946 | /* Unrecognised? */ | |
947 | if (c->d == 0) { | |
948 | DPRINTF("Cannot emulate %02x\n", c->b); | |
949 | return -1; | |
6aa8b732 AK |
950 | } |
951 | ||
6e3d5dfb AK |
952 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
953 | c->op_bytes = 8; | |
954 | ||
6aa8b732 | 955 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
956 | if (c->d & ModRM) |
957 | rc = decode_modrm(ctxt, ops); | |
958 | else if (c->d & MemAbs) | |
959 | rc = decode_abs(ctxt, ops); | |
960 | if (rc) | |
961 | goto done; | |
6aa8b732 | 962 | |
c7e75a3d AK |
963 | if (!c->override_base) |
964 | c->override_base = &ctxt->ds_base; | |
965 | if (mode == X86EMUL_MODE_PROT64 && | |
966 | c->override_base != &ctxt->fs_base && | |
967 | c->override_base != &ctxt->gs_base) | |
968 | c->override_base = NULL; | |
969 | ||
970 | if (c->override_base) | |
971 | c->modrm_ea += *c->override_base; | |
972 | ||
973 | if (c->ad_bytes != 8) | |
974 | c->modrm_ea = (u32)c->modrm_ea; | |
6aa8b732 AK |
975 | /* |
976 | * Decode and fetch the source operand: register, memory | |
977 | * or immediate. | |
978 | */ | |
e4e03ded | 979 | switch (c->d & SrcMask) { |
6aa8b732 AK |
980 | case SrcNone: |
981 | break; | |
982 | case SrcReg: | |
9f1ef3f8 | 983 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
984 | break; |
985 | case SrcMem16: | |
e4e03ded | 986 | c->src.bytes = 2; |
6aa8b732 AK |
987 | goto srcmem_common; |
988 | case SrcMem32: | |
e4e03ded | 989 | c->src.bytes = 4; |
6aa8b732 AK |
990 | goto srcmem_common; |
991 | case SrcMem: | |
e4e03ded LV |
992 | c->src.bytes = (c->d & ByteOp) ? 1 : |
993 | c->op_bytes; | |
b85b9ee9 | 994 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 995 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 996 | break; |
d77c26fc | 997 | srcmem_common: |
4e62417b AJ |
998 | /* |
999 | * For instructions with a ModR/M byte, switch to register | |
1000 | * access if Mod = 3. | |
1001 | */ | |
e4e03ded LV |
1002 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1003 | c->src.type = OP_REG; | |
4e62417b AJ |
1004 | break; |
1005 | } | |
e4e03ded | 1006 | c->src.type = OP_MEM; |
6aa8b732 AK |
1007 | break; |
1008 | case SrcImm: | |
e4e03ded LV |
1009 | c->src.type = OP_IMM; |
1010 | c->src.ptr = (unsigned long *)c->eip; | |
1011 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1012 | if (c->src.bytes == 8) | |
1013 | c->src.bytes = 4; | |
6aa8b732 | 1014 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1015 | switch (c->src.bytes) { |
6aa8b732 | 1016 | case 1: |
e4e03ded | 1017 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1018 | break; |
1019 | case 2: | |
e4e03ded | 1020 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1021 | break; |
1022 | case 4: | |
e4e03ded | 1023 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1024 | break; |
1025 | } | |
1026 | break; | |
1027 | case SrcImmByte: | |
e4e03ded LV |
1028 | c->src.type = OP_IMM; |
1029 | c->src.ptr = (unsigned long *)c->eip; | |
1030 | c->src.bytes = 1; | |
1031 | c->src.val = insn_fetch(s8, 1, c->eip); | |
6aa8b732 AK |
1032 | break; |
1033 | } | |
1034 | ||
038e51de | 1035 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1036 | switch (c->d & DstMask) { |
038e51de AK |
1037 | case ImplicitOps: |
1038 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1039 | return 0; |
038e51de | 1040 | case DstReg: |
9f1ef3f8 | 1041 | decode_register_operand(&c->dst, c, |
3c118e24 | 1042 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1043 | break; |
1044 | case DstMem: | |
e4e03ded LV |
1045 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1046 | c->dst.type = OP_REG; | |
4e62417b AJ |
1047 | break; |
1048 | } | |
8b4caf66 LV |
1049 | c->dst.type = OP_MEM; |
1050 | break; | |
1051 | } | |
1052 | ||
1053 | done: | |
1054 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1055 | } | |
1056 | ||
8cdbd2c9 LV |
1057 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
1058 | { | |
1059 | struct decode_cache *c = &ctxt->decode; | |
1060 | ||
1061 | c->dst.type = OP_MEM; | |
1062 | c->dst.bytes = c->op_bytes; | |
1063 | c->dst.val = c->src.val; | |
7a957275 | 1064 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
e4706772 | 1065 | c->dst.ptr = (void *) register_address(c, ctxt->ss_base, |
8cdbd2c9 LV |
1066 | c->regs[VCPU_REGS_RSP]); |
1067 | } | |
1068 | ||
1069 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, | |
1070 | struct x86_emulate_ops *ops) | |
1071 | { | |
1072 | struct decode_cache *c = &ctxt->decode; | |
1073 | int rc; | |
1074 | ||
e4706772 | 1075 | rc = ops->read_std(register_address(c, ctxt->ss_base, |
8cdbd2c9 LV |
1076 | c->regs[VCPU_REGS_RSP]), |
1077 | &c->dst.val, c->dst.bytes, ctxt->vcpu); | |
1078 | if (rc != 0) | |
1079 | return rc; | |
1080 | ||
7a957275 | 1081 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes); |
8cdbd2c9 LV |
1082 | |
1083 | return 0; | |
1084 | } | |
1085 | ||
05f086f8 | 1086 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1087 | { |
05f086f8 | 1088 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1089 | switch (c->modrm_reg) { |
1090 | case 0: /* rol */ | |
05f086f8 | 1091 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1092 | break; |
1093 | case 1: /* ror */ | |
05f086f8 | 1094 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1095 | break; |
1096 | case 2: /* rcl */ | |
05f086f8 | 1097 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1098 | break; |
1099 | case 3: /* rcr */ | |
05f086f8 | 1100 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1101 | break; |
1102 | case 4: /* sal/shl */ | |
1103 | case 6: /* sal/shl */ | |
05f086f8 | 1104 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1105 | break; |
1106 | case 5: /* shr */ | |
05f086f8 | 1107 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1108 | break; |
1109 | case 7: /* sar */ | |
05f086f8 | 1110 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1111 | break; |
1112 | } | |
1113 | } | |
1114 | ||
1115 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1116 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1117 | { |
1118 | struct decode_cache *c = &ctxt->decode; | |
1119 | int rc = 0; | |
1120 | ||
1121 | switch (c->modrm_reg) { | |
1122 | case 0 ... 1: /* test */ | |
05f086f8 | 1123 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1124 | break; |
1125 | case 2: /* not */ | |
1126 | c->dst.val = ~c->dst.val; | |
1127 | break; | |
1128 | case 3: /* neg */ | |
05f086f8 | 1129 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1130 | break; |
1131 | default: | |
1132 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1133 | rc = X86EMUL_UNHANDLEABLE; | |
1134 | break; | |
1135 | } | |
8cdbd2c9 LV |
1136 | return rc; |
1137 | } | |
1138 | ||
1139 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1140 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1141 | { |
1142 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1143 | |
1144 | switch (c->modrm_reg) { | |
1145 | case 0: /* inc */ | |
05f086f8 | 1146 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1147 | break; |
1148 | case 1: /* dec */ | |
05f086f8 | 1149 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1150 | break; |
1151 | case 4: /* jmp abs */ | |
fd60754e | 1152 | c->eip = c->src.val; |
8cdbd2c9 LV |
1153 | break; |
1154 | case 6: /* push */ | |
fd60754e | 1155 | emulate_push(ctxt); |
8cdbd2c9 | 1156 | break; |
8cdbd2c9 LV |
1157 | } |
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
1162 | struct x86_emulate_ops *ops, | |
e8d8d7fe | 1163 | unsigned long memop) |
8cdbd2c9 LV |
1164 | { |
1165 | struct decode_cache *c = &ctxt->decode; | |
1166 | u64 old, new; | |
1167 | int rc; | |
1168 | ||
e8d8d7fe | 1169 | rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1170 | if (rc != 0) |
1171 | return rc; | |
1172 | ||
1173 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1174 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1175 | ||
1176 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1177 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1178 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1179 | |
1180 | } else { | |
1181 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1182 | (u32) c->regs[VCPU_REGS_RBX]; | |
1183 | ||
e8d8d7fe | 1184 | rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1185 | if (rc != 0) |
1186 | return rc; | |
05f086f8 | 1187 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 LV |
1188 | } |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static inline int writeback(struct x86_emulate_ctxt *ctxt, | |
1193 | struct x86_emulate_ops *ops) | |
1194 | { | |
1195 | int rc; | |
1196 | struct decode_cache *c = &ctxt->decode; | |
1197 | ||
1198 | switch (c->dst.type) { | |
1199 | case OP_REG: | |
1200 | /* The 4-byte case *is* correct: | |
1201 | * in 64-bit mode we zero-extend. | |
1202 | */ | |
1203 | switch (c->dst.bytes) { | |
1204 | case 1: | |
1205 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1206 | break; | |
1207 | case 2: | |
1208 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1209 | break; | |
1210 | case 4: | |
1211 | *c->dst.ptr = (u32)c->dst.val; | |
1212 | break; /* 64b: zero-ext */ | |
1213 | case 8: | |
1214 | *c->dst.ptr = c->dst.val; | |
1215 | break; | |
1216 | } | |
1217 | break; | |
1218 | case OP_MEM: | |
1219 | if (c->lock_prefix) | |
1220 | rc = ops->cmpxchg_emulated( | |
1221 | (unsigned long)c->dst.ptr, | |
1222 | &c->dst.orig_val, | |
1223 | &c->dst.val, | |
1224 | c->dst.bytes, | |
1225 | ctxt->vcpu); | |
1226 | else | |
1227 | rc = ops->write_emulated( | |
1228 | (unsigned long)c->dst.ptr, | |
1229 | &c->dst.val, | |
1230 | c->dst.bytes, | |
1231 | ctxt->vcpu); | |
1232 | if (rc != 0) | |
1233 | return rc; | |
a01af5ec LV |
1234 | break; |
1235 | case OP_NONE: | |
1236 | /* no writeback */ | |
1237 | break; | |
8cdbd2c9 LV |
1238 | default: |
1239 | break; | |
1240 | } | |
1241 | return 0; | |
1242 | } | |
1243 | ||
8b4caf66 | 1244 | int |
1be3aa47 | 1245 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 1246 | { |
e8d8d7fe | 1247 | unsigned long memop = 0; |
8b4caf66 | 1248 | u64 msr_data; |
3427318f | 1249 | unsigned long saved_eip = 0; |
8b4caf66 | 1250 | struct decode_cache *c = &ctxt->decode; |
1be3aa47 | 1251 | int rc = 0; |
8b4caf66 | 1252 | |
3427318f LV |
1253 | /* Shadow copy of register state. Committed on successful emulation. |
1254 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
1255 | * modify them. | |
1256 | */ | |
1257 | ||
ad312c7c | 1258 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
3427318f LV |
1259 | saved_eip = c->eip; |
1260 | ||
c7e75a3d | 1261 | if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) |
e8d8d7fe | 1262 | memop = c->modrm_ea; |
8b4caf66 | 1263 | |
b9fa9d6b AK |
1264 | if (c->rep_prefix && (c->d & String)) { |
1265 | /* All REP prefixes have the same first termination condition */ | |
1266 | if (c->regs[VCPU_REGS_RCX] == 0) { | |
ad312c7c | 1267 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1268 | goto done; |
1269 | } | |
1270 | /* The second termination condition only applies for REPE | |
1271 | * and REPNE. Test if the repeat string operation prefix is | |
1272 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
1273 | * corresponding termination condition according to: | |
1274 | * - if REPE/REPZ and ZF = 0 then done | |
1275 | * - if REPNE/REPNZ and ZF = 1 then done | |
1276 | */ | |
1277 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
1278 | (c->b == 0xae) || (c->b == 0xaf)) { | |
1279 | if ((c->rep_prefix == REPE_PREFIX) && | |
1280 | ((ctxt->eflags & EFLG_ZF) == 0)) { | |
ad312c7c | 1281 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1282 | goto done; |
1283 | } | |
1284 | if ((c->rep_prefix == REPNE_PREFIX) && | |
1285 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) { | |
ad312c7c | 1286 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1287 | goto done; |
1288 | } | |
1289 | } | |
1290 | c->regs[VCPU_REGS_RCX]--; | |
ad312c7c | 1291 | c->eip = ctxt->vcpu->arch.rip; |
b9fa9d6b AK |
1292 | } |
1293 | ||
8b4caf66 | 1294 | if (c->src.type == OP_MEM) { |
e8d8d7fe | 1295 | c->src.ptr = (unsigned long *)memop; |
8b4caf66 | 1296 | c->src.val = 0; |
d77c26fc MD |
1297 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
1298 | &c->src.val, | |
1299 | c->src.bytes, | |
1300 | ctxt->vcpu); | |
1301 | if (rc != 0) | |
8b4caf66 LV |
1302 | goto done; |
1303 | c->src.orig_val = c->src.val; | |
1304 | } | |
1305 | ||
1306 | if ((c->d & DstMask) == ImplicitOps) | |
1307 | goto special_insn; | |
1308 | ||
1309 | ||
1310 | if (c->dst.type == OP_MEM) { | |
e8d8d7fe | 1311 | c->dst.ptr = (unsigned long *)memop; |
8b4caf66 LV |
1312 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
1313 | c->dst.val = 0; | |
e4e03ded LV |
1314 | if (c->d & BitOp) { |
1315 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
df513e2c | 1316 | |
e4e03ded LV |
1317 | c->dst.ptr = (void *)c->dst.ptr + |
1318 | (c->src.val & mask) / 8; | |
038e51de | 1319 | } |
e4e03ded LV |
1320 | if (!(c->d & Mov) && |
1321 | /* optimisation - avoid slow emulated read */ | |
1322 | ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1323 | &c->dst.val, | |
1324 | c->dst.bytes, ctxt->vcpu)) != 0)) | |
038e51de | 1325 | goto done; |
038e51de | 1326 | } |
e4e03ded | 1327 | c->dst.orig_val = c->dst.val; |
038e51de | 1328 | |
018a98db AK |
1329 | special_insn: |
1330 | ||
e4e03ded | 1331 | if (c->twobyte) |
6aa8b732 AK |
1332 | goto twobyte_insn; |
1333 | ||
e4e03ded | 1334 | switch (c->b) { |
6aa8b732 AK |
1335 | case 0x00 ... 0x05: |
1336 | add: /* add */ | |
05f086f8 | 1337 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1338 | break; |
1339 | case 0x08 ... 0x0d: | |
1340 | or: /* or */ | |
05f086f8 | 1341 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1342 | break; |
1343 | case 0x10 ... 0x15: | |
1344 | adc: /* adc */ | |
05f086f8 | 1345 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1346 | break; |
1347 | case 0x18 ... 0x1d: | |
1348 | sbb: /* sbb */ | |
05f086f8 | 1349 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1350 | break; |
19eb938e | 1351 | case 0x20 ... 0x23: |
6aa8b732 | 1352 | and: /* and */ |
05f086f8 | 1353 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1354 | break; |
19eb938e | 1355 | case 0x24: /* and al imm8 */ |
e4e03ded LV |
1356 | c->dst.type = OP_REG; |
1357 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1358 | c->dst.val = *(u8 *)c->dst.ptr; | |
1359 | c->dst.bytes = 1; | |
1360 | c->dst.orig_val = c->dst.val; | |
19eb938e NK |
1361 | goto and; |
1362 | case 0x25: /* and ax imm16, or eax imm32 */ | |
e4e03ded LV |
1363 | c->dst.type = OP_REG; |
1364 | c->dst.bytes = c->op_bytes; | |
1365 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1366 | if (c->op_bytes == 2) | |
1367 | c->dst.val = *(u16 *)c->dst.ptr; | |
19eb938e | 1368 | else |
e4e03ded LV |
1369 | c->dst.val = *(u32 *)c->dst.ptr; |
1370 | c->dst.orig_val = c->dst.val; | |
19eb938e | 1371 | goto and; |
6aa8b732 AK |
1372 | case 0x28 ... 0x2d: |
1373 | sub: /* sub */ | |
05f086f8 | 1374 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1375 | break; |
1376 | case 0x30 ... 0x35: | |
1377 | xor: /* xor */ | |
05f086f8 | 1378 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1379 | break; |
1380 | case 0x38 ... 0x3d: | |
1381 | cmp: /* cmp */ | |
05f086f8 | 1382 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1383 | break; |
33615aa9 AK |
1384 | case 0x40 ... 0x47: /* inc r16/r32 */ |
1385 | emulate_1op("inc", c->dst, ctxt->eflags); | |
1386 | break; | |
1387 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
1388 | emulate_1op("dec", c->dst, ctxt->eflags); | |
1389 | break; | |
1390 | case 0x50 ... 0x57: /* push reg */ | |
1391 | c->dst.type = OP_MEM; | |
1392 | c->dst.bytes = c->op_bytes; | |
1393 | c->dst.val = c->src.val; | |
7a957275 | 1394 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], |
33615aa9 AK |
1395 | -c->op_bytes); |
1396 | c->dst.ptr = (void *) register_address( | |
e4706772 | 1397 | c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]); |
33615aa9 AK |
1398 | break; |
1399 | case 0x58 ... 0x5f: /* pop reg */ | |
1400 | pop_instruction: | |
e4706772 | 1401 | if ((rc = ops->read_std(register_address(c, ctxt->ss_base, |
33615aa9 AK |
1402 | c->regs[VCPU_REGS_RSP]), c->dst.ptr, |
1403 | c->op_bytes, ctxt->vcpu)) != 0) | |
1404 | goto done; | |
1405 | ||
7a957275 | 1406 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], |
33615aa9 AK |
1407 | c->op_bytes); |
1408 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1409 | break; | |
6aa8b732 | 1410 | case 0x63: /* movsxd */ |
8b4caf66 | 1411 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 1412 | goto cannot_emulate; |
e4e03ded | 1413 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 1414 | break; |
018a98db AK |
1415 | case 0x6a: /* push imm8 */ |
1416 | c->src.val = 0L; | |
1417 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1418 | emulate_push(ctxt); | |
1419 | break; | |
1420 | case 0x6c: /* insb */ | |
1421 | case 0x6d: /* insw/insd */ | |
1422 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, | |
1423 | 1, | |
1424 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1425 | c->rep_prefix ? | |
e4706772 | 1426 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 1427 | (ctxt->eflags & EFLG_DF), |
e4706772 | 1428 | register_address(c, ctxt->es_base, |
018a98db AK |
1429 | c->regs[VCPU_REGS_RDI]), |
1430 | c->rep_prefix, | |
1431 | c->regs[VCPU_REGS_RDX]) == 0) { | |
1432 | c->eip = saved_eip; | |
1433 | return -1; | |
1434 | } | |
1435 | return 0; | |
1436 | case 0x6e: /* outsb */ | |
1437 | case 0x6f: /* outsw/outsd */ | |
1438 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, | |
1439 | 0, | |
1440 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1441 | c->rep_prefix ? | |
e4706772 | 1442 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 1443 | (ctxt->eflags & EFLG_DF), |
e4706772 | 1444 | register_address(c, c->override_base ? |
018a98db AK |
1445 | *c->override_base : |
1446 | ctxt->ds_base, | |
1447 | c->regs[VCPU_REGS_RSI]), | |
1448 | c->rep_prefix, | |
1449 | c->regs[VCPU_REGS_RDX]) == 0) { | |
1450 | c->eip = saved_eip; | |
1451 | return -1; | |
1452 | } | |
1453 | return 0; | |
1454 | case 0x70 ... 0x7f: /* jcc (short) */ { | |
1455 | int rel = insn_fetch(s8, 1, c->eip); | |
1456 | ||
1457 | if (test_cc(c->b, ctxt->eflags)) | |
7a957275 | 1458 | jmp_rel(c, rel); |
018a98db AK |
1459 | break; |
1460 | } | |
6aa8b732 | 1461 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 1462 | switch (c->modrm_reg) { |
6aa8b732 AK |
1463 | case 0: |
1464 | goto add; | |
1465 | case 1: | |
1466 | goto or; | |
1467 | case 2: | |
1468 | goto adc; | |
1469 | case 3: | |
1470 | goto sbb; | |
1471 | case 4: | |
1472 | goto and; | |
1473 | case 5: | |
1474 | goto sub; | |
1475 | case 6: | |
1476 | goto xor; | |
1477 | case 7: | |
1478 | goto cmp; | |
1479 | } | |
1480 | break; | |
1481 | case 0x84 ... 0x85: | |
05f086f8 | 1482 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1483 | break; |
1484 | case 0x86 ... 0x87: /* xchg */ | |
1485 | /* Write back the register source. */ | |
e4e03ded | 1486 | switch (c->dst.bytes) { |
6aa8b732 | 1487 | case 1: |
e4e03ded | 1488 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
1489 | break; |
1490 | case 2: | |
e4e03ded | 1491 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
1492 | break; |
1493 | case 4: | |
e4e03ded | 1494 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
1495 | break; /* 64b reg: zero-extend */ |
1496 | case 8: | |
e4e03ded | 1497 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
1498 | break; |
1499 | } | |
1500 | /* | |
1501 | * Write back the memory destination with implicit LOCK | |
1502 | * prefix. | |
1503 | */ | |
e4e03ded LV |
1504 | c->dst.val = c->src.val; |
1505 | c->lock_prefix = 1; | |
6aa8b732 | 1506 | break; |
6aa8b732 | 1507 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 1508 | goto mov; |
7e0b54b1 | 1509 | case 0x8d: /* lea r16/r32, m */ |
e4e03ded | 1510 | c->dst.val = c->modrm_val; |
7e0b54b1 | 1511 | break; |
6aa8b732 | 1512 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 LV |
1513 | rc = emulate_grp1a(ctxt, ops); |
1514 | if (rc != 0) | |
6aa8b732 | 1515 | goto done; |
6aa8b732 | 1516 | break; |
fd2a7608 | 1517 | case 0x9c: /* pushf */ |
05f086f8 | 1518 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
1519 | emulate_push(ctxt); |
1520 | break; | |
535eabcf | 1521 | case 0x9d: /* popf */ |
05f086f8 | 1522 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
535eabcf | 1523 | goto pop_instruction; |
018a98db AK |
1524 | case 0xa0 ... 0xa1: /* mov */ |
1525 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
1526 | c->dst.val = c->src.val; | |
1527 | break; | |
1528 | case 0xa2 ... 0xa3: /* mov */ | |
1529 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; | |
1530 | break; | |
6aa8b732 | 1531 | case 0xa4 ... 0xa5: /* movs */ |
e4e03ded LV |
1532 | c->dst.type = OP_MEM; |
1533 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1534 | c->dst.ptr = (unsigned long *)register_address(c, |
e4e03ded LV |
1535 | ctxt->es_base, |
1536 | c->regs[VCPU_REGS_RDI]); | |
e4706772 | 1537 | if ((rc = ops->read_emulated(register_address(c, |
e4e03ded LV |
1538 | c->override_base ? *c->override_base : |
1539 | ctxt->ds_base, | |
1540 | c->regs[VCPU_REGS_RSI]), | |
1541 | &c->dst.val, | |
1542 | c->dst.bytes, ctxt->vcpu)) != 0) | |
6aa8b732 | 1543 | goto done; |
7a957275 | 1544 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 1545 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1546 | : c->dst.bytes); |
7a957275 | 1547 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 1548 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1549 | : c->dst.bytes); |
6aa8b732 AK |
1550 | break; |
1551 | case 0xa6 ... 0xa7: /* cmps */ | |
d7e5117a GT |
1552 | c->src.type = OP_NONE; /* Disable writeback. */ |
1553 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1554 | c->src.ptr = (unsigned long *)register_address(c, |
d7e5117a GT |
1555 | c->override_base ? *c->override_base : |
1556 | ctxt->ds_base, | |
1557 | c->regs[VCPU_REGS_RSI]); | |
1558 | if ((rc = ops->read_emulated((unsigned long)c->src.ptr, | |
1559 | &c->src.val, | |
1560 | c->src.bytes, | |
1561 | ctxt->vcpu)) != 0) | |
1562 | goto done; | |
1563 | ||
1564 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1565 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1566 | c->dst.ptr = (unsigned long *)register_address(c, |
d7e5117a GT |
1567 | ctxt->es_base, |
1568 | c->regs[VCPU_REGS_RDI]); | |
1569 | if ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1570 | &c->dst.val, | |
1571 | c->dst.bytes, | |
1572 | ctxt->vcpu)) != 0) | |
1573 | goto done; | |
1574 | ||
1575 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); | |
1576 | ||
1577 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); | |
1578 | ||
7a957275 | 1579 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
d7e5117a GT |
1580 | (ctxt->eflags & EFLG_DF) ? -c->src.bytes |
1581 | : c->src.bytes); | |
7a957275 | 1582 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
d7e5117a GT |
1583 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
1584 | : c->dst.bytes); | |
1585 | ||
1586 | break; | |
6aa8b732 | 1587 | case 0xaa ... 0xab: /* stos */ |
e4e03ded LV |
1588 | c->dst.type = OP_MEM; |
1589 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1590 | c->dst.ptr = (unsigned long *)register_address(c, |
a7e6c88a SY |
1591 | ctxt->es_base, |
1592 | c->regs[VCPU_REGS_RDI]); | |
e4e03ded | 1593 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
7a957275 | 1594 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 1595 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1596 | : c->dst.bytes); |
6aa8b732 AK |
1597 | break; |
1598 | case 0xac ... 0xad: /* lods */ | |
e4e03ded LV |
1599 | c->dst.type = OP_REG; |
1600 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1601 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
e4706772 | 1602 | if ((rc = ops->read_emulated(register_address(c, |
a7e6c88a SY |
1603 | c->override_base ? *c->override_base : |
1604 | ctxt->ds_base, | |
1605 | c->regs[VCPU_REGS_RSI]), | |
1606 | &c->dst.val, | |
1607 | c->dst.bytes, | |
1608 | ctxt->vcpu)) != 0) | |
6aa8b732 | 1609 | goto done; |
7a957275 | 1610 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 1611 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1612 | : c->dst.bytes); |
6aa8b732 AK |
1613 | break; |
1614 | case 0xae ... 0xaf: /* scas */ | |
1615 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
1616 | goto cannot_emulate; | |
018a98db AK |
1617 | case 0xc0 ... 0xc1: |
1618 | emulate_grp2(ctxt); | |
1619 | break; | |
111de5d6 AK |
1620 | case 0xc3: /* ret */ |
1621 | c->dst.ptr = &c->eip; | |
1622 | goto pop_instruction; | |
018a98db AK |
1623 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
1624 | mov: | |
1625 | c->dst.val = c->src.val; | |
1626 | break; | |
1627 | case 0xd0 ... 0xd1: /* Grp2 */ | |
1628 | c->src.val = 1; | |
1629 | emulate_grp2(ctxt); | |
1630 | break; | |
1631 | case 0xd2 ... 0xd3: /* Grp2 */ | |
1632 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
1633 | emulate_grp2(ctxt); | |
1634 | break; | |
1a52e051 NK |
1635 | case 0xe8: /* call (near) */ { |
1636 | long int rel; | |
e4e03ded | 1637 | switch (c->op_bytes) { |
1a52e051 | 1638 | case 2: |
e4e03ded | 1639 | rel = insn_fetch(s16, 2, c->eip); |
1a52e051 NK |
1640 | break; |
1641 | case 4: | |
e4e03ded | 1642 | rel = insn_fetch(s32, 4, c->eip); |
1a52e051 | 1643 | break; |
1a52e051 NK |
1644 | default: |
1645 | DPRINTF("Call: Invalid op_bytes\n"); | |
1646 | goto cannot_emulate; | |
1647 | } | |
e4e03ded | 1648 | c->src.val = (unsigned long) c->eip; |
7a957275 | 1649 | jmp_rel(c, rel); |
e4e03ded | 1650 | c->op_bytes = c->ad_bytes; |
8cdbd2c9 LV |
1651 | emulate_push(ctxt); |
1652 | break; | |
1a52e051 NK |
1653 | } |
1654 | case 0xe9: /* jmp rel */ | |
1655 | case 0xeb: /* jmp rel short */ | |
7a957275 | 1656 | jmp_rel(c, c->src.val); |
a01af5ec | 1657 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 1658 | break; |
111de5d6 | 1659 | case 0xf4: /* hlt */ |
ad312c7c | 1660 | ctxt->vcpu->arch.halt_request = 1; |
111de5d6 AK |
1661 | goto done; |
1662 | case 0xf5: /* cmc */ | |
1663 | /* complement carry flag from eflags reg */ | |
1664 | ctxt->eflags ^= EFLG_CF; | |
1665 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1666 | break; | |
018a98db AK |
1667 | case 0xf6 ... 0xf7: /* Grp3 */ |
1668 | rc = emulate_grp3(ctxt, ops); | |
1669 | if (rc != 0) | |
1670 | goto done; | |
1671 | break; | |
111de5d6 AK |
1672 | case 0xf8: /* clc */ |
1673 | ctxt->eflags &= ~EFLG_CF; | |
1674 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1675 | break; | |
1676 | case 0xfa: /* cli */ | |
1677 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
1678 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1679 | break; | |
1680 | case 0xfb: /* sti */ | |
1681 | ctxt->eflags |= X86_EFLAGS_IF; | |
1682 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1683 | break; | |
018a98db AK |
1684 | case 0xfe ... 0xff: /* Grp4/Grp5 */ |
1685 | rc = emulate_grp45(ctxt, ops); | |
1686 | if (rc != 0) | |
1687 | goto done; | |
1688 | break; | |
6aa8b732 | 1689 | } |
018a98db AK |
1690 | |
1691 | writeback: | |
1692 | rc = writeback(ctxt, ops); | |
1693 | if (rc != 0) | |
1694 | goto done; | |
1695 | ||
1696 | /* Commit shadow register state. */ | |
ad312c7c ZX |
1697 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); |
1698 | ctxt->vcpu->arch.rip = c->eip; | |
018a98db AK |
1699 | |
1700 | done: | |
1701 | if (rc == X86EMUL_UNHANDLEABLE) { | |
1702 | c->eip = saved_eip; | |
1703 | return -1; | |
1704 | } | |
1705 | return 0; | |
6aa8b732 AK |
1706 | |
1707 | twobyte_insn: | |
e4e03ded | 1708 | switch (c->b) { |
6aa8b732 | 1709 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 1710 | switch (c->modrm_reg) { |
6aa8b732 AK |
1711 | u16 size; |
1712 | unsigned long address; | |
1713 | ||
aca7f966 | 1714 | case 0: /* vmcall */ |
e4e03ded | 1715 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
1716 | goto cannot_emulate; |
1717 | ||
7aa81cc0 AL |
1718 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1719 | if (rc) | |
1720 | goto done; | |
1721 | ||
1722 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1723 | break; |
6aa8b732 | 1724 | case 2: /* lgdt */ |
e4e03ded LV |
1725 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
1726 | &size, &address, c->op_bytes); | |
6aa8b732 AK |
1727 | if (rc) |
1728 | goto done; | |
1729 | realmode_lgdt(ctxt->vcpu, size, address); | |
1730 | break; | |
aca7f966 | 1731 | case 3: /* lidt/vmmcall */ |
e4e03ded | 1732 | if (c->modrm_mod == 3 && c->modrm_rm == 1) { |
7aa81cc0 AL |
1733 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1734 | if (rc) | |
1735 | goto done; | |
1736 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1737 | } else { |
e4e03ded | 1738 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 1739 | &size, &address, |
e4e03ded | 1740 | c->op_bytes); |
aca7f966 AL |
1741 | if (rc) |
1742 | goto done; | |
1743 | realmode_lidt(ctxt->vcpu, size, address); | |
1744 | } | |
6aa8b732 AK |
1745 | break; |
1746 | case 4: /* smsw */ | |
e4e03ded | 1747 | if (c->modrm_mod != 3) |
6aa8b732 | 1748 | goto cannot_emulate; |
e4e03ded | 1749 | *(u16 *)&c->regs[c->modrm_rm] |
6aa8b732 AK |
1750 | = realmode_get_cr(ctxt->vcpu, 0); |
1751 | break; | |
1752 | case 6: /* lmsw */ | |
e4e03ded | 1753 | if (c->modrm_mod != 3) |
6aa8b732 | 1754 | goto cannot_emulate; |
05f086f8 LV |
1755 | realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val, |
1756 | &ctxt->eflags); | |
6aa8b732 AK |
1757 | break; |
1758 | case 7: /* invlpg*/ | |
e8d8d7fe | 1759 | emulate_invlpg(ctxt->vcpu, memop); |
6aa8b732 AK |
1760 | break; |
1761 | default: | |
1762 | goto cannot_emulate; | |
1763 | } | |
a01af5ec LV |
1764 | /* Disable writeback. */ |
1765 | c->dst.type = OP_NONE; | |
6aa8b732 | 1766 | break; |
018a98db AK |
1767 | case 0x06: |
1768 | emulate_clts(ctxt->vcpu); | |
1769 | c->dst.type = OP_NONE; | |
1770 | break; | |
1771 | case 0x08: /* invd */ | |
1772 | case 0x09: /* wbinvd */ | |
1773 | case 0x0d: /* GrpP (prefetch) */ | |
1774 | case 0x18: /* Grp16 (prefetch/nop) */ | |
1775 | c->dst.type = OP_NONE; | |
1776 | break; | |
1777 | case 0x20: /* mov cr, reg */ | |
1778 | if (c->modrm_mod != 3) | |
1779 | goto cannot_emulate; | |
1780 | c->regs[c->modrm_rm] = | |
1781 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); | |
1782 | c->dst.type = OP_NONE; /* no writeback */ | |
1783 | break; | |
6aa8b732 | 1784 | case 0x21: /* mov from dr to reg */ |
e4e03ded | 1785 | if (c->modrm_mod != 3) |
6aa8b732 | 1786 | goto cannot_emulate; |
8cdbd2c9 | 1787 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
a01af5ec LV |
1788 | if (rc) |
1789 | goto cannot_emulate; | |
1790 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1791 | break; |
018a98db AK |
1792 | case 0x22: /* mov reg, cr */ |
1793 | if (c->modrm_mod != 3) | |
1794 | goto cannot_emulate; | |
1795 | realmode_set_cr(ctxt->vcpu, | |
1796 | c->modrm_reg, c->modrm_val, &ctxt->eflags); | |
1797 | c->dst.type = OP_NONE; | |
1798 | break; | |
6aa8b732 | 1799 | case 0x23: /* mov from reg to dr */ |
e4e03ded | 1800 | if (c->modrm_mod != 3) |
6aa8b732 | 1801 | goto cannot_emulate; |
e4e03ded LV |
1802 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
1803 | c->regs[c->modrm_rm]); | |
a01af5ec LV |
1804 | if (rc) |
1805 | goto cannot_emulate; | |
1806 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1807 | break; |
018a98db AK |
1808 | case 0x30: |
1809 | /* wrmsr */ | |
1810 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
1811 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
1812 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); | |
1813 | if (rc) { | |
c1a5d4f9 | 1814 | kvm_inject_gp(ctxt->vcpu, 0); |
ad312c7c | 1815 | c->eip = ctxt->vcpu->arch.rip; |
018a98db AK |
1816 | } |
1817 | rc = X86EMUL_CONTINUE; | |
1818 | c->dst.type = OP_NONE; | |
1819 | break; | |
1820 | case 0x32: | |
1821 | /* rdmsr */ | |
1822 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); | |
1823 | if (rc) { | |
c1a5d4f9 | 1824 | kvm_inject_gp(ctxt->vcpu, 0); |
ad312c7c | 1825 | c->eip = ctxt->vcpu->arch.rip; |
018a98db AK |
1826 | } else { |
1827 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
1828 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
1829 | } | |
1830 | rc = X86EMUL_CONTINUE; | |
1831 | c->dst.type = OP_NONE; | |
1832 | break; | |
6aa8b732 | 1833 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 1834 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
1835 | if (!test_cc(c->b, ctxt->eflags)) |
1836 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1837 | break; |
018a98db AK |
1838 | case 0x80 ... 0x8f: /* jnz rel, etc*/ { |
1839 | long int rel; | |
1840 | ||
1841 | switch (c->op_bytes) { | |
1842 | case 2: | |
1843 | rel = insn_fetch(s16, 2, c->eip); | |
1844 | break; | |
1845 | case 4: | |
1846 | rel = insn_fetch(s32, 4, c->eip); | |
1847 | break; | |
1848 | case 8: | |
1849 | rel = insn_fetch(s64, 8, c->eip); | |
1850 | break; | |
1851 | default: | |
1852 | DPRINTF("jnz: Invalid op_bytes\n"); | |
1853 | goto cannot_emulate; | |
1854 | } | |
1855 | if (test_cc(c->b, ctxt->eflags)) | |
7a957275 | 1856 | jmp_rel(c, rel); |
018a98db AK |
1857 | c->dst.type = OP_NONE; |
1858 | break; | |
1859 | } | |
7de75248 NK |
1860 | case 0xa3: |
1861 | bt: /* bt */ | |
e4f8e039 | 1862 | c->dst.type = OP_NONE; |
e4e03ded LV |
1863 | /* only subword offset */ |
1864 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1865 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 NK |
1866 | break; |
1867 | case 0xab: | |
1868 | bts: /* bts */ | |
e4e03ded LV |
1869 | /* only subword offset */ |
1870 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1871 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 1872 | break; |
6aa8b732 AK |
1873 | case 0xb0 ... 0xb1: /* cmpxchg */ |
1874 | /* | |
1875 | * Save real source value, then compare EAX against | |
1876 | * destination. | |
1877 | */ | |
e4e03ded LV |
1878 | c->src.orig_val = c->src.val; |
1879 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
1880 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
1881 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 1882 | /* Success: write back to memory. */ |
e4e03ded | 1883 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
1884 | } else { |
1885 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
1886 | c->dst.type = OP_REG; |
1887 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
1888 | } |
1889 | break; | |
6aa8b732 AK |
1890 | case 0xb3: |
1891 | btr: /* btr */ | |
e4e03ded LV |
1892 | /* only subword offset */ |
1893 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1894 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1895 | break; |
6aa8b732 | 1896 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
1897 | c->dst.bytes = c->op_bytes; |
1898 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
1899 | : (u16) c->src.val; | |
6aa8b732 | 1900 | break; |
6aa8b732 | 1901 | case 0xba: /* Grp8 */ |
e4e03ded | 1902 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
1903 | case 0: |
1904 | goto bt; | |
1905 | case 1: | |
1906 | goto bts; | |
1907 | case 2: | |
1908 | goto btr; | |
1909 | case 3: | |
1910 | goto btc; | |
1911 | } | |
1912 | break; | |
7de75248 NK |
1913 | case 0xbb: |
1914 | btc: /* btc */ | |
e4e03ded LV |
1915 | /* only subword offset */ |
1916 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1917 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 1918 | break; |
6aa8b732 | 1919 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
1920 | c->dst.bytes = c->op_bytes; |
1921 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
1922 | (s16) c->src.val; | |
6aa8b732 | 1923 | break; |
a012e65a | 1924 | case 0xc3: /* movnti */ |
e4e03ded LV |
1925 | c->dst.bytes = c->op_bytes; |
1926 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
1927 | (u64) c->src.val; | |
a012e65a | 1928 | break; |
6aa8b732 | 1929 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
e8d8d7fe | 1930 | rc = emulate_grp9(ctxt, ops, memop); |
8cdbd2c9 LV |
1931 | if (rc != 0) |
1932 | goto done; | |
018a98db | 1933 | c->dst.type = OP_NONE; |
8cdbd2c9 | 1934 | break; |
6aa8b732 AK |
1935 | } |
1936 | goto writeback; | |
1937 | ||
1938 | cannot_emulate: | |
e4e03ded | 1939 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 1940 | c->eip = saved_eip; |
6aa8b732 AK |
1941 | return -1; |
1942 | } |