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KVM: x86 emulator: Add std and cld instructions (opcodes 0xfc-0xfd)
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
50#define DstMask (3<<1)
51/* Source operand type. */
52#define SrcNone (0<<3) /* No source operand. */
53#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
54#define SrcReg (1<<3) /* Register operand. */
55#define SrcMem (2<<3) /* Memory operand. */
56#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
58#define SrcImm (5<<3) /* Immediate operand. */
59#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
60#define SrcMask (7<<3)
61/* Generic ModRM decode. */
62#define ModRM (1<<6)
63/* Destination is only written; never read. */
64#define Mov (1<<7)
038e51de 65#define BitOp (1<<8)
c7e75a3d 66#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 67#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 68#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 69#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
70#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
71#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 72
43bb19cd 73enum {
1d6ad207 74 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 75 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 76};
77
c7e75a3d 78static u16 opcode_table[256] = {
6aa8b732
AK		 79 /* 0x00 - 0x07 */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x08 - 0x0F */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 0, 0, 0, 0,
87 /* 0x10 - 0x17 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x18 - 0x1F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x20 - 0x27 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 98 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 99 /* 0x28 - 0x2F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x30 - 0x37 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 0, 0, 0, 0,
107 /* 0x38 - 0x3F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
d77a2507 111 /* 0x40 - 0x47 */
33615aa9 112 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 113 /* 0x48 - 0x4F */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 115 /* 0x50 - 0x57 */
6e3d5dfb
AK		 116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 118 /* 0x58 - 0x5F */
6e3d5dfb
AK		 119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 121 /* 0x60 - 0x67 */
6aa8b732 122 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 123 0, 0, 0, 0,
124 /* 0x68 - 0x6F */
91ed7a0e 125 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
127 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 128 /* 0x70 - 0x77 */
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 /* 0x78 - 0x7F */
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 134 /* 0x80 - 0x87 */
1d6ad207
AK		 135 Group | Group1_80, Group | Group1_81,
136 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
139 /* 0x88 - 0x8F */
140 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
141 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 142 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 143 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 144 /* 0x90 - 0x97 */
145 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
146 /* 0x98 - 0x9F */
6e3d5dfb 147 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 148 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 149 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
150 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 151 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 153 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 154 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
156 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 157 /* 0xB0 - 0xB7 */
158 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
159 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 /* 0xB8 - 0xBF */
163 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
164 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 167 /* 0xC0 - 0xC7 */
d9413cd7 168 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 169 0, ImplicitOps | Stack, 0, 0,
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 171 /* 0xC8 - 0xCF */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xD0 - 0xD7 */
174 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
175 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
176 0, 0, 0, 0,
177 /* 0xD8 - 0xDF */
178 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 179 /* 0xE0 - 0xE7 */
180 0, 0, 0, 0, 0, 0, 0, 0,
181 /* 0xE8 - 0xEF */
954cd36f
GT		 182 ImplicitOps | Stack, SrcImm | ImplicitOps,
183 ImplicitOps, SrcImmByte | ImplicitOps,
6e3d5dfb 184 0, 0, 0, 0,
6aa8b732
AK		 185 /* 0xF0 - 0xF7 */
186 0, 0, 0, 0,
7d858a19 187 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 188 /* 0xF8 - 0xFF */
b284be57 189 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 190 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 191};
192
038e51de 193static u16 twobyte_table[256] = {
6aa8b732 194 /* 0x00 - 0x0F */
d95058a1 195 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 196 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 197 /* 0x10 - 0x1F */
198 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
199 /* 0x20 - 0x2F */
200 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
201 0, 0, 0, 0, 0, 0, 0, 0,
202 /* 0x30 - 0x3F */
35f3f286 203 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 204 /* 0x40 - 0x47 */
205 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
206 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
207 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
208 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
209 /* 0x48 - 0x4F */
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 /* 0x50 - 0x5F */
215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x60 - 0x6F */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
218 /* 0x70 - 0x7F */
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
220 /* 0x80 - 0x8F */
bbe9abbd
NK		 221 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
222 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
223 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
224 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 225 /* 0x90 - 0x9F */
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
227 /* 0xA0 - 0xA7 */
038e51de 228 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 229 /* 0xA8 - 0xAF */
2a7c5b8b 230 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 231 /* 0xB0 - 0xB7 */
232 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 233 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 234 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem16 | ModRM | Mov,
236 /* 0xB8 - 0xBF */
038e51de 237 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 238 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
239 DstReg | SrcMem16 | ModRM | Mov,
240 /* 0xC0 - 0xCF */
a012e65a
SY		 241 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
242 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 243 /* 0xD0 - 0xDF */
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
245 /* 0xE0 - 0xEF */
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
247 /* 0xF0 - 0xFF */
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
249};
250
e09d082c 251static u16 group_table[] = {
1d6ad207
AK		 252 [Group1_80*8] =
253 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
255 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 [Group1_81*8] =
258 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
259 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
260 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
261 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
262 [Group1_82*8] =
263 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
264 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
265 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
266 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
267 [Group1_83*8] =
268 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
269 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
270 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
271 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 272 [Group1A*8] =
273 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 274 [Group3_Byte*8] =
275 ByteOp | SrcImm | DstMem | ModRM, 0,
276 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
277 0, 0, 0, 0,
278 [Group3*8] =
41afa025 279 DstMem | SrcImm | ModRM, 0,
6eb06cb2 280 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 281 0, 0, 0, 0,
fd60754e
AK		 282 [Group4*8] =
283 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
284 0, 0, 0, 0, 0, 0,
285 [Group5*8] =
286 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
287 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 288 [Group7*8] =
289 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 290 SrcNone | ModRM | DstMem | Mov, 0,
291 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 292};
293
294static u16 group2_table[] = {
d95058a1 295 [Group7*8] =
16286d08
AK		 296 SrcNone | ModRM, 0, 0, 0,
297 SrcNone | ModRM | DstMem | Mov, 0,
298 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 299};
300
6aa8b732
AK		 301/* EFLAGS bit definitions. */
302#define EFLG_OF (1<<11)
303#define EFLG_DF (1<<10)
304#define EFLG_SF (1<<7)
305#define EFLG_ZF (1<<6)
306#define EFLG_AF (1<<4)
307#define EFLG_PF (1<<2)
308#define EFLG_CF (1<<0)
309
310/*
311 * Instruction emulation:
312 * Most instructions are emulated directly via a fragment of inline assembly
313 * code. This allows us to save/restore EFLAGS and thus very easily pick up
314 * any modified flags.
315 */
316
05b3e0c2 317#if defined(CONFIG_X86_64)
6aa8b732
AK		 318#define _LO32 "k" /* force 32-bit operand */
319#define _STK "%%rsp" /* stack pointer */
320#elif defined(__i386__)
321#define _LO32 "" /* force 32-bit operand */
322#define _STK "%%esp" /* stack pointer */
323#endif
324
325/*
326 * These EFLAGS bits are restored from saved value during emulation, and
327 * any changes are written back to the saved value after emulation.
328 */
329#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
330
331/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 332#define _PRE_EFLAGS(_sav, _msk, _tmp) \
333 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
334 "movl %"_sav",%"_LO32 _tmp"; " \
335 "push %"_tmp"; " \
336 "push %"_tmp"; " \
337 "movl %"_msk",%"_LO32 _tmp"; " \
338 "andl %"_LO32 _tmp",("_STK"); " \
339 "pushf; " \
340 "notl %"_LO32 _tmp"; " \
341 "andl %"_LO32 _tmp",("_STK"); " \
342 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
343 "pop %"_tmp"; " \
344 "orl %"_LO32 _tmp",("_STK"); " \
345 "popf; " \
346 "pop %"_sav"; "
6aa8b732
AK		 347
348/* After executing instruction: write-back necessary bits in EFLAGS. */
349#define _POST_EFLAGS(_sav, _msk, _tmp) \
350 /* _sav |= EFLAGS & _msk; */ \
351 "pushf; " \
352 "pop %"_tmp"; " \
353 "andl %"_msk",%"_LO32 _tmp"; " \
354 "orl %"_LO32 _tmp",%"_sav"; "
355
356/* Raw emulation: instruction has two explicit operands. */
357#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
358 do { \
359 unsigned long _tmp; \
360 \
361 switch ((_dst).bytes) { \
362 case 2: \
363 __asm__ __volatile__ ( \
d77c26fc 364 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 365 _op"w %"_wx"3,%1; " \
d77c26fc 366 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 367 : "=m" (_eflags), "=m" ((_dst).val), \
368 "=&r" (_tmp) \
d77c26fc 369 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 370 break; \
371 case 4: \
372 __asm__ __volatile__ ( \
d77c26fc 373 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 374 _op"l %"_lx"3,%1; " \
d77c26fc 375 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 376 : "=m" (_eflags), "=m" ((_dst).val), \
377 "=&r" (_tmp) \
d77c26fc 378 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 379 break; \
380 case 8: \
381 __emulate_2op_8byte(_op, _src, _dst, \
382 _eflags, _qx, _qy); \
383 break; \
384 } \
385 } while (0)
386
387#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
388 do { \
77cd337f 389 unsigned long __tmp; \
d77c26fc 390 switch ((_dst).bytes) { \
6aa8b732
AK		 391 case 1: \
392 __asm__ __volatile__ ( \
d77c26fc 393 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 394 _op"b %"_bx"3,%1; " \
d77c26fc 395 _POST_EFLAGS("0", "4", "2") \
6aa8b732 396 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 397 "=&r" (__tmp) \
d77c26fc 398 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 399 break; \
400 default: \
401 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
402 _wx, _wy, _lx, _ly, _qx, _qy); \
403 break; \
404 } \
405 } while (0)
406
407/* Source operand is byte-sized and may be restricted to just %cl. */
408#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
409 __emulate_2op(_op, _src, _dst, _eflags, \
410 "b", "c", "b", "c", "b", "c", "b", "c")
411
412/* Source operand is byte, word, long or quad sized. */
413#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
414 __emulate_2op(_op, _src, _dst, _eflags, \
415 "b", "q", "w", "r", _LO32, "r", "", "r")
416
417/* Source operand is word, long or quad sized. */
418#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
419 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
420 "w", "r", _LO32, "r", "", "r")
421
422/* Instruction has only one explicit operand (no source operand). */
423#define emulate_1op(_op, _dst, _eflags) \
424 do { \
425 unsigned long _tmp; \
426 \
d77c26fc 427 switch ((_dst).bytes) { \
6aa8b732
AK		 428 case 1: \
429 __asm__ __volatile__ ( \
d77c26fc 430 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 431 _op"b %1; " \
d77c26fc 432 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 433 : "=m" (_eflags), "=m" ((_dst).val), \
434 "=&r" (_tmp) \
d77c26fc 435 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 436 break; \
437 case 2: \
438 __asm__ __volatile__ ( \
d77c26fc 439 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 440 _op"w %1; " \
d77c26fc 441 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 442 : "=m" (_eflags), "=m" ((_dst).val), \
443 "=&r" (_tmp) \
d77c26fc 444 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 445 break; \
446 case 4: \
447 __asm__ __volatile__ ( \
d77c26fc 448 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 449 _op"l %1; " \
d77c26fc 450 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 451 : "=m" (_eflags), "=m" ((_dst).val), \
452 "=&r" (_tmp) \
d77c26fc 453 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 454 break; \
455 case 8: \
456 __emulate_1op_8byte(_op, _dst, _eflags); \
457 break; \
458 } \
459 } while (0)
460
461/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 462#if defined(CONFIG_X86_64)
6aa8b732
AK		 463#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
464 do { \
465 __asm__ __volatile__ ( \
d77c26fc 466 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 467 _op"q %"_qx"3,%1; " \
d77c26fc 468 _POST_EFLAGS("0", "4", "2") \
6aa8b732 469 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 470 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 471 } while (0)
472
473#define __emulate_1op_8byte(_op, _dst, _eflags) \
474 do { \
475 __asm__ __volatile__ ( \
d77c26fc 476 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 477 _op"q %1; " \
d77c26fc 478 _POST_EFLAGS("0", "3", "2") \
6aa8b732 479 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 480 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 481 } while (0)
482
483#elif defined(__i386__)
484#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
485#define __emulate_1op_8byte(_op, _dst, _eflags)
486#endif /* __i386__ */
487
488/* Fetch next part of the instruction being emulated. */
489#define insn_fetch(_type, _size, _eip) \
490({ unsigned long _x; \
62266869 491 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 492 if (rc != 0) \
6aa8b732
AK		 493 goto done; \
494 (_eip) += (_size); \
495 (_type)_x; \
496})
497
ddcb2885
HH		 498static inline unsigned long ad_mask(struct decode_cache *c)
499{
500 return (1UL << (c->ad_bytes << 3)) - 1;
501}
502
6aa8b732 503/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 504static inline unsigned long
505address_mask(struct decode_cache *c, unsigned long reg)
506{
507 if (c->ad_bytes == sizeof(unsigned long))
508 return reg;
509 else
510 return reg & ad_mask(c);
511}
512
513static inline unsigned long
514register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
515{
516 return base + address_mask(c, reg);
517}
518
7a957275
HH		 519static inline void
520register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
521{
522 if (c->ad_bytes == sizeof(unsigned long))
523 *reg += inc;
524 else
525 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
526}
6aa8b732 527
7a957275
HH		 528static inline void jmp_rel(struct decode_cache *c, int rel)
529{
530 register_address_increment(c, &c->eip, rel);
531}
098c937b 532
7a5b56df
AK		 533static void set_seg_override(struct decode_cache *c, int seg)
534{
535 c->has_seg_override = true;
536 c->seg_override = seg;
537}
538
539static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
540{
541 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
542 return 0;
543
544 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
545}
546
547static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
548 struct decode_cache *c)
549{
550 if (!c->has_seg_override)
551 return 0;
552
553 return seg_base(ctxt, c->seg_override);
554}
555
556static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
557{
558 return seg_base(ctxt, VCPU_SREG_ES);
559}
560
561static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
562{
563 return seg_base(ctxt, VCPU_SREG_SS);
564}
565
62266869
AK		 566static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
567 struct x86_emulate_ops *ops,
568 unsigned long linear, u8 *dest)
569{
570 struct fetch_cache *fc = &ctxt->decode.fetch;
571 int rc;
572 int size;
573
574 if (linear < fc->start || linear >= fc->end) {
575 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
576 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
577 if (rc)
578 return rc;
579 fc->start = linear;
580 fc->end = linear + size;
581 }
582 *dest = fc->data[linear - fc->start];
583 return 0;
584}
585
586static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
587 struct x86_emulate_ops *ops,
588 unsigned long eip, void *dest, unsigned size)
589{
590 int rc = 0;
591
592 eip += ctxt->cs_base;
593 while (size--) {
594 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
595 if (rc)
596 return rc;
597 }
598 return 0;
599}
600
1e3c5cb0
RR		 601/*
602 * Given the 'reg' portion of a ModRM byte, and a register block, return a
603 * pointer into the block that addresses the relevant register.
604 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
605 */
606static void *decode_register(u8 modrm_reg, unsigned long *regs,
607 int highbyte_regs)
6aa8b732
AK		 608{
609 void *p;
610
611 p = &regs[modrm_reg];
612 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
613 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
614 return p;
615}
616
617static int read_descriptor(struct x86_emulate_ctxt *ctxt,
618 struct x86_emulate_ops *ops,
619 void *ptr,
620 u16 *size, unsigned long *address, int op_bytes)
621{
622 int rc;
623
624 if (op_bytes == 2)
625 op_bytes = 3;
626 *address = 0;
cebff02b
LV		 627 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
628 ctxt->vcpu);
6aa8b732
AK		 629 if (rc)
630 return rc;
cebff02b
LV		 631 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
632 ctxt->vcpu);
6aa8b732
AK		 633 return rc;
634}
635
bbe9abbd
NK		 636static int test_cc(unsigned int condition, unsigned int flags)
637{
638 int rc = 0;
639
640 switch ((condition & 15) >> 1) {
641 case 0: /* o */
642 rc |= (flags & EFLG_OF);
643 break;
644 case 1: /* b/c/nae */
645 rc |= (flags & EFLG_CF);
646 break;
647 case 2: /* z/e */
648 rc |= (flags & EFLG_ZF);
649 break;
650 case 3: /* be/na */
651 rc |= (flags & (EFLG_CF|EFLG_ZF));
652 break;
653 case 4: /* s */
654 rc |= (flags & EFLG_SF);
655 break;
656 case 5: /* p/pe */
657 rc |= (flags & EFLG_PF);
658 break;
659 case 7: /* le/ng */
660 rc |= (flags & EFLG_ZF);
661 /* fall through */
662 case 6: /* l/nge */
663 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
664 break;
665 }
666
667 /* Odd condition identifiers (lsb == 1) have inverted sense. */
668 return (!!rc ^ (condition & 1));
669}
670
3c118e24
AK		 671static void decode_register_operand(struct operand *op,
672 struct decode_cache *c,
3c118e24
AK		 673 int inhibit_bytereg)
674{
33615aa9 675 unsigned reg = c->modrm_reg;
9f1ef3f8 676 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 677
678 if (!(c->d & ModRM))
679 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 680 op->type = OP_REG;
681 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 682 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 683 op->val = *(u8 *)op->ptr;
684 op->bytes = 1;
685 } else {
33615aa9 686 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 687 op->bytes = c->op_bytes;
688 switch (op->bytes) {
689 case 2:
690 op->val = *(u16 *)op->ptr;
691 break;
692 case 4:
693 op->val = *(u32 *)op->ptr;
694 break;
695 case 8:
696 op->val = *(u64 *) op->ptr;
697 break;
698 }
699 }
700 op->orig_val = op->val;
701}
702
1c73ef66
AK		 703static int decode_modrm(struct x86_emulate_ctxt *ctxt,
704 struct x86_emulate_ops *ops)
705{
706 struct decode_cache *c = &ctxt->decode;
707 u8 sib;
f5b4edcd 708 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 709 int rc = 0;
710
711 if (c->rex_prefix) {
712 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
713 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
714 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
715 }
716
717 c->modrm = insn_fetch(u8, 1, c->eip);
718 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
719 c->modrm_reg |= (c->modrm & 0x38) >> 3;
720 c->modrm_rm |= (c->modrm & 0x07);
721 c->modrm_ea = 0;
722 c->use_modrm_ea = 1;
723
724 if (c->modrm_mod == 3) {
107d6d2e
AK		 725 c->modrm_ptr = decode_register(c->modrm_rm,
726 c->regs, c->d & ByteOp);
727 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 728 return rc;
729 }
730
731 if (c->ad_bytes == 2) {
732 unsigned bx = c->regs[VCPU_REGS_RBX];
733 unsigned bp = c->regs[VCPU_REGS_RBP];
734 unsigned si = c->regs[VCPU_REGS_RSI];
735 unsigned di = c->regs[VCPU_REGS_RDI];
736
737 /* 16-bit ModR/M decode. */
738 switch (c->modrm_mod) {
739 case 0:
740 if (c->modrm_rm == 6)
741 c->modrm_ea += insn_fetch(u16, 2, c->eip);
742 break;
743 case 1:
744 c->modrm_ea += insn_fetch(s8, 1, c->eip);
745 break;
746 case 2:
747 c->modrm_ea += insn_fetch(u16, 2, c->eip);
748 break;
749 }
750 switch (c->modrm_rm) {
751 case 0:
752 c->modrm_ea += bx + si;
753 break;
754 case 1:
755 c->modrm_ea += bx + di;
756 break;
757 case 2:
758 c->modrm_ea += bp + si;
759 break;
760 case 3:
761 c->modrm_ea += bp + di;
762 break;
763 case 4:
764 c->modrm_ea += si;
765 break;
766 case 5:
767 c->modrm_ea += di;
768 break;
769 case 6:
770 if (c->modrm_mod != 0)
771 c->modrm_ea += bp;
772 break;
773 case 7:
774 c->modrm_ea += bx;
775 break;
776 }
777 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
778 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 779 if (!c->has_seg_override)
780 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 781 c->modrm_ea = (u16)c->modrm_ea;
782 } else {
783 /* 32/64-bit ModR/M decode. */
84411d85 784 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 785 sib = insn_fetch(u8, 1, c->eip);
786 index_reg |= (sib >> 3) & 7;
787 base_reg |= sib & 7;
788 scale = sib >> 6;
789
dc71d0f1
AK		 790 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
791 c->modrm_ea += insn_fetch(s32, 4, c->eip);
792 else
1c73ef66 793 c->modrm_ea += c->regs[base_reg];
dc71d0f1 794 if (index_reg != 4)
1c73ef66 795 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 796 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
797 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 798 c->rip_relative = 1;
84411d85 799 } else
1c73ef66 800 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 801 switch (c->modrm_mod) {
802 case 0:
803 if (c->modrm_rm == 5)
804 c->modrm_ea += insn_fetch(s32, 4, c->eip);
805 break;
806 case 1:
807 c->modrm_ea += insn_fetch(s8, 1, c->eip);
808 break;
809 case 2:
810 c->modrm_ea += insn_fetch(s32, 4, c->eip);
811 break;
812 }
813 }
1c73ef66
AK		 814done:
815 return rc;
816}
817
818static int decode_abs(struct x86_emulate_ctxt *ctxt,
819 struct x86_emulate_ops *ops)
820{
821 struct decode_cache *c = &ctxt->decode;
822 int rc = 0;
823
824 switch (c->ad_bytes) {
825 case 2:
826 c->modrm_ea = insn_fetch(u16, 2, c->eip);
827 break;
828 case 4:
829 c->modrm_ea = insn_fetch(u32, 4, c->eip);
830 break;
831 case 8:
832 c->modrm_ea = insn_fetch(u64, 8, c->eip);
833 break;
834 }
835done:
836 return rc;
837}
838
6aa8b732 839int
8b4caf66 840x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 841{
e4e03ded 842 struct decode_cache *c = &ctxt->decode;
6aa8b732 843 int rc = 0;
6aa8b732 844 int mode = ctxt->mode;
e09d082c 845 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 846
847 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 848
e4e03ded 849 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 850 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 851 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 852 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 853
854 switch (mode) {
855 case X86EMUL_MODE_REAL:
856 case X86EMUL_MODE_PROT16:
f21b8bf4 857 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 858 break;
859 case X86EMUL_MODE_PROT32:
f21b8bf4 860 def_op_bytes = def_ad_bytes = 4;
6aa8b732 861 break;
05b3e0c2 862#ifdef CONFIG_X86_64
6aa8b732 863 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 864 def_op_bytes = 4;
865 def_ad_bytes = 8;
6aa8b732
AK		 866 break;
867#endif
868 default:
869 return -1;
870 }
871
f21b8bf4
AK		 872 c->op_bytes = def_op_bytes;
873 c->ad_bytes = def_ad_bytes;
874
6aa8b732 875 /* Legacy prefixes. */
b4c6abfe 876 for (;;) {
e4e03ded 877 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 878 case 0x66: /* operand-size override */
f21b8bf4
AK		 879 /* switch between 2/4 bytes */
880 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 881 break;
882 case 0x67: /* address-size override */
883 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 884 /* switch between 4/8 bytes */
f21b8bf4 885 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 886 else
e4e03ded 887 /* switch between 2/4 bytes */
f21b8bf4 888 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 889 break;
7a5b56df 890 case 0x26: /* ES override */
6aa8b732 891 case 0x2e: /* CS override */
7a5b56df 892 case 0x36: /* SS override */
6aa8b732 893 case 0x3e: /* DS override */
7a5b56df 894 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 895 break;
896 case 0x64: /* FS override */
6aa8b732 897 case 0x65: /* GS override */
7a5b56df 898 set_seg_override(c, c->b & 7);
6aa8b732 899 break;
b4c6abfe
LV		 900 case 0x40 ... 0x4f: /* REX */
901 if (mode != X86EMUL_MODE_PROT64)
902 goto done_prefixes;
33615aa9 903 c->rex_prefix = c->b;
b4c6abfe 904 continue;
6aa8b732 905 case 0xf0: /* LOCK */
e4e03ded 906 c->lock_prefix = 1;
6aa8b732 907 break;
ae6200ba 908 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 909 c->rep_prefix = REPNE_PREFIX;
910 break;
6aa8b732 911 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 912 c->rep_prefix = REPE_PREFIX;
6aa8b732 913 break;
6aa8b732
AK		 914 default:
915 goto done_prefixes;
916 }
b4c6abfe
LV		 917
918 /* Any legacy prefix after a REX prefix nullifies its effect. */
919
33615aa9 920 c->rex_prefix = 0;
6aa8b732
AK		 921 }
922
923done_prefixes:
924
925 /* REX prefix. */
1c73ef66 926 if (c->rex_prefix)
33615aa9 927 if (c->rex_prefix & 8)
e4e03ded 928 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 929
930 /* Opcode byte(s). */
e4e03ded
LV		 931 c->d = opcode_table[c->b];
932 if (c->d == 0) {
6aa8b732 933 /* Two-byte opcode? */
e4e03ded
LV		 934 if (c->b == 0x0f) {
935 c->twobyte = 1;
936 c->b = insn_fetch(u8, 1, c->eip);
937 c->d = twobyte_table[c->b];
6aa8b732 938 }
e09d082c 939 }
6aa8b732 940
e09d082c
AK		 941 if (c->d & Group) {
942 group = c->d & GroupMask;
943 c->modrm = insn_fetch(u8, 1, c->eip);
944 --c->eip;
945
946 group = (group << 3) + ((c->modrm >> 3) & 7);
947 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
948 c->d = group2_table[group];
949 else
950 c->d = group_table[group];
951 }
952
953 /* Unrecognised? */
954 if (c->d == 0) {
955 DPRINTF("Cannot emulate %02x\n", c->b);
956 return -1;
6aa8b732
AK		 957 }
958
6e3d5dfb
AK		 959 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
960 c->op_bytes = 8;
961
6aa8b732 962 /* ModRM and SIB bytes. */
1c73ef66
AK		 963 if (c->d & ModRM)
964 rc = decode_modrm(ctxt, ops);
965 else if (c->d & MemAbs)
966 rc = decode_abs(ctxt, ops);
967 if (rc)
968 goto done;
6aa8b732 969
7a5b56df
AK		 970 if (!c->has_seg_override)
971 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 972
7a5b56df
AK		 973 if (!(!c->twobyte && c->b == 0x8d))
974 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 975
976 if (c->ad_bytes != 8)
977 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 978 /*
979 * Decode and fetch the source operand: register, memory
980 * or immediate.
981 */
e4e03ded 982 switch (c->d & SrcMask) {
6aa8b732
AK		 983 case SrcNone:
984 break;
985 case SrcReg:
9f1ef3f8 986 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 987 break;
988 case SrcMem16:
e4e03ded 989 c->src.bytes = 2;
6aa8b732
AK		 990 goto srcmem_common;
991 case SrcMem32:
e4e03ded 992 c->src.bytes = 4;
6aa8b732
AK		 993 goto srcmem_common;
994 case SrcMem:
e4e03ded
LV		 995 c->src.bytes = (c->d & ByteOp) ? 1 :
996 c->op_bytes;
b85b9ee9 997 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 998 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 999 break;
d77c26fc 1000 srcmem_common:
4e62417b
AJ		 1001 /*
1002 * For instructions with a ModR/M byte, switch to register
1003 * access if Mod = 3.
1004 */
e4e03ded
LV		 1005 if ((c->d & ModRM) && c->modrm_mod == 3) {
1006 c->src.type = OP_REG;
66b85505 1007 c->src.val = c->modrm_val;
107d6d2e 1008 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1009 break;
1010 }
e4e03ded 1011 c->src.type = OP_MEM;
6aa8b732
AK		 1012 break;
1013 case SrcImm:
e4e03ded
LV		 1014 c->src.type = OP_IMM;
1015 c->src.ptr = (unsigned long *)c->eip;
1016 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1017 if (c->src.bytes == 8)
1018 c->src.bytes = 4;
6aa8b732 1019 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1020 switch (c->src.bytes) {
6aa8b732 1021 case 1:
e4e03ded 1022 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1023 break;
1024 case 2:
e4e03ded 1025 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1026 break;
1027 case 4:
e4e03ded 1028 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1029 break;
1030 }
1031 break;
1032 case SrcImmByte:
e4e03ded
LV		 1033 c->src.type = OP_IMM;
1034 c->src.ptr = (unsigned long *)c->eip;
1035 c->src.bytes = 1;
1036 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1037 break;
1038 }
1039
038e51de 1040 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1041 switch (c->d & DstMask) {
038e51de
AK		 1042 case ImplicitOps:
1043 /* Special instructions do their own operand decoding. */
8b4caf66 1044 return 0;
038e51de 1045 case DstReg:
9f1ef3f8 1046 decode_register_operand(&c->dst, c,
3c118e24 1047 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1048 break;
1049 case DstMem:
e4e03ded 1050 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1051 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1052 c->dst.type = OP_REG;
66b85505 1053 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1054 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1055 break;
1056 }
8b4caf66
LV		 1057 c->dst.type = OP_MEM;
1058 break;
1059 }
1060
f5b4edcd
AK		 1061 if (c->rip_relative)
1062 c->modrm_ea += c->eip;
1063
8b4caf66
LV		 1064done:
1065 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1066}
1067
8cdbd2c9
LV		 1068static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1069{
1070 struct decode_cache *c = &ctxt->decode;
1071
1072 c->dst.type = OP_MEM;
1073 c->dst.bytes = c->op_bytes;
1074 c->dst.val = c->src.val;
7a957275 1075 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1076 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1077 c->regs[VCPU_REGS_RSP]);
1078}
1079
1080static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1081 struct x86_emulate_ops *ops)
1082{
1083 struct decode_cache *c = &ctxt->decode;
1084 int rc;
1085
7a5b56df 1086 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1087 c->regs[VCPU_REGS_RSP]),
1088 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1089 if (rc != 0)
1090 return rc;
1091
7a957275 1092 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1093
1094 return 0;
1095}
1096
05f086f8 1097static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1098{
05f086f8 1099 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1100 switch (c->modrm_reg) {
1101 case 0: /* rol */
05f086f8 1102 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1103 break;
1104 case 1: /* ror */
05f086f8 1105 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1106 break;
1107 case 2: /* rcl */
05f086f8 1108 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1109 break;
1110 case 3: /* rcr */
05f086f8 1111 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1112 break;
1113 case 4: /* sal/shl */
1114 case 6: /* sal/shl */
05f086f8 1115 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1116 break;
1117 case 5: /* shr */
05f086f8 1118 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1119 break;
1120 case 7: /* sar */
05f086f8 1121 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1122 break;
1123 }
1124}
1125
1126static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1127 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1128{
1129 struct decode_cache *c = &ctxt->decode;
1130 int rc = 0;
1131
1132 switch (c->modrm_reg) {
1133 case 0 ... 1: /* test */
05f086f8 1134 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1135 break;
1136 case 2: /* not */
1137 c->dst.val = ~c->dst.val;
1138 break;
1139 case 3: /* neg */
05f086f8 1140 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1141 break;
1142 default:
1143 DPRINTF("Cannot emulate %02x\n", c->b);
1144 rc = X86EMUL_UNHANDLEABLE;
1145 break;
1146 }
8cdbd2c9
LV		 1147 return rc;
1148}
1149
1150static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1151 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1152{
1153 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1154
1155 switch (c->modrm_reg) {
1156 case 0: /* inc */
05f086f8 1157 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1158 break;
1159 case 1: /* dec */
05f086f8 1160 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1161 break;
1162 case 4: /* jmp abs */
fd60754e 1163 c->eip = c->src.val;
8cdbd2c9
LV		 1164 break;
1165 case 6: /* push */
fd60754e 1166 emulate_push(ctxt);
8cdbd2c9 1167 break;
8cdbd2c9
LV		 1168 }
1169 return 0;
1170}
1171
1172static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1173 struct x86_emulate_ops *ops,
e8d8d7fe 1174 unsigned long memop)
8cdbd2c9
LV		 1175{
1176 struct decode_cache *c = &ctxt->decode;
1177 u64 old, new;
1178 int rc;
1179
e8d8d7fe 1180 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1181 if (rc != 0)
1182 return rc;
1183
1184 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1185 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1186
1187 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1188 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1189 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1190
1191 } else {
1192 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1193 (u32) c->regs[VCPU_REGS_RBX];
1194
e8d8d7fe 1195 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1196 if (rc != 0)
1197 return rc;
05f086f8 1198 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1199 }
1200 return 0;
1201}
1202
1203static inline int writeback(struct x86_emulate_ctxt *ctxt,
1204 struct x86_emulate_ops *ops)
1205{
1206 int rc;
1207 struct decode_cache *c = &ctxt->decode;
1208
1209 switch (c->dst.type) {
1210 case OP_REG:
1211 /* The 4-byte case *is* correct:
1212 * in 64-bit mode we zero-extend.
1213 */
1214 switch (c->dst.bytes) {
1215 case 1:
1216 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1217 break;
1218 case 2:
1219 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1220 break;
1221 case 4:
1222 *c->dst.ptr = (u32)c->dst.val;
1223 break; /* 64b: zero-ext */
1224 case 8:
1225 *c->dst.ptr = c->dst.val;
1226 break;
1227 }
1228 break;
1229 case OP_MEM:
1230 if (c->lock_prefix)
1231 rc = ops->cmpxchg_emulated(
1232 (unsigned long)c->dst.ptr,
1233 &c->dst.orig_val,
1234 &c->dst.val,
1235 c->dst.bytes,
1236 ctxt->vcpu);
1237 else
1238 rc = ops->write_emulated(
1239 (unsigned long)c->dst.ptr,
1240 &c->dst.val,
1241 c->dst.bytes,
1242 ctxt->vcpu);
1243 if (rc != 0)
1244 return rc;
a01af5ec
LV		 1245 break;
1246 case OP_NONE:
1247 /* no writeback */
1248 break;
8cdbd2c9
LV		 1249 default:
1250 break;
1251 }
1252 return 0;
1253}
1254
8b4caf66 1255int
1be3aa47 1256x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1257{
e8d8d7fe 1258 unsigned long memop = 0;
8b4caf66 1259 u64 msr_data;
3427318f 1260 unsigned long saved_eip = 0;
8b4caf66 1261 struct decode_cache *c = &ctxt->decode;
1be3aa47 1262 int rc = 0;
8b4caf66 1263
3427318f
LV		 1264 /* Shadow copy of register state. Committed on successful emulation.
1265 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1266 * modify them.
1267 */
1268
ad312c7c 1269 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1270 saved_eip = c->eip;
1271
c7e75a3d 1272 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1273 memop = c->modrm_ea;
8b4caf66 1274
b9fa9d6b
AK		 1275 if (c->rep_prefix && (c->d & String)) {
1276 /* All REP prefixes have the same first termination condition */
1277 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1278 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1279 goto done;
1280 }
1281 /* The second termination condition only applies for REPE
1282 * and REPNE. Test if the repeat string operation prefix is
1283 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1284 * corresponding termination condition according to:
1285 * - if REPE/REPZ and ZF = 0 then done
1286 * - if REPNE/REPNZ and ZF = 1 then done
1287 */
1288 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1289 (c->b == 0xae) || (c->b == 0xaf)) {
1290 if ((c->rep_prefix == REPE_PREFIX) &&
1291 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1292 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1293 goto done;
1294 }
1295 if ((c->rep_prefix == REPNE_PREFIX) &&
1296 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1297 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1298 goto done;
1299 }
1300 }
1301 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1302 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1303 }
1304
8b4caf66 1305 if (c->src.type == OP_MEM) {
e8d8d7fe 1306 c->src.ptr = (unsigned long *)memop;
8b4caf66 1307 c->src.val = 0;
d77c26fc
MD		 1308 rc = ops->read_emulated((unsigned long)c->src.ptr,
1309 &c->src.val,
1310 c->src.bytes,
1311 ctxt->vcpu);
1312 if (rc != 0)
8b4caf66
LV		 1313 goto done;
1314 c->src.orig_val = c->src.val;
1315 }
1316
1317 if ((c->d & DstMask) == ImplicitOps)
1318 goto special_insn;
1319
1320
1321 if (c->dst.type == OP_MEM) {
e8d8d7fe 1322 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1323 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1324 c->dst.val = 0;
e4e03ded
LV		 1325 if (c->d & BitOp) {
1326 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1327
e4e03ded
LV		 1328 c->dst.ptr = (void *)c->dst.ptr +
1329 (c->src.val & mask) / 8;
038e51de 1330 }
e4e03ded
LV		 1331 if (!(c->d & Mov) &&
1332 /* optimisation - avoid slow emulated read */
1333 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1334 &c->dst.val,
1335 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1336 goto done;
038e51de 1337 }
e4e03ded 1338 c->dst.orig_val = c->dst.val;
038e51de 1339
018a98db
AK		 1340special_insn:
1341
e4e03ded 1342 if (c->twobyte)
6aa8b732
AK		 1343 goto twobyte_insn;
1344
e4e03ded 1345 switch (c->b) {
6aa8b732
AK		 1346 case 0x00 ... 0x05:
1347 add: /* add */
05f086f8 1348 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1349 break;
1350 case 0x08 ... 0x0d:
1351 or: /* or */
05f086f8 1352 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1353 break;
1354 case 0x10 ... 0x15:
1355 adc: /* adc */
05f086f8 1356 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1357 break;
1358 case 0x18 ... 0x1d:
1359 sbb: /* sbb */
05f086f8 1360 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1361 break;
19eb938e 1362 case 0x20 ... 0x23:
6aa8b732 1363 and: /* and */
05f086f8 1364 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1365 break;
19eb938e 1366 case 0x24: /* and al imm8 */
e4e03ded
LV		 1367 c->dst.type = OP_REG;
1368 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1369 c->dst.val = *(u8 *)c->dst.ptr;
1370 c->dst.bytes = 1;
1371 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1372 goto and;
1373 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1374 c->dst.type = OP_REG;
1375 c->dst.bytes = c->op_bytes;
1376 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1377 if (c->op_bytes == 2)
1378 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1379 else
e4e03ded
LV		 1380 c->dst.val = *(u32 *)c->dst.ptr;
1381 c->dst.orig_val = c->dst.val;
19eb938e 1382 goto and;
6aa8b732
AK		 1383 case 0x28 ... 0x2d:
1384 sub: /* sub */
05f086f8 1385 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1386 break;
1387 case 0x30 ... 0x35:
1388 xor: /* xor */
05f086f8 1389 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1390 break;
1391 case 0x38 ... 0x3d:
1392 cmp: /* cmp */
05f086f8 1393 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1394 break;
33615aa9
AK		 1395 case 0x40 ... 0x47: /* inc r16/r32 */
1396 emulate_1op("inc", c->dst, ctxt->eflags);
1397 break;
1398 case 0x48 ... 0x4f: /* dec r16/r32 */
1399 emulate_1op("dec", c->dst, ctxt->eflags);
1400 break;
1401 case 0x50 ... 0x57: /* push reg */
1402 c->dst.type = OP_MEM;
1403 c->dst.bytes = c->op_bytes;
1404 c->dst.val = c->src.val;
7a957275 1405 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1406 -c->op_bytes);
1407 c->dst.ptr = (void *) register_address(
7a5b56df 1408 c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1409 break;
1410 case 0x58 ... 0x5f: /* pop reg */
1411 pop_instruction:
7a5b56df 1412 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1413 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1414 c->op_bytes, ctxt->vcpu)) != 0)
1415 goto done;
1416
7a957275 1417 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1418 c->op_bytes);
1419 c->dst.type = OP_NONE; /* Disable writeback. */
1420 break;
6aa8b732 1421 case 0x63: /* movsxd */
8b4caf66 1422 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1423 goto cannot_emulate;
e4e03ded 1424 c->dst.val = (s32) c->src.val;
6aa8b732 1425 break;
91ed7a0e 1426 case 0x68: /* push imm */
018a98db 1427 case 0x6a: /* push imm8 */
018a98db
AK		 1428 emulate_push(ctxt);
1429 break;
1430 case 0x6c: /* insb */
1431 case 0x6d: /* insw/insd */
1432 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1433 1,
1434 (c->d & ByteOp) ? 1 : c->op_bytes,
1435 c->rep_prefix ?
e4706772 1436 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1437 (ctxt->eflags & EFLG_DF),
7a5b56df 1438 register_address(c, es_base(ctxt),
018a98db
AK		 1439 c->regs[VCPU_REGS_RDI]),
1440 c->rep_prefix,
1441 c->regs[VCPU_REGS_RDX]) == 0) {
1442 c->eip = saved_eip;
1443 return -1;
1444 }
1445 return 0;
1446 case 0x6e: /* outsb */
1447 case 0x6f: /* outsw/outsd */
1448 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1449 0,
1450 (c->d & ByteOp) ? 1 : c->op_bytes,
1451 c->rep_prefix ?
e4706772 1452 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1453 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1454 register_address(c,
1455 seg_override_base(ctxt, c),
018a98db
AK		 1456 c->regs[VCPU_REGS_RSI]),
1457 c->rep_prefix,
1458 c->regs[VCPU_REGS_RDX]) == 0) {
1459 c->eip = saved_eip;
1460 return -1;
1461 }
1462 return 0;
1463 case 0x70 ... 0x7f: /* jcc (short) */ {
1464 int rel = insn_fetch(s8, 1, c->eip);
1465
1466 if (test_cc(c->b, ctxt->eflags))
7a957275 1467 jmp_rel(c, rel);
018a98db
AK		 1468 break;
1469 }
6aa8b732 1470 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1471 switch (c->modrm_reg) {
6aa8b732
AK		 1472 case 0:
1473 goto add;
1474 case 1:
1475 goto or;
1476 case 2:
1477 goto adc;
1478 case 3:
1479 goto sbb;
1480 case 4:
1481 goto and;
1482 case 5:
1483 goto sub;
1484 case 6:
1485 goto xor;
1486 case 7:
1487 goto cmp;
1488 }
1489 break;
1490 case 0x84 ... 0x85:
05f086f8 1491 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1492 break;
1493 case 0x86 ... 0x87: /* xchg */
b13354f8 1494 xchg:
6aa8b732 1495 /* Write back the register source. */
e4e03ded 1496 switch (c->dst.bytes) {
6aa8b732 1497 case 1:
e4e03ded 1498 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1499 break;
1500 case 2:
e4e03ded 1501 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1502 break;
1503 case 4:
e4e03ded 1504 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1505 break; /* 64b reg: zero-extend */
1506 case 8:
e4e03ded 1507 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1508 break;
1509 }
1510 /*
1511 * Write back the memory destination with implicit LOCK
1512 * prefix.
1513 */
e4e03ded
LV		 1514 c->dst.val = c->src.val;
1515 c->lock_prefix = 1;
6aa8b732 1516 break;
6aa8b732 1517 case 0x88 ... 0x8b: /* mov */
7de75248 1518 goto mov;
38d5bc6d
GT		 1519 case 0x8c: { /* mov r/m, sreg */
1520 struct kvm_segment segreg;
1521
1522 if (c->modrm_reg <= 5)
1523 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1524 else {
1525 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1526 c->modrm);
1527 goto cannot_emulate;
1528 }
1529 c->dst.val = segreg.selector;
1530 break;
1531 }
7e0b54b1 1532 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1533 c->dst.val = c->modrm_ea;
7e0b54b1 1534 break;
4257198a
GT		 1535 case 0x8e: { /* mov seg, r/m16 */
1536 uint16_t sel;
1537 int type_bits;
1538 int err;
1539
1540 sel = c->src.val;
1541 if (c->modrm_reg <= 5) {
1542 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1543 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1544 type_bits, c->modrm_reg);
1545 } else {
1546 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1547 c->modrm);
1548 goto cannot_emulate;
1549 }
1550
1551 if (err < 0)
1552 goto cannot_emulate;
1553
1554 c->dst.type = OP_NONE; /* Disable writeback. */
1555 break;
1556 }
6aa8b732 1557 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1558 rc = emulate_grp1a(ctxt, ops);
1559 if (rc != 0)
6aa8b732 1560 goto done;
6aa8b732 1561 break;
b13354f8
MG		 1562 case 0x90: /* nop / xchg r8,rax */
1563 if (!(c->rex_prefix & 1)) { /* nop */
1564 c->dst.type = OP_NONE;
1565 break;
1566 }
1567 case 0x91 ... 0x97: /* xchg reg,rax */
1568 c->src.type = c->dst.type = OP_REG;
1569 c->src.bytes = c->dst.bytes = c->op_bytes;
1570 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1571 c->src.val = *(c->src.ptr);
1572 goto xchg;
fd2a7608 1573 case 0x9c: /* pushf */
05f086f8 1574 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1575 emulate_push(ctxt);
1576 break;
535eabcf 1577 case 0x9d: /* popf */
05f086f8 1578 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1579 goto pop_instruction;
018a98db
AK		 1580 case 0xa0 ... 0xa1: /* mov */
1581 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1582 c->dst.val = c->src.val;
1583 break;
1584 case 0xa2 ... 0xa3: /* mov */
1585 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1586 break;
6aa8b732 1587 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1588 c->dst.type = OP_MEM;
1589 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1590 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1591 es_base(ctxt),
e4e03ded 1592 c->regs[VCPU_REGS_RDI]);
e4706772 1593 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1594 seg_override_base(ctxt, c),
e4e03ded
LV		 1595 c->regs[VCPU_REGS_RSI]),
1596 &c->dst.val,
1597 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1598 goto done;
7a957275 1599 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1600 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1601 : c->dst.bytes);
7a957275 1602 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1603 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1604 : c->dst.bytes);
6aa8b732
AK		 1605 break;
1606 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1607 c->src.type = OP_NONE; /* Disable writeback. */
1608 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1609 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1610 seg_override_base(ctxt, c),
d7e5117a
GT		 1611 c->regs[VCPU_REGS_RSI]);
1612 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1613 &c->src.val,
1614 c->src.bytes,
1615 ctxt->vcpu)) != 0)
1616 goto done;
1617
1618 c->dst.type = OP_NONE; /* Disable writeback. */
1619 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1620 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1621 es_base(ctxt),
d7e5117a
GT		 1622 c->regs[VCPU_REGS_RDI]);
1623 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1624 &c->dst.val,
1625 c->dst.bytes,
1626 ctxt->vcpu)) != 0)
1627 goto done;
1628
1629 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1630
1631 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1632
7a957275 1633 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1634 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1635 : c->src.bytes);
7a957275 1636 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1637 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1638 : c->dst.bytes);
1639
1640 break;
6aa8b732 1641 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1642 c->dst.type = OP_MEM;
1643 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1644 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1645 es_base(ctxt),
a7e6c88a 1646 c->regs[VCPU_REGS_RDI]);
e4e03ded 1647 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1648 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1649 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1650 : c->dst.bytes);
6aa8b732
AK		 1651 break;
1652 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1653 c->dst.type = OP_REG;
1654 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1655 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1656 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1657 seg_override_base(ctxt, c),
a7e6c88a
SY		 1658 c->regs[VCPU_REGS_RSI]),
1659 &c->dst.val,
1660 c->dst.bytes,
1661 ctxt->vcpu)) != 0)
6aa8b732 1662 goto done;
7a957275 1663 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1664 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1665 : c->dst.bytes);
6aa8b732
AK		 1666 break;
1667 case 0xae ... 0xaf: /* scas */
1668 DPRINTF("Urk! I don't handle SCAS.\n");
1669 goto cannot_emulate;
a5e2e82b 1670 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1671 goto mov;
018a98db
AK		 1672 case 0xc0 ... 0xc1:
1673 emulate_grp2(ctxt);
1674 break;
111de5d6
AK		 1675 case 0xc3: /* ret */
1676 c->dst.ptr = &c->eip;
1677 goto pop_instruction;
018a98db
AK		 1678 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1679 mov:
1680 c->dst.val = c->src.val;
1681 break;
1682 case 0xd0 ... 0xd1: /* Grp2 */
1683 c->src.val = 1;
1684 emulate_grp2(ctxt);
1685 break;
1686 case 0xd2 ... 0xd3: /* Grp2 */
1687 c->src.val = c->regs[VCPU_REGS_RCX];
1688 emulate_grp2(ctxt);
1689 break;
1a52e051
NK		 1690 case 0xe8: /* call (near) */ {
1691 long int rel;
e4e03ded 1692 switch (c->op_bytes) {
1a52e051 1693 case 2:
e4e03ded 1694 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1695 break;
1696 case 4:
e4e03ded 1697 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1698 break;
1a52e051
NK		 1699 default:
1700 DPRINTF("Call: Invalid op_bytes\n");
1701 goto cannot_emulate;
1702 }
e4e03ded 1703 c->src.val = (unsigned long) c->eip;
7a957275 1704 jmp_rel(c, rel);
e4e03ded 1705 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1706 emulate_push(ctxt);
1707 break;
1a52e051
NK		 1708 }
1709 case 0xe9: /* jmp rel */
954cd36f
GT		 1710 goto jmp;
1711 case 0xea: /* jmp far */ {
1712 uint32_t eip;
1713 uint16_t sel;
1714
1715 switch (c->op_bytes) {
1716 case 2:
1717 eip = insn_fetch(u16, 2, c->eip);
1718 break;
1719 case 4:
1720 eip = insn_fetch(u32, 4, c->eip);
1721 break;
1722 default:
1723 DPRINTF("jmp far: Invalid op_bytes\n");
1724 goto cannot_emulate;
1725 }
1726 sel = insn_fetch(u16, 2, c->eip);
1727 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1728 DPRINTF("jmp far: Failed to load CS descriptor\n");
1729 goto cannot_emulate;
1730 }
1731
1732 c->eip = eip;
1733 break;
1734 }
1735 case 0xeb:
1736 jmp: /* jmp rel short */
7a957275 1737 jmp_rel(c, c->src.val);
a01af5ec 1738 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1739 break;
111de5d6 1740 case 0xf4: /* hlt */
ad312c7c 1741 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1742 break;
111de5d6
AK		 1743 case 0xf5: /* cmc */
1744 /* complement carry flag from eflags reg */
1745 ctxt->eflags ^= EFLG_CF;
1746 c->dst.type = OP_NONE; /* Disable writeback. */
1747 break;
018a98db
AK		 1748 case 0xf6 ... 0xf7: /* Grp3 */
1749 rc = emulate_grp3(ctxt, ops);
1750 if (rc != 0)
1751 goto done;
1752 break;
111de5d6
AK		 1753 case 0xf8: /* clc */
1754 ctxt->eflags &= ~EFLG_CF;
1755 c->dst.type = OP_NONE; /* Disable writeback. */
1756 break;
1757 case 0xfa: /* cli */
1758 ctxt->eflags &= ~X86_EFLAGS_IF;
1759 c->dst.type = OP_NONE; /* Disable writeback. */
1760 break;
1761 case 0xfb: /* sti */
1762 ctxt->eflags |= X86_EFLAGS_IF;
1763 c->dst.type = OP_NONE; /* Disable writeback. */
1764 break;
fb4616f4
MG		 1765 case 0xfc: /* cld */
1766 ctxt->eflags &= ~EFLG_DF;
1767 c->dst.type = OP_NONE; /* Disable writeback. */
1768 break;
1769 case 0xfd: /* std */
1770 ctxt->eflags |= EFLG_DF;
1771 c->dst.type = OP_NONE; /* Disable writeback. */
1772 break;
018a98db
AK		 1773 case 0xfe ... 0xff: /* Grp4/Grp5 */
1774 rc = emulate_grp45(ctxt, ops);
1775 if (rc != 0)
1776 goto done;
1777 break;
6aa8b732 1778 }
018a98db
AK		 1779
1780writeback:
1781 rc = writeback(ctxt, ops);
1782 if (rc != 0)
1783 goto done;
1784
1785 /* Commit shadow register state. */
ad312c7c 1786 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1787 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1788
1789done:
1790 if (rc == X86EMUL_UNHANDLEABLE) {
1791 c->eip = saved_eip;
1792 return -1;
1793 }
1794 return 0;
6aa8b732
AK		 1795
1796twobyte_insn:
e4e03ded 1797 switch (c->b) {
6aa8b732 1798 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1799 switch (c->modrm_reg) {
6aa8b732
AK		 1800 u16 size;
1801 unsigned long address;
1802
aca7f966 1803 case 0: /* vmcall */
e4e03ded 1804 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1805 goto cannot_emulate;
1806
7aa81cc0
AL		 1807 rc = kvm_fix_hypercall(ctxt->vcpu);
1808 if (rc)
1809 goto done;
1810
33e3885d 1811 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1812 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1813 /* Disable writeback. */
1814 c->dst.type = OP_NONE;
aca7f966 1815 break;
6aa8b732 1816 case 2: /* lgdt */
e4e03ded
LV		 1817 rc = read_descriptor(ctxt, ops, c->src.ptr,
1818 &size, &address, c->op_bytes);
6aa8b732
AK		 1819 if (rc)
1820 goto done;
1821 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1822 /* Disable writeback. */
1823 c->dst.type = OP_NONE;
6aa8b732 1824 break;
aca7f966 1825 case 3: /* lidt/vmmcall */
e4e03ded 1826 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1827 rc = kvm_fix_hypercall(ctxt->vcpu);
1828 if (rc)
1829 goto done;
1830 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1831 } else {
e4e03ded 1832 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1833 &size, &address,
e4e03ded 1834 c->op_bytes);
aca7f966
AL		 1835 if (rc)
1836 goto done;
1837 realmode_lidt(ctxt->vcpu, size, address);
1838 }
16286d08
AK		 1839 /* Disable writeback. */
1840 c->dst.type = OP_NONE;
6aa8b732
AK		 1841 break;
1842 case 4: /* smsw */
16286d08
AK		 1843 c->dst.bytes = 2;
1844 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1845 break;
1846 case 6: /* lmsw */
16286d08
AK		 1847 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1848 &ctxt->eflags);
dc7457ea 1849 c->dst.type = OP_NONE;
6aa8b732
AK		 1850 break;
1851 case 7: /* invlpg*/
e8d8d7fe 1852 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1853 /* Disable writeback. */
1854 c->dst.type = OP_NONE;
6aa8b732
AK		 1855 break;
1856 default:
1857 goto cannot_emulate;
1858 }
1859 break;
018a98db
AK		 1860 case 0x06:
1861 emulate_clts(ctxt->vcpu);
1862 c->dst.type = OP_NONE;
1863 break;
1864 case 0x08: /* invd */
1865 case 0x09: /* wbinvd */
1866 case 0x0d: /* GrpP (prefetch) */
1867 case 0x18: /* Grp16 (prefetch/nop) */
1868 c->dst.type = OP_NONE;
1869 break;
1870 case 0x20: /* mov cr, reg */
1871 if (c->modrm_mod != 3)
1872 goto cannot_emulate;
1873 c->regs[c->modrm_rm] =
1874 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1875 c->dst.type = OP_NONE; /* no writeback */
1876 break;
6aa8b732 1877 case 0x21: /* mov from dr to reg */
e4e03ded 1878 if (c->modrm_mod != 3)
6aa8b732 1879 goto cannot_emulate;
8cdbd2c9 1880 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1881 if (rc)
1882 goto cannot_emulate;
1883 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1884 break;
018a98db
AK		 1885 case 0x22: /* mov reg, cr */
1886 if (c->modrm_mod != 3)
1887 goto cannot_emulate;
1888 realmode_set_cr(ctxt->vcpu,
1889 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1890 c->dst.type = OP_NONE;
1891 break;
6aa8b732 1892 case 0x23: /* mov from reg to dr */
e4e03ded 1893 if (c->modrm_mod != 3)
6aa8b732 1894 goto cannot_emulate;
e4e03ded
LV		 1895 rc = emulator_set_dr(ctxt, c->modrm_reg,
1896 c->regs[c->modrm_rm]);
a01af5ec
LV		 1897 if (rc)
1898 goto cannot_emulate;
1899 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1900 break;
018a98db
AK		 1901 case 0x30:
1902 /* wrmsr */
1903 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1904 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1905 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1906 if (rc) {
c1a5d4f9 1907 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1908 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1909 }
1910 rc = X86EMUL_CONTINUE;
1911 c->dst.type = OP_NONE;
1912 break;
1913 case 0x32:
1914 /* rdmsr */
1915 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1916 if (rc) {
c1a5d4f9 1917 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1918 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1919 } else {
1920 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1921 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1922 }
1923 rc = X86EMUL_CONTINUE;
1924 c->dst.type = OP_NONE;
1925 break;
6aa8b732 1926 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1927 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1928 if (!test_cc(c->b, ctxt->eflags))
1929 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1930 break;
018a98db
AK		 1931 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1932 long int rel;
1933
1934 switch (c->op_bytes) {
1935 case 2:
1936 rel = insn_fetch(s16, 2, c->eip);
1937 break;
1938 case 4:
1939 rel = insn_fetch(s32, 4, c->eip);
1940 break;
1941 case 8:
1942 rel = insn_fetch(s64, 8, c->eip);
1943 break;
1944 default:
1945 DPRINTF("jnz: Invalid op_bytes\n");
1946 goto cannot_emulate;
1947 }
1948 if (test_cc(c->b, ctxt->eflags))
7a957275 1949 jmp_rel(c, rel);
018a98db
AK		 1950 c->dst.type = OP_NONE;
1951 break;
1952 }
7de75248
NK		 1953 case 0xa3:
1954 bt: /* bt */
e4f8e039 1955 c->dst.type = OP_NONE;
e4e03ded
LV		 1956 /* only subword offset */
1957 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1958 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1959 break;
1960 case 0xab:
1961 bts: /* bts */
e4e03ded
LV		 1962 /* only subword offset */
1963 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1964 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1965 break;
2a7c5b8b
GC		 1966 case 0xae: /* clflush */
1967 break;
6aa8b732
AK		 1968 case 0xb0 ... 0xb1: /* cmpxchg */
1969 /*
1970 * Save real source value, then compare EAX against
1971 * destination.
1972 */
e4e03ded
LV		 1973 c->src.orig_val = c->src.val;
1974 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1975 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1976 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1977 /* Success: write back to memory. */
e4e03ded 1978 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1979 } else {
1980 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1981 c->dst.type = OP_REG;
1982 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1983 }
1984 break;
6aa8b732
AK		 1985 case 0xb3:
1986 btr: /* btr */
e4e03ded
LV		 1987 /* only subword offset */
1988 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1989 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1990 break;
6aa8b732 1991 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1992 c->dst.bytes = c->op_bytes;
1993 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1994 : (u16) c->src.val;
6aa8b732 1995 break;
6aa8b732 1996 case 0xba: /* Grp8 */
e4e03ded 1997 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1998 case 0:
1999 goto bt;
2000 case 1:
2001 goto bts;
2002 case 2:
2003 goto btr;
2004 case 3:
2005 goto btc;
2006 }
2007 break;
7de75248
NK		 2008 case 0xbb:
2009 btc: /* btc */
e4e03ded
LV		 2010 /* only subword offset */
2011 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2012 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2013 break;
6aa8b732 2014 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2015 c->dst.bytes = c->op_bytes;
2016 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2017 (s16) c->src.val;
6aa8b732 2018 break;
a012e65a 2019 case 0xc3: /* movnti */
e4e03ded
LV		 2020 c->dst.bytes = c->op_bytes;
2021 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2022 (u64) c->src.val;
a012e65a 2023 break;
6aa8b732 2024 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2025 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2026 if (rc != 0)
2027 goto done;
018a98db 2028 c->dst.type = OP_NONE;
8cdbd2c9 2029 break;
6aa8b732
AK		 2030 }
2031 goto writeback;
2032
2033cannot_emulate:
e4e03ded 2034 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2035 c->eip = saved_eip;
6aa8b732
AK		 2036 return -1;
2037}
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