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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4
LT
2/*
3 * Precise Delay Loops for i386
4 *
5 * Copyright (C) 1993 Linus Torvalds
6 * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
e01b70ef 7 * Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
1da177e4
LT
8 *
9 * The __delay function must _NOT_ be inlined as its execution time
10 * depends wildly on alignment on many x86 processors. The additional
11 * jump magic is needed to get the timing stable on all the CPU's
12 * we have to worry about.
13 */
14
e683014c 15#include <linux/export.h>
1da177e4 16#include <linux/sched.h>
941e492b 17#include <linux/timex.h>
35d5d08a 18#include <linux/preempt.h>
1da177e4 19#include <linux/delay.h>
6f84fa2f 20
1da177e4
LT
21#include <asm/processor.h>
22#include <asm/delay.h>
23#include <asm/timer.h>
b466bdb6 24#include <asm/mwait.h>
1da177e4
LT
25
26#ifdef CONFIG_SMP
6f84fa2f 27# include <asm/smp.h>
1da177e4
LT
28#endif
29
6f84fa2f
JS
30/* simple loop based delay: */
31static void delay_loop(unsigned long loops)
32{
f0fbf0ab 33 asm volatile(
e01b70ef
JH
34 " test %0,%0 \n"
35 " jz 3f \n"
36 " jmp 1f \n"
37
38 ".align 16 \n"
39 "1: jmp 2f \n"
40
41 ".align 16 \n"
ff1b15b6 42 "2: dec %0 \n"
e01b70ef 43 " jnz 2b \n"
ff1b15b6 44 "3: dec %0 \n"
e01b70ef
JH
45
46 : /* we don't need output */
47 :"a" (loops)
48 );
6f84fa2f
JS
49}
50
51/* TSC based delay: */
a7f4255f 52static void delay_tsc(unsigned long __loops)
6f84fa2f 53{
9cfa1a02 54 u64 bclock, now, loops = __loops;
5c1ea082 55 int cpu;
6f84fa2f 56
5c1ea082
SR
57 preempt_disable();
58 cpu = smp_processor_id();
03b9730b 59 bclock = rdtsc_ordered();
5c1ea082 60 for (;;) {
03b9730b 61 now = rdtsc_ordered();
5c1ea082
SR
62 if ((now - bclock) >= loops)
63 break;
64
65 /* Allow RT tasks to run */
66 preempt_enable();
67 rep_nop();
68 preempt_disable();
69
70 /*
71 * It is possible that we moved to another CPU, and
72 * since TSC's are per-cpu we need to calculate
73 * that. The delay must guarantee that we wait "at
74 * least" the amount of time. Being moved to another
75 * CPU could make the wait longer but we just need to
76 * make sure we waited long enough. Rebalance the
77 * counter for this CPU.
78 */
79 if (unlikely(cpu != smp_processor_id())) {
80 loops -= (now - bclock);
81 cpu = smp_processor_id();
03b9730b 82 bclock = rdtsc_ordered();
5c1ea082
SR
83 }
84 }
35d5d08a 85 preempt_enable();
6f84fa2f
JS
86}
87
b466bdb6
HR
88/*
89 * On some AMD platforms, MWAITX has a configurable 32-bit timer, that
90 * counts with TSC frequency. The input value is the loop of the
91 * counter, it will exit when the timer expires.
92 */
93static void delay_mwaitx(unsigned long __loops)
94{
95 u64 start, end, delay, loops = __loops;
96
88d879d2
JN
97 /*
98 * Timer value of 0 causes MWAITX to wait indefinitely, unless there
99 * is a store on the memory monitored by MONITORX.
100 */
101 if (loops == 0)
102 return;
103
b466bdb6
HR
104 start = rdtsc_ordered();
105
106 for (;;) {
107 delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
108
109 /*
110 * Use cpu_tss as a cacheline-aligned, seldomly
111 * accessed per-cpu variable as the monitor target.
112 */
84477336 113 __monitorx(raw_cpu_ptr(&cpu_tss), 0, 0);
b466bdb6
HR
114
115 /*
116 * AMD, like Intel, supports the EAX hint and EAX=0xf
117 * means, do not enter any deep C-state and we use it
118 * here in delay() to minimize wakeup latency.
119 */
120 __mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
121
122 end = rdtsc_ordered();
123
124 if (loops <= end - start)
125 break;
126
127 loops -= end - start;
128
129 start = end;
130 }
131}
132
6f84fa2f
JS
133/*
134 * Since we calibrate only once at boot, this
135 * function should be set once at boot and not changed
136 */
137static void (*delay_fn)(unsigned long) = delay_loop;
138
139void use_tsc_delay(void)
140{
b466bdb6
HR
141 if (delay_fn == delay_loop)
142 delay_fn = delay_tsc;
143}
144
145void use_mwaitx_delay(void)
146{
147 delay_fn = delay_mwaitx;
6f84fa2f
JS
148}
149
a18e3690 150int read_current_timer(unsigned long *timer_val)
6f84fa2f
JS
151{
152 if (delay_fn == delay_tsc) {
4ea1636b 153 *timer_val = rdtsc();
6f84fa2f
JS
154 return 0;
155 }
156 return -1;
157}
1da177e4
LT
158
159void __delay(unsigned long loops)
160{
6f84fa2f 161 delay_fn(loops);
1da177e4 162}
f0fbf0ab 163EXPORT_SYMBOL(__delay);
1da177e4
LT
164
165inline void __const_udelay(unsigned long xloops)
166{
4c45c516 167 unsigned long lpj = this_cpu_read(cpu_info.loops_per_jiffy) ? : loops_per_jiffy;
1da177e4 168 int d0;
6f84fa2f 169
1da177e4 170 xloops *= 4;
f0fbf0ab 171 asm("mull %%edx"
1da177e4 172 :"=d" (xloops), "=&a" (d0)
4c45c516 173 :"1" (xloops), "0" (lpj * (HZ / 4)));
6f84fa2f
JS
174
175 __delay(++xloops);
1da177e4 176}
f0fbf0ab 177EXPORT_SYMBOL(__const_udelay);
1da177e4
LT
178
179void __udelay(unsigned long usecs)
180{
6f84fa2f 181 __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
1da177e4 182}
f0fbf0ab 183EXPORT_SYMBOL(__udelay);
1da177e4
LT
184
185void __ndelay(unsigned long nsecs)
186{
6f84fa2f 187 __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
1da177e4 188}
129f6946 189EXPORT_SYMBOL(__ndelay);