]>
Commit | Line | Data |
---|---|---|
5a0e3ad6 | 1 | #include <linux/gfp.h> |
2c1b284e | 2 | #include <linux/initrd.h> |
540aca06 | 3 | #include <linux/ioport.h> |
e5b2bb55 | 4 | #include <linux/swap.h> |
a9ce6bc1 | 5 | #include <linux/memblock.h> |
17623915 | 6 | #include <linux/bootmem.h> /* for max_low_pfn */ |
540aca06 | 7 | |
d1163651 | 8 | #include <asm/set_memory.h> |
66441bd3 | 9 | #include <asm/e820/api.h> |
4fcb2083 | 10 | #include <asm/init.h> |
e5b2bb55 | 11 | #include <asm/page.h> |
540aca06 | 12 | #include <asm/page_types.h> |
e5b2bb55 | 13 | #include <asm/sections.h> |
49834396 | 14 | #include <asm/setup.h> |
f765090a | 15 | #include <asm/tlbflush.h> |
9518e0e4 | 16 | #include <asm/tlb.h> |
76c06927 | 17 | #include <asm/proto.h> |
17623915 | 18 | #include <asm/dma.h> /* for MAX_DMA_PFN */ |
cd745be8 | 19 | #include <asm/microcode.h> |
0483e1fa | 20 | #include <asm/kaslr.h> |
c138d811 | 21 | #include <asm/hypervisor.h> |
c7ad5ad2 | 22 | #include <asm/cpufeature.h> |
9518e0e4 | 23 | |
d17d8f9d DH |
24 | /* |
25 | * We need to define the tracepoints somewhere, and tlb.c | |
26 | * is only compied when SMP=y. | |
27 | */ | |
28 | #define CREATE_TRACE_POINTS | |
29 | #include <trace/events/tlb.h> | |
30 | ||
5c51bdbe YL |
31 | #include "mm_internal.h" |
32 | ||
281d4078 JG |
33 | /* |
34 | * Tables translating between page_cache_type_t and pte encoding. | |
c709feda | 35 | * |
d5dc861b TK |
36 | * The default values are defined statically as minimal supported mode; |
37 | * WC and WT fall back to UC-. pat_init() updates these values to support | |
38 | * more cache modes, WC and WT, when it is safe to do so. See pat_init() | |
39 | * for the details. Note, __early_ioremap() used during early boot-time | |
40 | * takes pgprot_t (pte encoding) and does not use these tables. | |
c709feda IM |
41 | * |
42 | * Index into __cachemode2pte_tbl[] is the cachemode. | |
43 | * | |
44 | * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte | |
45 | * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. | |
281d4078 JG |
46 | */ |
47 | uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { | |
c709feda | 48 | [_PAGE_CACHE_MODE_WB ] = 0 | 0 , |
9cd25aac | 49 | [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, |
c709feda IM |
50 | [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, |
51 | [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, | |
52 | [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, | |
53 | [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, | |
281d4078 | 54 | }; |
31bb7723 | 55 | EXPORT_SYMBOL(__cachemode2pte_tbl); |
c709feda | 56 | |
281d4078 | 57 | uint8_t __pte2cachemode_tbl[8] = { |
c709feda | 58 | [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, |
9cd25aac | 59 | [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, |
c709feda IM |
60 | [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, |
61 | [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, | |
62 | [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, | |
9cd25aac | 63 | [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, |
c709feda | 64 | [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, |
281d4078 JG |
65 | [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, |
66 | }; | |
31bb7723 | 67 | EXPORT_SYMBOL(__pte2cachemode_tbl); |
281d4078 | 68 | |
cf470659 YL |
69 | static unsigned long __initdata pgt_buf_start; |
70 | static unsigned long __initdata pgt_buf_end; | |
71 | static unsigned long __initdata pgt_buf_top; | |
f765090a | 72 | |
9985b4c6 YL |
73 | static unsigned long min_pfn_mapped; |
74 | ||
c9b3234a YL |
75 | static bool __initdata can_use_brk_pgt = true; |
76 | ||
ddd3509d SS |
77 | /* |
78 | * Pages returned are already directly mapped. | |
79 | * | |
80 | * Changing that is likely to break Xen, see commit: | |
81 | * | |
82 | * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve | |
83 | * | |
84 | * for detailed information. | |
85 | */ | |
22c8ca2a | 86 | __ref void *alloc_low_pages(unsigned int num) |
5c51bdbe YL |
87 | { |
88 | unsigned long pfn; | |
22c8ca2a | 89 | int i; |
5c51bdbe | 90 | |
5c51bdbe | 91 | if (after_bootmem) { |
22c8ca2a | 92 | unsigned int order; |
5c51bdbe | 93 | |
22c8ca2a | 94 | order = get_order((unsigned long)num << PAGE_SHIFT); |
75f296d9 | 95 | return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); |
5c51bdbe | 96 | } |
5c51bdbe | 97 | |
c9b3234a | 98 | if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { |
5c51bdbe YL |
99 | unsigned long ret; |
100 | if (min_pfn_mapped >= max_pfn_mapped) | |
d4dd100f | 101 | panic("alloc_low_pages: ran out of memory"); |
5c51bdbe YL |
102 | ret = memblock_find_in_range(min_pfn_mapped << PAGE_SHIFT, |
103 | max_pfn_mapped << PAGE_SHIFT, | |
22c8ca2a | 104 | PAGE_SIZE * num , PAGE_SIZE); |
5c51bdbe | 105 | if (!ret) |
d4dd100f | 106 | panic("alloc_low_pages: can not alloc memory"); |
22c8ca2a | 107 | memblock_reserve(ret, PAGE_SIZE * num); |
5c51bdbe | 108 | pfn = ret >> PAGE_SHIFT; |
22c8ca2a YL |
109 | } else { |
110 | pfn = pgt_buf_end; | |
111 | pgt_buf_end += num; | |
c9b3234a YL |
112 | printk(KERN_DEBUG "BRK [%#010lx, %#010lx] PGTABLE\n", |
113 | pfn << PAGE_SHIFT, (pgt_buf_end << PAGE_SHIFT) - 1); | |
22c8ca2a YL |
114 | } |
115 | ||
116 | for (i = 0; i < num; i++) { | |
117 | void *adr; | |
118 | ||
119 | adr = __va((pfn + i) << PAGE_SHIFT); | |
120 | clear_page(adr); | |
121 | } | |
5c51bdbe | 122 | |
22c8ca2a | 123 | return __va(pfn << PAGE_SHIFT); |
5c51bdbe YL |
124 | } |
125 | ||
fb754f95 TG |
126 | /* |
127 | * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS. | |
128 | * With KASLR memory randomization, depending on the machine e820 memory | |
129 | * and the PUD alignment. We may need twice more pages when KASLR memory | |
130 | * randomization is enabled. | |
131 | */ | |
132 | #ifndef CONFIG_RANDOMIZE_MEMORY | |
133 | #define INIT_PGD_PAGE_COUNT 6 | |
134 | #else | |
135 | #define INIT_PGD_PAGE_COUNT 12 | |
136 | #endif | |
137 | #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) | |
8d57470d YL |
138 | RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); |
139 | void __init early_alloc_pgt_buf(void) | |
140 | { | |
141 | unsigned long tables = INIT_PGT_BUF_SIZE; | |
142 | phys_addr_t base; | |
143 | ||
144 | base = __pa(extend_brk(tables, PAGE_SIZE)); | |
145 | ||
146 | pgt_buf_start = base >> PAGE_SHIFT; | |
147 | pgt_buf_end = pgt_buf_start; | |
148 | pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); | |
149 | } | |
150 | ||
f765090a PE |
151 | int after_bootmem; |
152 | ||
10971ab2 | 153 | early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); |
148b2098 | 154 | |
844ab6f9 JS |
155 | struct map_range { |
156 | unsigned long start; | |
157 | unsigned long end; | |
158 | unsigned page_size_mask; | |
159 | }; | |
160 | ||
fa62aafe | 161 | static int page_size_mask; |
f765090a | 162 | |
22ddfcaa | 163 | static void __init probe_page_size_mask(void) |
fa62aafe | 164 | { |
fa62aafe | 165 | /* |
288cf3c6 CB |
166 | * For CONFIG_KMEMCHECK or pagealloc debugging, identity mapping will |
167 | * use small pages. | |
fa62aafe YL |
168 | * This will simplify cpa(), which otherwise needs to support splitting |
169 | * large pages into small in interrupt context, etc. | |
170 | */ | |
d9ee35ac | 171 | if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled() && !IS_ENABLED(CONFIG_KMEMCHECK)) |
fa62aafe | 172 | page_size_mask |= 1 << PG_LEVEL_2M; |
d9ee35ac VB |
173 | else |
174 | direct_gbpages = 0; | |
fa62aafe YL |
175 | |
176 | /* Enable PSE if available */ | |
16bf9226 | 177 | if (boot_cpu_has(X86_FEATURE_PSE)) |
375074cc | 178 | cr4_set_bits_and_update_boot(X86_CR4_PSE); |
fa62aafe YL |
179 | |
180 | /* Enable PGE if available */ | |
c109bf95 | 181 | if (boot_cpu_has(X86_FEATURE_PGE)) { |
375074cc | 182 | cr4_set_bits_and_update_boot(X86_CR4_PGE); |
fa62aafe | 183 | __supported_pte_mask |= _PAGE_GLOBAL; |
0cdb81be JB |
184 | } else |
185 | __supported_pte_mask &= ~_PAGE_GLOBAL; | |
e61980a7 IM |
186 | |
187 | /* Enable 1 GB linear kernel mappings if available: */ | |
b8291adc | 188 | if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { |
e61980a7 IM |
189 | printk(KERN_INFO "Using GB pages for direct mapping\n"); |
190 | page_size_mask |= 1 << PG_LEVEL_1G; | |
191 | } else { | |
192 | direct_gbpages = 0; | |
193 | } | |
fa62aafe | 194 | } |
279b706b | 195 | |
c7ad5ad2 AL |
196 | static void setup_pcid(void) |
197 | { | |
198 | #ifdef CONFIG_X86_64 | |
199 | if (boot_cpu_has(X86_FEATURE_PCID)) { | |
200 | if (boot_cpu_has(X86_FEATURE_PGE)) { | |
201 | /* | |
202 | * This can't be cr4_set_bits_and_update_boot() -- | |
203 | * the trampoline code can't handle CR4.PCIDE and | |
204 | * it wouldn't do any good anyway. Despite the name, | |
205 | * cr4_set_bits_and_update_boot() doesn't actually | |
206 | * cause the bits in question to remain set all the | |
207 | * way through the secondary boot asm. | |
208 | * | |
209 | * Instead, we brute-force it and set CR4.PCIDE | |
210 | * manually in start_secondary(). | |
211 | */ | |
212 | cr4_set_bits(X86_CR4_PCIDE); | |
213 | } else { | |
214 | /* | |
215 | * flush_tlb_all(), as currently implemented, won't | |
216 | * work if PCID is on but PGE is not. Since that | |
217 | * combination doesn't exist on real hardware, there's | |
218 | * no reason to try to fully support it, but it's | |
219 | * polite to avoid corrupting data if we're on | |
220 | * an improperly configured VM. | |
221 | */ | |
222 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
223 | } | |
224 | } | |
225 | #endif | |
226 | } | |
227 | ||
f765090a PE |
228 | #ifdef CONFIG_X86_32 |
229 | #define NR_RANGE_MR 3 | |
230 | #else /* CONFIG_X86_64 */ | |
231 | #define NR_RANGE_MR 5 | |
232 | #endif | |
233 | ||
dc9dd5cc JB |
234 | static int __meminit save_mr(struct map_range *mr, int nr_range, |
235 | unsigned long start_pfn, unsigned long end_pfn, | |
236 | unsigned long page_size_mask) | |
f765090a PE |
237 | { |
238 | if (start_pfn < end_pfn) { | |
239 | if (nr_range >= NR_RANGE_MR) | |
240 | panic("run out of range for init_memory_mapping\n"); | |
241 | mr[nr_range].start = start_pfn<<PAGE_SHIFT; | |
242 | mr[nr_range].end = end_pfn<<PAGE_SHIFT; | |
243 | mr[nr_range].page_size_mask = page_size_mask; | |
244 | nr_range++; | |
245 | } | |
246 | ||
247 | return nr_range; | |
248 | } | |
249 | ||
aeebe84c YL |
250 | /* |
251 | * adjust the page_size_mask for small range to go with | |
252 | * big page size instead small one if nearby are ram too. | |
253 | */ | |
bd721ea7 | 254 | static void __ref adjust_range_page_size_mask(struct map_range *mr, |
aeebe84c YL |
255 | int nr_range) |
256 | { | |
257 | int i; | |
258 | ||
259 | for (i = 0; i < nr_range; i++) { | |
260 | if ((page_size_mask & (1<<PG_LEVEL_2M)) && | |
261 | !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { | |
262 | unsigned long start = round_down(mr[i].start, PMD_SIZE); | |
263 | unsigned long end = round_up(mr[i].end, PMD_SIZE); | |
264 | ||
265 | #ifdef CONFIG_X86_32 | |
266 | if ((end >> PAGE_SHIFT) > max_low_pfn) | |
267 | continue; | |
268 | #endif | |
269 | ||
270 | if (memblock_is_region_memory(start, end - start)) | |
271 | mr[i].page_size_mask |= 1<<PG_LEVEL_2M; | |
272 | } | |
273 | if ((page_size_mask & (1<<PG_LEVEL_1G)) && | |
274 | !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { | |
275 | unsigned long start = round_down(mr[i].start, PUD_SIZE); | |
276 | unsigned long end = round_up(mr[i].end, PUD_SIZE); | |
277 | ||
278 | if (memblock_is_region_memory(start, end - start)) | |
279 | mr[i].page_size_mask |= 1<<PG_LEVEL_1G; | |
280 | } | |
281 | } | |
282 | } | |
283 | ||
f15e0518 DH |
284 | static const char *page_size_string(struct map_range *mr) |
285 | { | |
286 | static const char str_1g[] = "1G"; | |
287 | static const char str_2m[] = "2M"; | |
288 | static const char str_4m[] = "4M"; | |
289 | static const char str_4k[] = "4k"; | |
290 | ||
291 | if (mr->page_size_mask & (1<<PG_LEVEL_1G)) | |
292 | return str_1g; | |
293 | /* | |
294 | * 32-bit without PAE has a 4M large page size. | |
295 | * PG_LEVEL_2M is misnamed, but we can at least | |
296 | * print out the right size in the string. | |
297 | */ | |
298 | if (IS_ENABLED(CONFIG_X86_32) && | |
299 | !IS_ENABLED(CONFIG_X86_PAE) && | |
300 | mr->page_size_mask & (1<<PG_LEVEL_2M)) | |
301 | return str_4m; | |
302 | ||
303 | if (mr->page_size_mask & (1<<PG_LEVEL_2M)) | |
304 | return str_2m; | |
305 | ||
306 | return str_4k; | |
307 | } | |
308 | ||
4e33e065 YL |
309 | static int __meminit split_mem_range(struct map_range *mr, int nr_range, |
310 | unsigned long start, | |
311 | unsigned long end) | |
f765090a | 312 | { |
2e8059ed | 313 | unsigned long start_pfn, end_pfn, limit_pfn; |
1829ae9a | 314 | unsigned long pfn; |
4e33e065 | 315 | int i; |
f765090a | 316 | |
2e8059ed YL |
317 | limit_pfn = PFN_DOWN(end); |
318 | ||
f765090a | 319 | /* head if not big page alignment ? */ |
1829ae9a | 320 | pfn = start_pfn = PFN_DOWN(start); |
f765090a PE |
321 | #ifdef CONFIG_X86_32 |
322 | /* | |
323 | * Don't use a large page for the first 2/4MB of memory | |
324 | * because there are often fixed size MTRRs in there | |
325 | * and overlapping MTRRs into large pages can cause | |
326 | * slowdowns. | |
327 | */ | |
1829ae9a | 328 | if (pfn == 0) |
84d77001 | 329 | end_pfn = PFN_DOWN(PMD_SIZE); |
f765090a | 330 | else |
1829ae9a | 331 | end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); |
f765090a | 332 | #else /* CONFIG_X86_64 */ |
1829ae9a | 333 | end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); |
f765090a | 334 | #endif |
2e8059ed YL |
335 | if (end_pfn > limit_pfn) |
336 | end_pfn = limit_pfn; | |
f765090a PE |
337 | if (start_pfn < end_pfn) { |
338 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); | |
1829ae9a | 339 | pfn = end_pfn; |
f765090a PE |
340 | } |
341 | ||
342 | /* big page (2M) range */ | |
1829ae9a | 343 | start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); |
f765090a | 344 | #ifdef CONFIG_X86_32 |
2e8059ed | 345 | end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); |
f765090a | 346 | #else /* CONFIG_X86_64 */ |
1829ae9a | 347 | end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); |
2e8059ed YL |
348 | if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) |
349 | end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); | |
f765090a PE |
350 | #endif |
351 | ||
352 | if (start_pfn < end_pfn) { | |
353 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | |
354 | page_size_mask & (1<<PG_LEVEL_2M)); | |
1829ae9a | 355 | pfn = end_pfn; |
f765090a PE |
356 | } |
357 | ||
358 | #ifdef CONFIG_X86_64 | |
359 | /* big page (1G) range */ | |
1829ae9a | 360 | start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); |
2e8059ed | 361 | end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); |
f765090a PE |
362 | if (start_pfn < end_pfn) { |
363 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | |
364 | page_size_mask & | |
365 | ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); | |
1829ae9a | 366 | pfn = end_pfn; |
f765090a PE |
367 | } |
368 | ||
369 | /* tail is not big page (1G) alignment */ | |
1829ae9a | 370 | start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); |
2e8059ed | 371 | end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); |
f765090a PE |
372 | if (start_pfn < end_pfn) { |
373 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | |
374 | page_size_mask & (1<<PG_LEVEL_2M)); | |
1829ae9a | 375 | pfn = end_pfn; |
f765090a PE |
376 | } |
377 | #endif | |
378 | ||
379 | /* tail is not big page (2M) alignment */ | |
1829ae9a | 380 | start_pfn = pfn; |
2e8059ed | 381 | end_pfn = limit_pfn; |
f765090a PE |
382 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); |
383 | ||
7de3d66b YL |
384 | if (!after_bootmem) |
385 | adjust_range_page_size_mask(mr, nr_range); | |
386 | ||
f765090a PE |
387 | /* try to merge same page size and continuous */ |
388 | for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { | |
389 | unsigned long old_start; | |
390 | if (mr[i].end != mr[i+1].start || | |
391 | mr[i].page_size_mask != mr[i+1].page_size_mask) | |
392 | continue; | |
393 | /* move it */ | |
394 | old_start = mr[i].start; | |
395 | memmove(&mr[i], &mr[i+1], | |
396 | (nr_range - 1 - i) * sizeof(struct map_range)); | |
397 | mr[i--].start = old_start; | |
398 | nr_range--; | |
399 | } | |
400 | ||
401 | for (i = 0; i < nr_range; i++) | |
c9cdaeb2 | 402 | pr_debug(" [mem %#010lx-%#010lx] page %s\n", |
365811d6 | 403 | mr[i].start, mr[i].end - 1, |
f15e0518 | 404 | page_size_string(&mr[i])); |
f765090a | 405 | |
4e33e065 YL |
406 | return nr_range; |
407 | } | |
408 | ||
08b46d5d | 409 | struct range pfn_mapped[E820_MAX_ENTRIES]; |
0e691cf8 | 410 | int nr_pfn_mapped; |
66520ebc JS |
411 | |
412 | static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) | |
413 | { | |
08b46d5d | 414 | nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, |
66520ebc | 415 | nr_pfn_mapped, start_pfn, end_pfn); |
08b46d5d | 416 | nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); |
66520ebc JS |
417 | |
418 | max_pfn_mapped = max(max_pfn_mapped, end_pfn); | |
419 | ||
420 | if (start_pfn < (1UL<<(32-PAGE_SHIFT))) | |
421 | max_low_pfn_mapped = max(max_low_pfn_mapped, | |
422 | min(end_pfn, 1UL<<(32-PAGE_SHIFT))); | |
423 | } | |
424 | ||
425 | bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) | |
426 | { | |
427 | int i; | |
428 | ||
429 | for (i = 0; i < nr_pfn_mapped; i++) | |
430 | if ((start_pfn >= pfn_mapped[i].start) && | |
431 | (end_pfn <= pfn_mapped[i].end)) | |
432 | return true; | |
433 | ||
434 | return false; | |
435 | } | |
436 | ||
4e33e065 YL |
437 | /* |
438 | * Setup the direct mapping of the physical memory at PAGE_OFFSET. | |
439 | * This runs before bootmem is initialized and gets pages directly from | |
440 | * the physical memory. To access them they are temporarily mapped. | |
441 | */ | |
bd721ea7 | 442 | unsigned long __ref init_memory_mapping(unsigned long start, |
4e33e065 YL |
443 | unsigned long end) |
444 | { | |
445 | struct map_range mr[NR_RANGE_MR]; | |
446 | unsigned long ret = 0; | |
447 | int nr_range, i; | |
448 | ||
c9cdaeb2 | 449 | pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", |
4e33e065 YL |
450 | start, end - 1); |
451 | ||
452 | memset(mr, 0, sizeof(mr)); | |
453 | nr_range = split_mem_range(mr, 0, start, end); | |
454 | ||
f765090a PE |
455 | for (i = 0; i < nr_range; i++) |
456 | ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, | |
457 | mr[i].page_size_mask); | |
f765090a | 458 | |
66520ebc JS |
459 | add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); |
460 | ||
c14fa0b6 YL |
461 | return ret >> PAGE_SHIFT; |
462 | } | |
463 | ||
66520ebc | 464 | /* |
cf8b166d | 465 | * We need to iterate through the E820 memory map and create direct mappings |
09821ff1 | 466 | * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply |
cf8b166d ZY |
467 | * create direct mappings for all pfns from [0 to max_low_pfn) and |
468 | * [4GB to max_pfn) because of possible memory holes in high addresses | |
469 | * that cannot be marked as UC by fixed/variable range MTRRs. | |
470 | * Depending on the alignment of E820 ranges, this may possibly result | |
471 | * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. | |
472 | * | |
473 | * init_mem_mapping() calls init_range_memory_mapping() with big range. | |
474 | * That range would have hole in the middle or ends, and only ram parts | |
475 | * will be mapped in init_range_memory_mapping(). | |
66520ebc | 476 | */ |
8d57470d | 477 | static unsigned long __init init_range_memory_mapping( |
b8fd39c0 YL |
478 | unsigned long r_start, |
479 | unsigned long r_end) | |
66520ebc JS |
480 | { |
481 | unsigned long start_pfn, end_pfn; | |
8d57470d | 482 | unsigned long mapped_ram_size = 0; |
66520ebc JS |
483 | int i; |
484 | ||
66520ebc | 485 | for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { |
b8fd39c0 YL |
486 | u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); |
487 | u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); | |
488 | if (start >= end) | |
66520ebc JS |
489 | continue; |
490 | ||
c9b3234a YL |
491 | /* |
492 | * if it is overlapping with brk pgt, we need to | |
493 | * alloc pgt buf from memblock instead. | |
494 | */ | |
495 | can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= | |
496 | min(end, (u64)pgt_buf_top<<PAGE_SHIFT); | |
f763ad1d | 497 | init_memory_mapping(start, end); |
8d57470d | 498 | mapped_ram_size += end - start; |
c9b3234a | 499 | can_use_brk_pgt = true; |
66520ebc | 500 | } |
8d57470d YL |
501 | |
502 | return mapped_ram_size; | |
66520ebc JS |
503 | } |
504 | ||
6979287a YL |
505 | static unsigned long __init get_new_step_size(unsigned long step_size) |
506 | { | |
507 | /* | |
132978b9 | 508 | * Initial mapped size is PMD_SIZE (2M). |
6979287a YL |
509 | * We can not set step_size to be PUD_SIZE (1G) yet. |
510 | * In worse case, when we cross the 1G boundary, and | |
511 | * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) | |
132978b9 JB |
512 | * to map 1G range with PTE. Hence we use one less than the |
513 | * difference of page table level shifts. | |
6979287a | 514 | * |
132978b9 JB |
515 | * Don't need to worry about overflow in the top-down case, on 32bit, |
516 | * when step_size is 0, round_down() returns 0 for start, and that | |
517 | * turns it into 0x100000000ULL. | |
518 | * In the bottom-up case, round_up(x, 0) returns 0 though too, which | |
519 | * needs to be taken into consideration by the code below. | |
6979287a | 520 | */ |
132978b9 | 521 | return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); |
6979287a YL |
522 | } |
523 | ||
0167d7d8 TC |
524 | /** |
525 | * memory_map_top_down - Map [map_start, map_end) top down | |
526 | * @map_start: start address of the target memory range | |
527 | * @map_end: end address of the target memory range | |
528 | * | |
529 | * This function will setup direct mapping for memory range | |
530 | * [map_start, map_end) in top-down. That said, the page tables | |
531 | * will be allocated at the end of the memory, and we map the | |
532 | * memory in top-down. | |
533 | */ | |
534 | static void __init memory_map_top_down(unsigned long map_start, | |
535 | unsigned long map_end) | |
c14fa0b6 | 536 | { |
0167d7d8 | 537 | unsigned long real_end, start, last_start; |
8d57470d YL |
538 | unsigned long step_size; |
539 | unsigned long addr; | |
540 | unsigned long mapped_ram_size = 0; | |
ab951937 | 541 | |
98e7a989 | 542 | /* xen has big range in reserved near end of ram, skip it at first.*/ |
0167d7d8 | 543 | addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE); |
8d57470d YL |
544 | real_end = addr + PMD_SIZE; |
545 | ||
546 | /* step_size need to be small so pgt_buf from BRK could cover it */ | |
547 | step_size = PMD_SIZE; | |
548 | max_pfn_mapped = 0; /* will get exact value next */ | |
549 | min_pfn_mapped = real_end >> PAGE_SHIFT; | |
550 | last_start = start = real_end; | |
cf8b166d ZY |
551 | |
552 | /* | |
553 | * We start from the top (end of memory) and go to the bottom. | |
554 | * The memblock_find_in_range() gets us a block of RAM from the | |
555 | * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages | |
556 | * for page table. | |
557 | */ | |
0167d7d8 | 558 | while (last_start > map_start) { |
8d57470d YL |
559 | if (last_start > step_size) { |
560 | start = round_down(last_start - 1, step_size); | |
0167d7d8 TC |
561 | if (start < map_start) |
562 | start = map_start; | |
8d57470d | 563 | } else |
0167d7d8 | 564 | start = map_start; |
132978b9 | 565 | mapped_ram_size += init_range_memory_mapping(start, |
8d57470d YL |
566 | last_start); |
567 | last_start = start; | |
568 | min_pfn_mapped = last_start >> PAGE_SHIFT; | |
132978b9 | 569 | if (mapped_ram_size >= step_size) |
6979287a | 570 | step_size = get_new_step_size(step_size); |
8d57470d YL |
571 | } |
572 | ||
0167d7d8 TC |
573 | if (real_end < map_end) |
574 | init_range_memory_mapping(real_end, map_end); | |
575 | } | |
576 | ||
b959ed6c TC |
577 | /** |
578 | * memory_map_bottom_up - Map [map_start, map_end) bottom up | |
579 | * @map_start: start address of the target memory range | |
580 | * @map_end: end address of the target memory range | |
581 | * | |
582 | * This function will setup direct mapping for memory range | |
583 | * [map_start, map_end) in bottom-up. Since we have limited the | |
584 | * bottom-up allocation above the kernel, the page tables will | |
585 | * be allocated just above the kernel and we map the memory | |
586 | * in [map_start, map_end) in bottom-up. | |
587 | */ | |
588 | static void __init memory_map_bottom_up(unsigned long map_start, | |
589 | unsigned long map_end) | |
590 | { | |
132978b9 | 591 | unsigned long next, start; |
b959ed6c TC |
592 | unsigned long mapped_ram_size = 0; |
593 | /* step_size need to be small so pgt_buf from BRK could cover it */ | |
594 | unsigned long step_size = PMD_SIZE; | |
595 | ||
596 | start = map_start; | |
597 | min_pfn_mapped = start >> PAGE_SHIFT; | |
598 | ||
599 | /* | |
600 | * We start from the bottom (@map_start) and go to the top (@map_end). | |
601 | * The memblock_find_in_range() gets us a block of RAM from the | |
602 | * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages | |
603 | * for page table. | |
604 | */ | |
605 | while (start < map_end) { | |
132978b9 | 606 | if (step_size && map_end - start > step_size) { |
b959ed6c TC |
607 | next = round_up(start + 1, step_size); |
608 | if (next > map_end) | |
609 | next = map_end; | |
132978b9 | 610 | } else { |
b959ed6c | 611 | next = map_end; |
132978b9 | 612 | } |
b959ed6c | 613 | |
132978b9 | 614 | mapped_ram_size += init_range_memory_mapping(start, next); |
b959ed6c TC |
615 | start = next; |
616 | ||
132978b9 | 617 | if (mapped_ram_size >= step_size) |
b959ed6c | 618 | step_size = get_new_step_size(step_size); |
b959ed6c TC |
619 | } |
620 | } | |
621 | ||
0167d7d8 TC |
622 | void __init init_mem_mapping(void) |
623 | { | |
624 | unsigned long end; | |
625 | ||
626 | probe_page_size_mask(); | |
c7ad5ad2 | 627 | setup_pcid(); |
0167d7d8 TC |
628 | |
629 | #ifdef CONFIG_X86_64 | |
630 | end = max_pfn << PAGE_SHIFT; | |
631 | #else | |
632 | end = max_low_pfn << PAGE_SHIFT; | |
633 | #endif | |
634 | ||
635 | /* the ISA range is always mapped regardless of memory holes */ | |
636 | init_memory_mapping(0, ISA_END_ADDRESS); | |
637 | ||
b234e8a0 TG |
638 | /* Init the trampoline, possibly with KASLR memory offset */ |
639 | init_trampoline(); | |
640 | ||
b959ed6c TC |
641 | /* |
642 | * If the allocation is in bottom-up direction, we setup direct mapping | |
643 | * in bottom-up, otherwise we setup direct mapping in top-down. | |
644 | */ | |
645 | if (memblock_bottom_up()) { | |
646 | unsigned long kernel_end = __pa_symbol(_end); | |
647 | ||
648 | /* | |
649 | * we need two separate calls here. This is because we want to | |
650 | * allocate page tables above the kernel. So we first map | |
651 | * [kernel_end, end) to make memory above the kernel be mapped | |
652 | * as soon as possible. And then use page tables allocated above | |
653 | * the kernel to map [ISA_END_ADDRESS, kernel_end). | |
654 | */ | |
655 | memory_map_bottom_up(kernel_end, end); | |
656 | memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); | |
657 | } else { | |
658 | memory_map_top_down(ISA_END_ADDRESS, end); | |
659 | } | |
8d57470d | 660 | |
f763ad1d YL |
661 | #ifdef CONFIG_X86_64 |
662 | if (max_pfn > max_low_pfn) { | |
663 | /* can we preseve max_low_pfn ?*/ | |
664 | max_low_pfn = max_pfn; | |
665 | } | |
719272c4 YL |
666 | #else |
667 | early_ioremap_page_table_range_init(); | |
8170e6be PA |
668 | #endif |
669 | ||
719272c4 YL |
670 | load_cr3(swapper_pg_dir); |
671 | __flush_tlb_all(); | |
719272c4 | 672 | |
f72e38e8 | 673 | x86_init.hyper.init_mem_mapping(); |
c138d811 | 674 | |
c14fa0b6 | 675 | early_memtest(0, max_pfn_mapped << PAGE_SHIFT); |
22ddfcaa | 676 | } |
e5b2bb55 | 677 | |
540aca06 PE |
678 | /* |
679 | * devmem_is_allowed() checks to see if /dev/mem access to a certain address | |
680 | * is valid. The argument is a physical page number. | |
681 | * | |
a4866aa8 KC |
682 | * On x86, access has to be given to the first megabyte of RAM because that |
683 | * area traditionally contains BIOS code and data regions used by X, dosemu, | |
684 | * and similar apps. Since they map the entire memory range, the whole range | |
685 | * must be allowed (for mapping), but any areas that would otherwise be | |
686 | * disallowed are flagged as being "zero filled" instead of rejected. | |
687 | * Access has to be given to non-kernel-ram areas as well, these contain the | |
688 | * PCI mmio resources as well as potential bios/acpi data regions. | |
540aca06 PE |
689 | */ |
690 | int devmem_is_allowed(unsigned long pagenr) | |
691 | { | |
a4866aa8 KC |
692 | if (page_is_ram(pagenr)) { |
693 | /* | |
694 | * For disallowed memory regions in the low 1MB range, | |
695 | * request that the page be shown as all zeros. | |
696 | */ | |
697 | if (pagenr < 256) | |
698 | return 2; | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | /* | |
704 | * This must follow RAM test, since System RAM is considered a | |
705 | * restricted resource under CONFIG_STRICT_IOMEM. | |
706 | */ | |
707 | if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { | |
708 | /* Low 1MB bypasses iomem restrictions. */ | |
709 | if (pagenr < 256) | |
710 | return 1; | |
711 | ||
540aca06 | 712 | return 0; |
a4866aa8 KC |
713 | } |
714 | ||
715 | return 1; | |
540aca06 PE |
716 | } |
717 | ||
e5b2bb55 PE |
718 | void free_init_pages(char *what, unsigned long begin, unsigned long end) |
719 | { | |
c967da6a | 720 | unsigned long begin_aligned, end_aligned; |
e5b2bb55 | 721 | |
c967da6a YL |
722 | /* Make sure boundaries are page aligned */ |
723 | begin_aligned = PAGE_ALIGN(begin); | |
724 | end_aligned = end & PAGE_MASK; | |
725 | ||
726 | if (WARN_ON(begin_aligned != begin || end_aligned != end)) { | |
727 | begin = begin_aligned; | |
728 | end = end_aligned; | |
729 | } | |
730 | ||
731 | if (begin >= end) | |
e5b2bb55 PE |
732 | return; |
733 | ||
734 | /* | |
735 | * If debugging page accesses then do not free this memory but | |
736 | * mark them not present - any buggy init-section access will | |
737 | * create a kernel page fault: | |
738 | */ | |
a75e1f63 CB |
739 | if (debug_pagealloc_enabled()) { |
740 | pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", | |
741 | begin, end - 1); | |
742 | set_memory_np(begin, (end - begin) >> PAGE_SHIFT); | |
743 | } else { | |
744 | /* | |
745 | * We just marked the kernel text read only above, now that | |
746 | * we are going to free part of that, we need to make that | |
747 | * writeable and non-executable first. | |
748 | */ | |
749 | set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); | |
750 | set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); | |
e5b2bb55 | 751 | |
a75e1f63 CB |
752 | free_reserved_area((void *)begin, (void *)end, |
753 | POISON_FREE_INITMEM, what); | |
754 | } | |
e5b2bb55 PE |
755 | } |
756 | ||
18278229 | 757 | void __ref free_initmem(void) |
e5b2bb55 | 758 | { |
0c6fc11a | 759 | e820__reallocate_tables(); |
47533968 | 760 | |
c88442ec | 761 | free_init_pages("unused kernel", |
e5b2bb55 PE |
762 | (unsigned long)(&__init_begin), |
763 | (unsigned long)(&__init_end)); | |
764 | } | |
731ddea6 PE |
765 | |
766 | #ifdef CONFIG_BLK_DEV_INITRD | |
0d26d1d8 | 767 | void __init free_initrd_mem(unsigned long start, unsigned long end) |
731ddea6 | 768 | { |
c967da6a YL |
769 | /* |
770 | * end could be not aligned, and We can not align that, | |
771 | * decompresser could be confused by aligned initrd_end | |
772 | * We already reserve the end partial page before in | |
773 | * - i386_start_kernel() | |
774 | * - x86_64_start_kernel() | |
775 | * - relocate_initrd() | |
776 | * So here We can do PAGE_ALIGN() safely to get partial page to be freed | |
777 | */ | |
c88442ec | 778 | free_init_pages("initrd", start, PAGE_ALIGN(end)); |
731ddea6 PE |
779 | } |
780 | #endif | |
17623915 | 781 | |
4270fd8b IM |
782 | /* |
783 | * Calculate the precise size of the DMA zone (first 16 MB of RAM), | |
784 | * and pass it to the MM layer - to help it set zone watermarks more | |
785 | * accurately. | |
786 | * | |
787 | * Done on 64-bit systems only for the time being, although 32-bit systems | |
788 | * might benefit from this as well. | |
789 | */ | |
790 | void __init memblock_find_dma_reserve(void) | |
791 | { | |
792 | #ifdef CONFIG_X86_64 | |
793 | u64 nr_pages = 0, nr_free_pages = 0; | |
794 | unsigned long start_pfn, end_pfn; | |
795 | phys_addr_t start_addr, end_addr; | |
796 | int i; | |
797 | u64 u; | |
798 | ||
799 | /* | |
800 | * Iterate over all memory ranges (free and reserved ones alike), | |
801 | * to calculate the total number of pages in the first 16 MB of RAM: | |
802 | */ | |
803 | nr_pages = 0; | |
804 | for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { | |
805 | start_pfn = min(start_pfn, MAX_DMA_PFN); | |
806 | end_pfn = min(end_pfn, MAX_DMA_PFN); | |
807 | ||
808 | nr_pages += end_pfn - start_pfn; | |
809 | } | |
810 | ||
811 | /* | |
812 | * Iterate over free memory ranges to calculate the number of free | |
813 | * pages in the DMA zone, while not counting potential partial | |
814 | * pages at the beginning or the end of the range: | |
815 | */ | |
816 | nr_free_pages = 0; | |
817 | for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { | |
818 | start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); | |
819 | end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); | |
820 | ||
821 | if (start_pfn < end_pfn) | |
822 | nr_free_pages += end_pfn - start_pfn; | |
823 | } | |
824 | ||
825 | set_dma_reserve(nr_pages - nr_free_pages); | |
826 | #endif | |
827 | } | |
828 | ||
17623915 PE |
829 | void __init zone_sizes_init(void) |
830 | { | |
831 | unsigned long max_zone_pfns[MAX_NR_ZONES]; | |
832 | ||
833 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); | |
834 | ||
835 | #ifdef CONFIG_ZONE_DMA | |
c072b90c | 836 | max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); |
17623915 PE |
837 | #endif |
838 | #ifdef CONFIG_ZONE_DMA32 | |
c072b90c | 839 | max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); |
17623915 PE |
840 | #endif |
841 | max_zone_pfns[ZONE_NORMAL] = max_low_pfn; | |
842 | #ifdef CONFIG_HIGHMEM | |
843 | max_zone_pfns[ZONE_HIGHMEM] = max_pfn; | |
844 | #endif | |
845 | ||
846 | free_area_init_nodes(max_zone_pfns); | |
847 | } | |
848 | ||
1e02ce4c | 849 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { |
3d28ebce | 850 | .loaded_mm = &init_mm, |
10af6235 | 851 | .next_asid = 1, |
1e02ce4c AL |
852 | .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ |
853 | }; | |
854 | EXPORT_SYMBOL_GPL(cpu_tlbstate); | |
855 | ||
bd809af1 JG |
856 | void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) |
857 | { | |
858 | /* entry 0 MUST be WB (hardwired to speed up translations) */ | |
859 | BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); | |
860 | ||
861 | __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); | |
862 | __pte2cachemode_tbl[entry] = cache; | |
863 | } |