]>
Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
9f4c815c | 16 | |
950f9d95 | 17 | #include <asm/e820.h> |
1da177e4 LT |
18 | #include <asm/processor.h> |
19 | #include <asm/tlbflush.h> | |
f8af095d | 20 | #include <asm/sections.h> |
93dbda7c | 21 | #include <asm/setup.h> |
9f4c815c IM |
22 | #include <asm/uaccess.h> |
23 | #include <asm/pgalloc.h> | |
c31c7d48 | 24 | #include <asm/proto.h> |
1219333d | 25 | #include <asm/pat.h> |
1da177e4 | 26 | |
9df84993 IM |
27 | /* |
28 | * The current flushing context - we pass it instead of 5 arguments: | |
29 | */ | |
72e458df | 30 | struct cpa_data { |
d75586ad | 31 | unsigned long *vaddr; |
72e458df TG |
32 | pgprot_t mask_set; |
33 | pgprot_t mask_clr; | |
65e074df | 34 | int numpages; |
d75586ad | 35 | int flags; |
c31c7d48 | 36 | unsigned long pfn; |
c9caa02c | 37 | unsigned force_split : 1; |
d75586ad | 38 | int curpage; |
9ae28475 | 39 | struct page **pages; |
72e458df TG |
40 | }; |
41 | ||
ad5ca55f SS |
42 | /* |
43 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
44 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
45 | * entries change the page attribute in parallel to some other cpu | |
46 | * splitting a large page entry along with changing the attribute. | |
47 | */ | |
48 | static DEFINE_SPINLOCK(cpa_lock); | |
49 | ||
d75586ad SL |
50 | #define CPA_FLUSHTLB 1 |
51 | #define CPA_ARRAY 2 | |
9ae28475 | 52 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 53 | |
65280e61 | 54 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
55 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
56 | ||
65280e61 | 57 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 58 | { |
ce0c0e50 | 59 | unsigned long flags; |
65280e61 | 60 | |
ce0c0e50 AK |
61 | /* Protect against CPA */ |
62 | spin_lock_irqsave(&pgd_lock, flags); | |
63 | direct_pages_count[level] += pages; | |
64 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
65280e61 | 84 | #ifdef CONFIG_X86_64 |
a06de630 | 85 | if (direct_gbpages) |
b9c3bfc2 | 86 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 87 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
88 | #endif |
89 | } | |
65280e61 TG |
90 | #else |
91 | static inline void split_page_count(int level) { } | |
92 | #endif | |
ce0c0e50 | 93 | |
c31c7d48 TG |
94 | #ifdef CONFIG_X86_64 |
95 | ||
96 | static inline unsigned long highmap_start_pfn(void) | |
97 | { | |
98 | return __pa(_text) >> PAGE_SHIFT; | |
99 | } | |
100 | ||
101 | static inline unsigned long highmap_end_pfn(void) | |
102 | { | |
93dbda7c | 103 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
104 | } |
105 | ||
106 | #endif | |
107 | ||
92cb54a3 IM |
108 | #ifdef CONFIG_DEBUG_PAGEALLOC |
109 | # define debug_pagealloc 1 | |
110 | #else | |
111 | # define debug_pagealloc 0 | |
112 | #endif | |
113 | ||
ed724be6 AV |
114 | static inline int |
115 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 116 | { |
ed724be6 AV |
117 | return addr >= start && addr < end; |
118 | } | |
119 | ||
d7c8f21a TG |
120 | /* |
121 | * Flushing functions | |
122 | */ | |
cd8ddf1a | 123 | |
cd8ddf1a TG |
124 | /** |
125 | * clflush_cache_range - flush a cache range with clflush | |
126 | * @addr: virtual start address | |
127 | * @size: number of bytes to flush | |
128 | * | |
129 | * clflush is an unordered instruction which needs fencing with mfence | |
130 | * to avoid ordering issues. | |
131 | */ | |
4c61afcd | 132 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 133 | { |
4c61afcd | 134 | void *vend = vaddr + size - 1; |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd IM |
137 | |
138 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
139 | clflush(vaddr); | |
140 | /* | |
141 | * Flush any possible final partial cacheline: | |
142 | */ | |
143 | clflush(vend); | |
144 | ||
cd8ddf1a | 145 | mb(); |
d7c8f21a | 146 | } |
e517a5e9 | 147 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 148 | |
af1e6844 | 149 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 150 | { |
6bb8383b AK |
151 | unsigned long cache = (unsigned long)arg; |
152 | ||
d7c8f21a TG |
153 | /* |
154 | * Flush all to work around Errata in early athlons regarding | |
155 | * large page flushing. | |
156 | */ | |
157 | __flush_tlb_all(); | |
158 | ||
0b827537 | 159 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
160 | wbinvd(); |
161 | } | |
162 | ||
6bb8383b | 163 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
164 | { |
165 | BUG_ON(irqs_disabled()); | |
166 | ||
15c8b6c1 | 167 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
168 | } |
169 | ||
57a6a46a TG |
170 | static void __cpa_flush_range(void *arg) |
171 | { | |
57a6a46a TG |
172 | /* |
173 | * We could optimize that further and do individual per page | |
174 | * tlb invalidates for a low number of pages. Caveat: we must | |
175 | * flush the high aliases on 64bit as well. | |
176 | */ | |
177 | __flush_tlb_all(); | |
57a6a46a TG |
178 | } |
179 | ||
6bb8383b | 180 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 181 | { |
4c61afcd IM |
182 | unsigned int i, level; |
183 | unsigned long addr; | |
184 | ||
57a6a46a | 185 | BUG_ON(irqs_disabled()); |
4c61afcd | 186 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 187 | |
15c8b6c1 | 188 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 189 | |
6bb8383b AK |
190 | if (!cache) |
191 | return; | |
192 | ||
3b233e52 TG |
193 | /* |
194 | * We only need to flush on one CPU, | |
195 | * clflush is a MESI-coherent instruction that | |
196 | * will cause all other CPUs to flush the same | |
197 | * cachelines: | |
198 | */ | |
4c61afcd IM |
199 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
200 | pte_t *pte = lookup_address(addr, &level); | |
201 | ||
202 | /* | |
203 | * Only flush present addresses: | |
204 | */ | |
7bfb72e8 | 205 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
206 | clflush_cache_range((void *) addr, PAGE_SIZE); |
207 | } | |
57a6a46a TG |
208 | } |
209 | ||
9ae28475 | 210 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
211 | int in_flags, struct page **pages) | |
d75586ad SL |
212 | { |
213 | unsigned int i, level; | |
2171787b | 214 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
215 | |
216 | BUG_ON(irqs_disabled()); | |
217 | ||
2171787b | 218 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 219 | |
2171787b | 220 | if (!cache || do_wbinvd) |
d75586ad SL |
221 | return; |
222 | ||
d75586ad SL |
223 | /* |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
9ae28475 | 229 | for (i = 0; i < numpages; i++) { |
230 | unsigned long addr; | |
231 | pte_t *pte; | |
232 | ||
233 | if (in_flags & CPA_PAGES_ARRAY) | |
234 | addr = (unsigned long)page_address(pages[i]); | |
235 | else | |
236 | addr = start[i]; | |
237 | ||
238 | pte = lookup_address(addr, &level); | |
d75586ad SL |
239 | |
240 | /* | |
241 | * Only flush present addresses: | |
242 | */ | |
243 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 244 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
245 | } |
246 | } | |
247 | ||
ed724be6 AV |
248 | /* |
249 | * Certain areas of memory on x86 require very specific protection flags, | |
250 | * for example the BIOS area or kernel text. Callers don't always get this | |
251 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
252 | * checks and fixes these known static required protection bits. | |
253 | */ | |
c31c7d48 TG |
254 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
255 | unsigned long pfn) | |
ed724be6 AV |
256 | { |
257 | pgprot_t forbidden = __pgprot(0); | |
258 | ||
687c4825 | 259 | /* |
ed724be6 AV |
260 | * The BIOS area between 640k and 1Mb needs to be executable for |
261 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 262 | */ |
c31c7d48 | 263 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
264 | pgprot_val(forbidden) |= _PAGE_NX; |
265 | ||
266 | /* | |
267 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
268 | * Does not cover __inittext since that is gone later on. On |
269 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
270 | */ |
271 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
272 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 273 | |
cc0f21bb | 274 | /* |
c31c7d48 TG |
275 | * The .rodata section needs to be read-only. Using the pfn |
276 | * catches all aliases. | |
cc0f21bb | 277 | */ |
c31c7d48 TG |
278 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
279 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 280 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 281 | |
55ca3cc1 | 282 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 283 | /* |
502f6604 SS |
284 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
285 | * kernel text mappings for the large page aligned text, rodata sections | |
286 | * will be always read-only. For the kernel identity mappings covering | |
287 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
288 | * |
289 | * This will preserve the large page mappings for kernel text/data | |
290 | * at no extra cost. | |
291 | */ | |
502f6604 SS |
292 | if (kernel_set_to_readonly && |
293 | within(address, (unsigned long)_text, | |
281ff33b SS |
294 | (unsigned long)__end_rodata_hpage_align)) { |
295 | unsigned int level; | |
296 | ||
297 | /* | |
298 | * Don't enforce the !RW mapping for the kernel text mapping, | |
299 | * if the current mapping is already using small page mapping. | |
300 | * No need to work hard to preserve large page mappings in this | |
301 | * case. | |
302 | * | |
303 | * This also fixes the Linux Xen paravirt guest boot failure | |
304 | * (because of unexpected read-only mappings for kernel identity | |
305 | * mappings). In this paravirt guest case, the kernel text | |
306 | * mapping and the kernel identity mapping share the same | |
307 | * page-table pages. Thus we can't really use different | |
308 | * protections for the kernel text and identity mappings. Also, | |
309 | * these shared mappings are made of small page mappings. | |
310 | * Thus this don't enforce !RW mapping for small page kernel | |
311 | * text mapping logic will help Linux Xen parvirt guest boot | |
312 | * aswell. | |
313 | */ | |
314 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
315 | pgprot_val(forbidden) |= _PAGE_RW; | |
316 | } | |
74e08179 SS |
317 | #endif |
318 | ||
ed724be6 | 319 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
320 | |
321 | return prot; | |
322 | } | |
323 | ||
9a14aefc TG |
324 | /* |
325 | * Lookup the page table entry for a virtual address. Return a pointer | |
326 | * to the entry and the level of the mapping. | |
327 | * | |
328 | * Note: We return pud and pmd either when the entry is marked large | |
329 | * or when the present bit is not set. Otherwise we would return a | |
330 | * pointer to a nonexisting mapping. | |
331 | */ | |
da7bfc50 | 332 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 333 | { |
1da177e4 LT |
334 | pgd_t *pgd = pgd_offset_k(address); |
335 | pud_t *pud; | |
336 | pmd_t *pmd; | |
9f4c815c | 337 | |
30551bb3 TG |
338 | *level = PG_LEVEL_NONE; |
339 | ||
1da177e4 LT |
340 | if (pgd_none(*pgd)) |
341 | return NULL; | |
9df84993 | 342 | |
1da177e4 LT |
343 | pud = pud_offset(pgd, address); |
344 | if (pud_none(*pud)) | |
345 | return NULL; | |
c2f71ee2 AK |
346 | |
347 | *level = PG_LEVEL_1G; | |
348 | if (pud_large(*pud) || !pud_present(*pud)) | |
349 | return (pte_t *)pud; | |
350 | ||
1da177e4 LT |
351 | pmd = pmd_offset(pud, address); |
352 | if (pmd_none(*pmd)) | |
353 | return NULL; | |
30551bb3 TG |
354 | |
355 | *level = PG_LEVEL_2M; | |
9a14aefc | 356 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 357 | return (pte_t *)pmd; |
1da177e4 | 358 | |
30551bb3 | 359 | *level = PG_LEVEL_4K; |
9df84993 | 360 | |
9f4c815c IM |
361 | return pte_offset_kernel(pmd, address); |
362 | } | |
75bb8835 | 363 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 364 | |
9df84993 IM |
365 | /* |
366 | * Set the new pmd in all the pgds we know about: | |
367 | */ | |
9a3dc780 | 368 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 369 | { |
9f4c815c IM |
370 | /* change init_mm */ |
371 | set_pte_atomic(kpte, pte); | |
44af6c41 | 372 | #ifdef CONFIG_X86_32 |
e4b71dcf | 373 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
374 | struct page *page; |
375 | ||
e3ed910d | 376 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
377 | pgd_t *pgd; |
378 | pud_t *pud; | |
379 | pmd_t *pmd; | |
380 | ||
381 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
382 | pud = pud_offset(pgd, address); | |
383 | pmd = pmd_offset(pud, address); | |
384 | set_pte_atomic((pte_t *)pmd, pte); | |
385 | } | |
1da177e4 | 386 | } |
44af6c41 | 387 | #endif |
1da177e4 LT |
388 | } |
389 | ||
9df84993 IM |
390 | static int |
391 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
392 | struct cpa_data *cpa) | |
65e074df | 393 | { |
c31c7d48 | 394 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
395 | pte_t new_pte, old_pte, *tmp; |
396 | pgprot_t old_prot, new_prot; | |
fac84939 | 397 | int i, do_split = 1; |
da7bfc50 | 398 | unsigned int level; |
65e074df | 399 | |
c9caa02c AK |
400 | if (cpa->force_split) |
401 | return 1; | |
402 | ||
65e074df TG |
403 | spin_lock_irqsave(&pgd_lock, flags); |
404 | /* | |
405 | * Check for races, another CPU might have split this page | |
406 | * up already: | |
407 | */ | |
408 | tmp = lookup_address(address, &level); | |
409 | if (tmp != kpte) | |
410 | goto out_unlock; | |
411 | ||
412 | switch (level) { | |
413 | case PG_LEVEL_2M: | |
31422c51 AK |
414 | psize = PMD_PAGE_SIZE; |
415 | pmask = PMD_PAGE_MASK; | |
65e074df | 416 | break; |
f07333fd | 417 | #ifdef CONFIG_X86_64 |
65e074df | 418 | case PG_LEVEL_1G: |
5d3c8b21 AK |
419 | psize = PUD_PAGE_SIZE; |
420 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
421 | break; |
422 | #endif | |
65e074df | 423 | default: |
beaff633 | 424 | do_split = -EINVAL; |
65e074df TG |
425 | goto out_unlock; |
426 | } | |
427 | ||
428 | /* | |
429 | * Calculate the number of pages, which fit into this large | |
430 | * page starting at address: | |
431 | */ | |
432 | nextpage_addr = (address + psize) & pmask; | |
433 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
434 | if (numpages < cpa->numpages) |
435 | cpa->numpages = numpages; | |
65e074df TG |
436 | |
437 | /* | |
438 | * We are safe now. Check whether the new pgprot is the same: | |
439 | */ | |
440 | old_pte = *kpte; | |
441 | old_prot = new_prot = pte_pgprot(old_pte); | |
442 | ||
443 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
444 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
445 | |
446 | /* | |
447 | * old_pte points to the large page base address. So we need | |
448 | * to add the offset of the virtual address: | |
449 | */ | |
450 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
451 | cpa->pfn = pfn; | |
452 | ||
453 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 454 | |
fac84939 TG |
455 | /* |
456 | * We need to check the full range, whether | |
457 | * static_protection() requires a different pgprot for one of | |
458 | * the pages in the range we try to preserve: | |
459 | */ | |
460 | addr = address + PAGE_SIZE; | |
c31c7d48 | 461 | pfn++; |
9b5cf48b | 462 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 463 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
464 | |
465 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
466 | goto out_unlock; | |
467 | } | |
468 | ||
65e074df TG |
469 | /* |
470 | * If there are no changes, return. maxpages has been updated | |
471 | * above: | |
472 | */ | |
473 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 474 | do_split = 0; |
65e074df TG |
475 | goto out_unlock; |
476 | } | |
477 | ||
478 | /* | |
479 | * We need to change the attributes. Check, whether we can | |
480 | * change the large page in one go. We request a split, when | |
481 | * the address is not aligned and the number of pages is | |
482 | * smaller than the number of pages in the large page. Note | |
483 | * that we limited the number of possible pages already to | |
484 | * the number of pages in the large page. | |
485 | */ | |
9b5cf48b | 486 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
487 | /* |
488 | * The address is aligned and the number of pages | |
489 | * covers the full page. | |
490 | */ | |
491 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
492 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 493 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 494 | do_split = 0; |
65e074df TG |
495 | } |
496 | ||
497 | out_unlock: | |
498 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 499 | |
beaff633 | 500 | return do_split; |
65e074df TG |
501 | } |
502 | ||
7afe15b9 | 503 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 504 | { |
7b610eec | 505 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 506 | unsigned int i, level; |
bb5c2dbd | 507 | pte_t *pbase, *tmp; |
9df84993 | 508 | pgprot_t ref_prot; |
ad5ca55f SS |
509 | struct page *base; |
510 | ||
511 | if (!debug_pagealloc) | |
512 | spin_unlock(&cpa_lock); | |
9e730237 | 513 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
514 | if (!debug_pagealloc) |
515 | spin_lock(&cpa_lock); | |
8311eb84 SS |
516 | if (!base) |
517 | return -ENOMEM; | |
bb5c2dbd | 518 | |
eb5b5f02 | 519 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
520 | /* |
521 | * Check for races, another CPU might have split this page | |
522 | * up for us already: | |
523 | */ | |
524 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 525 | if (tmp != kpte) |
bb5c2dbd IM |
526 | goto out_unlock; |
527 | ||
bb5c2dbd | 528 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 529 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 530 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
531 | /* |
532 | * If we ever want to utilize the PAT bit, we need to | |
533 | * update this function to make sure it's converted from | |
534 | * bit 12 to bit 7 when we cross from the 2MB level to | |
535 | * the 4K level: | |
536 | */ | |
537 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 538 | |
f07333fd AK |
539 | #ifdef CONFIG_X86_64 |
540 | if (level == PG_LEVEL_1G) { | |
541 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
542 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
543 | } |
544 | #endif | |
545 | ||
63c1dcf4 TG |
546 | /* |
547 | * Get the target pfn from the original entry: | |
548 | */ | |
549 | pfn = pte_pfn(*kpte); | |
f07333fd | 550 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 551 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 552 | |
ce0c0e50 | 553 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
554 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
555 | split_page_count(level); | |
556 | ||
557 | #ifdef CONFIG_X86_64 | |
558 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
559 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
560 | split_page_count(level); | |
f361a450 | 561 | #endif |
ce0c0e50 | 562 | |
bb5c2dbd | 563 | /* |
07a66d7c | 564 | * Install the new, split up pagetable. |
4c881ca1 | 565 | * |
07a66d7c IM |
566 | * We use the standard kernel pagetable protections for the new |
567 | * pagetable protections, the actual ptes set above control the | |
568 | * primary protection behavior: | |
bb5c2dbd | 569 | */ |
07a66d7c | 570 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
571 | |
572 | /* | |
573 | * Intel Atom errata AAH41 workaround. | |
574 | * | |
575 | * The real fix should be in hw or in a microcode update, but | |
576 | * we also probabilistically try to reduce the window of having | |
577 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
578 | * going on. | |
579 | */ | |
580 | __flush_tlb_all(); | |
581 | ||
bb5c2dbd IM |
582 | base = NULL; |
583 | ||
584 | out_unlock: | |
eb5b5f02 TG |
585 | /* |
586 | * If we dropped out via the lookup_address check under | |
587 | * pgd_lock then stick the page back into the pool: | |
588 | */ | |
8311eb84 SS |
589 | if (base) |
590 | __free_page(base); | |
9a3dc780 | 591 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 592 | |
bb5c2dbd IM |
593 | return 0; |
594 | } | |
595 | ||
a1e46212 SS |
596 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
597 | int primary) | |
598 | { | |
599 | /* | |
600 | * Ignore all non primary paths. | |
601 | */ | |
602 | if (!primary) | |
603 | return 0; | |
604 | ||
605 | /* | |
606 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
607 | * to have holes. | |
608 | * Also set numpages to '1' indicating that we processed cpa req for | |
609 | * one virtual address page and its pfn. TBD: numpages can be set based | |
610 | * on the initial value and the level returned by lookup_address(). | |
611 | */ | |
612 | if (within(vaddr, PAGE_OFFSET, | |
613 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
614 | cpa->numpages = 1; | |
615 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
616 | return 0; | |
617 | } else { | |
618 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
619 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
620 | *cpa->vaddr); | |
621 | ||
622 | return -EFAULT; | |
623 | } | |
624 | } | |
625 | ||
c31c7d48 | 626 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 627 | { |
d75586ad | 628 | unsigned long address; |
da7bfc50 HH |
629 | int do_split, err; |
630 | unsigned int level; | |
c31c7d48 | 631 | pte_t *kpte, old_pte; |
1da177e4 | 632 | |
8523acfe TH |
633 | if (cpa->flags & CPA_PAGES_ARRAY) { |
634 | struct page *page = cpa->pages[cpa->curpage]; | |
635 | if (unlikely(PageHighMem(page))) | |
636 | return 0; | |
637 | address = (unsigned long)page_address(page); | |
638 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
639 | address = cpa->vaddr[cpa->curpage]; |
640 | else | |
641 | address = *cpa->vaddr; | |
97f99fed | 642 | repeat: |
f0646e43 | 643 | kpte = lookup_address(address, &level); |
1da177e4 | 644 | if (!kpte) |
a1e46212 | 645 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
646 | |
647 | old_pte = *kpte; | |
a1e46212 SS |
648 | if (!pte_val(old_pte)) |
649 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 650 | |
30551bb3 | 651 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 652 | pte_t new_pte; |
626c2c9d | 653 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 654 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 655 | |
72e458df TG |
656 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
657 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 658 | |
c31c7d48 | 659 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 660 | |
626c2c9d AV |
661 | /* |
662 | * We need to keep the pfn from the existing PTE, | |
663 | * after all we're only going to change it's attributes | |
664 | * not the memory it points to | |
665 | */ | |
c31c7d48 TG |
666 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
667 | cpa->pfn = pfn; | |
f4ae5da0 TG |
668 | /* |
669 | * Do we really change anything ? | |
670 | */ | |
671 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
672 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 673 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 674 | } |
9b5cf48b | 675 | cpa->numpages = 1; |
65e074df | 676 | return 0; |
1da177e4 | 677 | } |
65e074df TG |
678 | |
679 | /* | |
680 | * Check, whether we can keep the large page intact | |
681 | * and just change the pte: | |
682 | */ | |
beaff633 | 683 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
684 | /* |
685 | * When the range fits into the existing large page, | |
9b5cf48b | 686 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
687 | * try_large_page: |
688 | */ | |
87f7f8fe IM |
689 | if (do_split <= 0) |
690 | return do_split; | |
65e074df TG |
691 | |
692 | /* | |
693 | * We have to split the large page: | |
694 | */ | |
87f7f8fe IM |
695 | err = split_large_page(kpte, address); |
696 | if (!err) { | |
ad5ca55f SS |
697 | /* |
698 | * Do a global flush tlb after splitting the large page | |
699 | * and before we do the actual change page attribute in the PTE. | |
700 | * | |
701 | * With out this, we violate the TLB application note, that says | |
702 | * "The TLBs may contain both ordinary and large-page | |
703 | * translations for a 4-KByte range of linear addresses. This | |
704 | * may occur if software modifies the paging structures so that | |
705 | * the page size used for the address range changes. If the two | |
706 | * translations differ with respect to page frame or attributes | |
707 | * (e.g., permissions), processor behavior is undefined and may | |
708 | * be implementation-specific." | |
709 | * | |
710 | * We do this global tlb flush inside the cpa_lock, so that we | |
711 | * don't allow any other cpu, with stale tlb entries change the | |
712 | * page attribute in parallel, that also falls into the | |
713 | * just split large page entry. | |
714 | */ | |
715 | flush_tlb_all(); | |
87f7f8fe IM |
716 | goto repeat; |
717 | } | |
beaff633 | 718 | |
87f7f8fe | 719 | return err; |
9f4c815c | 720 | } |
1da177e4 | 721 | |
c31c7d48 TG |
722 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
723 | ||
724 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 725 | { |
c31c7d48 | 726 | struct cpa_data alias_cpa; |
992f4c1c | 727 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 728 | unsigned long vaddr; |
992f4c1c | 729 | int ret; |
44af6c41 | 730 | |
965194c1 | 731 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 732 | return 0; |
626c2c9d | 733 | |
f361a450 | 734 | #ifdef CONFIG_X86_64 |
965194c1 | 735 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
736 | return 0; |
737 | #endif | |
f34b439f TG |
738 | /* |
739 | * No need to redo, when the primary call touched the direct | |
740 | * mapping already: | |
741 | */ | |
8523acfe TH |
742 | if (cpa->flags & CPA_PAGES_ARRAY) { |
743 | struct page *page = cpa->pages[cpa->curpage]; | |
744 | if (unlikely(PageHighMem(page))) | |
745 | return 0; | |
746 | vaddr = (unsigned long)page_address(page); | |
747 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
748 | vaddr = cpa->vaddr[cpa->curpage]; |
749 | else | |
750 | vaddr = *cpa->vaddr; | |
751 | ||
752 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 753 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 754 | |
f34b439f | 755 | alias_cpa = *cpa; |
992f4c1c | 756 | alias_cpa.vaddr = &laddr; |
9ae28475 | 757 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 758 | |
f34b439f | 759 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
760 | if (ret) |
761 | return ret; | |
f34b439f | 762 | } |
44af6c41 | 763 | |
44af6c41 | 764 | #ifdef CONFIG_X86_64 |
488fd995 | 765 | /* |
992f4c1c TH |
766 | * If the primary call didn't touch the high mapping already |
767 | * and the physical address is inside the kernel map, we need | |
0879750f | 768 | * to touch the high mapped kernel as well: |
488fd995 | 769 | */ |
992f4c1c TH |
770 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
771 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
772 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
773 | __START_KERNEL_map - phys_base; | |
774 | alias_cpa = *cpa; | |
775 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
776 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 777 | |
992f4c1c TH |
778 | /* |
779 | * The high mapping range is imprecise, so ignore the | |
780 | * return value. | |
781 | */ | |
782 | __change_page_attr_set_clr(&alias_cpa, 0); | |
783 | } | |
488fd995 | 784 | #endif |
992f4c1c TH |
785 | |
786 | return 0; | |
1da177e4 LT |
787 | } |
788 | ||
c31c7d48 | 789 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 790 | { |
65e074df | 791 | int ret, numpages = cpa->numpages; |
ff31452b | 792 | |
65e074df TG |
793 | while (numpages) { |
794 | /* | |
795 | * Store the remaining nr of pages for the large page | |
796 | * preservation check. | |
797 | */ | |
9b5cf48b | 798 | cpa->numpages = numpages; |
d75586ad | 799 | /* for array changes, we can't use large page */ |
9ae28475 | 800 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 801 | cpa->numpages = 1; |
c31c7d48 | 802 | |
ad5ca55f SS |
803 | if (!debug_pagealloc) |
804 | spin_lock(&cpa_lock); | |
c31c7d48 | 805 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
806 | if (!debug_pagealloc) |
807 | spin_unlock(&cpa_lock); | |
ff31452b TG |
808 | if (ret) |
809 | return ret; | |
ff31452b | 810 | |
c31c7d48 TG |
811 | if (checkalias) { |
812 | ret = cpa_process_alias(cpa); | |
813 | if (ret) | |
814 | return ret; | |
815 | } | |
816 | ||
65e074df TG |
817 | /* |
818 | * Adjust the number of pages with the result of the | |
819 | * CPA operation. Either a large page has been | |
820 | * preserved or a single page update happened. | |
821 | */ | |
9b5cf48b RW |
822 | BUG_ON(cpa->numpages > numpages); |
823 | numpages -= cpa->numpages; | |
9ae28475 | 824 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
825 | cpa->curpage++; |
826 | else | |
827 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
828 | ||
65e074df | 829 | } |
ff31452b TG |
830 | return 0; |
831 | } | |
832 | ||
6bb8383b AK |
833 | static inline int cache_attr(pgprot_t attr) |
834 | { | |
835 | return pgprot_val(attr) & | |
836 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
837 | } | |
838 | ||
d75586ad | 839 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 840 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 841 | int force_split, int in_flag, |
842 | struct page **pages) | |
ff31452b | 843 | { |
72e458df | 844 | struct cpa_data cpa; |
cacf8906 | 845 | int ret, cache, checkalias; |
fa526d0d | 846 | unsigned long baddr = 0; |
331e4065 TG |
847 | |
848 | /* | |
849 | * Check, if we are requested to change a not supported | |
850 | * feature: | |
851 | */ | |
852 | mask_set = canon_pgprot(mask_set); | |
853 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 854 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
855 | return 0; |
856 | ||
69b1415e | 857 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 858 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
859 | int i; |
860 | for (i = 0; i < numpages; i++) { | |
861 | if (addr[i] & ~PAGE_MASK) { | |
862 | addr[i] &= PAGE_MASK; | |
863 | WARN_ON_ONCE(1); | |
864 | } | |
865 | } | |
9ae28475 | 866 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
867 | /* | |
868 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
869 | * No need to cehck in that case | |
870 | */ | |
871 | if (*addr & ~PAGE_MASK) { | |
872 | *addr &= PAGE_MASK; | |
873 | /* | |
874 | * People should not be passing in unaligned addresses: | |
875 | */ | |
876 | WARN_ON_ONCE(1); | |
877 | } | |
fa526d0d JS |
878 | /* |
879 | * Save address for cache flush. *addr is modified in the call | |
880 | * to __change_page_attr_set_clr() below. | |
881 | */ | |
882 | baddr = *addr; | |
69b1415e TG |
883 | } |
884 | ||
5843d9a4 NP |
885 | /* Must avoid aliasing mappings in the highmem code */ |
886 | kmap_flush_unused(); | |
887 | ||
db64fe02 NP |
888 | vm_unmap_aliases(); |
889 | ||
72e458df | 890 | cpa.vaddr = addr; |
9ae28475 | 891 | cpa.pages = pages; |
72e458df TG |
892 | cpa.numpages = numpages; |
893 | cpa.mask_set = mask_set; | |
894 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
895 | cpa.flags = 0; |
896 | cpa.curpage = 0; | |
c9caa02c | 897 | cpa.force_split = force_split; |
72e458df | 898 | |
9ae28475 | 899 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
900 | cpa.flags |= in_flag; | |
d75586ad | 901 | |
af96e443 TG |
902 | /* No alias checking for _NX bit modifications */ |
903 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
904 | ||
905 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 906 | |
f4ae5da0 TG |
907 | /* |
908 | * Check whether we really changed something: | |
909 | */ | |
d75586ad | 910 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 911 | goto out; |
cacf8906 | 912 | |
6bb8383b AK |
913 | /* |
914 | * No need to flush, when we did not set any of the caching | |
915 | * attributes: | |
916 | */ | |
917 | cache = cache_attr(mask_set); | |
918 | ||
57a6a46a TG |
919 | /* |
920 | * On success we use clflush, when the CPU supports it to | |
921 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 922 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
923 | * wbindv): |
924 | */ | |
d75586ad | 925 | if (!ret && cpu_has_clflush) { |
9ae28475 | 926 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
927 | cpa_flush_array(addr, numpages, cache, | |
928 | cpa.flags, pages); | |
929 | } else | |
fa526d0d | 930 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 931 | } else |
6bb8383b | 932 | cpa_flush_all(cache); |
cacf8906 | 933 | |
76ebd054 | 934 | out: |
ff31452b TG |
935 | return ret; |
936 | } | |
937 | ||
d75586ad SL |
938 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
939 | pgprot_t mask, int array) | |
75cbade8 | 940 | { |
d75586ad | 941 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 942 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
943 | } |
944 | ||
d75586ad SL |
945 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
946 | pgprot_t mask, int array) | |
72932c7a | 947 | { |
d75586ad | 948 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 949 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
950 | } |
951 | ||
0f350755 | 952 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
953 | pgprot_t mask) | |
954 | { | |
955 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
956 | CPA_PAGES_ARRAY, pages); | |
957 | } | |
958 | ||
959 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
960 | pgprot_t mask) | |
961 | { | |
962 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
963 | CPA_PAGES_ARRAY, pages); | |
964 | } | |
965 | ||
1219333d | 966 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 967 | { |
de33c442 SS |
968 | /* |
969 | * for now UC MINUS. see comments in ioremap_nocache() | |
970 | */ | |
d75586ad SL |
971 | return change_page_attr_set(&addr, numpages, |
972 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 973 | } |
1219333d | 974 | |
975 | int set_memory_uc(unsigned long addr, int numpages) | |
976 | { | |
9fa3ab39 | 977 | int ret; |
978 | ||
de33c442 SS |
979 | /* |
980 | * for now UC MINUS. see comments in ioremap_nocache() | |
981 | */ | |
9fa3ab39 | 982 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
983 | _PAGE_CACHE_UC_MINUS, NULL); | |
984 | if (ret) | |
985 | goto out_err; | |
986 | ||
987 | ret = _set_memory_uc(addr, numpages); | |
988 | if (ret) | |
989 | goto out_free; | |
990 | ||
991 | return 0; | |
1219333d | 992 | |
9fa3ab39 | 993 | out_free: |
994 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
995 | out_err: | |
996 | return ret; | |
1219333d | 997 | } |
75cbade8 AV |
998 | EXPORT_SYMBOL(set_memory_uc); |
999 | ||
d75586ad SL |
1000 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
1001 | { | |
9fa3ab39 | 1002 | int i, j; |
1003 | int ret; | |
1004 | ||
d75586ad SL |
1005 | /* |
1006 | * for now UC MINUS. see comments in ioremap_nocache() | |
1007 | */ | |
1008 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 1009 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
1010 | _PAGE_CACHE_UC_MINUS, NULL); | |
1011 | if (ret) | |
1012 | goto out_free; | |
d75586ad SL |
1013 | } |
1014 | ||
9fa3ab39 | 1015 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 1016 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
9fa3ab39 | 1017 | if (ret) |
1018 | goto out_free; | |
1019 | ||
1020 | return 0; | |
1021 | ||
1022 | out_free: | |
1023 | for (j = 0; j < i; j++) | |
1024 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1025 | ||
1026 | return ret; | |
d75586ad SL |
1027 | } |
1028 | EXPORT_SYMBOL(set_memory_array_uc); | |
1029 | ||
ef354af4 | 1030 | int _set_memory_wc(unsigned long addr, int numpages) |
1031 | { | |
3869c4aa | 1032 | int ret; |
bdc6340f PV |
1033 | unsigned long addr_copy = addr; |
1034 | ||
3869c4aa | 1035 | ret = change_page_attr_set(&addr, numpages, |
1036 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1037 | if (!ret) { |
bdc6340f PV |
1038 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1039 | __pgprot(_PAGE_CACHE_WC), | |
1040 | __pgprot(_PAGE_CACHE_MASK), | |
1041 | 0, 0, NULL); | |
3869c4aa | 1042 | } |
1043 | return ret; | |
ef354af4 | 1044 | } |
1045 | ||
1046 | int set_memory_wc(unsigned long addr, int numpages) | |
1047 | { | |
9fa3ab39 | 1048 | int ret; |
1049 | ||
499f8f84 | 1050 | if (!pat_enabled) |
ef354af4 | 1051 | return set_memory_uc(addr, numpages); |
1052 | ||
9fa3ab39 | 1053 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1054 | _PAGE_CACHE_WC, NULL); | |
1055 | if (ret) | |
1056 | goto out_err; | |
ef354af4 | 1057 | |
9fa3ab39 | 1058 | ret = _set_memory_wc(addr, numpages); |
1059 | if (ret) | |
1060 | goto out_free; | |
1061 | ||
1062 | return 0; | |
1063 | ||
1064 | out_free: | |
1065 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1066 | out_err: | |
1067 | return ret; | |
ef354af4 | 1068 | } |
1069 | EXPORT_SYMBOL(set_memory_wc); | |
1070 | ||
1219333d | 1071 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1072 | { |
d75586ad SL |
1073 | return change_page_attr_clear(&addr, numpages, |
1074 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1075 | } |
1219333d | 1076 | |
1077 | int set_memory_wb(unsigned long addr, int numpages) | |
1078 | { | |
9fa3ab39 | 1079 | int ret; |
1080 | ||
1081 | ret = _set_memory_wb(addr, numpages); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
c15238df | 1085 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1086 | return 0; |
1219333d | 1087 | } |
75cbade8 AV |
1088 | EXPORT_SYMBOL(set_memory_wb); |
1089 | ||
d75586ad SL |
1090 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1091 | { | |
1092 | int i; | |
a5593e0b | 1093 | int ret; |
1094 | ||
1095 | ret = change_page_attr_clear(addr, addrinarray, | |
1096 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1097 | if (ret) |
1098 | return ret; | |
d75586ad | 1099 | |
9fa3ab39 | 1100 | for (i = 0; i < addrinarray; i++) |
1101 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1102 | |
9fa3ab39 | 1103 | return 0; |
d75586ad SL |
1104 | } |
1105 | EXPORT_SYMBOL(set_memory_array_wb); | |
1106 | ||
75cbade8 AV |
1107 | int set_memory_x(unsigned long addr, int numpages) |
1108 | { | |
583140af PA |
1109 | if (!(__supported_pte_mask & _PAGE_NX)) |
1110 | return 0; | |
1111 | ||
d75586ad | 1112 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1113 | } |
1114 | EXPORT_SYMBOL(set_memory_x); | |
1115 | ||
1116 | int set_memory_nx(unsigned long addr, int numpages) | |
1117 | { | |
583140af PA |
1118 | if (!(__supported_pte_mask & _PAGE_NX)) |
1119 | return 0; | |
1120 | ||
d75586ad | 1121 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1122 | } |
1123 | EXPORT_SYMBOL(set_memory_nx); | |
1124 | ||
1125 | int set_memory_ro(unsigned long addr, int numpages) | |
1126 | { | |
d75586ad | 1127 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1128 | } |
a03352d2 | 1129 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1130 | |
1131 | int set_memory_rw(unsigned long addr, int numpages) | |
1132 | { | |
d75586ad | 1133 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1134 | } |
a03352d2 | 1135 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1136 | |
1137 | int set_memory_np(unsigned long addr, int numpages) | |
1138 | { | |
d75586ad | 1139 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1140 | } |
75cbade8 | 1141 | |
c9caa02c AK |
1142 | int set_memory_4k(unsigned long addr, int numpages) |
1143 | { | |
d75586ad | 1144 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1145 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1146 | } |
1147 | ||
75cbade8 AV |
1148 | int set_pages_uc(struct page *page, int numpages) |
1149 | { | |
1150 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1151 | |
d7c8f21a | 1152 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1153 | } |
1154 | EXPORT_SYMBOL(set_pages_uc); | |
1155 | ||
0f350755 | 1156 | int set_pages_array_uc(struct page **pages, int addrinarray) |
1157 | { | |
1158 | unsigned long start; | |
1159 | unsigned long end; | |
1160 | int i; | |
1161 | int free_idx; | |
1162 | ||
1163 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1164 | if (PageHighMem(pages[i])) |
1165 | continue; | |
1166 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1167 | end = start + PAGE_SIZE; |
1168 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
1169 | goto err_out; | |
1170 | } | |
1171 | ||
1172 | if (cpa_set_pages_array(pages, addrinarray, | |
1173 | __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) { | |
1174 | return 0; /* Success */ | |
1175 | } | |
1176 | err_out: | |
1177 | free_idx = i; | |
1178 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1179 | if (PageHighMem(pages[i])) |
1180 | continue; | |
1181 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1182 | end = start + PAGE_SIZE; |
1183 | free_memtype(start, end); | |
1184 | } | |
1185 | return -EINVAL; | |
1186 | } | |
1187 | EXPORT_SYMBOL(set_pages_array_uc); | |
1188 | ||
75cbade8 AV |
1189 | int set_pages_wb(struct page *page, int numpages) |
1190 | { | |
1191 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1192 | |
d7c8f21a | 1193 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1194 | } |
1195 | EXPORT_SYMBOL(set_pages_wb); | |
1196 | ||
0f350755 | 1197 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1198 | { | |
1199 | int retval; | |
1200 | unsigned long start; | |
1201 | unsigned long end; | |
1202 | int i; | |
1203 | ||
1204 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1205 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1206 | if (retval) |
1207 | return retval; | |
0f350755 | 1208 | |
1209 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1210 | if (PageHighMem(pages[i])) |
1211 | continue; | |
1212 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1213 | end = start + PAGE_SIZE; |
1214 | free_memtype(start, end); | |
1215 | } | |
1216 | ||
9fa3ab39 | 1217 | return 0; |
0f350755 | 1218 | } |
1219 | EXPORT_SYMBOL(set_pages_array_wb); | |
1220 | ||
75cbade8 AV |
1221 | int set_pages_x(struct page *page, int numpages) |
1222 | { | |
1223 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1224 | |
d7c8f21a | 1225 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1226 | } |
1227 | EXPORT_SYMBOL(set_pages_x); | |
1228 | ||
1229 | int set_pages_nx(struct page *page, int numpages) | |
1230 | { | |
1231 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1232 | |
d7c8f21a | 1233 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1234 | } |
1235 | EXPORT_SYMBOL(set_pages_nx); | |
1236 | ||
1237 | int set_pages_ro(struct page *page, int numpages) | |
1238 | { | |
1239 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1240 | |
d7c8f21a | 1241 | return set_memory_ro(addr, numpages); |
75cbade8 | 1242 | } |
75cbade8 AV |
1243 | |
1244 | int set_pages_rw(struct page *page, int numpages) | |
1245 | { | |
1246 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1247 | |
d7c8f21a | 1248 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1249 | } |
1250 | ||
1da177e4 | 1251 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1252 | |
1253 | static int __set_pages_p(struct page *page, int numpages) | |
1254 | { | |
d75586ad SL |
1255 | unsigned long tempaddr = (unsigned long) page_address(page); |
1256 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1257 | .numpages = numpages, |
1258 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1259 | .mask_clr = __pgprot(0), |
1260 | .flags = 0}; | |
72932c7a | 1261 | |
55121b43 SS |
1262 | /* |
1263 | * No alias checking needed for setting present flag. otherwise, | |
1264 | * we may need to break large pages for 64-bit kernel text | |
1265 | * mappings (this adds to complexity if we want to do this from | |
1266 | * atomic context especially). Let's keep it simple! | |
1267 | */ | |
1268 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1269 | } |
1270 | ||
1271 | static int __set_pages_np(struct page *page, int numpages) | |
1272 | { | |
d75586ad SL |
1273 | unsigned long tempaddr = (unsigned long) page_address(page); |
1274 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1275 | .numpages = numpages, |
1276 | .mask_set = __pgprot(0), | |
d75586ad SL |
1277 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1278 | .flags = 0}; | |
72932c7a | 1279 | |
55121b43 SS |
1280 | /* |
1281 | * No alias checking needed for setting not present flag. otherwise, | |
1282 | * we may need to break large pages for 64-bit kernel text | |
1283 | * mappings (this adds to complexity if we want to do this from | |
1284 | * atomic context especially). Let's keep it simple! | |
1285 | */ | |
1286 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1287 | } |
1288 | ||
1da177e4 LT |
1289 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1290 | { | |
1291 | if (PageHighMem(page)) | |
1292 | return; | |
9f4c815c | 1293 | if (!enable) { |
f9b8404c IM |
1294 | debug_check_no_locks_freed(page_address(page), |
1295 | numpages * PAGE_SIZE); | |
9f4c815c | 1296 | } |
de5097c2 | 1297 | |
12d6f21e IM |
1298 | /* |
1299 | * If page allocator is not up yet then do not call c_p_a(): | |
1300 | */ | |
1301 | if (!debug_pagealloc_enabled) | |
1302 | return; | |
1303 | ||
9f4c815c | 1304 | /* |
f8d8406b | 1305 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1306 | * Large pages for identity mappings are not used at boot time |
1307 | * and hence no memory allocations during large page split. | |
1da177e4 | 1308 | */ |
f62d0f00 IM |
1309 | if (enable) |
1310 | __set_pages_p(page, numpages); | |
1311 | else | |
1312 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1313 | |
1314 | /* | |
e4b71dcf IM |
1315 | * We should perform an IPI and flush all tlbs, |
1316 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1317 | */ |
1318 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1319 | } |
1320 | ||
8a235efa RW |
1321 | #ifdef CONFIG_HIBERNATION |
1322 | ||
1323 | bool kernel_page_present(struct page *page) | |
1324 | { | |
1325 | unsigned int level; | |
1326 | pte_t *pte; | |
1327 | ||
1328 | if (PageHighMem(page)) | |
1329 | return false; | |
1330 | ||
1331 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1332 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1333 | } | |
1334 | ||
1335 | #endif /* CONFIG_HIBERNATION */ | |
1336 | ||
1337 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1338 | |
1339 | /* | |
1340 | * The testcases use internal knowledge of the implementation that shouldn't | |
1341 | * be exposed to the rest of the kernel. Include these directly here. | |
1342 | */ | |
1343 | #ifdef CONFIG_CPA_DEBUG | |
1344 | #include "pageattr-test.c" | |
1345 | #endif |