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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
9f4c815c IM |
19 | #include <asm/uaccess.h> |
20 | #include <asm/pgalloc.h> | |
c31c7d48 | 21 | #include <asm/proto.h> |
1219333d | 22 | #include <asm/pat.h> |
1da177e4 | 23 | |
9df84993 IM |
24 | /* |
25 | * The current flushing context - we pass it instead of 5 arguments: | |
26 | */ | |
72e458df TG |
27 | struct cpa_data { |
28 | unsigned long vaddr; | |
72e458df TG |
29 | pgprot_t mask_set; |
30 | pgprot_t mask_clr; | |
65e074df | 31 | int numpages; |
f4ae5da0 | 32 | int flushtlb; |
c31c7d48 | 33 | unsigned long pfn; |
c9caa02c | 34 | unsigned force_split : 1; |
72e458df TG |
35 | }; |
36 | ||
c31c7d48 TG |
37 | #ifdef CONFIG_X86_64 |
38 | ||
39 | static inline unsigned long highmap_start_pfn(void) | |
40 | { | |
41 | return __pa(_text) >> PAGE_SHIFT; | |
42 | } | |
43 | ||
44 | static inline unsigned long highmap_end_pfn(void) | |
45 | { | |
46 | return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT; | |
47 | } | |
48 | ||
49 | #endif | |
50 | ||
92cb54a3 IM |
51 | #ifdef CONFIG_DEBUG_PAGEALLOC |
52 | # define debug_pagealloc 1 | |
53 | #else | |
54 | # define debug_pagealloc 0 | |
55 | #endif | |
56 | ||
ed724be6 AV |
57 | static inline int |
58 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 59 | { |
ed724be6 AV |
60 | return addr >= start && addr < end; |
61 | } | |
62 | ||
d7c8f21a TG |
63 | /* |
64 | * Flushing functions | |
65 | */ | |
cd8ddf1a | 66 | |
cd8ddf1a TG |
67 | /** |
68 | * clflush_cache_range - flush a cache range with clflush | |
69 | * @addr: virtual start address | |
70 | * @size: number of bytes to flush | |
71 | * | |
72 | * clflush is an unordered instruction which needs fencing with mfence | |
73 | * to avoid ordering issues. | |
74 | */ | |
4c61afcd | 75 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 76 | { |
4c61afcd | 77 | void *vend = vaddr + size - 1; |
d7c8f21a | 78 | |
cd8ddf1a | 79 | mb(); |
4c61afcd IM |
80 | |
81 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
82 | clflush(vaddr); | |
83 | /* | |
84 | * Flush any possible final partial cacheline: | |
85 | */ | |
86 | clflush(vend); | |
87 | ||
cd8ddf1a | 88 | mb(); |
d7c8f21a TG |
89 | } |
90 | ||
af1e6844 | 91 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 92 | { |
6bb8383b AK |
93 | unsigned long cache = (unsigned long)arg; |
94 | ||
d7c8f21a TG |
95 | /* |
96 | * Flush all to work around Errata in early athlons regarding | |
97 | * large page flushing. | |
98 | */ | |
99 | __flush_tlb_all(); | |
100 | ||
6bb8383b | 101 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
102 | wbinvd(); |
103 | } | |
104 | ||
6bb8383b | 105 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
106 | { |
107 | BUG_ON(irqs_disabled()); | |
108 | ||
6bb8383b | 109 | on_each_cpu(__cpa_flush_all, (void *) cache, 1, 1); |
d7c8f21a TG |
110 | } |
111 | ||
57a6a46a TG |
112 | static void __cpa_flush_range(void *arg) |
113 | { | |
57a6a46a TG |
114 | /* |
115 | * We could optimize that further and do individual per page | |
116 | * tlb invalidates for a low number of pages. Caveat: we must | |
117 | * flush the high aliases on 64bit as well. | |
118 | */ | |
119 | __flush_tlb_all(); | |
57a6a46a TG |
120 | } |
121 | ||
6bb8383b | 122 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 123 | { |
4c61afcd IM |
124 | unsigned int i, level; |
125 | unsigned long addr; | |
126 | ||
57a6a46a | 127 | BUG_ON(irqs_disabled()); |
4c61afcd | 128 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 129 | |
3b233e52 | 130 | on_each_cpu(__cpa_flush_range, NULL, 1, 1); |
57a6a46a | 131 | |
6bb8383b AK |
132 | if (!cache) |
133 | return; | |
134 | ||
3b233e52 TG |
135 | /* |
136 | * We only need to flush on one CPU, | |
137 | * clflush is a MESI-coherent instruction that | |
138 | * will cause all other CPUs to flush the same | |
139 | * cachelines: | |
140 | */ | |
4c61afcd IM |
141 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
142 | pte_t *pte = lookup_address(addr, &level); | |
143 | ||
144 | /* | |
145 | * Only flush present addresses: | |
146 | */ | |
7bfb72e8 | 147 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
148 | clflush_cache_range((void *) addr, PAGE_SIZE); |
149 | } | |
57a6a46a TG |
150 | } |
151 | ||
ed724be6 AV |
152 | /* |
153 | * Certain areas of memory on x86 require very specific protection flags, | |
154 | * for example the BIOS area or kernel text. Callers don't always get this | |
155 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
156 | * checks and fixes these known static required protection bits. | |
157 | */ | |
c31c7d48 TG |
158 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
159 | unsigned long pfn) | |
ed724be6 AV |
160 | { |
161 | pgprot_t forbidden = __pgprot(0); | |
162 | ||
687c4825 | 163 | /* |
ed724be6 AV |
164 | * The BIOS area between 640k and 1Mb needs to be executable for |
165 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 166 | */ |
c31c7d48 | 167 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
168 | pgprot_val(forbidden) |= _PAGE_NX; |
169 | ||
170 | /* | |
171 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
172 | * Does not cover __inittext since that is gone later on. On |
173 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
174 | */ |
175 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
176 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 177 | |
cc0f21bb | 178 | /* |
c31c7d48 TG |
179 | * The .rodata section needs to be read-only. Using the pfn |
180 | * catches all aliases. | |
cc0f21bb | 181 | */ |
c31c7d48 TG |
182 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
183 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 184 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
185 | |
186 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
187 | |
188 | return prot; | |
189 | } | |
190 | ||
9a14aefc TG |
191 | /* |
192 | * Lookup the page table entry for a virtual address. Return a pointer | |
193 | * to the entry and the level of the mapping. | |
194 | * | |
195 | * Note: We return pud and pmd either when the entry is marked large | |
196 | * or when the present bit is not set. Otherwise we would return a | |
197 | * pointer to a nonexisting mapping. | |
198 | */ | |
da7bfc50 | 199 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 200 | { |
1da177e4 LT |
201 | pgd_t *pgd = pgd_offset_k(address); |
202 | pud_t *pud; | |
203 | pmd_t *pmd; | |
9f4c815c | 204 | |
30551bb3 TG |
205 | *level = PG_LEVEL_NONE; |
206 | ||
1da177e4 LT |
207 | if (pgd_none(*pgd)) |
208 | return NULL; | |
9df84993 | 209 | |
1da177e4 LT |
210 | pud = pud_offset(pgd, address); |
211 | if (pud_none(*pud)) | |
212 | return NULL; | |
c2f71ee2 AK |
213 | |
214 | *level = PG_LEVEL_1G; | |
215 | if (pud_large(*pud) || !pud_present(*pud)) | |
216 | return (pte_t *)pud; | |
217 | ||
1da177e4 LT |
218 | pmd = pmd_offset(pud, address); |
219 | if (pmd_none(*pmd)) | |
220 | return NULL; | |
30551bb3 TG |
221 | |
222 | *level = PG_LEVEL_2M; | |
9a14aefc | 223 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 224 | return (pte_t *)pmd; |
1da177e4 | 225 | |
30551bb3 | 226 | *level = PG_LEVEL_4K; |
9df84993 | 227 | |
9f4c815c IM |
228 | return pte_offset_kernel(pmd, address); |
229 | } | |
230 | ||
9df84993 IM |
231 | /* |
232 | * Set the new pmd in all the pgds we know about: | |
233 | */ | |
9a3dc780 | 234 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 235 | { |
9f4c815c IM |
236 | /* change init_mm */ |
237 | set_pte_atomic(kpte, pte); | |
44af6c41 | 238 | #ifdef CONFIG_X86_32 |
e4b71dcf | 239 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
240 | struct page *page; |
241 | ||
e3ed910d | 242 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
243 | pgd_t *pgd; |
244 | pud_t *pud; | |
245 | pmd_t *pmd; | |
246 | ||
247 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
248 | pud = pud_offset(pgd, address); | |
249 | pmd = pmd_offset(pud, address); | |
250 | set_pte_atomic((pte_t *)pmd, pte); | |
251 | } | |
1da177e4 | 252 | } |
44af6c41 | 253 | #endif |
1da177e4 LT |
254 | } |
255 | ||
9df84993 IM |
256 | static int |
257 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
258 | struct cpa_data *cpa) | |
65e074df | 259 | { |
c31c7d48 | 260 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
261 | pte_t new_pte, old_pte, *tmp; |
262 | pgprot_t old_prot, new_prot; | |
fac84939 | 263 | int i, do_split = 1; |
da7bfc50 | 264 | unsigned int level; |
65e074df | 265 | |
c9caa02c AK |
266 | if (cpa->force_split) |
267 | return 1; | |
268 | ||
65e074df TG |
269 | spin_lock_irqsave(&pgd_lock, flags); |
270 | /* | |
271 | * Check for races, another CPU might have split this page | |
272 | * up already: | |
273 | */ | |
274 | tmp = lookup_address(address, &level); | |
275 | if (tmp != kpte) | |
276 | goto out_unlock; | |
277 | ||
278 | switch (level) { | |
279 | case PG_LEVEL_2M: | |
31422c51 AK |
280 | psize = PMD_PAGE_SIZE; |
281 | pmask = PMD_PAGE_MASK; | |
65e074df | 282 | break; |
f07333fd | 283 | #ifdef CONFIG_X86_64 |
65e074df | 284 | case PG_LEVEL_1G: |
5d3c8b21 AK |
285 | psize = PUD_PAGE_SIZE; |
286 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
287 | break; |
288 | #endif | |
65e074df | 289 | default: |
beaff633 | 290 | do_split = -EINVAL; |
65e074df TG |
291 | goto out_unlock; |
292 | } | |
293 | ||
294 | /* | |
295 | * Calculate the number of pages, which fit into this large | |
296 | * page starting at address: | |
297 | */ | |
298 | nextpage_addr = (address + psize) & pmask; | |
299 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
300 | if (numpages < cpa->numpages) |
301 | cpa->numpages = numpages; | |
65e074df TG |
302 | |
303 | /* | |
304 | * We are safe now. Check whether the new pgprot is the same: | |
305 | */ | |
306 | old_pte = *kpte; | |
307 | old_prot = new_prot = pte_pgprot(old_pte); | |
308 | ||
309 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
310 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
311 | |
312 | /* | |
313 | * old_pte points to the large page base address. So we need | |
314 | * to add the offset of the virtual address: | |
315 | */ | |
316 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
317 | cpa->pfn = pfn; | |
318 | ||
319 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 320 | |
fac84939 TG |
321 | /* |
322 | * We need to check the full range, whether | |
323 | * static_protection() requires a different pgprot for one of | |
324 | * the pages in the range we try to preserve: | |
325 | */ | |
326 | addr = address + PAGE_SIZE; | |
c31c7d48 | 327 | pfn++; |
9b5cf48b | 328 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 329 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
330 | |
331 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
332 | goto out_unlock; | |
333 | } | |
334 | ||
65e074df TG |
335 | /* |
336 | * If there are no changes, return. maxpages has been updated | |
337 | * above: | |
338 | */ | |
339 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 340 | do_split = 0; |
65e074df TG |
341 | goto out_unlock; |
342 | } | |
343 | ||
344 | /* | |
345 | * We need to change the attributes. Check, whether we can | |
346 | * change the large page in one go. We request a split, when | |
347 | * the address is not aligned and the number of pages is | |
348 | * smaller than the number of pages in the large page. Note | |
349 | * that we limited the number of possible pages already to | |
350 | * the number of pages in the large page. | |
351 | */ | |
9b5cf48b | 352 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
353 | /* |
354 | * The address is aligned and the number of pages | |
355 | * covers the full page. | |
356 | */ | |
357 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
358 | __set_pmd_pte(kpte, address, new_pte); | |
359 | cpa->flushtlb = 1; | |
beaff633 | 360 | do_split = 0; |
65e074df TG |
361 | } |
362 | ||
363 | out_unlock: | |
364 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 365 | |
beaff633 | 366 | return do_split; |
65e074df TG |
367 | } |
368 | ||
76ebd054 TG |
369 | static LIST_HEAD(page_pool); |
370 | static unsigned long pool_size, pool_pages, pool_low; | |
92cb54a3 | 371 | static unsigned long pool_used, pool_failed; |
76ebd054 | 372 | |
92cb54a3 | 373 | static void cpa_fill_pool(struct page **ret) |
76ebd054 | 374 | { |
76ebd054 | 375 | gfp_t gfp = GFP_KERNEL; |
92cb54a3 IM |
376 | unsigned long flags; |
377 | struct page *p; | |
76ebd054 | 378 | |
76ebd054 | 379 | /* |
92cb54a3 IM |
380 | * Avoid recursion (on debug-pagealloc) and also signal |
381 | * our priority to get to these pagetables: | |
76ebd054 | 382 | */ |
92cb54a3 | 383 | if (current->flags & PF_MEMALLOC) |
76ebd054 | 384 | return; |
92cb54a3 | 385 | current->flags |= PF_MEMALLOC; |
76ebd054 | 386 | |
76ebd054 | 387 | /* |
92cb54a3 | 388 | * Allocate atomically from atomic contexts: |
76ebd054 | 389 | */ |
92cb54a3 IM |
390 | if (in_atomic() || irqs_disabled() || debug_pagealloc) |
391 | gfp = GFP_ATOMIC | __GFP_NORETRY | __GFP_NOWARN; | |
76ebd054 | 392 | |
92cb54a3 | 393 | while (pool_pages < pool_size || (ret && !*ret)) { |
76ebd054 TG |
394 | p = alloc_pages(gfp, 0); |
395 | if (!p) { | |
396 | pool_failed++; | |
397 | break; | |
398 | } | |
92cb54a3 IM |
399 | /* |
400 | * If the call site needs a page right now, provide it: | |
401 | */ | |
402 | if (ret && !*ret) { | |
403 | *ret = p; | |
404 | continue; | |
405 | } | |
406 | spin_lock_irqsave(&pgd_lock, flags); | |
76ebd054 TG |
407 | list_add(&p->lru, &page_pool); |
408 | pool_pages++; | |
92cb54a3 | 409 | spin_unlock_irqrestore(&pgd_lock, flags); |
76ebd054 | 410 | } |
92cb54a3 IM |
411 | |
412 | current->flags &= ~PF_MEMALLOC; | |
76ebd054 TG |
413 | } |
414 | ||
415 | #define SHIFT_MB (20 - PAGE_SHIFT) | |
416 | #define ROUND_MB_GB ((1 << 10) - 1) | |
417 | #define SHIFT_MB_GB 10 | |
418 | #define POOL_PAGES_PER_GB 16 | |
419 | ||
420 | void __init cpa_init(void) | |
421 | { | |
422 | struct sysinfo si; | |
423 | unsigned long gb; | |
424 | ||
425 | si_meminfo(&si); | |
426 | /* | |
427 | * Calculate the number of pool pages: | |
428 | * | |
429 | * Convert totalram (nr of pages) to MiB and round to the next | |
430 | * GiB. Shift MiB to Gib and multiply the result by | |
431 | * POOL_PAGES_PER_GB: | |
432 | */ | |
92cb54a3 IM |
433 | if (debug_pagealloc) { |
434 | gb = ((si.totalram >> SHIFT_MB) + ROUND_MB_GB) >> SHIFT_MB_GB; | |
435 | pool_size = POOL_PAGES_PER_GB * gb; | |
436 | } else { | |
437 | pool_size = 1; | |
438 | } | |
76ebd054 TG |
439 | pool_low = pool_size; |
440 | ||
92cb54a3 | 441 | cpa_fill_pool(NULL); |
76ebd054 TG |
442 | printk(KERN_DEBUG |
443 | "CPA: page pool initialized %lu of %lu pages preallocated\n", | |
444 | pool_pages, pool_size); | |
445 | } | |
446 | ||
7afe15b9 | 447 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 448 | { |
7b610eec | 449 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 450 | unsigned int i, level; |
bb5c2dbd | 451 | pte_t *pbase, *tmp; |
9df84993 | 452 | pgprot_t ref_prot; |
bb5c2dbd IM |
453 | struct page *base; |
454 | ||
eb5b5f02 TG |
455 | /* |
456 | * Get a page from the pool. The pool list is protected by the | |
457 | * pgd_lock, which we have to take anyway for the split | |
458 | * operation: | |
459 | */ | |
460 | spin_lock_irqsave(&pgd_lock, flags); | |
461 | if (list_empty(&page_pool)) { | |
462 | spin_unlock_irqrestore(&pgd_lock, flags); | |
92cb54a3 IM |
463 | base = NULL; |
464 | cpa_fill_pool(&base); | |
465 | if (!base) | |
466 | return -ENOMEM; | |
467 | spin_lock_irqsave(&pgd_lock, flags); | |
468 | } else { | |
469 | base = list_first_entry(&page_pool, struct page, lru); | |
470 | list_del(&base->lru); | |
471 | pool_pages--; | |
472 | ||
473 | if (pool_pages < pool_low) | |
474 | pool_low = pool_pages; | |
eb5b5f02 TG |
475 | } |
476 | ||
bb5c2dbd IM |
477 | /* |
478 | * Check for races, another CPU might have split this page | |
479 | * up for us already: | |
480 | */ | |
481 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 482 | if (tmp != kpte) |
bb5c2dbd IM |
483 | goto out_unlock; |
484 | ||
bb5c2dbd IM |
485 | pbase = (pte_t *)page_address(base); |
486 | paravirt_alloc_pt(&init_mm, page_to_pfn(base)); | |
07cf89c0 | 487 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
bb5c2dbd | 488 | |
f07333fd AK |
489 | #ifdef CONFIG_X86_64 |
490 | if (level == PG_LEVEL_1G) { | |
491 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
492 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
493 | } |
494 | #endif | |
495 | ||
63c1dcf4 TG |
496 | /* |
497 | * Get the target pfn from the original entry: | |
498 | */ | |
499 | pfn = pte_pfn(*kpte); | |
f07333fd | 500 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 501 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd IM |
502 | |
503 | /* | |
07cf89c0 | 504 | * Install the new, split up pagetable. Important details here: |
4c881ca1 HY |
505 | * |
506 | * On Intel the NX bit of all levels must be cleared to make a | |
507 | * page executable. See section 4.13.2 of Intel 64 and IA-32 | |
508 | * Architectures Software Developer's Manual). | |
07cf89c0 TG |
509 | * |
510 | * Mark the entry present. The current mapping might be | |
511 | * set to not present, which we preserved above. | |
bb5c2dbd | 512 | */ |
4c881ca1 | 513 | ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); |
07cf89c0 | 514 | pgprot_val(ref_prot) |= _PAGE_PRESENT; |
9a3dc780 | 515 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
516 | base = NULL; |
517 | ||
518 | out_unlock: | |
eb5b5f02 TG |
519 | /* |
520 | * If we dropped out via the lookup_address check under | |
521 | * pgd_lock then stick the page back into the pool: | |
522 | */ | |
523 | if (base) { | |
524 | list_add(&base->lru, &page_pool); | |
525 | pool_pages++; | |
526 | } else | |
527 | pool_used++; | |
9a3dc780 | 528 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 529 | |
bb5c2dbd IM |
530 | return 0; |
531 | } | |
532 | ||
c31c7d48 | 533 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 534 | { |
c31c7d48 | 535 | unsigned long address = cpa->vaddr; |
da7bfc50 HH |
536 | int do_split, err; |
537 | unsigned int level; | |
c31c7d48 | 538 | pte_t *kpte, old_pte; |
1da177e4 | 539 | |
97f99fed | 540 | repeat: |
f0646e43 | 541 | kpte = lookup_address(address, &level); |
1da177e4 | 542 | if (!kpte) |
d1a4be63 | 543 | return 0; |
c31c7d48 TG |
544 | |
545 | old_pte = *kpte; | |
546 | if (!pte_val(old_pte)) { | |
547 | if (!primary) | |
548 | return 0; | |
549 | printk(KERN_WARNING "CPA: called for zero pte. " | |
550 | "vaddr = %lx cpa->vaddr = %lx\n", address, | |
551 | cpa->vaddr); | |
552 | WARN_ON(1); | |
1da177e4 | 553 | return -EINVAL; |
c31c7d48 | 554 | } |
9f4c815c | 555 | |
30551bb3 | 556 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 557 | pte_t new_pte; |
626c2c9d | 558 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 559 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 560 | |
72e458df TG |
561 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
562 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 563 | |
c31c7d48 | 564 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 565 | |
626c2c9d AV |
566 | /* |
567 | * We need to keep the pfn from the existing PTE, | |
568 | * after all we're only going to change it's attributes | |
569 | * not the memory it points to | |
570 | */ | |
c31c7d48 TG |
571 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
572 | cpa->pfn = pfn; | |
f4ae5da0 TG |
573 | /* |
574 | * Do we really change anything ? | |
575 | */ | |
576 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
577 | set_pte_atomic(kpte, new_pte); | |
578 | cpa->flushtlb = 1; | |
579 | } | |
9b5cf48b | 580 | cpa->numpages = 1; |
65e074df | 581 | return 0; |
1da177e4 | 582 | } |
65e074df TG |
583 | |
584 | /* | |
585 | * Check, whether we can keep the large page intact | |
586 | * and just change the pte: | |
587 | */ | |
beaff633 | 588 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
589 | /* |
590 | * When the range fits into the existing large page, | |
9b5cf48b | 591 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
592 | * try_large_page: |
593 | */ | |
87f7f8fe IM |
594 | if (do_split <= 0) |
595 | return do_split; | |
65e074df TG |
596 | |
597 | /* | |
598 | * We have to split the large page: | |
599 | */ | |
87f7f8fe IM |
600 | err = split_large_page(kpte, address); |
601 | if (!err) { | |
602 | cpa->flushtlb = 1; | |
603 | goto repeat; | |
604 | } | |
beaff633 | 605 | |
87f7f8fe | 606 | return err; |
9f4c815c | 607 | } |
1da177e4 | 608 | |
c31c7d48 TG |
609 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
610 | ||
611 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 612 | { |
c31c7d48 | 613 | struct cpa_data alias_cpa; |
f34b439f | 614 | int ret = 0; |
44af6c41 | 615 | |
c31c7d48 TG |
616 | if (cpa->pfn > max_pfn_mapped) |
617 | return 0; | |
626c2c9d | 618 | |
f34b439f TG |
619 | /* |
620 | * No need to redo, when the primary call touched the direct | |
621 | * mapping already: | |
622 | */ | |
623 | if (!within(cpa->vaddr, PAGE_OFFSET, | |
624 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
44af6c41 | 625 | |
f34b439f TG |
626 | alias_cpa = *cpa; |
627 | alias_cpa.vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); | |
628 | ||
629 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
630 | } | |
44af6c41 | 631 | |
44af6c41 | 632 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
633 | if (ret) |
634 | return ret; | |
f34b439f TG |
635 | /* |
636 | * No need to redo, when the primary call touched the high | |
637 | * mapping already: | |
638 | */ | |
639 | if (within(cpa->vaddr, (unsigned long) _text, (unsigned long) _end)) | |
640 | return 0; | |
641 | ||
488fd995 | 642 | /* |
0879750f TG |
643 | * If the physical address is inside the kernel map, we need |
644 | * to touch the high mapped kernel as well: | |
488fd995 | 645 | */ |
c31c7d48 TG |
646 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
647 | return 0; | |
0879750f | 648 | |
c31c7d48 TG |
649 | alias_cpa = *cpa; |
650 | alias_cpa.vaddr = | |
651 | (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; | |
652 | ||
653 | /* | |
654 | * The high mapping range is imprecise, so ignore the return value. | |
655 | */ | |
656 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 657 | #endif |
c31c7d48 | 658 | return ret; |
1da177e4 LT |
659 | } |
660 | ||
c31c7d48 | 661 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 662 | { |
65e074df | 663 | int ret, numpages = cpa->numpages; |
ff31452b | 664 | |
65e074df TG |
665 | while (numpages) { |
666 | /* | |
667 | * Store the remaining nr of pages for the large page | |
668 | * preservation check. | |
669 | */ | |
9b5cf48b | 670 | cpa->numpages = numpages; |
c31c7d48 TG |
671 | |
672 | ret = __change_page_attr(cpa, checkalias); | |
ff31452b TG |
673 | if (ret) |
674 | return ret; | |
ff31452b | 675 | |
c31c7d48 TG |
676 | if (checkalias) { |
677 | ret = cpa_process_alias(cpa); | |
678 | if (ret) | |
679 | return ret; | |
680 | } | |
681 | ||
65e074df TG |
682 | /* |
683 | * Adjust the number of pages with the result of the | |
684 | * CPA operation. Either a large page has been | |
685 | * preserved or a single page update happened. | |
686 | */ | |
9b5cf48b RW |
687 | BUG_ON(cpa->numpages > numpages); |
688 | numpages -= cpa->numpages; | |
689 | cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
65e074df | 690 | } |
ff31452b TG |
691 | return 0; |
692 | } | |
693 | ||
6bb8383b AK |
694 | static inline int cache_attr(pgprot_t attr) |
695 | { | |
696 | return pgprot_val(attr) & | |
697 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
698 | } | |
699 | ||
ff31452b | 700 | static int change_page_attr_set_clr(unsigned long addr, int numpages, |
c9caa02c AK |
701 | pgprot_t mask_set, pgprot_t mask_clr, |
702 | int force_split) | |
ff31452b | 703 | { |
72e458df | 704 | struct cpa_data cpa; |
af96e443 | 705 | int ret, cache, checkalias; |
331e4065 TG |
706 | |
707 | /* | |
708 | * Check, if we are requested to change a not supported | |
709 | * feature: | |
710 | */ | |
711 | mask_set = canon_pgprot(mask_set); | |
712 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 713 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
714 | return 0; |
715 | ||
69b1415e TG |
716 | /* Ensure we are PAGE_SIZE aligned */ |
717 | if (addr & ~PAGE_MASK) { | |
718 | addr &= PAGE_MASK; | |
719 | /* | |
720 | * People should not be passing in unaligned addresses: | |
721 | */ | |
722 | WARN_ON_ONCE(1); | |
723 | } | |
724 | ||
72e458df TG |
725 | cpa.vaddr = addr; |
726 | cpa.numpages = numpages; | |
727 | cpa.mask_set = mask_set; | |
728 | cpa.mask_clr = mask_clr; | |
f4ae5da0 | 729 | cpa.flushtlb = 0; |
c9caa02c | 730 | cpa.force_split = force_split; |
72e458df | 731 | |
af96e443 TG |
732 | /* No alias checking for _NX bit modifications */ |
733 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
734 | ||
735 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 736 | |
f4ae5da0 TG |
737 | /* |
738 | * Check whether we really changed something: | |
739 | */ | |
740 | if (!cpa.flushtlb) | |
76ebd054 | 741 | goto out; |
f4ae5da0 | 742 | |
6bb8383b AK |
743 | /* |
744 | * No need to flush, when we did not set any of the caching | |
745 | * attributes: | |
746 | */ | |
747 | cache = cache_attr(mask_set); | |
748 | ||
57a6a46a TG |
749 | /* |
750 | * On success we use clflush, when the CPU supports it to | |
751 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 752 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
753 | * wbindv): |
754 | */ | |
755 | if (!ret && cpu_has_clflush) | |
6bb8383b | 756 | cpa_flush_range(addr, numpages, cache); |
57a6a46a | 757 | else |
6bb8383b | 758 | cpa_flush_all(cache); |
ff31452b | 759 | |
76ebd054 | 760 | out: |
92cb54a3 IM |
761 | cpa_fill_pool(NULL); |
762 | ||
ff31452b TG |
763 | return ret; |
764 | } | |
765 | ||
56744546 TG |
766 | static inline int change_page_attr_set(unsigned long addr, int numpages, |
767 | pgprot_t mask) | |
75cbade8 | 768 | { |
c9caa02c | 769 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0); |
75cbade8 AV |
770 | } |
771 | ||
56744546 TG |
772 | static inline int change_page_attr_clear(unsigned long addr, int numpages, |
773 | pgprot_t mask) | |
72932c7a | 774 | { |
c9caa02c | 775 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0); |
72932c7a TG |
776 | } |
777 | ||
1219333d | 778 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a TG |
779 | { |
780 | return change_page_attr_set(addr, numpages, | |
2e5d9c85 | 781 | __pgprot(_PAGE_CACHE_UC)); |
75cbade8 | 782 | } |
1219333d | 783 | |
784 | int set_memory_uc(unsigned long addr, int numpages) | |
785 | { | |
786 | if (reserve_memtype(addr, addr + numpages * PAGE_SIZE, | |
787 | _PAGE_CACHE_UC, NULL)) | |
788 | return -EINVAL; | |
789 | ||
790 | return _set_memory_uc(addr, numpages); | |
791 | } | |
75cbade8 AV |
792 | EXPORT_SYMBOL(set_memory_uc); |
793 | ||
ef354af4 | 794 | int _set_memory_wc(unsigned long addr, int numpages) |
795 | { | |
796 | return change_page_attr_set(addr, numpages, | |
797 | __pgprot(_PAGE_CACHE_WC)); | |
798 | } | |
799 | ||
800 | int set_memory_wc(unsigned long addr, int numpages) | |
801 | { | |
802 | if (!pat_wc_enabled) | |
803 | return set_memory_uc(addr, numpages); | |
804 | ||
805 | if (reserve_memtype(addr, addr + numpages * PAGE_SIZE, | |
806 | _PAGE_CACHE_WC, NULL)) | |
807 | return -EINVAL; | |
808 | ||
809 | return _set_memory_wc(addr, numpages); | |
810 | } | |
811 | EXPORT_SYMBOL(set_memory_wc); | |
812 | ||
1219333d | 813 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 814 | { |
72932c7a | 815 | return change_page_attr_clear(addr, numpages, |
2e5d9c85 | 816 | __pgprot(_PAGE_CACHE_MASK)); |
75cbade8 | 817 | } |
1219333d | 818 | |
819 | int set_memory_wb(unsigned long addr, int numpages) | |
820 | { | |
821 | free_memtype(addr, addr + numpages * PAGE_SIZE); | |
822 | ||
823 | return _set_memory_wb(addr, numpages); | |
824 | } | |
75cbade8 AV |
825 | EXPORT_SYMBOL(set_memory_wb); |
826 | ||
827 | int set_memory_x(unsigned long addr, int numpages) | |
828 | { | |
72932c7a | 829 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX)); |
75cbade8 AV |
830 | } |
831 | EXPORT_SYMBOL(set_memory_x); | |
832 | ||
833 | int set_memory_nx(unsigned long addr, int numpages) | |
834 | { | |
72932c7a | 835 | return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX)); |
75cbade8 AV |
836 | } |
837 | EXPORT_SYMBOL(set_memory_nx); | |
838 | ||
839 | int set_memory_ro(unsigned long addr, int numpages) | |
840 | { | |
72932c7a | 841 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW)); |
75cbade8 | 842 | } |
75cbade8 AV |
843 | |
844 | int set_memory_rw(unsigned long addr, int numpages) | |
845 | { | |
72932c7a | 846 | return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW)); |
75cbade8 | 847 | } |
f62d0f00 IM |
848 | |
849 | int set_memory_np(unsigned long addr, int numpages) | |
850 | { | |
72932c7a | 851 | return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT)); |
f62d0f00 | 852 | } |
75cbade8 | 853 | |
c9caa02c AK |
854 | int set_memory_4k(unsigned long addr, int numpages) |
855 | { | |
856 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), | |
857 | __pgprot(0), 1); | |
858 | } | |
859 | ||
75cbade8 AV |
860 | int set_pages_uc(struct page *page, int numpages) |
861 | { | |
862 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 863 | |
d7c8f21a | 864 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
865 | } |
866 | EXPORT_SYMBOL(set_pages_uc); | |
867 | ||
868 | int set_pages_wb(struct page *page, int numpages) | |
869 | { | |
870 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 871 | |
d7c8f21a | 872 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
873 | } |
874 | EXPORT_SYMBOL(set_pages_wb); | |
875 | ||
876 | int set_pages_x(struct page *page, int numpages) | |
877 | { | |
878 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 879 | |
d7c8f21a | 880 | return set_memory_x(addr, numpages); |
75cbade8 AV |
881 | } |
882 | EXPORT_SYMBOL(set_pages_x); | |
883 | ||
884 | int set_pages_nx(struct page *page, int numpages) | |
885 | { | |
886 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 887 | |
d7c8f21a | 888 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
889 | } |
890 | EXPORT_SYMBOL(set_pages_nx); | |
891 | ||
892 | int set_pages_ro(struct page *page, int numpages) | |
893 | { | |
894 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 895 | |
d7c8f21a | 896 | return set_memory_ro(addr, numpages); |
75cbade8 | 897 | } |
75cbade8 AV |
898 | |
899 | int set_pages_rw(struct page *page, int numpages) | |
900 | { | |
901 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 902 | |
d7c8f21a | 903 | return set_memory_rw(addr, numpages); |
78c94aba IM |
904 | } |
905 | ||
1da177e4 | 906 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
907 | |
908 | static int __set_pages_p(struct page *page, int numpages) | |
909 | { | |
72e458df TG |
910 | struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page), |
911 | .numpages = numpages, | |
912 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
913 | .mask_clr = __pgprot(0)}; | |
72932c7a | 914 | |
c31c7d48 | 915 | return __change_page_attr_set_clr(&cpa, 1); |
f62d0f00 IM |
916 | } |
917 | ||
918 | static int __set_pages_np(struct page *page, int numpages) | |
919 | { | |
72e458df TG |
920 | struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page), |
921 | .numpages = numpages, | |
922 | .mask_set = __pgprot(0), | |
923 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW)}; | |
72932c7a | 924 | |
c31c7d48 | 925 | return __change_page_attr_set_clr(&cpa, 1); |
f62d0f00 IM |
926 | } |
927 | ||
1da177e4 LT |
928 | void kernel_map_pages(struct page *page, int numpages, int enable) |
929 | { | |
930 | if (PageHighMem(page)) | |
931 | return; | |
9f4c815c | 932 | if (!enable) { |
f9b8404c IM |
933 | debug_check_no_locks_freed(page_address(page), |
934 | numpages * PAGE_SIZE); | |
9f4c815c | 935 | } |
de5097c2 | 936 | |
12d6f21e IM |
937 | /* |
938 | * If page allocator is not up yet then do not call c_p_a(): | |
939 | */ | |
940 | if (!debug_pagealloc_enabled) | |
941 | return; | |
942 | ||
9f4c815c | 943 | /* |
f8d8406b IM |
944 | * The return value is ignored as the calls cannot fail. |
945 | * Large pages are kept enabled at boot time, and are | |
946 | * split up quickly with DEBUG_PAGEALLOC. If a splitup | |
947 | * fails here (due to temporary memory shortage) no damage | |
948 | * is done because we just keep the largepage intact up | |
949 | * to the next attempt when it will likely be split up: | |
1da177e4 | 950 | */ |
f62d0f00 IM |
951 | if (enable) |
952 | __set_pages_p(page, numpages); | |
953 | else | |
954 | __set_pages_np(page, numpages); | |
9f4c815c IM |
955 | |
956 | /* | |
e4b71dcf IM |
957 | * We should perform an IPI and flush all tlbs, |
958 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
959 | */ |
960 | __flush_tlb_all(); | |
76ebd054 TG |
961 | |
962 | /* | |
963 | * Try to refill the page pool here. We can do this only after | |
964 | * the tlb flush. | |
965 | */ | |
92cb54a3 | 966 | cpa_fill_pool(NULL); |
1da177e4 | 967 | } |
8a235efa | 968 | |
ee7ae7a1 TG |
969 | #ifdef CONFIG_DEBUG_FS |
970 | static int dpa_show(struct seq_file *m, void *v) | |
971 | { | |
972 | seq_puts(m, "DEBUG_PAGEALLOC\n"); | |
973 | seq_printf(m, "pool_size : %lu\n", pool_size); | |
974 | seq_printf(m, "pool_pages : %lu\n", pool_pages); | |
975 | seq_printf(m, "pool_low : %lu\n", pool_low); | |
976 | seq_printf(m, "pool_used : %lu\n", pool_used); | |
977 | seq_printf(m, "pool_failed : %lu\n", pool_failed); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | static int dpa_open(struct inode *inode, struct file *filp) | |
983 | { | |
984 | return single_open(filp, dpa_show, NULL); | |
985 | } | |
986 | ||
987 | static const struct file_operations dpa_fops = { | |
988 | .open = dpa_open, | |
989 | .read = seq_read, | |
990 | .llseek = seq_lseek, | |
991 | .release = single_release, | |
992 | }; | |
993 | ||
994 | int __init debug_pagealloc_proc_init(void) | |
995 | { | |
996 | struct dentry *de; | |
997 | ||
998 | de = debugfs_create_file("debug_pagealloc", 0600, NULL, NULL, | |
999 | &dpa_fops); | |
1000 | if (!de) | |
1001 | return -ENOMEM; | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | __initcall(debug_pagealloc_proc_init); | |
1006 | #endif | |
1007 | ||
8a235efa RW |
1008 | #ifdef CONFIG_HIBERNATION |
1009 | ||
1010 | bool kernel_page_present(struct page *page) | |
1011 | { | |
1012 | unsigned int level; | |
1013 | pte_t *pte; | |
1014 | ||
1015 | if (PageHighMem(page)) | |
1016 | return false; | |
1017 | ||
1018 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1019 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1020 | } | |
1021 | ||
1022 | #endif /* CONFIG_HIBERNATION */ | |
1023 | ||
1024 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1025 | |
1026 | /* | |
1027 | * The testcases use internal knowledge of the implementation that shouldn't | |
1028 | * be exposed to the rest of the kernel. Include these directly here. | |
1029 | */ | |
1030 | #ifdef CONFIG_CPA_DEBUG | |
1031 | #include "pageattr-test.c" | |
1032 | #endif |