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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
5bd5a452 | 16 | #include <linux/pci.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
0fd64c23 | 33 | pgd_t *pgd; |
72e458df TG |
34 | pgprot_t mask_set; |
35 | pgprot_t mask_clr; | |
65e074df | 36 | int numpages; |
d75586ad | 37 | int flags; |
c31c7d48 | 38 | unsigned long pfn; |
c9caa02c | 39 | unsigned force_split : 1; |
d75586ad | 40 | int curpage; |
9ae28475 | 41 | struct page **pages; |
72e458df TG |
42 | }; |
43 | ||
ad5ca55f SS |
44 | /* |
45 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
46 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
47 | * entries change the page attribute in parallel to some other cpu | |
48 | * splitting a large page entry along with changing the attribute. | |
49 | */ | |
50 | static DEFINE_SPINLOCK(cpa_lock); | |
51 | ||
d75586ad SL |
52 | #define CPA_FLUSHTLB 1 |
53 | #define CPA_ARRAY 2 | |
9ae28475 | 54 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 55 | |
65280e61 | 56 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
57 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
58 | ||
65280e61 | 59 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 60 | { |
ce0c0e50 | 61 | /* Protect against CPA */ |
a79e53d8 | 62 | spin_lock(&pgd_lock); |
ce0c0e50 | 63 | direct_pages_count[level] += pages; |
a79e53d8 | 64 | spin_unlock(&pgd_lock); |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
65280e61 | 84 | #ifdef CONFIG_X86_64 |
a06de630 | 85 | if (direct_gbpages) |
b9c3bfc2 | 86 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 87 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
88 | #endif |
89 | } | |
65280e61 TG |
90 | #else |
91 | static inline void split_page_count(int level) { } | |
92 | #endif | |
ce0c0e50 | 93 | |
c31c7d48 TG |
94 | #ifdef CONFIG_X86_64 |
95 | ||
96 | static inline unsigned long highmap_start_pfn(void) | |
97 | { | |
fc8d7826 | 98 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
99 | } |
100 | ||
101 | static inline unsigned long highmap_end_pfn(void) | |
102 | { | |
fc8d7826 | 103 | return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
104 | } |
105 | ||
106 | #endif | |
107 | ||
92cb54a3 IM |
108 | #ifdef CONFIG_DEBUG_PAGEALLOC |
109 | # define debug_pagealloc 1 | |
110 | #else | |
111 | # define debug_pagealloc 0 | |
112 | #endif | |
113 | ||
ed724be6 AV |
114 | static inline int |
115 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 116 | { |
ed724be6 AV |
117 | return addr >= start && addr < end; |
118 | } | |
119 | ||
d7c8f21a TG |
120 | /* |
121 | * Flushing functions | |
122 | */ | |
cd8ddf1a | 123 | |
cd8ddf1a TG |
124 | /** |
125 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 126 | * @vaddr: virtual start address |
cd8ddf1a TG |
127 | * @size: number of bytes to flush |
128 | * | |
129 | * clflush is an unordered instruction which needs fencing with mfence | |
130 | * to avoid ordering issues. | |
131 | */ | |
4c61afcd | 132 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 133 | { |
4c61afcd | 134 | void *vend = vaddr + size - 1; |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd IM |
137 | |
138 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
139 | clflush(vaddr); | |
140 | /* | |
141 | * Flush any possible final partial cacheline: | |
142 | */ | |
143 | clflush(vend); | |
144 | ||
cd8ddf1a | 145 | mb(); |
d7c8f21a | 146 | } |
e517a5e9 | 147 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 148 | |
af1e6844 | 149 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 150 | { |
6bb8383b AK |
151 | unsigned long cache = (unsigned long)arg; |
152 | ||
d7c8f21a TG |
153 | /* |
154 | * Flush all to work around Errata in early athlons regarding | |
155 | * large page flushing. | |
156 | */ | |
157 | __flush_tlb_all(); | |
158 | ||
0b827537 | 159 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
160 | wbinvd(); |
161 | } | |
162 | ||
6bb8383b | 163 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
164 | { |
165 | BUG_ON(irqs_disabled()); | |
166 | ||
15c8b6c1 | 167 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
168 | } |
169 | ||
57a6a46a TG |
170 | static void __cpa_flush_range(void *arg) |
171 | { | |
57a6a46a TG |
172 | /* |
173 | * We could optimize that further and do individual per page | |
174 | * tlb invalidates for a low number of pages. Caveat: we must | |
175 | * flush the high aliases on 64bit as well. | |
176 | */ | |
177 | __flush_tlb_all(); | |
57a6a46a TG |
178 | } |
179 | ||
6bb8383b | 180 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 181 | { |
4c61afcd IM |
182 | unsigned int i, level; |
183 | unsigned long addr; | |
184 | ||
57a6a46a | 185 | BUG_ON(irqs_disabled()); |
4c61afcd | 186 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 187 | |
15c8b6c1 | 188 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 189 | |
6bb8383b AK |
190 | if (!cache) |
191 | return; | |
192 | ||
3b233e52 TG |
193 | /* |
194 | * We only need to flush on one CPU, | |
195 | * clflush is a MESI-coherent instruction that | |
196 | * will cause all other CPUs to flush the same | |
197 | * cachelines: | |
198 | */ | |
4c61afcd IM |
199 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
200 | pte_t *pte = lookup_address(addr, &level); | |
201 | ||
202 | /* | |
203 | * Only flush present addresses: | |
204 | */ | |
7bfb72e8 | 205 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
206 | clflush_cache_range((void *) addr, PAGE_SIZE); |
207 | } | |
57a6a46a TG |
208 | } |
209 | ||
9ae28475 | 210 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
211 | int in_flags, struct page **pages) | |
d75586ad SL |
212 | { |
213 | unsigned int i, level; | |
2171787b | 214 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
215 | |
216 | BUG_ON(irqs_disabled()); | |
217 | ||
2171787b | 218 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 219 | |
2171787b | 220 | if (!cache || do_wbinvd) |
d75586ad SL |
221 | return; |
222 | ||
d75586ad SL |
223 | /* |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
9ae28475 | 229 | for (i = 0; i < numpages; i++) { |
230 | unsigned long addr; | |
231 | pte_t *pte; | |
232 | ||
233 | if (in_flags & CPA_PAGES_ARRAY) | |
234 | addr = (unsigned long)page_address(pages[i]); | |
235 | else | |
236 | addr = start[i]; | |
237 | ||
238 | pte = lookup_address(addr, &level); | |
d75586ad SL |
239 | |
240 | /* | |
241 | * Only flush present addresses: | |
242 | */ | |
243 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 244 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
245 | } |
246 | } | |
247 | ||
ed724be6 AV |
248 | /* |
249 | * Certain areas of memory on x86 require very specific protection flags, | |
250 | * for example the BIOS area or kernel text. Callers don't always get this | |
251 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
252 | * checks and fixes these known static required protection bits. | |
253 | */ | |
c31c7d48 TG |
254 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
255 | unsigned long pfn) | |
ed724be6 AV |
256 | { |
257 | pgprot_t forbidden = __pgprot(0); | |
258 | ||
687c4825 | 259 | /* |
ed724be6 AV |
260 | * The BIOS area between 640k and 1Mb needs to be executable for |
261 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 262 | */ |
5bd5a452 MC |
263 | #ifdef CONFIG_PCI_BIOS |
264 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 265 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 266 | #endif |
ed724be6 AV |
267 | |
268 | /* | |
269 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
270 | * Does not cover __inittext since that is gone later on. On |
271 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
272 | */ |
273 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
274 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 275 | |
cc0f21bb | 276 | /* |
c31c7d48 TG |
277 | * The .rodata section needs to be read-only. Using the pfn |
278 | * catches all aliases. | |
cc0f21bb | 279 | */ |
fc8d7826 AD |
280 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
281 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 282 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 283 | |
55ca3cc1 | 284 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 285 | /* |
502f6604 SS |
286 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
287 | * kernel text mappings for the large page aligned text, rodata sections | |
288 | * will be always read-only. For the kernel identity mappings covering | |
289 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
290 | * |
291 | * This will preserve the large page mappings for kernel text/data | |
292 | * at no extra cost. | |
293 | */ | |
502f6604 SS |
294 | if (kernel_set_to_readonly && |
295 | within(address, (unsigned long)_text, | |
281ff33b SS |
296 | (unsigned long)__end_rodata_hpage_align)) { |
297 | unsigned int level; | |
298 | ||
299 | /* | |
300 | * Don't enforce the !RW mapping for the kernel text mapping, | |
301 | * if the current mapping is already using small page mapping. | |
302 | * No need to work hard to preserve large page mappings in this | |
303 | * case. | |
304 | * | |
305 | * This also fixes the Linux Xen paravirt guest boot failure | |
306 | * (because of unexpected read-only mappings for kernel identity | |
307 | * mappings). In this paravirt guest case, the kernel text | |
308 | * mapping and the kernel identity mapping share the same | |
309 | * page-table pages. Thus we can't really use different | |
310 | * protections for the kernel text and identity mappings. Also, | |
311 | * these shared mappings are made of small page mappings. | |
312 | * Thus this don't enforce !RW mapping for small page kernel | |
313 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 314 | * as well. |
281ff33b SS |
315 | */ |
316 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
317 | pgprot_val(forbidden) |= _PAGE_RW; | |
318 | } | |
74e08179 SS |
319 | #endif |
320 | ||
ed724be6 | 321 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
322 | |
323 | return prot; | |
324 | } | |
325 | ||
0fd64c23 BP |
326 | static pte_t *__lookup_address_in_pgd(pgd_t *pgd, unsigned long address, |
327 | unsigned int *level) | |
9f4c815c | 328 | { |
1da177e4 LT |
329 | pud_t *pud; |
330 | pmd_t *pmd; | |
9f4c815c | 331 | |
30551bb3 TG |
332 | *level = PG_LEVEL_NONE; |
333 | ||
1da177e4 LT |
334 | if (pgd_none(*pgd)) |
335 | return NULL; | |
9df84993 | 336 | |
1da177e4 LT |
337 | pud = pud_offset(pgd, address); |
338 | if (pud_none(*pud)) | |
339 | return NULL; | |
c2f71ee2 AK |
340 | |
341 | *level = PG_LEVEL_1G; | |
342 | if (pud_large(*pud) || !pud_present(*pud)) | |
343 | return (pte_t *)pud; | |
344 | ||
1da177e4 LT |
345 | pmd = pmd_offset(pud, address); |
346 | if (pmd_none(*pmd)) | |
347 | return NULL; | |
30551bb3 TG |
348 | |
349 | *level = PG_LEVEL_2M; | |
9a14aefc | 350 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 351 | return (pte_t *)pmd; |
1da177e4 | 352 | |
30551bb3 | 353 | *level = PG_LEVEL_4K; |
9df84993 | 354 | |
9f4c815c IM |
355 | return pte_offset_kernel(pmd, address); |
356 | } | |
0fd64c23 BP |
357 | |
358 | /* | |
359 | * Lookup the page table entry for a virtual address. Return a pointer | |
360 | * to the entry and the level of the mapping. | |
361 | * | |
362 | * Note: We return pud and pmd either when the entry is marked large | |
363 | * or when the present bit is not set. Otherwise we would return a | |
364 | * pointer to a nonexisting mapping. | |
365 | */ | |
366 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
367 | { | |
368 | return __lookup_address_in_pgd(pgd_offset_k(address), address, level); | |
369 | } | |
75bb8835 | 370 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 371 | |
0fd64c23 BP |
372 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
373 | unsigned int *level) | |
374 | { | |
375 | if (cpa->pgd) | |
376 | return __lookup_address_in_pgd(cpa->pgd + pgd_index(address), | |
377 | address, level); | |
378 | ||
379 | return lookup_address(address, level); | |
380 | } | |
381 | ||
d7656534 DH |
382 | /* |
383 | * This is necessary because __pa() does not work on some | |
384 | * kinds of memory, like vmalloc() or the alloc_remap() | |
385 | * areas on 32-bit NUMA systems. The percpu areas can | |
386 | * end up in this kind of memory, for instance. | |
387 | * | |
388 | * This could be optimized, but it is only intended to be | |
389 | * used at inititalization time, and keeping it | |
390 | * unoptimized should increase the testing coverage for | |
391 | * the more obscure platforms. | |
392 | */ | |
393 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
394 | { | |
395 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
396 | phys_addr_t phys_addr; | |
397 | unsigned long offset; | |
398 | enum pg_level level; | |
399 | unsigned long psize; | |
400 | unsigned long pmask; | |
401 | pte_t *pte; | |
402 | ||
403 | pte = lookup_address(virt_addr, &level); | |
404 | BUG_ON(!pte); | |
405 | psize = page_level_size(level); | |
406 | pmask = page_level_mask(level); | |
407 | offset = virt_addr & ~pmask; | |
408 | phys_addr = pte_pfn(*pte) << PAGE_SHIFT; | |
409 | return (phys_addr | offset); | |
410 | } | |
411 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
412 | ||
9df84993 IM |
413 | /* |
414 | * Set the new pmd in all the pgds we know about: | |
415 | */ | |
9a3dc780 | 416 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 417 | { |
9f4c815c IM |
418 | /* change init_mm */ |
419 | set_pte_atomic(kpte, pte); | |
44af6c41 | 420 | #ifdef CONFIG_X86_32 |
e4b71dcf | 421 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
422 | struct page *page; |
423 | ||
e3ed910d | 424 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
425 | pgd_t *pgd; |
426 | pud_t *pud; | |
427 | pmd_t *pmd; | |
428 | ||
429 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
430 | pud = pud_offset(pgd, address); | |
431 | pmd = pmd_offset(pud, address); | |
432 | set_pte_atomic((pte_t *)pmd, pte); | |
433 | } | |
1da177e4 | 434 | } |
44af6c41 | 435 | #endif |
1da177e4 LT |
436 | } |
437 | ||
9df84993 IM |
438 | static int |
439 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
440 | struct cpa_data *cpa) | |
65e074df | 441 | { |
a79e53d8 | 442 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn; |
65e074df | 443 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 444 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 445 | int i, do_split = 1; |
f3c4fbb6 | 446 | enum pg_level level; |
65e074df | 447 | |
c9caa02c AK |
448 | if (cpa->force_split) |
449 | return 1; | |
450 | ||
a79e53d8 | 451 | spin_lock(&pgd_lock); |
65e074df TG |
452 | /* |
453 | * Check for races, another CPU might have split this page | |
454 | * up already: | |
455 | */ | |
456 | tmp = lookup_address(address, &level); | |
457 | if (tmp != kpte) | |
458 | goto out_unlock; | |
459 | ||
460 | switch (level) { | |
461 | case PG_LEVEL_2M: | |
f07333fd | 462 | #ifdef CONFIG_X86_64 |
65e074df | 463 | case PG_LEVEL_1G: |
f07333fd | 464 | #endif |
f3c4fbb6 DH |
465 | psize = page_level_size(level); |
466 | pmask = page_level_mask(level); | |
467 | break; | |
65e074df | 468 | default: |
beaff633 | 469 | do_split = -EINVAL; |
65e074df TG |
470 | goto out_unlock; |
471 | } | |
472 | ||
473 | /* | |
474 | * Calculate the number of pages, which fit into this large | |
475 | * page starting at address: | |
476 | */ | |
477 | nextpage_addr = (address + psize) & pmask; | |
478 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
479 | if (numpages < cpa->numpages) |
480 | cpa->numpages = numpages; | |
65e074df TG |
481 | |
482 | /* | |
483 | * We are safe now. Check whether the new pgprot is the same: | |
484 | */ | |
485 | old_pte = *kpte; | |
f76cfa3c | 486 | old_prot = req_prot = pte_pgprot(old_pte); |
65e074df | 487 | |
64edc8ed MC |
488 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
489 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 490 | |
a8aed3e0 AA |
491 | /* |
492 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
493 | * set otherwise pmd_present/pmd_huge will return true even on | |
494 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
495 | * for the ancient hardware that doesn't support it. | |
496 | */ | |
f76cfa3c AA |
497 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
498 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 499 | else |
f76cfa3c | 500 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 501 | |
f76cfa3c | 502 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 503 | |
c31c7d48 TG |
504 | /* |
505 | * old_pte points to the large page base address. So we need | |
506 | * to add the offset of the virtual address: | |
507 | */ | |
508 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
509 | cpa->pfn = pfn; | |
510 | ||
64edc8ed | 511 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 512 | |
fac84939 TG |
513 | /* |
514 | * We need to check the full range, whether | |
515 | * static_protection() requires a different pgprot for one of | |
516 | * the pages in the range we try to preserve: | |
517 | */ | |
64edc8ed MC |
518 | addr = address & pmask; |
519 | pfn = pte_pfn(old_pte); | |
520 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { | |
521 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
522 | |
523 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
524 | goto out_unlock; | |
525 | } | |
526 | ||
65e074df TG |
527 | /* |
528 | * If there are no changes, return. maxpages has been updated | |
529 | * above: | |
530 | */ | |
531 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 532 | do_split = 0; |
65e074df TG |
533 | goto out_unlock; |
534 | } | |
535 | ||
536 | /* | |
537 | * We need to change the attributes. Check, whether we can | |
538 | * change the large page in one go. We request a split, when | |
539 | * the address is not aligned and the number of pages is | |
540 | * smaller than the number of pages in the large page. Note | |
541 | * that we limited the number of possible pages already to | |
542 | * the number of pages in the large page. | |
543 | */ | |
64edc8ed | 544 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
545 | /* |
546 | * The address is aligned and the number of pages | |
547 | * covers the full page. | |
548 | */ | |
a8aed3e0 | 549 | new_pte = pfn_pte(pte_pfn(old_pte), new_prot); |
65e074df | 550 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 551 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 552 | do_split = 0; |
65e074df TG |
553 | } |
554 | ||
555 | out_unlock: | |
a79e53d8 | 556 | spin_unlock(&pgd_lock); |
9df84993 | 557 | |
beaff633 | 558 | return do_split; |
65e074df TG |
559 | } |
560 | ||
5952886b BP |
561 | static int |
562 | __split_large_page(pte_t *kpte, unsigned long address, struct page *base) | |
bb5c2dbd | 563 | { |
5952886b | 564 | pte_t *pbase = (pte_t *)page_address(base); |
a79e53d8 | 565 | unsigned long pfn, pfninc = 1; |
9df84993 | 566 | unsigned int i, level; |
ae9aae9e | 567 | pte_t *tmp; |
9df84993 | 568 | pgprot_t ref_prot; |
bb5c2dbd | 569 | |
a79e53d8 | 570 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
571 | /* |
572 | * Check for races, another CPU might have split this page | |
573 | * up for us already: | |
574 | */ | |
575 | tmp = lookup_address(address, &level); | |
ae9aae9e WC |
576 | if (tmp != kpte) { |
577 | spin_unlock(&pgd_lock); | |
578 | return 1; | |
579 | } | |
bb5c2dbd | 580 | |
6944a9c8 | 581 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 582 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
583 | /* |
584 | * If we ever want to utilize the PAT bit, we need to | |
585 | * update this function to make sure it's converted from | |
586 | * bit 12 to bit 7 when we cross from the 2MB level to | |
587 | * the 4K level: | |
588 | */ | |
589 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 590 | |
f07333fd AK |
591 | #ifdef CONFIG_X86_64 |
592 | if (level == PG_LEVEL_1G) { | |
593 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
a8aed3e0 AA |
594 | /* |
595 | * Set the PSE flags only if the PRESENT flag is set | |
596 | * otherwise pmd_present/pmd_huge will return true | |
597 | * even on a non present pmd. | |
598 | */ | |
599 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
600 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
601 | else | |
602 | pgprot_val(ref_prot) &= ~_PAGE_PSE; | |
f07333fd AK |
603 | } |
604 | #endif | |
605 | ||
a8aed3e0 AA |
606 | /* |
607 | * Set the GLOBAL flags only if the PRESENT flag is set | |
608 | * otherwise pmd/pte_present will return true even on a non | |
609 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
610 | * for the ancient hardware that doesn't support it. | |
611 | */ | |
612 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
613 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
614 | else | |
615 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
616 | ||
63c1dcf4 TG |
617 | /* |
618 | * Get the target pfn from the original entry: | |
619 | */ | |
620 | pfn = pte_pfn(*kpte); | |
f07333fd | 621 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 622 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 623 | |
8eb5779f YL |
624 | if (pfn_range_is_mapped(PFN_DOWN(__pa(address)), |
625 | PFN_DOWN(__pa(address)) + 1)) | |
f361a450 YL |
626 | split_page_count(level); |
627 | ||
bb5c2dbd | 628 | /* |
07a66d7c | 629 | * Install the new, split up pagetable. |
4c881ca1 | 630 | * |
07a66d7c IM |
631 | * We use the standard kernel pagetable protections for the new |
632 | * pagetable protections, the actual ptes set above control the | |
633 | * primary protection behavior: | |
bb5c2dbd | 634 | */ |
07a66d7c | 635 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
636 | |
637 | /* | |
638 | * Intel Atom errata AAH41 workaround. | |
639 | * | |
640 | * The real fix should be in hw or in a microcode update, but | |
641 | * we also probabilistically try to reduce the window of having | |
642 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
643 | * going on. | |
644 | */ | |
645 | __flush_tlb_all(); | |
ae9aae9e | 646 | spin_unlock(&pgd_lock); |
211b3d03 | 647 | |
ae9aae9e WC |
648 | return 0; |
649 | } | |
bb5c2dbd | 650 | |
ae9aae9e WC |
651 | static int split_large_page(pte_t *kpte, unsigned long address) |
652 | { | |
ae9aae9e WC |
653 | struct page *base; |
654 | ||
655 | if (!debug_pagealloc) | |
656 | spin_unlock(&cpa_lock); | |
657 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
658 | if (!debug_pagealloc) | |
659 | spin_lock(&cpa_lock); | |
660 | if (!base) | |
661 | return -ENOMEM; | |
662 | ||
5952886b | 663 | if (__split_large_page(kpte, address, base)) |
8311eb84 | 664 | __free_page(base); |
bb5c2dbd | 665 | |
bb5c2dbd IM |
666 | return 0; |
667 | } | |
668 | ||
4b23538d BP |
669 | static int alloc_pmd_page(pud_t *pud) |
670 | { | |
671 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
672 | if (!pmd) | |
673 | return -1; | |
674 | ||
675 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
676 | return 0; | |
677 | } | |
678 | ||
679 | #define populate_pmd(cpa, start, end, pages, pud, pgprot) (-1) | |
680 | ||
681 | static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd, | |
682 | pgprot_t pgprot) | |
683 | { | |
684 | pud_t *pud; | |
685 | unsigned long end; | |
686 | int cur_pages = 0; | |
687 | ||
688 | end = start + (cpa->numpages << PAGE_SHIFT); | |
689 | ||
690 | /* | |
691 | * Not on a Gb page boundary? => map everything up to it with | |
692 | * smaller pages. | |
693 | */ | |
694 | if (start & (PUD_SIZE - 1)) { | |
695 | unsigned long pre_end; | |
696 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
697 | ||
698 | pre_end = min_t(unsigned long, end, next_page); | |
699 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
700 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
701 | ||
702 | pud = pud_offset(pgd, start); | |
703 | ||
704 | /* | |
705 | * Need a PMD page? | |
706 | */ | |
707 | if (pud_none(*pud)) | |
708 | if (alloc_pmd_page(pud)) | |
709 | return -1; | |
710 | ||
711 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
712 | pud, pgprot); | |
713 | if (cur_pages < 0) | |
714 | return cur_pages; | |
715 | ||
716 | start = pre_end; | |
717 | } | |
718 | ||
719 | /* We mapped them all? */ | |
720 | if (cpa->numpages == cur_pages) | |
721 | return cur_pages; | |
722 | ||
723 | pud = pud_offset(pgd, start); | |
724 | ||
725 | /* | |
726 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
727 | */ | |
728 | while (end - start >= PUD_SIZE) { | |
729 | set_pud(pud, __pud(cpa->pfn | _PAGE_PSE | massage_pgprot(pgprot))); | |
730 | ||
731 | start += PUD_SIZE; | |
732 | cpa->pfn += PUD_SIZE; | |
733 | cur_pages += PUD_SIZE >> PAGE_SHIFT; | |
734 | pud++; | |
735 | } | |
736 | ||
737 | /* Map trailing leftover */ | |
738 | if (start < end) { | |
739 | int tmp; | |
740 | ||
741 | pud = pud_offset(pgd, start); | |
742 | if (pud_none(*pud)) | |
743 | if (alloc_pmd_page(pud)) | |
744 | return -1; | |
745 | ||
746 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
747 | pud, pgprot); | |
748 | if (tmp < 0) | |
749 | return cur_pages; | |
750 | ||
751 | cur_pages += tmp; | |
752 | } | |
753 | return cur_pages; | |
754 | } | |
f3f72966 BP |
755 | |
756 | /* | |
757 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
758 | * an alternate PGD. | |
759 | */ | |
760 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
761 | { | |
762 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
763 | bool allocd_pgd = false; | |
764 | pgd_t *pgd_entry; | |
765 | pud_t *pud = NULL; /* shut up gcc */ | |
766 | int ret; | |
767 | ||
768 | pgd_entry = cpa->pgd + pgd_index(addr); | |
769 | ||
770 | /* | |
771 | * Allocate a PUD page and hand it down for mapping. | |
772 | */ | |
773 | if (pgd_none(*pgd_entry)) { | |
774 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
775 | if (!pud) | |
776 | return -1; | |
777 | ||
778 | set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE)); | |
779 | allocd_pgd = true; | |
780 | } | |
781 | ||
782 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
783 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
784 | ||
785 | ret = populate_pud(cpa, addr, pgd_entry, pgprot); | |
786 | if (ret < 0) | |
787 | return ret; | |
788 | ||
789 | cpa->numpages = ret; | |
790 | return 0; | |
791 | } | |
792 | ||
a1e46212 SS |
793 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
794 | int primary) | |
795 | { | |
796 | /* | |
797 | * Ignore all non primary paths. | |
798 | */ | |
799 | if (!primary) | |
800 | return 0; | |
801 | ||
802 | /* | |
803 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
804 | * to have holes. | |
805 | * Also set numpages to '1' indicating that we processed cpa req for | |
806 | * one virtual address page and its pfn. TBD: numpages can be set based | |
807 | * on the initial value and the level returned by lookup_address(). | |
808 | */ | |
809 | if (within(vaddr, PAGE_OFFSET, | |
810 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
811 | cpa->numpages = 1; | |
812 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
813 | return 0; | |
814 | } else { | |
815 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
816 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
817 | *cpa->vaddr); | |
818 | ||
819 | return -EFAULT; | |
820 | } | |
821 | } | |
822 | ||
c31c7d48 | 823 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 824 | { |
d75586ad | 825 | unsigned long address; |
da7bfc50 HH |
826 | int do_split, err; |
827 | unsigned int level; | |
c31c7d48 | 828 | pte_t *kpte, old_pte; |
1da177e4 | 829 | |
8523acfe TH |
830 | if (cpa->flags & CPA_PAGES_ARRAY) { |
831 | struct page *page = cpa->pages[cpa->curpage]; | |
832 | if (unlikely(PageHighMem(page))) | |
833 | return 0; | |
834 | address = (unsigned long)page_address(page); | |
835 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
836 | address = cpa->vaddr[cpa->curpage]; |
837 | else | |
838 | address = *cpa->vaddr; | |
97f99fed | 839 | repeat: |
f0646e43 | 840 | kpte = lookup_address(address, &level); |
1da177e4 | 841 | if (!kpte) |
a1e46212 | 842 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
843 | |
844 | old_pte = *kpte; | |
a1e46212 SS |
845 | if (!pte_val(old_pte)) |
846 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 847 | |
30551bb3 | 848 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 849 | pte_t new_pte; |
626c2c9d | 850 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 851 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 852 | |
72e458df TG |
853 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
854 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 855 | |
c31c7d48 | 856 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 857 | |
a8aed3e0 AA |
858 | /* |
859 | * Set the GLOBAL flags only if the PRESENT flag is | |
860 | * set otherwise pte_present will return true even on | |
861 | * a non present pte. The canon_pgprot will clear | |
862 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
863 | * support it. | |
864 | */ | |
865 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
866 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
867 | else | |
868 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
869 | ||
626c2c9d AV |
870 | /* |
871 | * We need to keep the pfn from the existing PTE, | |
872 | * after all we're only going to change it's attributes | |
873 | * not the memory it points to | |
874 | */ | |
c31c7d48 TG |
875 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
876 | cpa->pfn = pfn; | |
f4ae5da0 TG |
877 | /* |
878 | * Do we really change anything ? | |
879 | */ | |
880 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
881 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 882 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 883 | } |
9b5cf48b | 884 | cpa->numpages = 1; |
65e074df | 885 | return 0; |
1da177e4 | 886 | } |
65e074df TG |
887 | |
888 | /* | |
889 | * Check, whether we can keep the large page intact | |
890 | * and just change the pte: | |
891 | */ | |
beaff633 | 892 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
893 | /* |
894 | * When the range fits into the existing large page, | |
9b5cf48b | 895 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
896 | * try_large_page: |
897 | */ | |
87f7f8fe IM |
898 | if (do_split <= 0) |
899 | return do_split; | |
65e074df TG |
900 | |
901 | /* | |
902 | * We have to split the large page: | |
903 | */ | |
87f7f8fe IM |
904 | err = split_large_page(kpte, address); |
905 | if (!err) { | |
ad5ca55f SS |
906 | /* |
907 | * Do a global flush tlb after splitting the large page | |
908 | * and before we do the actual change page attribute in the PTE. | |
909 | * | |
910 | * With out this, we violate the TLB application note, that says | |
911 | * "The TLBs may contain both ordinary and large-page | |
912 | * translations for a 4-KByte range of linear addresses. This | |
913 | * may occur if software modifies the paging structures so that | |
914 | * the page size used for the address range changes. If the two | |
915 | * translations differ with respect to page frame or attributes | |
916 | * (e.g., permissions), processor behavior is undefined and may | |
917 | * be implementation-specific." | |
918 | * | |
919 | * We do this global tlb flush inside the cpa_lock, so that we | |
920 | * don't allow any other cpu, with stale tlb entries change the | |
921 | * page attribute in parallel, that also falls into the | |
922 | * just split large page entry. | |
923 | */ | |
924 | flush_tlb_all(); | |
87f7f8fe IM |
925 | goto repeat; |
926 | } | |
beaff633 | 927 | |
87f7f8fe | 928 | return err; |
9f4c815c | 929 | } |
1da177e4 | 930 | |
c31c7d48 TG |
931 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
932 | ||
933 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 934 | { |
c31c7d48 | 935 | struct cpa_data alias_cpa; |
992f4c1c | 936 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 937 | unsigned long vaddr; |
992f4c1c | 938 | int ret; |
44af6c41 | 939 | |
8eb5779f | 940 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 941 | return 0; |
626c2c9d | 942 | |
f34b439f TG |
943 | /* |
944 | * No need to redo, when the primary call touched the direct | |
945 | * mapping already: | |
946 | */ | |
8523acfe TH |
947 | if (cpa->flags & CPA_PAGES_ARRAY) { |
948 | struct page *page = cpa->pages[cpa->curpage]; | |
949 | if (unlikely(PageHighMem(page))) | |
950 | return 0; | |
951 | vaddr = (unsigned long)page_address(page); | |
952 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
953 | vaddr = cpa->vaddr[cpa->curpage]; |
954 | else | |
955 | vaddr = *cpa->vaddr; | |
956 | ||
957 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 958 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 959 | |
f34b439f | 960 | alias_cpa = *cpa; |
992f4c1c | 961 | alias_cpa.vaddr = &laddr; |
9ae28475 | 962 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 963 | |
f34b439f | 964 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
965 | if (ret) |
966 | return ret; | |
f34b439f | 967 | } |
44af6c41 | 968 | |
44af6c41 | 969 | #ifdef CONFIG_X86_64 |
488fd995 | 970 | /* |
992f4c1c TH |
971 | * If the primary call didn't touch the high mapping already |
972 | * and the physical address is inside the kernel map, we need | |
0879750f | 973 | * to touch the high mapped kernel as well: |
488fd995 | 974 | */ |
992f4c1c TH |
975 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
976 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
977 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
978 | __START_KERNEL_map - phys_base; | |
979 | alias_cpa = *cpa; | |
980 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
981 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 982 | |
992f4c1c TH |
983 | /* |
984 | * The high mapping range is imprecise, so ignore the | |
985 | * return value. | |
986 | */ | |
987 | __change_page_attr_set_clr(&alias_cpa, 0); | |
988 | } | |
488fd995 | 989 | #endif |
992f4c1c TH |
990 | |
991 | return 0; | |
1da177e4 LT |
992 | } |
993 | ||
c31c7d48 | 994 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 995 | { |
65e074df | 996 | int ret, numpages = cpa->numpages; |
ff31452b | 997 | |
65e074df TG |
998 | while (numpages) { |
999 | /* | |
1000 | * Store the remaining nr of pages for the large page | |
1001 | * preservation check. | |
1002 | */ | |
9b5cf48b | 1003 | cpa->numpages = numpages; |
d75586ad | 1004 | /* for array changes, we can't use large page */ |
9ae28475 | 1005 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1006 | cpa->numpages = 1; |
c31c7d48 | 1007 | |
ad5ca55f SS |
1008 | if (!debug_pagealloc) |
1009 | spin_lock(&cpa_lock); | |
c31c7d48 | 1010 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
1011 | if (!debug_pagealloc) |
1012 | spin_unlock(&cpa_lock); | |
ff31452b TG |
1013 | if (ret) |
1014 | return ret; | |
ff31452b | 1015 | |
c31c7d48 TG |
1016 | if (checkalias) { |
1017 | ret = cpa_process_alias(cpa); | |
1018 | if (ret) | |
1019 | return ret; | |
1020 | } | |
1021 | ||
65e074df TG |
1022 | /* |
1023 | * Adjust the number of pages with the result of the | |
1024 | * CPA operation. Either a large page has been | |
1025 | * preserved or a single page update happened. | |
1026 | */ | |
9b5cf48b RW |
1027 | BUG_ON(cpa->numpages > numpages); |
1028 | numpages -= cpa->numpages; | |
9ae28475 | 1029 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1030 | cpa->curpage++; |
1031 | else | |
1032 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1033 | ||
65e074df | 1034 | } |
ff31452b TG |
1035 | return 0; |
1036 | } | |
1037 | ||
6bb8383b AK |
1038 | static inline int cache_attr(pgprot_t attr) |
1039 | { | |
1040 | return pgprot_val(attr) & | |
1041 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
1042 | } | |
1043 | ||
d75586ad | 1044 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1045 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1046 | int force_split, int in_flag, |
1047 | struct page **pages) | |
ff31452b | 1048 | { |
72e458df | 1049 | struct cpa_data cpa; |
cacf8906 | 1050 | int ret, cache, checkalias; |
fa526d0d | 1051 | unsigned long baddr = 0; |
331e4065 TG |
1052 | |
1053 | /* | |
1054 | * Check, if we are requested to change a not supported | |
1055 | * feature: | |
1056 | */ | |
1057 | mask_set = canon_pgprot(mask_set); | |
1058 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 1059 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1060 | return 0; |
1061 | ||
69b1415e | 1062 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1063 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1064 | int i; |
1065 | for (i = 0; i < numpages; i++) { | |
1066 | if (addr[i] & ~PAGE_MASK) { | |
1067 | addr[i] &= PAGE_MASK; | |
1068 | WARN_ON_ONCE(1); | |
1069 | } | |
1070 | } | |
9ae28475 | 1071 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1072 | /* | |
1073 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1074 | * No need to cehck in that case | |
1075 | */ | |
1076 | if (*addr & ~PAGE_MASK) { | |
1077 | *addr &= PAGE_MASK; | |
1078 | /* | |
1079 | * People should not be passing in unaligned addresses: | |
1080 | */ | |
1081 | WARN_ON_ONCE(1); | |
1082 | } | |
fa526d0d JS |
1083 | /* |
1084 | * Save address for cache flush. *addr is modified in the call | |
1085 | * to __change_page_attr_set_clr() below. | |
1086 | */ | |
1087 | baddr = *addr; | |
69b1415e TG |
1088 | } |
1089 | ||
5843d9a4 NP |
1090 | /* Must avoid aliasing mappings in the highmem code */ |
1091 | kmap_flush_unused(); | |
1092 | ||
db64fe02 NP |
1093 | vm_unmap_aliases(); |
1094 | ||
72e458df | 1095 | cpa.vaddr = addr; |
9ae28475 | 1096 | cpa.pages = pages; |
72e458df TG |
1097 | cpa.numpages = numpages; |
1098 | cpa.mask_set = mask_set; | |
1099 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1100 | cpa.flags = 0; |
1101 | cpa.curpage = 0; | |
c9caa02c | 1102 | cpa.force_split = force_split; |
72e458df | 1103 | |
9ae28475 | 1104 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1105 | cpa.flags |= in_flag; | |
d75586ad | 1106 | |
af96e443 TG |
1107 | /* No alias checking for _NX bit modifications */ |
1108 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1109 | ||
1110 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1111 | |
f4ae5da0 TG |
1112 | /* |
1113 | * Check whether we really changed something: | |
1114 | */ | |
d75586ad | 1115 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1116 | goto out; |
cacf8906 | 1117 | |
6bb8383b AK |
1118 | /* |
1119 | * No need to flush, when we did not set any of the caching | |
1120 | * attributes: | |
1121 | */ | |
1122 | cache = cache_attr(mask_set); | |
1123 | ||
57a6a46a TG |
1124 | /* |
1125 | * On success we use clflush, when the CPU supports it to | |
f026cfa8 PA |
1126 | * avoid the wbindv. If the CPU does not support it and in the |
1127 | * error case we fall back to cpa_flush_all (which uses | |
1128 | * wbindv): | |
57a6a46a | 1129 | */ |
f026cfa8 | 1130 | if (!ret && cpu_has_clflush) { |
9ae28475 | 1131 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1132 | cpa_flush_array(addr, numpages, cache, | |
1133 | cpa.flags, pages); | |
1134 | } else | |
fa526d0d | 1135 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1136 | } else |
6bb8383b | 1137 | cpa_flush_all(cache); |
cacf8906 | 1138 | |
76ebd054 | 1139 | out: |
ff31452b TG |
1140 | return ret; |
1141 | } | |
1142 | ||
d75586ad SL |
1143 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1144 | pgprot_t mask, int array) | |
75cbade8 | 1145 | { |
d75586ad | 1146 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1147 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1148 | } |
1149 | ||
d75586ad SL |
1150 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1151 | pgprot_t mask, int array) | |
72932c7a | 1152 | { |
d75586ad | 1153 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1154 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1155 | } |
1156 | ||
0f350755 | 1157 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1158 | pgprot_t mask) | |
1159 | { | |
1160 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1161 | CPA_PAGES_ARRAY, pages); | |
1162 | } | |
1163 | ||
1164 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1165 | pgprot_t mask) | |
1166 | { | |
1167 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1168 | CPA_PAGES_ARRAY, pages); | |
1169 | } | |
1170 | ||
1219333d | 1171 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1172 | { |
de33c442 SS |
1173 | /* |
1174 | * for now UC MINUS. see comments in ioremap_nocache() | |
1175 | */ | |
d75586ad SL |
1176 | return change_page_attr_set(&addr, numpages, |
1177 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 1178 | } |
1219333d | 1179 | |
1180 | int set_memory_uc(unsigned long addr, int numpages) | |
1181 | { | |
9fa3ab39 | 1182 | int ret; |
1183 | ||
de33c442 SS |
1184 | /* |
1185 | * for now UC MINUS. see comments in ioremap_nocache() | |
1186 | */ | |
9fa3ab39 | 1187 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1188 | _PAGE_CACHE_UC_MINUS, NULL); | |
1189 | if (ret) | |
1190 | goto out_err; | |
1191 | ||
1192 | ret = _set_memory_uc(addr, numpages); | |
1193 | if (ret) | |
1194 | goto out_free; | |
1195 | ||
1196 | return 0; | |
1219333d | 1197 | |
9fa3ab39 | 1198 | out_free: |
1199 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1200 | out_err: | |
1201 | return ret; | |
1219333d | 1202 | } |
75cbade8 AV |
1203 | EXPORT_SYMBOL(set_memory_uc); |
1204 | ||
2d070eff | 1205 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
4f646254 | 1206 | unsigned long new_type) |
d75586ad | 1207 | { |
9fa3ab39 | 1208 | int i, j; |
1209 | int ret; | |
1210 | ||
d75586ad SL |
1211 | /* |
1212 | * for now UC MINUS. see comments in ioremap_nocache() | |
1213 | */ | |
1214 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 1215 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1216 | new_type, NULL); |
9fa3ab39 | 1217 | if (ret) |
1218 | goto out_free; | |
d75586ad SL |
1219 | } |
1220 | ||
9fa3ab39 | 1221 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 1222 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
4f646254 PN |
1223 | |
1224 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1225 | ret = change_page_attr_set_clr(addr, addrinarray, | |
1226 | __pgprot(_PAGE_CACHE_WC), | |
1227 | __pgprot(_PAGE_CACHE_MASK), | |
1228 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1229 | if (ret) |
1230 | goto out_free; | |
1231 | ||
1232 | return 0; | |
1233 | ||
1234 | out_free: | |
1235 | for (j = 0; j < i; j++) | |
1236 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1237 | ||
1238 | return ret; | |
d75586ad | 1239 | } |
4f646254 PN |
1240 | |
1241 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1242 | { | |
1243 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1244 | } | |
d75586ad SL |
1245 | EXPORT_SYMBOL(set_memory_array_uc); |
1246 | ||
4f646254 PN |
1247 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1248 | { | |
1249 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC); | |
1250 | } | |
1251 | EXPORT_SYMBOL(set_memory_array_wc); | |
1252 | ||
ef354af4 | 1253 | int _set_memory_wc(unsigned long addr, int numpages) |
1254 | { | |
3869c4aa | 1255 | int ret; |
bdc6340f PV |
1256 | unsigned long addr_copy = addr; |
1257 | ||
3869c4aa | 1258 | ret = change_page_attr_set(&addr, numpages, |
1259 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1260 | if (!ret) { |
bdc6340f PV |
1261 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1262 | __pgprot(_PAGE_CACHE_WC), | |
1263 | __pgprot(_PAGE_CACHE_MASK), | |
1264 | 0, 0, NULL); | |
3869c4aa | 1265 | } |
1266 | return ret; | |
ef354af4 | 1267 | } |
1268 | ||
1269 | int set_memory_wc(unsigned long addr, int numpages) | |
1270 | { | |
9fa3ab39 | 1271 | int ret; |
1272 | ||
499f8f84 | 1273 | if (!pat_enabled) |
ef354af4 | 1274 | return set_memory_uc(addr, numpages); |
1275 | ||
9fa3ab39 | 1276 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1277 | _PAGE_CACHE_WC, NULL); | |
1278 | if (ret) | |
1279 | goto out_err; | |
ef354af4 | 1280 | |
9fa3ab39 | 1281 | ret = _set_memory_wc(addr, numpages); |
1282 | if (ret) | |
1283 | goto out_free; | |
1284 | ||
1285 | return 0; | |
1286 | ||
1287 | out_free: | |
1288 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1289 | out_err: | |
1290 | return ret; | |
ef354af4 | 1291 | } |
1292 | EXPORT_SYMBOL(set_memory_wc); | |
1293 | ||
1219333d | 1294 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1295 | { |
d75586ad SL |
1296 | return change_page_attr_clear(&addr, numpages, |
1297 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1298 | } |
1219333d | 1299 | |
1300 | int set_memory_wb(unsigned long addr, int numpages) | |
1301 | { | |
9fa3ab39 | 1302 | int ret; |
1303 | ||
1304 | ret = _set_memory_wb(addr, numpages); | |
1305 | if (ret) | |
1306 | return ret; | |
1307 | ||
c15238df | 1308 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1309 | return 0; |
1219333d | 1310 | } |
75cbade8 AV |
1311 | EXPORT_SYMBOL(set_memory_wb); |
1312 | ||
d75586ad SL |
1313 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1314 | { | |
1315 | int i; | |
a5593e0b | 1316 | int ret; |
1317 | ||
1318 | ret = change_page_attr_clear(addr, addrinarray, | |
1319 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1320 | if (ret) |
1321 | return ret; | |
d75586ad | 1322 | |
9fa3ab39 | 1323 | for (i = 0; i < addrinarray; i++) |
1324 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1325 | |
9fa3ab39 | 1326 | return 0; |
d75586ad SL |
1327 | } |
1328 | EXPORT_SYMBOL(set_memory_array_wb); | |
1329 | ||
75cbade8 AV |
1330 | int set_memory_x(unsigned long addr, int numpages) |
1331 | { | |
583140af PA |
1332 | if (!(__supported_pte_mask & _PAGE_NX)) |
1333 | return 0; | |
1334 | ||
d75586ad | 1335 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1336 | } |
1337 | EXPORT_SYMBOL(set_memory_x); | |
1338 | ||
1339 | int set_memory_nx(unsigned long addr, int numpages) | |
1340 | { | |
583140af PA |
1341 | if (!(__supported_pte_mask & _PAGE_NX)) |
1342 | return 0; | |
1343 | ||
d75586ad | 1344 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1345 | } |
1346 | EXPORT_SYMBOL(set_memory_nx); | |
1347 | ||
1348 | int set_memory_ro(unsigned long addr, int numpages) | |
1349 | { | |
d75586ad | 1350 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1351 | } |
a03352d2 | 1352 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1353 | |
1354 | int set_memory_rw(unsigned long addr, int numpages) | |
1355 | { | |
d75586ad | 1356 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1357 | } |
a03352d2 | 1358 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1359 | |
1360 | int set_memory_np(unsigned long addr, int numpages) | |
1361 | { | |
d75586ad | 1362 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1363 | } |
75cbade8 | 1364 | |
c9caa02c AK |
1365 | int set_memory_4k(unsigned long addr, int numpages) |
1366 | { | |
d75586ad | 1367 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1368 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1369 | } |
1370 | ||
75cbade8 AV |
1371 | int set_pages_uc(struct page *page, int numpages) |
1372 | { | |
1373 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1374 | |
d7c8f21a | 1375 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1376 | } |
1377 | EXPORT_SYMBOL(set_pages_uc); | |
1378 | ||
4f646254 PN |
1379 | static int _set_pages_array(struct page **pages, int addrinarray, |
1380 | unsigned long new_type) | |
0f350755 | 1381 | { |
1382 | unsigned long start; | |
1383 | unsigned long end; | |
1384 | int i; | |
1385 | int free_idx; | |
4f646254 | 1386 | int ret; |
0f350755 | 1387 | |
1388 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1389 | if (PageHighMem(pages[i])) |
1390 | continue; | |
1391 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1392 | end = start + PAGE_SIZE; |
4f646254 | 1393 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1394 | goto err_out; |
1395 | } | |
1396 | ||
4f646254 PN |
1397 | ret = cpa_set_pages_array(pages, addrinarray, |
1398 | __pgprot(_PAGE_CACHE_UC_MINUS)); | |
1399 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1400 | ret = change_page_attr_set_clr(NULL, addrinarray, | |
1401 | __pgprot(_PAGE_CACHE_WC), | |
1402 | __pgprot(_PAGE_CACHE_MASK), | |
1403 | 0, CPA_PAGES_ARRAY, pages); | |
1404 | if (ret) | |
1405 | goto err_out; | |
1406 | return 0; /* Success */ | |
0f350755 | 1407 | err_out: |
1408 | free_idx = i; | |
1409 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1410 | if (PageHighMem(pages[i])) |
1411 | continue; | |
1412 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1413 | end = start + PAGE_SIZE; |
1414 | free_memtype(start, end); | |
1415 | } | |
1416 | return -EINVAL; | |
1417 | } | |
4f646254 PN |
1418 | |
1419 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1420 | { | |
1421 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1422 | } | |
0f350755 | 1423 | EXPORT_SYMBOL(set_pages_array_uc); |
1424 | ||
4f646254 PN |
1425 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1426 | { | |
1427 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC); | |
1428 | } | |
1429 | EXPORT_SYMBOL(set_pages_array_wc); | |
1430 | ||
75cbade8 AV |
1431 | int set_pages_wb(struct page *page, int numpages) |
1432 | { | |
1433 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1434 | |
d7c8f21a | 1435 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1436 | } |
1437 | EXPORT_SYMBOL(set_pages_wb); | |
1438 | ||
0f350755 | 1439 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1440 | { | |
1441 | int retval; | |
1442 | unsigned long start; | |
1443 | unsigned long end; | |
1444 | int i; | |
1445 | ||
1446 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1447 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1448 | if (retval) |
1449 | return retval; | |
0f350755 | 1450 | |
1451 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1452 | if (PageHighMem(pages[i])) |
1453 | continue; | |
1454 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1455 | end = start + PAGE_SIZE; |
1456 | free_memtype(start, end); | |
1457 | } | |
1458 | ||
9fa3ab39 | 1459 | return 0; |
0f350755 | 1460 | } |
1461 | EXPORT_SYMBOL(set_pages_array_wb); | |
1462 | ||
75cbade8 AV |
1463 | int set_pages_x(struct page *page, int numpages) |
1464 | { | |
1465 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1466 | |
d7c8f21a | 1467 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1468 | } |
1469 | EXPORT_SYMBOL(set_pages_x); | |
1470 | ||
1471 | int set_pages_nx(struct page *page, int numpages) | |
1472 | { | |
1473 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1474 | |
d7c8f21a | 1475 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1476 | } |
1477 | EXPORT_SYMBOL(set_pages_nx); | |
1478 | ||
1479 | int set_pages_ro(struct page *page, int numpages) | |
1480 | { | |
1481 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1482 | |
d7c8f21a | 1483 | return set_memory_ro(addr, numpages); |
75cbade8 | 1484 | } |
75cbade8 AV |
1485 | |
1486 | int set_pages_rw(struct page *page, int numpages) | |
1487 | { | |
1488 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1489 | |
d7c8f21a | 1490 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1491 | } |
1492 | ||
1da177e4 | 1493 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1494 | |
1495 | static int __set_pages_p(struct page *page, int numpages) | |
1496 | { | |
d75586ad SL |
1497 | unsigned long tempaddr = (unsigned long) page_address(page); |
1498 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1499 | .numpages = numpages, |
1500 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1501 | .mask_clr = __pgprot(0), |
1502 | .flags = 0}; | |
72932c7a | 1503 | |
55121b43 SS |
1504 | /* |
1505 | * No alias checking needed for setting present flag. otherwise, | |
1506 | * we may need to break large pages for 64-bit kernel text | |
1507 | * mappings (this adds to complexity if we want to do this from | |
1508 | * atomic context especially). Let's keep it simple! | |
1509 | */ | |
1510 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1511 | } |
1512 | ||
1513 | static int __set_pages_np(struct page *page, int numpages) | |
1514 | { | |
d75586ad SL |
1515 | unsigned long tempaddr = (unsigned long) page_address(page); |
1516 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1517 | .numpages = numpages, |
1518 | .mask_set = __pgprot(0), | |
d75586ad SL |
1519 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1520 | .flags = 0}; | |
72932c7a | 1521 | |
55121b43 SS |
1522 | /* |
1523 | * No alias checking needed for setting not present flag. otherwise, | |
1524 | * we may need to break large pages for 64-bit kernel text | |
1525 | * mappings (this adds to complexity if we want to do this from | |
1526 | * atomic context especially). Let's keep it simple! | |
1527 | */ | |
1528 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1529 | } |
1530 | ||
1da177e4 LT |
1531 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1532 | { | |
1533 | if (PageHighMem(page)) | |
1534 | return; | |
9f4c815c | 1535 | if (!enable) { |
f9b8404c IM |
1536 | debug_check_no_locks_freed(page_address(page), |
1537 | numpages * PAGE_SIZE); | |
9f4c815c | 1538 | } |
de5097c2 | 1539 | |
9f4c815c | 1540 | /* |
f8d8406b | 1541 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1542 | * Large pages for identity mappings are not used at boot time |
1543 | * and hence no memory allocations during large page split. | |
1da177e4 | 1544 | */ |
f62d0f00 IM |
1545 | if (enable) |
1546 | __set_pages_p(page, numpages); | |
1547 | else | |
1548 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1549 | |
1550 | /* | |
e4b71dcf IM |
1551 | * We should perform an IPI and flush all tlbs, |
1552 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1553 | */ |
1554 | __flush_tlb_all(); | |
26564600 BO |
1555 | |
1556 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1557 | } |
1558 | ||
8a235efa RW |
1559 | #ifdef CONFIG_HIBERNATION |
1560 | ||
1561 | bool kernel_page_present(struct page *page) | |
1562 | { | |
1563 | unsigned int level; | |
1564 | pte_t *pte; | |
1565 | ||
1566 | if (PageHighMem(page)) | |
1567 | return false; | |
1568 | ||
1569 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1570 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1571 | } | |
1572 | ||
1573 | #endif /* CONFIG_HIBERNATION */ | |
1574 | ||
1575 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1576 | |
1577 | /* | |
1578 | * The testcases use internal knowledge of the implementation that shouldn't | |
1579 | * be exposed to the rest of the kernel. Include these directly here. | |
1580 | */ | |
1581 | #ifdef CONFIG_CPA_DEBUG | |
1582 | #include "pageattr-test.c" | |
1583 | #endif |