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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
9f4c815c IM |
19 | #include <asm/uaccess.h> |
20 | #include <asm/pgalloc.h> | |
c31c7d48 | 21 | #include <asm/proto.h> |
1219333d | 22 | #include <asm/pat.h> |
1da177e4 | 23 | |
9df84993 IM |
24 | /* |
25 | * The current flushing context - we pass it instead of 5 arguments: | |
26 | */ | |
72e458df | 27 | struct cpa_data { |
d75586ad | 28 | unsigned long *vaddr; |
72e458df TG |
29 | pgprot_t mask_set; |
30 | pgprot_t mask_clr; | |
65e074df | 31 | int numpages; |
d75586ad | 32 | int flags; |
c31c7d48 | 33 | unsigned long pfn; |
c9caa02c | 34 | unsigned force_split : 1; |
d75586ad | 35 | int curpage; |
72e458df TG |
36 | }; |
37 | ||
ad5ca55f SS |
38 | /* |
39 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
40 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
41 | * entries change the page attribute in parallel to some other cpu | |
42 | * splitting a large page entry along with changing the attribute. | |
43 | */ | |
44 | static DEFINE_SPINLOCK(cpa_lock); | |
45 | ||
d75586ad SL |
46 | #define CPA_FLUSHTLB 1 |
47 | #define CPA_ARRAY 2 | |
48 | ||
65280e61 | 49 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
50 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
51 | ||
65280e61 | 52 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 53 | { |
ce0c0e50 | 54 | unsigned long flags; |
65280e61 | 55 | |
ce0c0e50 AK |
56 | /* Protect against CPA */ |
57 | spin_lock_irqsave(&pgd_lock, flags); | |
58 | direct_pages_count[level] += pages; | |
59 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
60 | } |
61 | ||
62 | static void split_page_count(int level) | |
63 | { | |
64 | direct_pages_count[level]--; | |
65 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
66 | } | |
67 | ||
e1759c21 | 68 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 69 | { |
b9c3bfc2 | 70 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
71 | direct_pages_count[PG_LEVEL_4K] << 2); |
72 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 73 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
74 | direct_pages_count[PG_LEVEL_2M] << 11); |
75 | #else | |
b9c3bfc2 | 76 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
77 | direct_pages_count[PG_LEVEL_2M] << 12); |
78 | #endif | |
65280e61 | 79 | #ifdef CONFIG_X86_64 |
a06de630 | 80 | if (direct_gbpages) |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 82 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
83 | #endif |
84 | } | |
65280e61 TG |
85 | #else |
86 | static inline void split_page_count(int level) { } | |
87 | #endif | |
ce0c0e50 | 88 | |
c31c7d48 TG |
89 | #ifdef CONFIG_X86_64 |
90 | ||
91 | static inline unsigned long highmap_start_pfn(void) | |
92 | { | |
93 | return __pa(_text) >> PAGE_SHIFT; | |
94 | } | |
95 | ||
96 | static inline unsigned long highmap_end_pfn(void) | |
97 | { | |
15ae2d76 | 98 | return __pa(roundup((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
99 | } |
100 | ||
101 | #endif | |
102 | ||
92cb54a3 IM |
103 | #ifdef CONFIG_DEBUG_PAGEALLOC |
104 | # define debug_pagealloc 1 | |
105 | #else | |
106 | # define debug_pagealloc 0 | |
107 | #endif | |
108 | ||
ed724be6 AV |
109 | static inline int |
110 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 111 | { |
ed724be6 AV |
112 | return addr >= start && addr < end; |
113 | } | |
114 | ||
d7c8f21a TG |
115 | /* |
116 | * Flushing functions | |
117 | */ | |
cd8ddf1a | 118 | |
cd8ddf1a TG |
119 | /** |
120 | * clflush_cache_range - flush a cache range with clflush | |
121 | * @addr: virtual start address | |
122 | * @size: number of bytes to flush | |
123 | * | |
124 | * clflush is an unordered instruction which needs fencing with mfence | |
125 | * to avoid ordering issues. | |
126 | */ | |
4c61afcd | 127 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 128 | { |
4c61afcd | 129 | void *vend = vaddr + size - 1; |
d7c8f21a | 130 | |
cd8ddf1a | 131 | mb(); |
4c61afcd IM |
132 | |
133 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
134 | clflush(vaddr); | |
135 | /* | |
136 | * Flush any possible final partial cacheline: | |
137 | */ | |
138 | clflush(vend); | |
139 | ||
cd8ddf1a | 140 | mb(); |
d7c8f21a TG |
141 | } |
142 | ||
af1e6844 | 143 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 144 | { |
6bb8383b AK |
145 | unsigned long cache = (unsigned long)arg; |
146 | ||
d7c8f21a TG |
147 | /* |
148 | * Flush all to work around Errata in early athlons regarding | |
149 | * large page flushing. | |
150 | */ | |
151 | __flush_tlb_all(); | |
152 | ||
6bb8383b | 153 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
154 | wbinvd(); |
155 | } | |
156 | ||
6bb8383b | 157 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
158 | { |
159 | BUG_ON(irqs_disabled()); | |
160 | ||
15c8b6c1 | 161 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
162 | } |
163 | ||
57a6a46a TG |
164 | static void __cpa_flush_range(void *arg) |
165 | { | |
57a6a46a TG |
166 | /* |
167 | * We could optimize that further and do individual per page | |
168 | * tlb invalidates for a low number of pages. Caveat: we must | |
169 | * flush the high aliases on 64bit as well. | |
170 | */ | |
171 | __flush_tlb_all(); | |
57a6a46a TG |
172 | } |
173 | ||
6bb8383b | 174 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 175 | { |
4c61afcd IM |
176 | unsigned int i, level; |
177 | unsigned long addr; | |
178 | ||
57a6a46a | 179 | BUG_ON(irqs_disabled()); |
4c61afcd | 180 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 181 | |
15c8b6c1 | 182 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 183 | |
6bb8383b AK |
184 | if (!cache) |
185 | return; | |
186 | ||
3b233e52 TG |
187 | /* |
188 | * We only need to flush on one CPU, | |
189 | * clflush is a MESI-coherent instruction that | |
190 | * will cause all other CPUs to flush the same | |
191 | * cachelines: | |
192 | */ | |
4c61afcd IM |
193 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
194 | pte_t *pte = lookup_address(addr, &level); | |
195 | ||
196 | /* | |
197 | * Only flush present addresses: | |
198 | */ | |
7bfb72e8 | 199 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
200 | clflush_cache_range((void *) addr, PAGE_SIZE); |
201 | } | |
57a6a46a TG |
202 | } |
203 | ||
d75586ad SL |
204 | static void cpa_flush_array(unsigned long *start, int numpages, int cache) |
205 | { | |
206 | unsigned int i, level; | |
207 | unsigned long *addr; | |
208 | ||
209 | BUG_ON(irqs_disabled()); | |
210 | ||
211 | on_each_cpu(__cpa_flush_range, NULL, 1); | |
212 | ||
213 | if (!cache) | |
214 | return; | |
215 | ||
216 | /* 4M threshold */ | |
217 | if (numpages >= 1024) { | |
218 | if (boot_cpu_data.x86_model >= 4) | |
219 | wbinvd(); | |
220 | return; | |
221 | } | |
222 | /* | |
223 | * We only need to flush on one CPU, | |
224 | * clflush is a MESI-coherent instruction that | |
225 | * will cause all other CPUs to flush the same | |
226 | * cachelines: | |
227 | */ | |
228 | for (i = 0, addr = start; i < numpages; i++, addr++) { | |
229 | pte_t *pte = lookup_address(*addr, &level); | |
230 | ||
231 | /* | |
232 | * Only flush present addresses: | |
233 | */ | |
234 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
235 | clflush_cache_range((void *) *addr, PAGE_SIZE); | |
236 | } | |
237 | } | |
238 | ||
ed724be6 AV |
239 | /* |
240 | * Certain areas of memory on x86 require very specific protection flags, | |
241 | * for example the BIOS area or kernel text. Callers don't always get this | |
242 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
243 | * checks and fixes these known static required protection bits. | |
244 | */ | |
c31c7d48 TG |
245 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
246 | unsigned long pfn) | |
ed724be6 AV |
247 | { |
248 | pgprot_t forbidden = __pgprot(0); | |
249 | ||
687c4825 | 250 | /* |
ed724be6 AV |
251 | * The BIOS area between 640k and 1Mb needs to be executable for |
252 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 253 | */ |
c31c7d48 | 254 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
255 | pgprot_val(forbidden) |= _PAGE_NX; |
256 | ||
257 | /* | |
258 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
259 | * Does not cover __inittext since that is gone later on. On |
260 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
261 | */ |
262 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
263 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 264 | |
cc0f21bb | 265 | /* |
c31c7d48 TG |
266 | * The .rodata section needs to be read-only. Using the pfn |
267 | * catches all aliases. | |
cc0f21bb | 268 | */ |
c31c7d48 TG |
269 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
270 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 271 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
272 | |
273 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
274 | |
275 | return prot; | |
276 | } | |
277 | ||
9a14aefc TG |
278 | /* |
279 | * Lookup the page table entry for a virtual address. Return a pointer | |
280 | * to the entry and the level of the mapping. | |
281 | * | |
282 | * Note: We return pud and pmd either when the entry is marked large | |
283 | * or when the present bit is not set. Otherwise we would return a | |
284 | * pointer to a nonexisting mapping. | |
285 | */ | |
da7bfc50 | 286 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 287 | { |
1da177e4 LT |
288 | pgd_t *pgd = pgd_offset_k(address); |
289 | pud_t *pud; | |
290 | pmd_t *pmd; | |
9f4c815c | 291 | |
30551bb3 TG |
292 | *level = PG_LEVEL_NONE; |
293 | ||
1da177e4 LT |
294 | if (pgd_none(*pgd)) |
295 | return NULL; | |
9df84993 | 296 | |
1da177e4 LT |
297 | pud = pud_offset(pgd, address); |
298 | if (pud_none(*pud)) | |
299 | return NULL; | |
c2f71ee2 AK |
300 | |
301 | *level = PG_LEVEL_1G; | |
302 | if (pud_large(*pud) || !pud_present(*pud)) | |
303 | return (pte_t *)pud; | |
304 | ||
1da177e4 LT |
305 | pmd = pmd_offset(pud, address); |
306 | if (pmd_none(*pmd)) | |
307 | return NULL; | |
30551bb3 TG |
308 | |
309 | *level = PG_LEVEL_2M; | |
9a14aefc | 310 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 311 | return (pte_t *)pmd; |
1da177e4 | 312 | |
30551bb3 | 313 | *level = PG_LEVEL_4K; |
9df84993 | 314 | |
9f4c815c IM |
315 | return pte_offset_kernel(pmd, address); |
316 | } | |
75bb8835 | 317 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 318 | |
9df84993 IM |
319 | /* |
320 | * Set the new pmd in all the pgds we know about: | |
321 | */ | |
9a3dc780 | 322 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 323 | { |
9f4c815c IM |
324 | /* change init_mm */ |
325 | set_pte_atomic(kpte, pte); | |
44af6c41 | 326 | #ifdef CONFIG_X86_32 |
e4b71dcf | 327 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
328 | struct page *page; |
329 | ||
e3ed910d | 330 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
331 | pgd_t *pgd; |
332 | pud_t *pud; | |
333 | pmd_t *pmd; | |
334 | ||
335 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
336 | pud = pud_offset(pgd, address); | |
337 | pmd = pmd_offset(pud, address); | |
338 | set_pte_atomic((pte_t *)pmd, pte); | |
339 | } | |
1da177e4 | 340 | } |
44af6c41 | 341 | #endif |
1da177e4 LT |
342 | } |
343 | ||
9df84993 IM |
344 | static int |
345 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
346 | struct cpa_data *cpa) | |
65e074df | 347 | { |
c31c7d48 | 348 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
349 | pte_t new_pte, old_pte, *tmp; |
350 | pgprot_t old_prot, new_prot; | |
fac84939 | 351 | int i, do_split = 1; |
da7bfc50 | 352 | unsigned int level; |
65e074df | 353 | |
c9caa02c AK |
354 | if (cpa->force_split) |
355 | return 1; | |
356 | ||
65e074df TG |
357 | spin_lock_irqsave(&pgd_lock, flags); |
358 | /* | |
359 | * Check for races, another CPU might have split this page | |
360 | * up already: | |
361 | */ | |
362 | tmp = lookup_address(address, &level); | |
363 | if (tmp != kpte) | |
364 | goto out_unlock; | |
365 | ||
366 | switch (level) { | |
367 | case PG_LEVEL_2M: | |
31422c51 AK |
368 | psize = PMD_PAGE_SIZE; |
369 | pmask = PMD_PAGE_MASK; | |
65e074df | 370 | break; |
f07333fd | 371 | #ifdef CONFIG_X86_64 |
65e074df | 372 | case PG_LEVEL_1G: |
5d3c8b21 AK |
373 | psize = PUD_PAGE_SIZE; |
374 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
375 | break; |
376 | #endif | |
65e074df | 377 | default: |
beaff633 | 378 | do_split = -EINVAL; |
65e074df TG |
379 | goto out_unlock; |
380 | } | |
381 | ||
382 | /* | |
383 | * Calculate the number of pages, which fit into this large | |
384 | * page starting at address: | |
385 | */ | |
386 | nextpage_addr = (address + psize) & pmask; | |
387 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
388 | if (numpages < cpa->numpages) |
389 | cpa->numpages = numpages; | |
65e074df TG |
390 | |
391 | /* | |
392 | * We are safe now. Check whether the new pgprot is the same: | |
393 | */ | |
394 | old_pte = *kpte; | |
395 | old_prot = new_prot = pte_pgprot(old_pte); | |
396 | ||
397 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
398 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
399 | |
400 | /* | |
401 | * old_pte points to the large page base address. So we need | |
402 | * to add the offset of the virtual address: | |
403 | */ | |
404 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
405 | cpa->pfn = pfn; | |
406 | ||
407 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 408 | |
fac84939 TG |
409 | /* |
410 | * We need to check the full range, whether | |
411 | * static_protection() requires a different pgprot for one of | |
412 | * the pages in the range we try to preserve: | |
413 | */ | |
414 | addr = address + PAGE_SIZE; | |
c31c7d48 | 415 | pfn++; |
9b5cf48b | 416 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 417 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
418 | |
419 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
420 | goto out_unlock; | |
421 | } | |
422 | ||
65e074df TG |
423 | /* |
424 | * If there are no changes, return. maxpages has been updated | |
425 | * above: | |
426 | */ | |
427 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 428 | do_split = 0; |
65e074df TG |
429 | goto out_unlock; |
430 | } | |
431 | ||
432 | /* | |
433 | * We need to change the attributes. Check, whether we can | |
434 | * change the large page in one go. We request a split, when | |
435 | * the address is not aligned and the number of pages is | |
436 | * smaller than the number of pages in the large page. Note | |
437 | * that we limited the number of possible pages already to | |
438 | * the number of pages in the large page. | |
439 | */ | |
9b5cf48b | 440 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
441 | /* |
442 | * The address is aligned and the number of pages | |
443 | * covers the full page. | |
444 | */ | |
445 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
446 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 447 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 448 | do_split = 0; |
65e074df TG |
449 | } |
450 | ||
451 | out_unlock: | |
452 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 453 | |
beaff633 | 454 | return do_split; |
65e074df TG |
455 | } |
456 | ||
7afe15b9 | 457 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 458 | { |
7b610eec | 459 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 460 | unsigned int i, level; |
bb5c2dbd | 461 | pte_t *pbase, *tmp; |
9df84993 | 462 | pgprot_t ref_prot; |
ad5ca55f SS |
463 | struct page *base; |
464 | ||
465 | if (!debug_pagealloc) | |
466 | spin_unlock(&cpa_lock); | |
467 | base = alloc_pages(GFP_KERNEL, 0); | |
468 | if (!debug_pagealloc) | |
469 | spin_lock(&cpa_lock); | |
8311eb84 SS |
470 | if (!base) |
471 | return -ENOMEM; | |
bb5c2dbd | 472 | |
eb5b5f02 | 473 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
474 | /* |
475 | * Check for races, another CPU might have split this page | |
476 | * up for us already: | |
477 | */ | |
478 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 479 | if (tmp != kpte) |
bb5c2dbd IM |
480 | goto out_unlock; |
481 | ||
bb5c2dbd | 482 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 483 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 484 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
bb5c2dbd | 485 | |
f07333fd AK |
486 | #ifdef CONFIG_X86_64 |
487 | if (level == PG_LEVEL_1G) { | |
488 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
489 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
490 | } |
491 | #endif | |
492 | ||
63c1dcf4 TG |
493 | /* |
494 | * Get the target pfn from the original entry: | |
495 | */ | |
496 | pfn = pte_pfn(*kpte); | |
f07333fd | 497 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 498 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 499 | |
ce0c0e50 | 500 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
501 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
502 | split_page_count(level); | |
503 | ||
504 | #ifdef CONFIG_X86_64 | |
505 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
506 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
507 | split_page_count(level); | |
f361a450 | 508 | #endif |
ce0c0e50 | 509 | |
bb5c2dbd | 510 | /* |
07a66d7c | 511 | * Install the new, split up pagetable. |
4c881ca1 | 512 | * |
07a66d7c IM |
513 | * We use the standard kernel pagetable protections for the new |
514 | * pagetable protections, the actual ptes set above control the | |
515 | * primary protection behavior: | |
bb5c2dbd | 516 | */ |
07a66d7c | 517 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
bb5c2dbd IM |
518 | base = NULL; |
519 | ||
520 | out_unlock: | |
eb5b5f02 TG |
521 | /* |
522 | * If we dropped out via the lookup_address check under | |
523 | * pgd_lock then stick the page back into the pool: | |
524 | */ | |
8311eb84 SS |
525 | if (base) |
526 | __free_page(base); | |
9a3dc780 | 527 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 528 | |
bb5c2dbd IM |
529 | return 0; |
530 | } | |
531 | ||
a1e46212 SS |
532 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
533 | int primary) | |
534 | { | |
535 | /* | |
536 | * Ignore all non primary paths. | |
537 | */ | |
538 | if (!primary) | |
539 | return 0; | |
540 | ||
541 | /* | |
542 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
543 | * to have holes. | |
544 | * Also set numpages to '1' indicating that we processed cpa req for | |
545 | * one virtual address page and its pfn. TBD: numpages can be set based | |
546 | * on the initial value and the level returned by lookup_address(). | |
547 | */ | |
548 | if (within(vaddr, PAGE_OFFSET, | |
549 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
550 | cpa->numpages = 1; | |
551 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
552 | return 0; | |
553 | } else { | |
554 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
555 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
556 | *cpa->vaddr); | |
557 | ||
558 | return -EFAULT; | |
559 | } | |
560 | } | |
561 | ||
c31c7d48 | 562 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 563 | { |
d75586ad | 564 | unsigned long address; |
da7bfc50 HH |
565 | int do_split, err; |
566 | unsigned int level; | |
c31c7d48 | 567 | pte_t *kpte, old_pte; |
1da177e4 | 568 | |
d75586ad SL |
569 | if (cpa->flags & CPA_ARRAY) |
570 | address = cpa->vaddr[cpa->curpage]; | |
571 | else | |
572 | address = *cpa->vaddr; | |
97f99fed | 573 | repeat: |
f0646e43 | 574 | kpte = lookup_address(address, &level); |
1da177e4 | 575 | if (!kpte) |
a1e46212 | 576 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
577 | |
578 | old_pte = *kpte; | |
a1e46212 SS |
579 | if (!pte_val(old_pte)) |
580 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 581 | |
30551bb3 | 582 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 583 | pte_t new_pte; |
626c2c9d | 584 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 585 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 586 | |
72e458df TG |
587 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
588 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 589 | |
c31c7d48 | 590 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 591 | |
626c2c9d AV |
592 | /* |
593 | * We need to keep the pfn from the existing PTE, | |
594 | * after all we're only going to change it's attributes | |
595 | * not the memory it points to | |
596 | */ | |
c31c7d48 TG |
597 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
598 | cpa->pfn = pfn; | |
f4ae5da0 TG |
599 | /* |
600 | * Do we really change anything ? | |
601 | */ | |
602 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
603 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 604 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 605 | } |
9b5cf48b | 606 | cpa->numpages = 1; |
65e074df | 607 | return 0; |
1da177e4 | 608 | } |
65e074df TG |
609 | |
610 | /* | |
611 | * Check, whether we can keep the large page intact | |
612 | * and just change the pte: | |
613 | */ | |
beaff633 | 614 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
615 | /* |
616 | * When the range fits into the existing large page, | |
9b5cf48b | 617 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
618 | * try_large_page: |
619 | */ | |
87f7f8fe IM |
620 | if (do_split <= 0) |
621 | return do_split; | |
65e074df TG |
622 | |
623 | /* | |
624 | * We have to split the large page: | |
625 | */ | |
87f7f8fe IM |
626 | err = split_large_page(kpte, address); |
627 | if (!err) { | |
ad5ca55f SS |
628 | /* |
629 | * Do a global flush tlb after splitting the large page | |
630 | * and before we do the actual change page attribute in the PTE. | |
631 | * | |
632 | * With out this, we violate the TLB application note, that says | |
633 | * "The TLBs may contain both ordinary and large-page | |
634 | * translations for a 4-KByte range of linear addresses. This | |
635 | * may occur if software modifies the paging structures so that | |
636 | * the page size used for the address range changes. If the two | |
637 | * translations differ with respect to page frame or attributes | |
638 | * (e.g., permissions), processor behavior is undefined and may | |
639 | * be implementation-specific." | |
640 | * | |
641 | * We do this global tlb flush inside the cpa_lock, so that we | |
642 | * don't allow any other cpu, with stale tlb entries change the | |
643 | * page attribute in parallel, that also falls into the | |
644 | * just split large page entry. | |
645 | */ | |
646 | flush_tlb_all(); | |
87f7f8fe IM |
647 | goto repeat; |
648 | } | |
beaff633 | 649 | |
87f7f8fe | 650 | return err; |
9f4c815c | 651 | } |
1da177e4 | 652 | |
c31c7d48 TG |
653 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
654 | ||
655 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 656 | { |
c31c7d48 | 657 | struct cpa_data alias_cpa; |
f34b439f | 658 | int ret = 0; |
d75586ad | 659 | unsigned long temp_cpa_vaddr, vaddr; |
44af6c41 | 660 | |
965194c1 | 661 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 662 | return 0; |
626c2c9d | 663 | |
f361a450 | 664 | #ifdef CONFIG_X86_64 |
965194c1 | 665 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
666 | return 0; |
667 | #endif | |
f34b439f TG |
668 | /* |
669 | * No need to redo, when the primary call touched the direct | |
670 | * mapping already: | |
671 | */ | |
d75586ad SL |
672 | if (cpa->flags & CPA_ARRAY) |
673 | vaddr = cpa->vaddr[cpa->curpage]; | |
674 | else | |
675 | vaddr = *cpa->vaddr; | |
676 | ||
677 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 678 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 679 | |
f34b439f | 680 | alias_cpa = *cpa; |
d75586ad SL |
681 | temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); |
682 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
683 | alias_cpa.flags &= ~CPA_ARRAY; | |
684 | ||
f34b439f TG |
685 | |
686 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
687 | } | |
44af6c41 | 688 | |
44af6c41 | 689 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
690 | if (ret) |
691 | return ret; | |
f34b439f TG |
692 | /* |
693 | * No need to redo, when the primary call touched the high | |
694 | * mapping already: | |
695 | */ | |
d75586ad | 696 | if (within(vaddr, (unsigned long) _text, (unsigned long) _end)) |
f34b439f TG |
697 | return 0; |
698 | ||
488fd995 | 699 | /* |
0879750f TG |
700 | * If the physical address is inside the kernel map, we need |
701 | * to touch the high mapped kernel as well: | |
488fd995 | 702 | */ |
c31c7d48 TG |
703 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
704 | return 0; | |
0879750f | 705 | |
c31c7d48 | 706 | alias_cpa = *cpa; |
d75586ad SL |
707 | temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; |
708 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
709 | alias_cpa.flags &= ~CPA_ARRAY; | |
c31c7d48 TG |
710 | |
711 | /* | |
712 | * The high mapping range is imprecise, so ignore the return value. | |
713 | */ | |
714 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 715 | #endif |
c31c7d48 | 716 | return ret; |
1da177e4 LT |
717 | } |
718 | ||
c31c7d48 | 719 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 720 | { |
65e074df | 721 | int ret, numpages = cpa->numpages; |
ff31452b | 722 | |
65e074df TG |
723 | while (numpages) { |
724 | /* | |
725 | * Store the remaining nr of pages for the large page | |
726 | * preservation check. | |
727 | */ | |
9b5cf48b | 728 | cpa->numpages = numpages; |
d75586ad SL |
729 | /* for array changes, we can't use large page */ |
730 | if (cpa->flags & CPA_ARRAY) | |
731 | cpa->numpages = 1; | |
c31c7d48 | 732 | |
ad5ca55f SS |
733 | if (!debug_pagealloc) |
734 | spin_lock(&cpa_lock); | |
c31c7d48 | 735 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
736 | if (!debug_pagealloc) |
737 | spin_unlock(&cpa_lock); | |
ff31452b TG |
738 | if (ret) |
739 | return ret; | |
ff31452b | 740 | |
c31c7d48 TG |
741 | if (checkalias) { |
742 | ret = cpa_process_alias(cpa); | |
743 | if (ret) | |
744 | return ret; | |
745 | } | |
746 | ||
65e074df TG |
747 | /* |
748 | * Adjust the number of pages with the result of the | |
749 | * CPA operation. Either a large page has been | |
750 | * preserved or a single page update happened. | |
751 | */ | |
9b5cf48b RW |
752 | BUG_ON(cpa->numpages > numpages); |
753 | numpages -= cpa->numpages; | |
d75586ad SL |
754 | if (cpa->flags & CPA_ARRAY) |
755 | cpa->curpage++; | |
756 | else | |
757 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
758 | ||
65e074df | 759 | } |
ff31452b TG |
760 | return 0; |
761 | } | |
762 | ||
6bb8383b AK |
763 | static inline int cache_attr(pgprot_t attr) |
764 | { | |
765 | return pgprot_val(attr) & | |
766 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
767 | } | |
768 | ||
d75586ad | 769 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 770 | pgprot_t mask_set, pgprot_t mask_clr, |
d75586ad | 771 | int force_split, int array) |
ff31452b | 772 | { |
72e458df | 773 | struct cpa_data cpa; |
cacf8906 | 774 | int ret, cache, checkalias; |
331e4065 TG |
775 | |
776 | /* | |
777 | * Check, if we are requested to change a not supported | |
778 | * feature: | |
779 | */ | |
780 | mask_set = canon_pgprot(mask_set); | |
781 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 782 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
783 | return 0; |
784 | ||
69b1415e | 785 | /* Ensure we are PAGE_SIZE aligned */ |
d75586ad SL |
786 | if (!array) { |
787 | if (*addr & ~PAGE_MASK) { | |
788 | *addr &= PAGE_MASK; | |
789 | /* | |
790 | * People should not be passing in unaligned addresses: | |
791 | */ | |
792 | WARN_ON_ONCE(1); | |
793 | } | |
794 | } else { | |
795 | int i; | |
796 | for (i = 0; i < numpages; i++) { | |
797 | if (addr[i] & ~PAGE_MASK) { | |
798 | addr[i] &= PAGE_MASK; | |
799 | WARN_ON_ONCE(1); | |
800 | } | |
801 | } | |
69b1415e TG |
802 | } |
803 | ||
5843d9a4 NP |
804 | /* Must avoid aliasing mappings in the highmem code */ |
805 | kmap_flush_unused(); | |
806 | ||
db64fe02 NP |
807 | vm_unmap_aliases(); |
808 | ||
7ad9de6a TG |
809 | /* |
810 | * If we're called with lazy mmu updates enabled, the | |
811 | * in-memory pte state may be stale. Flush pending updates to | |
812 | * bring them up to date. | |
813 | */ | |
814 | arch_flush_lazy_mmu_mode(); | |
815 | ||
72e458df TG |
816 | cpa.vaddr = addr; |
817 | cpa.numpages = numpages; | |
818 | cpa.mask_set = mask_set; | |
819 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
820 | cpa.flags = 0; |
821 | cpa.curpage = 0; | |
c9caa02c | 822 | cpa.force_split = force_split; |
72e458df | 823 | |
d75586ad SL |
824 | if (array) |
825 | cpa.flags |= CPA_ARRAY; | |
826 | ||
af96e443 TG |
827 | /* No alias checking for _NX bit modifications */ |
828 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
829 | ||
830 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 831 | |
f4ae5da0 TG |
832 | /* |
833 | * Check whether we really changed something: | |
834 | */ | |
d75586ad | 835 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 836 | goto out; |
cacf8906 | 837 | |
6bb8383b AK |
838 | /* |
839 | * No need to flush, when we did not set any of the caching | |
840 | * attributes: | |
841 | */ | |
842 | cache = cache_attr(mask_set); | |
843 | ||
57a6a46a TG |
844 | /* |
845 | * On success we use clflush, when the CPU supports it to | |
846 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 847 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
848 | * wbindv): |
849 | */ | |
d75586ad SL |
850 | if (!ret && cpu_has_clflush) { |
851 | if (cpa.flags & CPA_ARRAY) | |
852 | cpa_flush_array(addr, numpages, cache); | |
853 | else | |
854 | cpa_flush_range(*addr, numpages, cache); | |
855 | } else | |
6bb8383b | 856 | cpa_flush_all(cache); |
cacf8906 | 857 | |
4f06b043 JF |
858 | /* |
859 | * If we've been called with lazy mmu updates enabled, then | |
860 | * make sure that everything gets flushed out before we | |
861 | * return. | |
862 | */ | |
863 | arch_flush_lazy_mmu_mode(); | |
864 | ||
76ebd054 | 865 | out: |
ff31452b TG |
866 | return ret; |
867 | } | |
868 | ||
d75586ad SL |
869 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
870 | pgprot_t mask, int array) | |
75cbade8 | 871 | { |
d75586ad SL |
872 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
873 | array); | |
75cbade8 AV |
874 | } |
875 | ||
d75586ad SL |
876 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
877 | pgprot_t mask, int array) | |
72932c7a | 878 | { |
d75586ad SL |
879 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
880 | array); | |
72932c7a TG |
881 | } |
882 | ||
1219333d | 883 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 884 | { |
de33c442 SS |
885 | /* |
886 | * for now UC MINUS. see comments in ioremap_nocache() | |
887 | */ | |
d75586ad SL |
888 | return change_page_attr_set(&addr, numpages, |
889 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 890 | } |
1219333d | 891 | |
892 | int set_memory_uc(unsigned long addr, int numpages) | |
893 | { | |
de33c442 SS |
894 | /* |
895 | * for now UC MINUS. see comments in ioremap_nocache() | |
896 | */ | |
c15238df | 897 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
de33c442 | 898 | _PAGE_CACHE_UC_MINUS, NULL)) |
1219333d | 899 | return -EINVAL; |
900 | ||
901 | return _set_memory_uc(addr, numpages); | |
902 | } | |
75cbade8 AV |
903 | EXPORT_SYMBOL(set_memory_uc); |
904 | ||
d75586ad SL |
905 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
906 | { | |
c5e147cf RH |
907 | unsigned long start; |
908 | unsigned long end; | |
d75586ad SL |
909 | int i; |
910 | /* | |
911 | * for now UC MINUS. see comments in ioremap_nocache() | |
912 | */ | |
913 | for (i = 0; i < addrinarray; i++) { | |
c5e147cf RH |
914 | start = __pa(addr[i]); |
915 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
916 | if (end != __pa(addr[i + 1])) | |
917 | break; | |
918 | i++; | |
919 | } | |
920 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
d75586ad SL |
921 | goto out; |
922 | } | |
923 | ||
924 | return change_page_attr_set(addr, addrinarray, | |
925 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); | |
926 | out: | |
c5e147cf RH |
927 | for (i = 0; i < addrinarray; i++) { |
928 | unsigned long tmp = __pa(addr[i]); | |
929 | ||
930 | if (tmp == start) | |
931 | break; | |
01de05af | 932 | for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { |
c5e147cf RH |
933 | if (end != __pa(addr[i + 1])) |
934 | break; | |
935 | i++; | |
936 | } | |
937 | free_memtype(tmp, end); | |
938 | } | |
d75586ad SL |
939 | return -EINVAL; |
940 | } | |
941 | EXPORT_SYMBOL(set_memory_array_uc); | |
942 | ||
ef354af4 | 943 | int _set_memory_wc(unsigned long addr, int numpages) |
944 | { | |
d75586ad SL |
945 | return change_page_attr_set(&addr, numpages, |
946 | __pgprot(_PAGE_CACHE_WC), 0); | |
ef354af4 | 947 | } |
948 | ||
949 | int set_memory_wc(unsigned long addr, int numpages) | |
950 | { | |
499f8f84 | 951 | if (!pat_enabled) |
ef354af4 | 952 | return set_memory_uc(addr, numpages); |
953 | ||
c15238df | 954 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
ef354af4 | 955 | _PAGE_CACHE_WC, NULL)) |
956 | return -EINVAL; | |
957 | ||
958 | return _set_memory_wc(addr, numpages); | |
959 | } | |
960 | EXPORT_SYMBOL(set_memory_wc); | |
961 | ||
1219333d | 962 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 963 | { |
d75586ad SL |
964 | return change_page_attr_clear(&addr, numpages, |
965 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 966 | } |
1219333d | 967 | |
968 | int set_memory_wb(unsigned long addr, int numpages) | |
969 | { | |
c15238df | 970 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
1219333d | 971 | |
972 | return _set_memory_wb(addr, numpages); | |
973 | } | |
75cbade8 AV |
974 | EXPORT_SYMBOL(set_memory_wb); |
975 | ||
d75586ad SL |
976 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
977 | { | |
978 | int i; | |
d75586ad | 979 | |
c5e147cf RH |
980 | for (i = 0; i < addrinarray; i++) { |
981 | unsigned long start = __pa(addr[i]); | |
982 | unsigned long end; | |
983 | ||
984 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
985 | if (end != __pa(addr[i + 1])) | |
986 | break; | |
987 | i++; | |
988 | } | |
989 | free_memtype(start, end); | |
990 | } | |
d75586ad SL |
991 | return change_page_attr_clear(addr, addrinarray, |
992 | __pgprot(_PAGE_CACHE_MASK), 1); | |
993 | } | |
994 | EXPORT_SYMBOL(set_memory_array_wb); | |
995 | ||
75cbade8 AV |
996 | int set_memory_x(unsigned long addr, int numpages) |
997 | { | |
d75586ad | 998 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
999 | } |
1000 | EXPORT_SYMBOL(set_memory_x); | |
1001 | ||
1002 | int set_memory_nx(unsigned long addr, int numpages) | |
1003 | { | |
d75586ad | 1004 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1005 | } |
1006 | EXPORT_SYMBOL(set_memory_nx); | |
1007 | ||
1008 | int set_memory_ro(unsigned long addr, int numpages) | |
1009 | { | |
d75586ad | 1010 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1011 | } |
a03352d2 | 1012 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1013 | |
1014 | int set_memory_rw(unsigned long addr, int numpages) | |
1015 | { | |
d75586ad | 1016 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1017 | } |
a03352d2 | 1018 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1019 | |
1020 | int set_memory_np(unsigned long addr, int numpages) | |
1021 | { | |
d75586ad | 1022 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1023 | } |
75cbade8 | 1024 | |
c9caa02c AK |
1025 | int set_memory_4k(unsigned long addr, int numpages) |
1026 | { | |
d75586ad SL |
1027 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
1028 | __pgprot(0), 1, 0); | |
c9caa02c AK |
1029 | } |
1030 | ||
75cbade8 AV |
1031 | int set_pages_uc(struct page *page, int numpages) |
1032 | { | |
1033 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1034 | |
d7c8f21a | 1035 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1036 | } |
1037 | EXPORT_SYMBOL(set_pages_uc); | |
1038 | ||
1039 | int set_pages_wb(struct page *page, int numpages) | |
1040 | { | |
1041 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1042 | |
d7c8f21a | 1043 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1044 | } |
1045 | EXPORT_SYMBOL(set_pages_wb); | |
1046 | ||
1047 | int set_pages_x(struct page *page, int numpages) | |
1048 | { | |
1049 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1050 | |
d7c8f21a | 1051 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1052 | } |
1053 | EXPORT_SYMBOL(set_pages_x); | |
1054 | ||
1055 | int set_pages_nx(struct page *page, int numpages) | |
1056 | { | |
1057 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1058 | |
d7c8f21a | 1059 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1060 | } |
1061 | EXPORT_SYMBOL(set_pages_nx); | |
1062 | ||
1063 | int set_pages_ro(struct page *page, int numpages) | |
1064 | { | |
1065 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1066 | |
d7c8f21a | 1067 | return set_memory_ro(addr, numpages); |
75cbade8 | 1068 | } |
75cbade8 AV |
1069 | |
1070 | int set_pages_rw(struct page *page, int numpages) | |
1071 | { | |
1072 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1073 | |
d7c8f21a | 1074 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1075 | } |
1076 | ||
1da177e4 | 1077 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1078 | |
1079 | static int __set_pages_p(struct page *page, int numpages) | |
1080 | { | |
d75586ad SL |
1081 | unsigned long tempaddr = (unsigned long) page_address(page); |
1082 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1083 | .numpages = numpages, |
1084 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1085 | .mask_clr = __pgprot(0), |
1086 | .flags = 0}; | |
72932c7a | 1087 | |
55121b43 SS |
1088 | /* |
1089 | * No alias checking needed for setting present flag. otherwise, | |
1090 | * we may need to break large pages for 64-bit kernel text | |
1091 | * mappings (this adds to complexity if we want to do this from | |
1092 | * atomic context especially). Let's keep it simple! | |
1093 | */ | |
1094 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1095 | } |
1096 | ||
1097 | static int __set_pages_np(struct page *page, int numpages) | |
1098 | { | |
d75586ad SL |
1099 | unsigned long tempaddr = (unsigned long) page_address(page); |
1100 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1101 | .numpages = numpages, |
1102 | .mask_set = __pgprot(0), | |
d75586ad SL |
1103 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1104 | .flags = 0}; | |
72932c7a | 1105 | |
55121b43 SS |
1106 | /* |
1107 | * No alias checking needed for setting not present flag. otherwise, | |
1108 | * we may need to break large pages for 64-bit kernel text | |
1109 | * mappings (this adds to complexity if we want to do this from | |
1110 | * atomic context especially). Let's keep it simple! | |
1111 | */ | |
1112 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1113 | } |
1114 | ||
1da177e4 LT |
1115 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1116 | { | |
1117 | if (PageHighMem(page)) | |
1118 | return; | |
9f4c815c | 1119 | if (!enable) { |
f9b8404c IM |
1120 | debug_check_no_locks_freed(page_address(page), |
1121 | numpages * PAGE_SIZE); | |
9f4c815c | 1122 | } |
de5097c2 | 1123 | |
12d6f21e IM |
1124 | /* |
1125 | * If page allocator is not up yet then do not call c_p_a(): | |
1126 | */ | |
1127 | if (!debug_pagealloc_enabled) | |
1128 | return; | |
1129 | ||
9f4c815c | 1130 | /* |
f8d8406b | 1131 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1132 | * Large pages for identity mappings are not used at boot time |
1133 | * and hence no memory allocations during large page split. | |
1da177e4 | 1134 | */ |
f62d0f00 IM |
1135 | if (enable) |
1136 | __set_pages_p(page, numpages); | |
1137 | else | |
1138 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1139 | |
1140 | /* | |
e4b71dcf IM |
1141 | * We should perform an IPI and flush all tlbs, |
1142 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1143 | */ |
1144 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1145 | } |
1146 | ||
8a235efa RW |
1147 | #ifdef CONFIG_HIBERNATION |
1148 | ||
1149 | bool kernel_page_present(struct page *page) | |
1150 | { | |
1151 | unsigned int level; | |
1152 | pte_t *pte; | |
1153 | ||
1154 | if (PageHighMem(page)) | |
1155 | return false; | |
1156 | ||
1157 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1158 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1159 | } | |
1160 | ||
1161 | #endif /* CONFIG_HIBERNATION */ | |
1162 | ||
1163 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1164 | |
1165 | /* | |
1166 | * The testcases use internal knowledge of the implementation that shouldn't | |
1167 | * be exposed to the rest of the kernel. Include these directly here. | |
1168 | */ | |
1169 | #ifdef CONFIG_CPA_DEBUG | |
1170 | #include "pageattr-test.c" | |
1171 | #endif |