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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
5bd5a452 | 16 | #include <linux/pci.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
72e458df TG |
33 | pgprot_t mask_set; |
34 | pgprot_t mask_clr; | |
65e074df | 35 | int numpages; |
d75586ad | 36 | int flags; |
c31c7d48 | 37 | unsigned long pfn; |
c9caa02c | 38 | unsigned force_split : 1; |
d75586ad | 39 | int curpage; |
9ae28475 | 40 | struct page **pages; |
72e458df TG |
41 | }; |
42 | ||
ad5ca55f SS |
43 | /* |
44 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
45 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
46 | * entries change the page attribute in parallel to some other cpu | |
47 | * splitting a large page entry along with changing the attribute. | |
48 | */ | |
49 | static DEFINE_SPINLOCK(cpa_lock); | |
50 | ||
d75586ad SL |
51 | #define CPA_FLUSHTLB 1 |
52 | #define CPA_ARRAY 2 | |
9ae28475 | 53 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 54 | |
65280e61 | 55 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
56 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
57 | ||
65280e61 | 58 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 59 | { |
ce0c0e50 | 60 | /* Protect against CPA */ |
a79e53d8 | 61 | spin_lock(&pgd_lock); |
ce0c0e50 | 62 | direct_pages_count[level] += pages; |
a79e53d8 | 63 | spin_unlock(&pgd_lock); |
65280e61 TG |
64 | } |
65 | ||
66 | static void split_page_count(int level) | |
67 | { | |
68 | direct_pages_count[level]--; | |
69 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
70 | } | |
71 | ||
e1759c21 | 72 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 73 | { |
b9c3bfc2 | 74 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
75 | direct_pages_count[PG_LEVEL_4K] << 2); |
76 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 77 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
78 | direct_pages_count[PG_LEVEL_2M] << 11); |
79 | #else | |
b9c3bfc2 | 80 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
81 | direct_pages_count[PG_LEVEL_2M] << 12); |
82 | #endif | |
65280e61 | 83 | #ifdef CONFIG_X86_64 |
a06de630 | 84 | if (direct_gbpages) |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 86 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
87 | #endif |
88 | } | |
65280e61 TG |
89 | #else |
90 | static inline void split_page_count(int level) { } | |
91 | #endif | |
ce0c0e50 | 92 | |
c31c7d48 TG |
93 | #ifdef CONFIG_X86_64 |
94 | ||
95 | static inline unsigned long highmap_start_pfn(void) | |
96 | { | |
97 | return __pa(_text) >> PAGE_SHIFT; | |
98 | } | |
99 | ||
100 | static inline unsigned long highmap_end_pfn(void) | |
101 | { | |
93dbda7c | 102 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
103 | } |
104 | ||
105 | #endif | |
106 | ||
92cb54a3 IM |
107 | #ifdef CONFIG_DEBUG_PAGEALLOC |
108 | # define debug_pagealloc 1 | |
109 | #else | |
110 | # define debug_pagealloc 0 | |
111 | #endif | |
112 | ||
ed724be6 AV |
113 | static inline int |
114 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 115 | { |
ed724be6 AV |
116 | return addr >= start && addr < end; |
117 | } | |
118 | ||
d7c8f21a TG |
119 | /* |
120 | * Flushing functions | |
121 | */ | |
cd8ddf1a | 122 | |
cd8ddf1a TG |
123 | /** |
124 | * clflush_cache_range - flush a cache range with clflush | |
125 | * @addr: virtual start address | |
126 | * @size: number of bytes to flush | |
127 | * | |
128 | * clflush is an unordered instruction which needs fencing with mfence | |
129 | * to avoid ordering issues. | |
130 | */ | |
4c61afcd | 131 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 132 | { |
4c61afcd | 133 | void *vend = vaddr + size - 1; |
d7c8f21a | 134 | |
cd8ddf1a | 135 | mb(); |
4c61afcd IM |
136 | |
137 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
138 | clflush(vaddr); | |
139 | /* | |
140 | * Flush any possible final partial cacheline: | |
141 | */ | |
142 | clflush(vend); | |
143 | ||
cd8ddf1a | 144 | mb(); |
d7c8f21a | 145 | } |
e517a5e9 | 146 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 147 | |
af1e6844 | 148 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 149 | { |
6bb8383b AK |
150 | unsigned long cache = (unsigned long)arg; |
151 | ||
d7c8f21a TG |
152 | /* |
153 | * Flush all to work around Errata in early athlons regarding | |
154 | * large page flushing. | |
155 | */ | |
156 | __flush_tlb_all(); | |
157 | ||
0b827537 | 158 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
159 | wbinvd(); |
160 | } | |
161 | ||
6bb8383b | 162 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
163 | { |
164 | BUG_ON(irqs_disabled()); | |
165 | ||
15c8b6c1 | 166 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
167 | } |
168 | ||
57a6a46a TG |
169 | static void __cpa_flush_range(void *arg) |
170 | { | |
57a6a46a TG |
171 | /* |
172 | * We could optimize that further and do individual per page | |
173 | * tlb invalidates for a low number of pages. Caveat: we must | |
174 | * flush the high aliases on 64bit as well. | |
175 | */ | |
176 | __flush_tlb_all(); | |
57a6a46a TG |
177 | } |
178 | ||
6bb8383b | 179 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 180 | { |
4c61afcd IM |
181 | unsigned int i, level; |
182 | unsigned long addr; | |
183 | ||
57a6a46a | 184 | BUG_ON(irqs_disabled()); |
4c61afcd | 185 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 186 | |
15c8b6c1 | 187 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 188 | |
6bb8383b AK |
189 | if (!cache) |
190 | return; | |
191 | ||
3b233e52 TG |
192 | /* |
193 | * We only need to flush on one CPU, | |
194 | * clflush is a MESI-coherent instruction that | |
195 | * will cause all other CPUs to flush the same | |
196 | * cachelines: | |
197 | */ | |
4c61afcd IM |
198 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
199 | pte_t *pte = lookup_address(addr, &level); | |
200 | ||
201 | /* | |
202 | * Only flush present addresses: | |
203 | */ | |
7bfb72e8 | 204 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
205 | clflush_cache_range((void *) addr, PAGE_SIZE); |
206 | } | |
57a6a46a TG |
207 | } |
208 | ||
9ae28475 | 209 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
210 | int in_flags, struct page **pages) | |
d75586ad SL |
211 | { |
212 | unsigned int i, level; | |
2171787b | 213 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
214 | |
215 | BUG_ON(irqs_disabled()); | |
216 | ||
2171787b | 217 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 218 | |
2171787b | 219 | if (!cache || do_wbinvd) |
d75586ad SL |
220 | return; |
221 | ||
d75586ad SL |
222 | /* |
223 | * We only need to flush on one CPU, | |
224 | * clflush is a MESI-coherent instruction that | |
225 | * will cause all other CPUs to flush the same | |
226 | * cachelines: | |
227 | */ | |
9ae28475 | 228 | for (i = 0; i < numpages; i++) { |
229 | unsigned long addr; | |
230 | pte_t *pte; | |
231 | ||
232 | if (in_flags & CPA_PAGES_ARRAY) | |
233 | addr = (unsigned long)page_address(pages[i]); | |
234 | else | |
235 | addr = start[i]; | |
236 | ||
237 | pte = lookup_address(addr, &level); | |
d75586ad SL |
238 | |
239 | /* | |
240 | * Only flush present addresses: | |
241 | */ | |
242 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 243 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
244 | } |
245 | } | |
246 | ||
ed724be6 AV |
247 | /* |
248 | * Certain areas of memory on x86 require very specific protection flags, | |
249 | * for example the BIOS area or kernel text. Callers don't always get this | |
250 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
251 | * checks and fixes these known static required protection bits. | |
252 | */ | |
c31c7d48 TG |
253 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
254 | unsigned long pfn) | |
ed724be6 AV |
255 | { |
256 | pgprot_t forbidden = __pgprot(0); | |
257 | ||
687c4825 | 258 | /* |
ed724be6 AV |
259 | * The BIOS area between 640k and 1Mb needs to be executable for |
260 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 261 | */ |
5bd5a452 MC |
262 | #ifdef CONFIG_PCI_BIOS |
263 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 264 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 265 | #endif |
ed724be6 AV |
266 | |
267 | /* | |
268 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
269 | * Does not cover __inittext since that is gone later on. On |
270 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
271 | */ |
272 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
273 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 274 | |
cc0f21bb | 275 | /* |
c31c7d48 TG |
276 | * The .rodata section needs to be read-only. Using the pfn |
277 | * catches all aliases. | |
cc0f21bb | 278 | */ |
c31c7d48 TG |
279 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
280 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 281 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 282 | |
55ca3cc1 | 283 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 284 | /* |
502f6604 SS |
285 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
286 | * kernel text mappings for the large page aligned text, rodata sections | |
287 | * will be always read-only. For the kernel identity mappings covering | |
288 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
289 | * |
290 | * This will preserve the large page mappings for kernel text/data | |
291 | * at no extra cost. | |
292 | */ | |
502f6604 SS |
293 | if (kernel_set_to_readonly && |
294 | within(address, (unsigned long)_text, | |
281ff33b SS |
295 | (unsigned long)__end_rodata_hpage_align)) { |
296 | unsigned int level; | |
297 | ||
298 | /* | |
299 | * Don't enforce the !RW mapping for the kernel text mapping, | |
300 | * if the current mapping is already using small page mapping. | |
301 | * No need to work hard to preserve large page mappings in this | |
302 | * case. | |
303 | * | |
304 | * This also fixes the Linux Xen paravirt guest boot failure | |
305 | * (because of unexpected read-only mappings for kernel identity | |
306 | * mappings). In this paravirt guest case, the kernel text | |
307 | * mapping and the kernel identity mapping share the same | |
308 | * page-table pages. Thus we can't really use different | |
309 | * protections for the kernel text and identity mappings. Also, | |
310 | * these shared mappings are made of small page mappings. | |
311 | * Thus this don't enforce !RW mapping for small page kernel | |
312 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 313 | * as well. |
281ff33b SS |
314 | */ |
315 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
316 | pgprot_val(forbidden) |= _PAGE_RW; | |
317 | } | |
74e08179 SS |
318 | #endif |
319 | ||
ed724be6 | 320 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
321 | |
322 | return prot; | |
323 | } | |
324 | ||
9a14aefc TG |
325 | /* |
326 | * Lookup the page table entry for a virtual address. Return a pointer | |
327 | * to the entry and the level of the mapping. | |
328 | * | |
329 | * Note: We return pud and pmd either when the entry is marked large | |
330 | * or when the present bit is not set. Otherwise we would return a | |
331 | * pointer to a nonexisting mapping. | |
332 | */ | |
da7bfc50 | 333 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 334 | { |
1da177e4 LT |
335 | pgd_t *pgd = pgd_offset_k(address); |
336 | pud_t *pud; | |
337 | pmd_t *pmd; | |
9f4c815c | 338 | |
30551bb3 TG |
339 | *level = PG_LEVEL_NONE; |
340 | ||
1da177e4 LT |
341 | if (pgd_none(*pgd)) |
342 | return NULL; | |
9df84993 | 343 | |
1da177e4 LT |
344 | pud = pud_offset(pgd, address); |
345 | if (pud_none(*pud)) | |
346 | return NULL; | |
c2f71ee2 AK |
347 | |
348 | *level = PG_LEVEL_1G; | |
349 | if (pud_large(*pud) || !pud_present(*pud)) | |
350 | return (pte_t *)pud; | |
351 | ||
1da177e4 LT |
352 | pmd = pmd_offset(pud, address); |
353 | if (pmd_none(*pmd)) | |
354 | return NULL; | |
30551bb3 TG |
355 | |
356 | *level = PG_LEVEL_2M; | |
9a14aefc | 357 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 358 | return (pte_t *)pmd; |
1da177e4 | 359 | |
30551bb3 | 360 | *level = PG_LEVEL_4K; |
9df84993 | 361 | |
9f4c815c IM |
362 | return pte_offset_kernel(pmd, address); |
363 | } | |
75bb8835 | 364 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 365 | |
9df84993 IM |
366 | /* |
367 | * Set the new pmd in all the pgds we know about: | |
368 | */ | |
9a3dc780 | 369 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 370 | { |
9f4c815c IM |
371 | /* change init_mm */ |
372 | set_pte_atomic(kpte, pte); | |
44af6c41 | 373 | #ifdef CONFIG_X86_32 |
e4b71dcf | 374 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
375 | struct page *page; |
376 | ||
e3ed910d | 377 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
378 | pgd_t *pgd; |
379 | pud_t *pud; | |
380 | pmd_t *pmd; | |
381 | ||
382 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
383 | pud = pud_offset(pgd, address); | |
384 | pmd = pmd_offset(pud, address); | |
385 | set_pte_atomic((pte_t *)pmd, pte); | |
386 | } | |
1da177e4 | 387 | } |
44af6c41 | 388 | #endif |
1da177e4 LT |
389 | } |
390 | ||
9df84993 IM |
391 | static int |
392 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
393 | struct cpa_data *cpa) | |
65e074df | 394 | { |
a79e53d8 | 395 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn; |
65e074df | 396 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 397 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 398 | int i, do_split = 1; |
da7bfc50 | 399 | unsigned int level; |
65e074df | 400 | |
c9caa02c AK |
401 | if (cpa->force_split) |
402 | return 1; | |
403 | ||
a79e53d8 | 404 | spin_lock(&pgd_lock); |
65e074df TG |
405 | /* |
406 | * Check for races, another CPU might have split this page | |
407 | * up already: | |
408 | */ | |
409 | tmp = lookup_address(address, &level); | |
410 | if (tmp != kpte) | |
411 | goto out_unlock; | |
412 | ||
413 | switch (level) { | |
414 | case PG_LEVEL_2M: | |
31422c51 AK |
415 | psize = PMD_PAGE_SIZE; |
416 | pmask = PMD_PAGE_MASK; | |
65e074df | 417 | break; |
f07333fd | 418 | #ifdef CONFIG_X86_64 |
65e074df | 419 | case PG_LEVEL_1G: |
5d3c8b21 AK |
420 | psize = PUD_PAGE_SIZE; |
421 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
422 | break; |
423 | #endif | |
65e074df | 424 | default: |
beaff633 | 425 | do_split = -EINVAL; |
65e074df TG |
426 | goto out_unlock; |
427 | } | |
428 | ||
429 | /* | |
430 | * Calculate the number of pages, which fit into this large | |
431 | * page starting at address: | |
432 | */ | |
433 | nextpage_addr = (address + psize) & pmask; | |
434 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
435 | if (numpages < cpa->numpages) |
436 | cpa->numpages = numpages; | |
65e074df TG |
437 | |
438 | /* | |
439 | * We are safe now. Check whether the new pgprot is the same: | |
440 | */ | |
441 | old_pte = *kpte; | |
64edc8ed | 442 | old_prot = new_prot = req_prot = pte_pgprot(old_pte); |
65e074df | 443 | |
64edc8ed MC |
444 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
445 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
446 | |
447 | /* | |
448 | * old_pte points to the large page base address. So we need | |
449 | * to add the offset of the virtual address: | |
450 | */ | |
451 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
452 | cpa->pfn = pfn; | |
453 | ||
64edc8ed | 454 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 455 | |
fac84939 TG |
456 | /* |
457 | * We need to check the full range, whether | |
458 | * static_protection() requires a different pgprot for one of | |
459 | * the pages in the range we try to preserve: | |
460 | */ | |
64edc8ed MC |
461 | addr = address & pmask; |
462 | pfn = pte_pfn(old_pte); | |
463 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { | |
464 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
465 | |
466 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
467 | goto out_unlock; | |
468 | } | |
469 | ||
65e074df TG |
470 | /* |
471 | * If there are no changes, return. maxpages has been updated | |
472 | * above: | |
473 | */ | |
474 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 475 | do_split = 0; |
65e074df TG |
476 | goto out_unlock; |
477 | } | |
478 | ||
479 | /* | |
480 | * We need to change the attributes. Check, whether we can | |
481 | * change the large page in one go. We request a split, when | |
482 | * the address is not aligned and the number of pages is | |
483 | * smaller than the number of pages in the large page. Note | |
484 | * that we limited the number of possible pages already to | |
485 | * the number of pages in the large page. | |
486 | */ | |
64edc8ed | 487 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
488 | /* |
489 | * The address is aligned and the number of pages | |
490 | * covers the full page. | |
491 | */ | |
492 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
493 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 494 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 495 | do_split = 0; |
65e074df TG |
496 | } |
497 | ||
498 | out_unlock: | |
a79e53d8 | 499 | spin_unlock(&pgd_lock); |
9df84993 | 500 | |
beaff633 | 501 | return do_split; |
65e074df TG |
502 | } |
503 | ||
7afe15b9 | 504 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 505 | { |
a79e53d8 | 506 | unsigned long pfn, pfninc = 1; |
9df84993 | 507 | unsigned int i, level; |
bb5c2dbd | 508 | pte_t *pbase, *tmp; |
9df84993 | 509 | pgprot_t ref_prot; |
ad5ca55f SS |
510 | struct page *base; |
511 | ||
512 | if (!debug_pagealloc) | |
513 | spin_unlock(&cpa_lock); | |
9e730237 | 514 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
515 | if (!debug_pagealloc) |
516 | spin_lock(&cpa_lock); | |
8311eb84 SS |
517 | if (!base) |
518 | return -ENOMEM; | |
bb5c2dbd | 519 | |
a79e53d8 | 520 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
521 | /* |
522 | * Check for races, another CPU might have split this page | |
523 | * up for us already: | |
524 | */ | |
525 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 526 | if (tmp != kpte) |
bb5c2dbd IM |
527 | goto out_unlock; |
528 | ||
bb5c2dbd | 529 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 530 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 531 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
532 | /* |
533 | * If we ever want to utilize the PAT bit, we need to | |
534 | * update this function to make sure it's converted from | |
535 | * bit 12 to bit 7 when we cross from the 2MB level to | |
536 | * the 4K level: | |
537 | */ | |
538 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 539 | |
f07333fd AK |
540 | #ifdef CONFIG_X86_64 |
541 | if (level == PG_LEVEL_1G) { | |
542 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
543 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
544 | } |
545 | #endif | |
546 | ||
63c1dcf4 TG |
547 | /* |
548 | * Get the target pfn from the original entry: | |
549 | */ | |
550 | pfn = pte_pfn(*kpte); | |
f07333fd | 551 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 552 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 553 | |
ce0c0e50 | 554 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
555 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
556 | split_page_count(level); | |
557 | ||
558 | #ifdef CONFIG_X86_64 | |
559 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
560 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
561 | split_page_count(level); | |
f361a450 | 562 | #endif |
ce0c0e50 | 563 | |
bb5c2dbd | 564 | /* |
07a66d7c | 565 | * Install the new, split up pagetable. |
4c881ca1 | 566 | * |
07a66d7c IM |
567 | * We use the standard kernel pagetable protections for the new |
568 | * pagetable protections, the actual ptes set above control the | |
569 | * primary protection behavior: | |
bb5c2dbd | 570 | */ |
07a66d7c | 571 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
572 | |
573 | /* | |
574 | * Intel Atom errata AAH41 workaround. | |
575 | * | |
576 | * The real fix should be in hw or in a microcode update, but | |
577 | * we also probabilistically try to reduce the window of having | |
578 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
579 | * going on. | |
580 | */ | |
581 | __flush_tlb_all(); | |
582 | ||
bb5c2dbd IM |
583 | base = NULL; |
584 | ||
585 | out_unlock: | |
eb5b5f02 TG |
586 | /* |
587 | * If we dropped out via the lookup_address check under | |
588 | * pgd_lock then stick the page back into the pool: | |
589 | */ | |
8311eb84 SS |
590 | if (base) |
591 | __free_page(base); | |
a79e53d8 | 592 | spin_unlock(&pgd_lock); |
bb5c2dbd | 593 | |
bb5c2dbd IM |
594 | return 0; |
595 | } | |
596 | ||
a1e46212 SS |
597 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
598 | int primary) | |
599 | { | |
600 | /* | |
601 | * Ignore all non primary paths. | |
602 | */ | |
603 | if (!primary) | |
604 | return 0; | |
605 | ||
606 | /* | |
607 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
608 | * to have holes. | |
609 | * Also set numpages to '1' indicating that we processed cpa req for | |
610 | * one virtual address page and its pfn. TBD: numpages can be set based | |
611 | * on the initial value and the level returned by lookup_address(). | |
612 | */ | |
613 | if (within(vaddr, PAGE_OFFSET, | |
614 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
615 | cpa->numpages = 1; | |
616 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
617 | return 0; | |
618 | } else { | |
619 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
620 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
621 | *cpa->vaddr); | |
622 | ||
623 | return -EFAULT; | |
624 | } | |
625 | } | |
626 | ||
c31c7d48 | 627 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 628 | { |
d75586ad | 629 | unsigned long address; |
da7bfc50 HH |
630 | int do_split, err; |
631 | unsigned int level; | |
c31c7d48 | 632 | pte_t *kpte, old_pte; |
1da177e4 | 633 | |
8523acfe TH |
634 | if (cpa->flags & CPA_PAGES_ARRAY) { |
635 | struct page *page = cpa->pages[cpa->curpage]; | |
636 | if (unlikely(PageHighMem(page))) | |
637 | return 0; | |
638 | address = (unsigned long)page_address(page); | |
639 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
640 | address = cpa->vaddr[cpa->curpage]; |
641 | else | |
642 | address = *cpa->vaddr; | |
97f99fed | 643 | repeat: |
f0646e43 | 644 | kpte = lookup_address(address, &level); |
1da177e4 | 645 | if (!kpte) |
a1e46212 | 646 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
647 | |
648 | old_pte = *kpte; | |
a1e46212 SS |
649 | if (!pte_val(old_pte)) |
650 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 651 | |
30551bb3 | 652 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 653 | pte_t new_pte; |
626c2c9d | 654 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 655 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 656 | |
72e458df TG |
657 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
658 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 659 | |
c31c7d48 | 660 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 661 | |
626c2c9d AV |
662 | /* |
663 | * We need to keep the pfn from the existing PTE, | |
664 | * after all we're only going to change it's attributes | |
665 | * not the memory it points to | |
666 | */ | |
c31c7d48 TG |
667 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
668 | cpa->pfn = pfn; | |
f4ae5da0 TG |
669 | /* |
670 | * Do we really change anything ? | |
671 | */ | |
672 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
673 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 674 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 675 | } |
9b5cf48b | 676 | cpa->numpages = 1; |
65e074df | 677 | return 0; |
1da177e4 | 678 | } |
65e074df TG |
679 | |
680 | /* | |
681 | * Check, whether we can keep the large page intact | |
682 | * and just change the pte: | |
683 | */ | |
beaff633 | 684 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
685 | /* |
686 | * When the range fits into the existing large page, | |
9b5cf48b | 687 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
688 | * try_large_page: |
689 | */ | |
87f7f8fe IM |
690 | if (do_split <= 0) |
691 | return do_split; | |
65e074df TG |
692 | |
693 | /* | |
694 | * We have to split the large page: | |
695 | */ | |
87f7f8fe IM |
696 | err = split_large_page(kpte, address); |
697 | if (!err) { | |
ad5ca55f SS |
698 | /* |
699 | * Do a global flush tlb after splitting the large page | |
700 | * and before we do the actual change page attribute in the PTE. | |
701 | * | |
702 | * With out this, we violate the TLB application note, that says | |
703 | * "The TLBs may contain both ordinary and large-page | |
704 | * translations for a 4-KByte range of linear addresses. This | |
705 | * may occur if software modifies the paging structures so that | |
706 | * the page size used for the address range changes. If the two | |
707 | * translations differ with respect to page frame or attributes | |
708 | * (e.g., permissions), processor behavior is undefined and may | |
709 | * be implementation-specific." | |
710 | * | |
711 | * We do this global tlb flush inside the cpa_lock, so that we | |
712 | * don't allow any other cpu, with stale tlb entries change the | |
713 | * page attribute in parallel, that also falls into the | |
714 | * just split large page entry. | |
715 | */ | |
716 | flush_tlb_all(); | |
87f7f8fe IM |
717 | goto repeat; |
718 | } | |
beaff633 | 719 | |
87f7f8fe | 720 | return err; |
9f4c815c | 721 | } |
1da177e4 | 722 | |
c31c7d48 TG |
723 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
724 | ||
725 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 726 | { |
c31c7d48 | 727 | struct cpa_data alias_cpa; |
992f4c1c | 728 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 729 | unsigned long vaddr; |
992f4c1c | 730 | int ret; |
44af6c41 | 731 | |
965194c1 | 732 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 733 | return 0; |
626c2c9d | 734 | |
f361a450 | 735 | #ifdef CONFIG_X86_64 |
965194c1 | 736 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
737 | return 0; |
738 | #endif | |
f34b439f TG |
739 | /* |
740 | * No need to redo, when the primary call touched the direct | |
741 | * mapping already: | |
742 | */ | |
8523acfe TH |
743 | if (cpa->flags & CPA_PAGES_ARRAY) { |
744 | struct page *page = cpa->pages[cpa->curpage]; | |
745 | if (unlikely(PageHighMem(page))) | |
746 | return 0; | |
747 | vaddr = (unsigned long)page_address(page); | |
748 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
749 | vaddr = cpa->vaddr[cpa->curpage]; |
750 | else | |
751 | vaddr = *cpa->vaddr; | |
752 | ||
753 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 754 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 755 | |
f34b439f | 756 | alias_cpa = *cpa; |
992f4c1c | 757 | alias_cpa.vaddr = &laddr; |
9ae28475 | 758 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 759 | |
f34b439f | 760 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
761 | if (ret) |
762 | return ret; | |
f34b439f | 763 | } |
44af6c41 | 764 | |
44af6c41 | 765 | #ifdef CONFIG_X86_64 |
488fd995 | 766 | /* |
992f4c1c TH |
767 | * If the primary call didn't touch the high mapping already |
768 | * and the physical address is inside the kernel map, we need | |
0879750f | 769 | * to touch the high mapped kernel as well: |
488fd995 | 770 | */ |
992f4c1c TH |
771 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
772 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
773 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
774 | __START_KERNEL_map - phys_base; | |
775 | alias_cpa = *cpa; | |
776 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
777 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 778 | |
992f4c1c TH |
779 | /* |
780 | * The high mapping range is imprecise, so ignore the | |
781 | * return value. | |
782 | */ | |
783 | __change_page_attr_set_clr(&alias_cpa, 0); | |
784 | } | |
488fd995 | 785 | #endif |
992f4c1c TH |
786 | |
787 | return 0; | |
1da177e4 LT |
788 | } |
789 | ||
c31c7d48 | 790 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 791 | { |
65e074df | 792 | int ret, numpages = cpa->numpages; |
ff31452b | 793 | |
65e074df TG |
794 | while (numpages) { |
795 | /* | |
796 | * Store the remaining nr of pages for the large page | |
797 | * preservation check. | |
798 | */ | |
9b5cf48b | 799 | cpa->numpages = numpages; |
d75586ad | 800 | /* for array changes, we can't use large page */ |
9ae28475 | 801 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 802 | cpa->numpages = 1; |
c31c7d48 | 803 | |
ad5ca55f SS |
804 | if (!debug_pagealloc) |
805 | spin_lock(&cpa_lock); | |
c31c7d48 | 806 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
807 | if (!debug_pagealloc) |
808 | spin_unlock(&cpa_lock); | |
ff31452b TG |
809 | if (ret) |
810 | return ret; | |
ff31452b | 811 | |
c31c7d48 TG |
812 | if (checkalias) { |
813 | ret = cpa_process_alias(cpa); | |
814 | if (ret) | |
815 | return ret; | |
816 | } | |
817 | ||
65e074df TG |
818 | /* |
819 | * Adjust the number of pages with the result of the | |
820 | * CPA operation. Either a large page has been | |
821 | * preserved or a single page update happened. | |
822 | */ | |
9b5cf48b RW |
823 | BUG_ON(cpa->numpages > numpages); |
824 | numpages -= cpa->numpages; | |
9ae28475 | 825 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
826 | cpa->curpage++; |
827 | else | |
828 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
829 | ||
65e074df | 830 | } |
ff31452b TG |
831 | return 0; |
832 | } | |
833 | ||
6bb8383b AK |
834 | static inline int cache_attr(pgprot_t attr) |
835 | { | |
836 | return pgprot_val(attr) & | |
837 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
838 | } | |
839 | ||
d75586ad | 840 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 841 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 842 | int force_split, int in_flag, |
843 | struct page **pages) | |
ff31452b | 844 | { |
72e458df | 845 | struct cpa_data cpa; |
cacf8906 | 846 | int ret, cache, checkalias; |
fa526d0d | 847 | unsigned long baddr = 0; |
331e4065 TG |
848 | |
849 | /* | |
850 | * Check, if we are requested to change a not supported | |
851 | * feature: | |
852 | */ | |
853 | mask_set = canon_pgprot(mask_set); | |
854 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 855 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
856 | return 0; |
857 | ||
69b1415e | 858 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 859 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
860 | int i; |
861 | for (i = 0; i < numpages; i++) { | |
862 | if (addr[i] & ~PAGE_MASK) { | |
863 | addr[i] &= PAGE_MASK; | |
864 | WARN_ON_ONCE(1); | |
865 | } | |
866 | } | |
9ae28475 | 867 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
868 | /* | |
869 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
870 | * No need to cehck in that case | |
871 | */ | |
872 | if (*addr & ~PAGE_MASK) { | |
873 | *addr &= PAGE_MASK; | |
874 | /* | |
875 | * People should not be passing in unaligned addresses: | |
876 | */ | |
877 | WARN_ON_ONCE(1); | |
878 | } | |
fa526d0d JS |
879 | /* |
880 | * Save address for cache flush. *addr is modified in the call | |
881 | * to __change_page_attr_set_clr() below. | |
882 | */ | |
883 | baddr = *addr; | |
69b1415e TG |
884 | } |
885 | ||
5843d9a4 NP |
886 | /* Must avoid aliasing mappings in the highmem code */ |
887 | kmap_flush_unused(); | |
888 | ||
db64fe02 NP |
889 | vm_unmap_aliases(); |
890 | ||
72e458df | 891 | cpa.vaddr = addr; |
9ae28475 | 892 | cpa.pages = pages; |
72e458df TG |
893 | cpa.numpages = numpages; |
894 | cpa.mask_set = mask_set; | |
895 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
896 | cpa.flags = 0; |
897 | cpa.curpage = 0; | |
c9caa02c | 898 | cpa.force_split = force_split; |
72e458df | 899 | |
9ae28475 | 900 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
901 | cpa.flags |= in_flag; | |
d75586ad | 902 | |
af96e443 TG |
903 | /* No alias checking for _NX bit modifications */ |
904 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
905 | ||
906 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 907 | |
f4ae5da0 TG |
908 | /* |
909 | * Check whether we really changed something: | |
910 | */ | |
d75586ad | 911 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 912 | goto out; |
cacf8906 | 913 | |
6bb8383b AK |
914 | /* |
915 | * No need to flush, when we did not set any of the caching | |
916 | * attributes: | |
917 | */ | |
918 | cache = cache_attr(mask_set); | |
919 | ||
57a6a46a TG |
920 | /* |
921 | * On success we use clflush, when the CPU supports it to | |
922 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 923 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
924 | * wbindv): |
925 | */ | |
d75586ad | 926 | if (!ret && cpu_has_clflush) { |
9ae28475 | 927 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
928 | cpa_flush_array(addr, numpages, cache, | |
929 | cpa.flags, pages); | |
930 | } else | |
fa526d0d | 931 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 932 | } else |
6bb8383b | 933 | cpa_flush_all(cache); |
cacf8906 | 934 | |
76ebd054 | 935 | out: |
ff31452b TG |
936 | return ret; |
937 | } | |
938 | ||
d75586ad SL |
939 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
940 | pgprot_t mask, int array) | |
75cbade8 | 941 | { |
d75586ad | 942 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 943 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
944 | } |
945 | ||
d75586ad SL |
946 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
947 | pgprot_t mask, int array) | |
72932c7a | 948 | { |
d75586ad | 949 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 950 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
951 | } |
952 | ||
0f350755 | 953 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
954 | pgprot_t mask) | |
955 | { | |
956 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
957 | CPA_PAGES_ARRAY, pages); | |
958 | } | |
959 | ||
960 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
961 | pgprot_t mask) | |
962 | { | |
963 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
964 | CPA_PAGES_ARRAY, pages); | |
965 | } | |
966 | ||
1219333d | 967 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 968 | { |
de33c442 SS |
969 | /* |
970 | * for now UC MINUS. see comments in ioremap_nocache() | |
971 | */ | |
d75586ad SL |
972 | return change_page_attr_set(&addr, numpages, |
973 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 974 | } |
1219333d | 975 | |
976 | int set_memory_uc(unsigned long addr, int numpages) | |
977 | { | |
9fa3ab39 | 978 | int ret; |
979 | ||
de33c442 SS |
980 | /* |
981 | * for now UC MINUS. see comments in ioremap_nocache() | |
982 | */ | |
9fa3ab39 | 983 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
984 | _PAGE_CACHE_UC_MINUS, NULL); | |
985 | if (ret) | |
986 | goto out_err; | |
987 | ||
988 | ret = _set_memory_uc(addr, numpages); | |
989 | if (ret) | |
990 | goto out_free; | |
991 | ||
992 | return 0; | |
1219333d | 993 | |
9fa3ab39 | 994 | out_free: |
995 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
996 | out_err: | |
997 | return ret; | |
1219333d | 998 | } |
75cbade8 AV |
999 | EXPORT_SYMBOL(set_memory_uc); |
1000 | ||
2d070eff | 1001 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
4f646254 | 1002 | unsigned long new_type) |
d75586ad | 1003 | { |
9fa3ab39 | 1004 | int i, j; |
1005 | int ret; | |
1006 | ||
d75586ad SL |
1007 | /* |
1008 | * for now UC MINUS. see comments in ioremap_nocache() | |
1009 | */ | |
1010 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 1011 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1012 | new_type, NULL); |
9fa3ab39 | 1013 | if (ret) |
1014 | goto out_free; | |
d75586ad SL |
1015 | } |
1016 | ||
9fa3ab39 | 1017 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 1018 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
4f646254 PN |
1019 | |
1020 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1021 | ret = change_page_attr_set_clr(addr, addrinarray, | |
1022 | __pgprot(_PAGE_CACHE_WC), | |
1023 | __pgprot(_PAGE_CACHE_MASK), | |
1024 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1025 | if (ret) |
1026 | goto out_free; | |
1027 | ||
1028 | return 0; | |
1029 | ||
1030 | out_free: | |
1031 | for (j = 0; j < i; j++) | |
1032 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1033 | ||
1034 | return ret; | |
d75586ad | 1035 | } |
4f646254 PN |
1036 | |
1037 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1038 | { | |
1039 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1040 | } | |
d75586ad SL |
1041 | EXPORT_SYMBOL(set_memory_array_uc); |
1042 | ||
4f646254 PN |
1043 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1044 | { | |
1045 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC); | |
1046 | } | |
1047 | EXPORT_SYMBOL(set_memory_array_wc); | |
1048 | ||
ef354af4 | 1049 | int _set_memory_wc(unsigned long addr, int numpages) |
1050 | { | |
3869c4aa | 1051 | int ret; |
bdc6340f PV |
1052 | unsigned long addr_copy = addr; |
1053 | ||
3869c4aa | 1054 | ret = change_page_attr_set(&addr, numpages, |
1055 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1056 | if (!ret) { |
bdc6340f PV |
1057 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1058 | __pgprot(_PAGE_CACHE_WC), | |
1059 | __pgprot(_PAGE_CACHE_MASK), | |
1060 | 0, 0, NULL); | |
3869c4aa | 1061 | } |
1062 | return ret; | |
ef354af4 | 1063 | } |
1064 | ||
1065 | int set_memory_wc(unsigned long addr, int numpages) | |
1066 | { | |
9fa3ab39 | 1067 | int ret; |
1068 | ||
499f8f84 | 1069 | if (!pat_enabled) |
ef354af4 | 1070 | return set_memory_uc(addr, numpages); |
1071 | ||
9fa3ab39 | 1072 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1073 | _PAGE_CACHE_WC, NULL); | |
1074 | if (ret) | |
1075 | goto out_err; | |
ef354af4 | 1076 | |
9fa3ab39 | 1077 | ret = _set_memory_wc(addr, numpages); |
1078 | if (ret) | |
1079 | goto out_free; | |
1080 | ||
1081 | return 0; | |
1082 | ||
1083 | out_free: | |
1084 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1085 | out_err: | |
1086 | return ret; | |
ef354af4 | 1087 | } |
1088 | EXPORT_SYMBOL(set_memory_wc); | |
1089 | ||
1219333d | 1090 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1091 | { |
d75586ad SL |
1092 | return change_page_attr_clear(&addr, numpages, |
1093 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1094 | } |
1219333d | 1095 | |
1096 | int set_memory_wb(unsigned long addr, int numpages) | |
1097 | { | |
9fa3ab39 | 1098 | int ret; |
1099 | ||
1100 | ret = _set_memory_wb(addr, numpages); | |
1101 | if (ret) | |
1102 | return ret; | |
1103 | ||
c15238df | 1104 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1105 | return 0; |
1219333d | 1106 | } |
75cbade8 AV |
1107 | EXPORT_SYMBOL(set_memory_wb); |
1108 | ||
d75586ad SL |
1109 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1110 | { | |
1111 | int i; | |
a5593e0b | 1112 | int ret; |
1113 | ||
1114 | ret = change_page_attr_clear(addr, addrinarray, | |
1115 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1116 | if (ret) |
1117 | return ret; | |
d75586ad | 1118 | |
9fa3ab39 | 1119 | for (i = 0; i < addrinarray; i++) |
1120 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1121 | |
9fa3ab39 | 1122 | return 0; |
d75586ad SL |
1123 | } |
1124 | EXPORT_SYMBOL(set_memory_array_wb); | |
1125 | ||
75cbade8 AV |
1126 | int set_memory_x(unsigned long addr, int numpages) |
1127 | { | |
583140af PA |
1128 | if (!(__supported_pte_mask & _PAGE_NX)) |
1129 | return 0; | |
1130 | ||
d75586ad | 1131 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1132 | } |
1133 | EXPORT_SYMBOL(set_memory_x); | |
1134 | ||
1135 | int set_memory_nx(unsigned long addr, int numpages) | |
1136 | { | |
583140af PA |
1137 | if (!(__supported_pte_mask & _PAGE_NX)) |
1138 | return 0; | |
1139 | ||
d75586ad | 1140 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1141 | } |
1142 | EXPORT_SYMBOL(set_memory_nx); | |
1143 | ||
1144 | int set_memory_ro(unsigned long addr, int numpages) | |
1145 | { | |
d75586ad | 1146 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1147 | } |
a03352d2 | 1148 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1149 | |
1150 | int set_memory_rw(unsigned long addr, int numpages) | |
1151 | { | |
d75586ad | 1152 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1153 | } |
a03352d2 | 1154 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1155 | |
1156 | int set_memory_np(unsigned long addr, int numpages) | |
1157 | { | |
d75586ad | 1158 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1159 | } |
75cbade8 | 1160 | |
c9caa02c AK |
1161 | int set_memory_4k(unsigned long addr, int numpages) |
1162 | { | |
d75586ad | 1163 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1164 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1165 | } |
1166 | ||
75cbade8 AV |
1167 | int set_pages_uc(struct page *page, int numpages) |
1168 | { | |
1169 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1170 | |
d7c8f21a | 1171 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1172 | } |
1173 | EXPORT_SYMBOL(set_pages_uc); | |
1174 | ||
4f646254 PN |
1175 | static int _set_pages_array(struct page **pages, int addrinarray, |
1176 | unsigned long new_type) | |
0f350755 | 1177 | { |
1178 | unsigned long start; | |
1179 | unsigned long end; | |
1180 | int i; | |
1181 | int free_idx; | |
4f646254 | 1182 | int ret; |
0f350755 | 1183 | |
1184 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1185 | if (PageHighMem(pages[i])) |
1186 | continue; | |
1187 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1188 | end = start + PAGE_SIZE; |
4f646254 | 1189 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1190 | goto err_out; |
1191 | } | |
1192 | ||
4f646254 PN |
1193 | ret = cpa_set_pages_array(pages, addrinarray, |
1194 | __pgprot(_PAGE_CACHE_UC_MINUS)); | |
1195 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1196 | ret = change_page_attr_set_clr(NULL, addrinarray, | |
1197 | __pgprot(_PAGE_CACHE_WC), | |
1198 | __pgprot(_PAGE_CACHE_MASK), | |
1199 | 0, CPA_PAGES_ARRAY, pages); | |
1200 | if (ret) | |
1201 | goto err_out; | |
1202 | return 0; /* Success */ | |
0f350755 | 1203 | err_out: |
1204 | free_idx = i; | |
1205 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1206 | if (PageHighMem(pages[i])) |
1207 | continue; | |
1208 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1209 | end = start + PAGE_SIZE; |
1210 | free_memtype(start, end); | |
1211 | } | |
1212 | return -EINVAL; | |
1213 | } | |
4f646254 PN |
1214 | |
1215 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1216 | { | |
1217 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1218 | } | |
0f350755 | 1219 | EXPORT_SYMBOL(set_pages_array_uc); |
1220 | ||
4f646254 PN |
1221 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1222 | { | |
1223 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC); | |
1224 | } | |
1225 | EXPORT_SYMBOL(set_pages_array_wc); | |
1226 | ||
75cbade8 AV |
1227 | int set_pages_wb(struct page *page, int numpages) |
1228 | { | |
1229 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1230 | |
d7c8f21a | 1231 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1232 | } |
1233 | EXPORT_SYMBOL(set_pages_wb); | |
1234 | ||
0f350755 | 1235 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1236 | { | |
1237 | int retval; | |
1238 | unsigned long start; | |
1239 | unsigned long end; | |
1240 | int i; | |
1241 | ||
1242 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1243 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1244 | if (retval) |
1245 | return retval; | |
0f350755 | 1246 | |
1247 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1248 | if (PageHighMem(pages[i])) |
1249 | continue; | |
1250 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1251 | end = start + PAGE_SIZE; |
1252 | free_memtype(start, end); | |
1253 | } | |
1254 | ||
9fa3ab39 | 1255 | return 0; |
0f350755 | 1256 | } |
1257 | EXPORT_SYMBOL(set_pages_array_wb); | |
1258 | ||
75cbade8 AV |
1259 | int set_pages_x(struct page *page, int numpages) |
1260 | { | |
1261 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1262 | |
d7c8f21a | 1263 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1264 | } |
1265 | EXPORT_SYMBOL(set_pages_x); | |
1266 | ||
1267 | int set_pages_nx(struct page *page, int numpages) | |
1268 | { | |
1269 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1270 | |
d7c8f21a | 1271 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1272 | } |
1273 | EXPORT_SYMBOL(set_pages_nx); | |
1274 | ||
1275 | int set_pages_ro(struct page *page, int numpages) | |
1276 | { | |
1277 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1278 | |
d7c8f21a | 1279 | return set_memory_ro(addr, numpages); |
75cbade8 | 1280 | } |
75cbade8 AV |
1281 | |
1282 | int set_pages_rw(struct page *page, int numpages) | |
1283 | { | |
1284 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1285 | |
d7c8f21a | 1286 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1287 | } |
1288 | ||
1da177e4 | 1289 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1290 | |
1291 | static int __set_pages_p(struct page *page, int numpages) | |
1292 | { | |
d75586ad SL |
1293 | unsigned long tempaddr = (unsigned long) page_address(page); |
1294 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1295 | .numpages = numpages, |
1296 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1297 | .mask_clr = __pgprot(0), |
1298 | .flags = 0}; | |
72932c7a | 1299 | |
55121b43 SS |
1300 | /* |
1301 | * No alias checking needed for setting present flag. otherwise, | |
1302 | * we may need to break large pages for 64-bit kernel text | |
1303 | * mappings (this adds to complexity if we want to do this from | |
1304 | * atomic context especially). Let's keep it simple! | |
1305 | */ | |
1306 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1307 | } |
1308 | ||
1309 | static int __set_pages_np(struct page *page, int numpages) | |
1310 | { | |
d75586ad SL |
1311 | unsigned long tempaddr = (unsigned long) page_address(page); |
1312 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1313 | .numpages = numpages, |
1314 | .mask_set = __pgprot(0), | |
d75586ad SL |
1315 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1316 | .flags = 0}; | |
72932c7a | 1317 | |
55121b43 SS |
1318 | /* |
1319 | * No alias checking needed for setting not present flag. otherwise, | |
1320 | * we may need to break large pages for 64-bit kernel text | |
1321 | * mappings (this adds to complexity if we want to do this from | |
1322 | * atomic context especially). Let's keep it simple! | |
1323 | */ | |
1324 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1325 | } |
1326 | ||
1da177e4 LT |
1327 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1328 | { | |
1329 | if (PageHighMem(page)) | |
1330 | return; | |
9f4c815c | 1331 | if (!enable) { |
f9b8404c IM |
1332 | debug_check_no_locks_freed(page_address(page), |
1333 | numpages * PAGE_SIZE); | |
9f4c815c | 1334 | } |
de5097c2 | 1335 | |
9f4c815c | 1336 | /* |
f8d8406b | 1337 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1338 | * Large pages for identity mappings are not used at boot time |
1339 | * and hence no memory allocations during large page split. | |
1da177e4 | 1340 | */ |
f62d0f00 IM |
1341 | if (enable) |
1342 | __set_pages_p(page, numpages); | |
1343 | else | |
1344 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1345 | |
1346 | /* | |
e4b71dcf IM |
1347 | * We should perform an IPI and flush all tlbs, |
1348 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1349 | */ |
1350 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1351 | } |
1352 | ||
8a235efa RW |
1353 | #ifdef CONFIG_HIBERNATION |
1354 | ||
1355 | bool kernel_page_present(struct page *page) | |
1356 | { | |
1357 | unsigned int level; | |
1358 | pte_t *pte; | |
1359 | ||
1360 | if (PageHighMem(page)) | |
1361 | return false; | |
1362 | ||
1363 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1364 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1365 | } | |
1366 | ||
1367 | #endif /* CONFIG_HIBERNATION */ | |
1368 | ||
1369 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1370 | |
1371 | /* | |
1372 | * The testcases use internal knowledge of the implementation that shouldn't | |
1373 | * be exposed to the rest of the kernel. Include these directly here. | |
1374 | */ | |
1375 | #ifdef CONFIG_CPA_DEBUG | |
1376 | #include "pageattr-test.c" | |
1377 | #endif |