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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c IM |
10 | #include <linux/mm.h> |
11 | ||
950f9d95 | 12 | #include <asm/e820.h> |
1da177e4 LT |
13 | #include <asm/processor.h> |
14 | #include <asm/tlbflush.h> | |
f8af095d | 15 | #include <asm/sections.h> |
9f4c815c IM |
16 | #include <asm/uaccess.h> |
17 | #include <asm/pgalloc.h> | |
1da177e4 | 18 | |
ed724be6 AV |
19 | static inline int |
20 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 21 | { |
ed724be6 AV |
22 | return addr >= start && addr < end; |
23 | } | |
24 | ||
25 | /* | |
26 | * Certain areas of memory on x86 require very specific protection flags, | |
27 | * for example the BIOS area or kernel text. Callers don't always get this | |
28 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
29 | * checks and fixes these known static required protection bits. | |
30 | */ | |
31 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address) | |
32 | { | |
33 | pgprot_t forbidden = __pgprot(0); | |
34 | ||
687c4825 | 35 | /* |
ed724be6 AV |
36 | * The BIOS area between 640k and 1Mb needs to be executable for |
37 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 38 | */ |
ed724be6 AV |
39 | if (within(__pa(address), BIOS_BEGIN, BIOS_END)) |
40 | pgprot_val(forbidden) |= _PAGE_NX; | |
41 | ||
42 | /* | |
43 | * The kernel text needs to be executable for obvious reasons | |
44 | * Does not cover __inittext since that is gone later on | |
45 | */ | |
46 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
47 | pgprot_val(forbidden) |= _PAGE_NX; | |
48 | ||
49 | #ifdef CONFIG_DEBUG_RODATA | |
50 | /* The .rodata section needs to be read-only */ | |
51 | if (within(address, (unsigned long)__start_rodata, | |
52 | (unsigned long)__end_rodata)) | |
53 | pgprot_val(forbidden) |= _PAGE_RW; | |
54 | #endif | |
55 | ||
56 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
57 | |
58 | return prot; | |
59 | } | |
60 | ||
f0646e43 | 61 | pte_t *lookup_address(unsigned long address, int *level) |
9f4c815c | 62 | { |
1da177e4 LT |
63 | pgd_t *pgd = pgd_offset_k(address); |
64 | pud_t *pud; | |
65 | pmd_t *pmd; | |
9f4c815c | 66 | |
30551bb3 TG |
67 | *level = PG_LEVEL_NONE; |
68 | ||
1da177e4 LT |
69 | if (pgd_none(*pgd)) |
70 | return NULL; | |
71 | pud = pud_offset(pgd, address); | |
72 | if (pud_none(*pud)) | |
73 | return NULL; | |
74 | pmd = pmd_offset(pud, address); | |
75 | if (pmd_none(*pmd)) | |
76 | return NULL; | |
30551bb3 TG |
77 | |
78 | *level = PG_LEVEL_2M; | |
1da177e4 LT |
79 | if (pmd_large(*pmd)) |
80 | return (pte_t *)pmd; | |
1da177e4 | 81 | |
30551bb3 | 82 | *level = PG_LEVEL_4K; |
9f4c815c IM |
83 | return pte_offset_kernel(pmd, address); |
84 | } | |
85 | ||
9a3dc780 | 86 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 87 | { |
9f4c815c IM |
88 | /* change init_mm */ |
89 | set_pte_atomic(kpte, pte); | |
44af6c41 | 90 | #ifdef CONFIG_X86_32 |
e4b71dcf | 91 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
92 | struct page *page; |
93 | ||
94 | for (page = pgd_list; page; page = (struct page *)page->index) { | |
95 | pgd_t *pgd; | |
96 | pud_t *pud; | |
97 | pmd_t *pmd; | |
98 | ||
99 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
100 | pud = pud_offset(pgd, address); | |
101 | pmd = pmd_offset(pud, address); | |
102 | set_pte_atomic((pte_t *)pmd, pte); | |
103 | } | |
1da177e4 | 104 | } |
44af6c41 | 105 | #endif |
1da177e4 LT |
106 | } |
107 | ||
7afe15b9 | 108 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 109 | { |
7afe15b9 | 110 | pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
12d6f21e | 111 | gfp_t gfp_flags = GFP_KERNEL; |
9a3dc780 | 112 | unsigned long flags; |
bb5c2dbd IM |
113 | unsigned long addr; |
114 | pte_t *pbase, *tmp; | |
115 | struct page *base; | |
7afe15b9 | 116 | int i, level; |
bb5c2dbd | 117 | |
12d6f21e IM |
118 | #ifdef CONFIG_DEBUG_PAGEALLOC |
119 | gfp_flags = GFP_ATOMIC; | |
120 | #endif | |
121 | base = alloc_pages(gfp_flags, 0); | |
bb5c2dbd IM |
122 | if (!base) |
123 | return -ENOMEM; | |
124 | ||
9a3dc780 | 125 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
126 | /* |
127 | * Check for races, another CPU might have split this page | |
128 | * up for us already: | |
129 | */ | |
130 | tmp = lookup_address(address, &level); | |
5508a748 IM |
131 | if (tmp != kpte) { |
132 | WARN_ON_ONCE(1); | |
bb5c2dbd | 133 | goto out_unlock; |
5508a748 | 134 | } |
bb5c2dbd IM |
135 | |
136 | address = __pa(address); | |
137 | addr = address & LARGE_PAGE_MASK; | |
138 | pbase = (pte_t *)page_address(base); | |
44af6c41 | 139 | #ifdef CONFIG_X86_32 |
bb5c2dbd | 140 | paravirt_alloc_pt(&init_mm, page_to_pfn(base)); |
44af6c41 | 141 | #endif |
bb5c2dbd IM |
142 | |
143 | for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) | |
144 | set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot)); | |
145 | ||
146 | /* | |
4c881ca1 HY |
147 | * Install the new, split up pagetable. Important detail here: |
148 | * | |
149 | * On Intel the NX bit of all levels must be cleared to make a | |
150 | * page executable. See section 4.13.2 of Intel 64 and IA-32 | |
151 | * Architectures Software Developer's Manual). | |
bb5c2dbd | 152 | */ |
4c881ca1 | 153 | ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); |
9a3dc780 | 154 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
155 | base = NULL; |
156 | ||
157 | out_unlock: | |
9a3dc780 | 158 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd IM |
159 | |
160 | if (base) | |
161 | __free_pages(base, 0); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
44af6c41 | 166 | static int |
8192206d | 167 | __change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot) |
9f4c815c | 168 | { |
1da177e4 | 169 | struct page *kpte_page; |
bb5c2dbd | 170 | int level, err = 0; |
9f4c815c | 171 | pte_t *kpte; |
1da177e4 | 172 | |
8192206d IM |
173 | #ifdef CONFIG_X86_32 |
174 | BUG_ON(pfn > max_low_pfn); | |
175 | #endif | |
1da177e4 | 176 | |
97f99fed | 177 | repeat: |
f0646e43 | 178 | kpte = lookup_address(address, &level); |
1da177e4 LT |
179 | if (!kpte) |
180 | return -EINVAL; | |
9f4c815c | 181 | |
1da177e4 | 182 | kpte_page = virt_to_page(kpte); |
65d2f0bc AK |
183 | BUG_ON(PageLRU(kpte_page)); |
184 | BUG_ON(PageCompound(kpte_page)); | |
185 | ||
ed724be6 | 186 | prot = static_protections(prot, address); |
65d2f0bc | 187 | |
30551bb3 | 188 | if (level == PG_LEVEL_4K) { |
8192206d | 189 | set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot))); |
78c94aba | 190 | } else { |
7afe15b9 | 191 | err = split_large_page(kpte, address); |
bb5c2dbd IM |
192 | if (!err) |
193 | goto repeat; | |
1da177e4 | 194 | } |
bb5c2dbd | 195 | return err; |
9f4c815c | 196 | } |
1da177e4 | 197 | |
44af6c41 IM |
198 | /** |
199 | * change_page_attr_addr - Change page table attributes in linear mapping | |
200 | * @address: Virtual address in linear mapping. | |
201 | * @numpages: Number of pages to change | |
202 | * @prot: New page table attribute (PAGE_*) | |
1da177e4 | 203 | * |
44af6c41 IM |
204 | * Change page attributes of a page in the direct mapping. This is a variant |
205 | * of change_page_attr() that also works on memory holes that do not have | |
206 | * mem_map entry (pfn_valid() is false). | |
9f4c815c | 207 | * |
44af6c41 | 208 | * See change_page_attr() documentation for more details. |
75cbade8 AV |
209 | * |
210 | * Modules and drivers should use the set_memory_* APIs instead. | |
1da177e4 | 211 | */ |
44af6c41 IM |
212 | |
213 | int change_page_attr_addr(unsigned long address, int numpages, pgprot_t prot) | |
1da177e4 | 214 | { |
44af6c41 IM |
215 | int err = 0, kernel_map = 0, i; |
216 | ||
217 | #ifdef CONFIG_X86_64 | |
218 | if (address >= __START_KERNEL_map && | |
219 | address < __START_KERNEL_map + KERNEL_TEXT_SIZE) { | |
1da177e4 | 220 | |
44af6c41 IM |
221 | address = (unsigned long)__va(__pa(address)); |
222 | kernel_map = 1; | |
223 | } | |
224 | #endif | |
225 | ||
226 | for (i = 0; i < numpages; i++, address += PAGE_SIZE) { | |
227 | unsigned long pfn = __pa(address) >> PAGE_SHIFT; | |
228 | ||
229 | if (!kernel_map || pte_present(pfn_pte(0, prot))) { | |
8192206d | 230 | err = __change_page_attr(address, pfn, prot); |
44af6c41 IM |
231 | if (err) |
232 | break; | |
233 | } | |
234 | #ifdef CONFIG_X86_64 | |
235 | /* | |
236 | * Handle kernel mapping too which aliases part of | |
237 | * lowmem: | |
238 | */ | |
239 | if (__pa(address) < KERNEL_TEXT_SIZE) { | |
240 | unsigned long addr2; | |
241 | pgprot_t prot2; | |
242 | ||
243 | addr2 = __START_KERNEL_map + __pa(address); | |
244 | /* Make sure the kernel mappings stay executable */ | |
245 | prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot))); | |
8192206d | 246 | err = __change_page_attr(addr2, pfn, prot2); |
44af6c41 IM |
247 | } |
248 | #endif | |
9f4c815c | 249 | } |
9f4c815c | 250 | |
1da177e4 LT |
251 | return err; |
252 | } | |
253 | ||
44af6c41 IM |
254 | /** |
255 | * change_page_attr - Change page table attributes in the linear mapping. | |
256 | * @page: First page to change | |
257 | * @numpages: Number of pages to change | |
258 | * @prot: New protection/caching type (PAGE_*) | |
259 | * | |
260 | * Returns 0 on success, otherwise a negated errno. | |
261 | * | |
262 | * This should be used when a page is mapped with a different caching policy | |
263 | * than write-back somewhere - some CPUs do not like it when mappings with | |
264 | * different caching policies exist. This changes the page attributes of the | |
265 | * in kernel linear mapping too. | |
266 | * | |
267 | * Caller must call global_flush_tlb() later to make the changes active. | |
268 | * | |
269 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
270 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
271 | * | |
272 | * For MMIO areas without mem_map use change_page_attr_addr() instead. | |
75cbade8 AV |
273 | * |
274 | * Modules and drivers should use the set_pages_* APIs instead. | |
44af6c41 IM |
275 | */ |
276 | int change_page_attr(struct page *page, int numpages, pgprot_t prot) | |
626ab0e6 | 277 | { |
44af6c41 | 278 | unsigned long addr = (unsigned long)page_address(page); |
5508a748 | 279 | |
44af6c41 | 280 | return change_page_attr_addr(addr, numpages, prot); |
78c94aba | 281 | } |
e1271f68 | 282 | EXPORT_UNUSED_SYMBOL(change_page_attr); /* to be removed in 2.6.27 */ |
78c94aba | 283 | |
75cbade8 AV |
284 | /** |
285 | * change_page_attr_set - Change page table attributes in the linear mapping. | |
286 | * @addr: Virtual address in linear mapping. | |
287 | * @numpages: Number of pages to change | |
288 | * @prot: Protection/caching type bits to set (PAGE_*) | |
289 | * | |
290 | * Returns 0 on success, otherwise a negated errno. | |
291 | * | |
292 | * This should be used when a page is mapped with a different caching policy | |
293 | * than write-back somewhere - some CPUs do not like it when mappings with | |
294 | * different caching policies exist. This changes the page attributes of the | |
295 | * in kernel linear mapping too. | |
296 | * | |
297 | * Caller must call global_flush_tlb() later to make the changes active. | |
298 | * | |
299 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
300 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
301 | * | |
302 | * This function is different from change_page_attr() in that only selected bits | |
303 | * are impacted, all other bits remain as is. | |
304 | */ | |
305 | int change_page_attr_set(unsigned long addr, int numpages, pgprot_t prot) | |
306 | { | |
307 | pgprot_t current_prot; | |
308 | int level; | |
309 | pte_t *pte; | |
310 | ||
311 | pte = lookup_address(addr, &level); | |
312 | if (pte) | |
313 | current_prot = pte_pgprot(*pte); | |
314 | else | |
315 | pgprot_val(current_prot) = 0; | |
316 | ||
317 | pgprot_val(prot) = pgprot_val(current_prot) | pgprot_val(prot); | |
318 | ||
319 | return change_page_attr_addr(addr, numpages, prot); | |
320 | } | |
321 | ||
322 | /** | |
323 | * change_page_attr_clear - Change page table attributes in the linear mapping. | |
324 | * @addr: Virtual address in linear mapping. | |
325 | * @numpages: Number of pages to change | |
326 | * @prot: Protection/caching type bits to clear (PAGE_*) | |
327 | * | |
328 | * Returns 0 on success, otherwise a negated errno. | |
329 | * | |
330 | * This should be used when a page is mapped with a different caching policy | |
331 | * than write-back somewhere - some CPUs do not like it when mappings with | |
332 | * different caching policies exist. This changes the page attributes of the | |
333 | * in kernel linear mapping too. | |
334 | * | |
335 | * Caller must call global_flush_tlb() later to make the changes active. | |
336 | * | |
337 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
338 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
339 | * | |
340 | * This function is different from change_page_attr() in that only selected bits | |
341 | * are impacted, all other bits remain as is. | |
342 | */ | |
343 | int change_page_attr_clear(unsigned long addr, int numpages, pgprot_t prot) | |
344 | { | |
345 | pgprot_t current_prot; | |
346 | int level; | |
347 | pte_t *pte; | |
348 | ||
349 | pte = lookup_address(addr, &level); | |
350 | if (pte) | |
351 | current_prot = pte_pgprot(*pte); | |
352 | else | |
353 | pgprot_val(current_prot) = 0; | |
354 | ||
355 | pgprot_val(prot) = pgprot_val(current_prot) & ~pgprot_val(prot); | |
356 | ||
357 | return change_page_attr_addr(addr, numpages, prot); | |
358 | } | |
359 | ||
360 | ||
361 | ||
362 | int set_memory_uc(unsigned long addr, int numpages) | |
363 | { | |
364 | pgprot_t uncached; | |
365 | ||
366 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
367 | return change_page_attr_set(addr, numpages, uncached); | |
368 | } | |
369 | EXPORT_SYMBOL(set_memory_uc); | |
370 | ||
371 | int set_memory_wb(unsigned long addr, int numpages) | |
372 | { | |
373 | pgprot_t uncached; | |
374 | ||
375 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
376 | return change_page_attr_clear(addr, numpages, uncached); | |
377 | } | |
378 | EXPORT_SYMBOL(set_memory_wb); | |
379 | ||
380 | int set_memory_x(unsigned long addr, int numpages) | |
381 | { | |
382 | pgprot_t nx; | |
383 | ||
384 | pgprot_val(nx) = _PAGE_NX; | |
385 | return change_page_attr_clear(addr, numpages, nx); | |
386 | } | |
387 | EXPORT_SYMBOL(set_memory_x); | |
388 | ||
389 | int set_memory_nx(unsigned long addr, int numpages) | |
390 | { | |
391 | pgprot_t nx; | |
392 | ||
393 | pgprot_val(nx) = _PAGE_NX; | |
394 | return change_page_attr_set(addr, numpages, nx); | |
395 | } | |
396 | EXPORT_SYMBOL(set_memory_nx); | |
397 | ||
398 | int set_memory_ro(unsigned long addr, int numpages) | |
399 | { | |
400 | pgprot_t rw; | |
401 | ||
402 | pgprot_val(rw) = _PAGE_RW; | |
403 | return change_page_attr_clear(addr, numpages, rw); | |
404 | } | |
405 | EXPORT_SYMBOL(set_memory_ro); | |
406 | ||
407 | int set_memory_rw(unsigned long addr, int numpages) | |
408 | { | |
409 | pgprot_t rw; | |
410 | ||
411 | pgprot_val(rw) = _PAGE_RW; | |
412 | return change_page_attr_set(addr, numpages, rw); | |
413 | } | |
414 | EXPORT_SYMBOL(set_memory_rw); | |
415 | ||
416 | int set_pages_uc(struct page *page, int numpages) | |
417 | { | |
418 | unsigned long addr = (unsigned long)page_address(page); | |
419 | pgprot_t uncached; | |
420 | ||
421 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
422 | return change_page_attr_set(addr, numpages, uncached); | |
423 | } | |
424 | EXPORT_SYMBOL(set_pages_uc); | |
425 | ||
426 | int set_pages_wb(struct page *page, int numpages) | |
427 | { | |
428 | unsigned long addr = (unsigned long)page_address(page); | |
429 | pgprot_t uncached; | |
430 | ||
431 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
432 | return change_page_attr_clear(addr, numpages, uncached); | |
433 | } | |
434 | EXPORT_SYMBOL(set_pages_wb); | |
435 | ||
436 | int set_pages_x(struct page *page, int numpages) | |
437 | { | |
438 | unsigned long addr = (unsigned long)page_address(page); | |
439 | pgprot_t nx; | |
440 | ||
441 | pgprot_val(nx) = _PAGE_NX; | |
442 | return change_page_attr_clear(addr, numpages, nx); | |
443 | } | |
444 | EXPORT_SYMBOL(set_pages_x); | |
445 | ||
446 | int set_pages_nx(struct page *page, int numpages) | |
447 | { | |
448 | unsigned long addr = (unsigned long)page_address(page); | |
449 | pgprot_t nx; | |
450 | ||
451 | pgprot_val(nx) = _PAGE_NX; | |
452 | return change_page_attr_set(addr, numpages, nx); | |
453 | } | |
454 | EXPORT_SYMBOL(set_pages_nx); | |
455 | ||
456 | int set_pages_ro(struct page *page, int numpages) | |
457 | { | |
458 | unsigned long addr = (unsigned long)page_address(page); | |
459 | pgprot_t rw; | |
460 | ||
461 | pgprot_val(rw) = _PAGE_RW; | |
462 | return change_page_attr_clear(addr, numpages, rw); | |
463 | } | |
464 | EXPORT_SYMBOL(set_pages_ro); | |
465 | ||
466 | int set_pages_rw(struct page *page, int numpages) | |
467 | { | |
468 | unsigned long addr = (unsigned long)page_address(page); | |
469 | pgprot_t rw; | |
470 | ||
471 | pgprot_val(rw) = _PAGE_RW; | |
472 | return change_page_attr_set(addr, numpages, rw); | |
473 | } | |
474 | EXPORT_SYMBOL(set_pages_rw); | |
475 | ||
476 | ||
e81d5dc4 IM |
477 | void clflush_cache_range(void *addr, int size) |
478 | { | |
479 | int i; | |
480 | ||
481 | for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size) | |
482 | clflush(addr+i); | |
483 | } | |
484 | ||
78c94aba IM |
485 | static void flush_kernel_map(void *arg) |
486 | { | |
487 | /* | |
488 | * Flush all to work around Errata in early athlons regarding | |
489 | * large page flushing. | |
490 | */ | |
491 | __flush_tlb_all(); | |
492 | ||
493 | if (boot_cpu_data.x86_model >= 4) | |
494 | wbinvd(); | |
495 | } | |
496 | ||
497 | void global_flush_tlb(void) | |
498 | { | |
1da177e4 LT |
499 | BUG_ON(irqs_disabled()); |
500 | ||
78c94aba | 501 | on_each_cpu(flush_kernel_map, NULL, 1, 1); |
626ab0e6 | 502 | } |
9f4c815c | 503 | EXPORT_SYMBOL(global_flush_tlb); |
1da177e4 LT |
504 | |
505 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
506 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
507 | { | |
508 | if (PageHighMem(page)) | |
509 | return; | |
9f4c815c | 510 | if (!enable) { |
f9b8404c IM |
511 | debug_check_no_locks_freed(page_address(page), |
512 | numpages * PAGE_SIZE); | |
9f4c815c | 513 | } |
de5097c2 | 514 | |
12d6f21e IM |
515 | /* |
516 | * If page allocator is not up yet then do not call c_p_a(): | |
517 | */ | |
518 | if (!debug_pagealloc_enabled) | |
519 | return; | |
520 | ||
9f4c815c | 521 | /* |
e4b71dcf IM |
522 | * The return value is ignored - the calls cannot fail, |
523 | * large pages are disabled at boot time: | |
1da177e4 LT |
524 | */ |
525 | change_page_attr(page, numpages, enable ? PAGE_KERNEL : __pgprot(0)); | |
9f4c815c IM |
526 | |
527 | /* | |
e4b71dcf IM |
528 | * We should perform an IPI and flush all tlbs, |
529 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
530 | */ |
531 | __flush_tlb_all(); | |
532 | } | |
533 | #endif |