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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
0fd64c23 | 33 | pgd_t *pgd; |
72e458df TG |
34 | pgprot_t mask_set; |
35 | pgprot_t mask_clr; | |
65e074df | 36 | int numpages; |
d75586ad | 37 | int flags; |
c31c7d48 | 38 | unsigned long pfn; |
c9caa02c | 39 | unsigned force_split : 1; |
d75586ad | 40 | int curpage; |
9ae28475 | 41 | struct page **pages; |
72e458df TG |
42 | }; |
43 | ||
ad5ca55f SS |
44 | /* |
45 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
46 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
47 | * entries change the page attribute in parallel to some other cpu | |
48 | * splitting a large page entry along with changing the attribute. | |
49 | */ | |
50 | static DEFINE_SPINLOCK(cpa_lock); | |
51 | ||
d75586ad SL |
52 | #define CPA_FLUSHTLB 1 |
53 | #define CPA_ARRAY 2 | |
9ae28475 | 54 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 55 | |
65280e61 | 56 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
57 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
58 | ||
65280e61 | 59 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 60 | { |
ce0c0e50 | 61 | /* Protect against CPA */ |
a79e53d8 | 62 | spin_lock(&pgd_lock); |
ce0c0e50 | 63 | direct_pages_count[level] += pages; |
a79e53d8 | 64 | spin_unlock(&pgd_lock); |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
a06de630 | 84 | if (direct_gbpages) |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 86 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 87 | } |
65280e61 TG |
88 | #else |
89 | static inline void split_page_count(int level) { } | |
90 | #endif | |
ce0c0e50 | 91 | |
c31c7d48 TG |
92 | #ifdef CONFIG_X86_64 |
93 | ||
94 | static inline unsigned long highmap_start_pfn(void) | |
95 | { | |
fc8d7826 | 96 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
97 | } |
98 | ||
99 | static inline unsigned long highmap_end_pfn(void) | |
100 | { | |
fc8d7826 | 101 | return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
102 | } |
103 | ||
104 | #endif | |
105 | ||
92cb54a3 IM |
106 | #ifdef CONFIG_DEBUG_PAGEALLOC |
107 | # define debug_pagealloc 1 | |
108 | #else | |
109 | # define debug_pagealloc 0 | |
110 | #endif | |
111 | ||
ed724be6 AV |
112 | static inline int |
113 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 114 | { |
ed724be6 AV |
115 | return addr >= start && addr < end; |
116 | } | |
117 | ||
d7c8f21a TG |
118 | /* |
119 | * Flushing functions | |
120 | */ | |
cd8ddf1a | 121 | |
cd8ddf1a TG |
122 | /** |
123 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 124 | * @vaddr: virtual start address |
cd8ddf1a TG |
125 | * @size: number of bytes to flush |
126 | * | |
8b80fd8b RZ |
127 | * clflushopt is an unordered instruction which needs fencing with mfence or |
128 | * sfence to avoid ordering issues. | |
cd8ddf1a | 129 | */ |
4c61afcd | 130 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 131 | { |
6c434d61 RZ |
132 | unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1; |
133 | void *vend = vaddr + size; | |
134 | void *p; | |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd | 137 | |
6c434d61 RZ |
138 | for (p = (void *)((unsigned long)vaddr & ~clflush_mask); |
139 | p < vend; p += boot_cpu_data.x86_clflush_size) | |
140 | clflushopt(p); | |
4c61afcd | 141 | |
cd8ddf1a | 142 | mb(); |
d7c8f21a | 143 | } |
e517a5e9 | 144 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 145 | |
af1e6844 | 146 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 147 | { |
6bb8383b AK |
148 | unsigned long cache = (unsigned long)arg; |
149 | ||
d7c8f21a TG |
150 | /* |
151 | * Flush all to work around Errata in early athlons regarding | |
152 | * large page flushing. | |
153 | */ | |
154 | __flush_tlb_all(); | |
155 | ||
0b827537 | 156 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
157 | wbinvd(); |
158 | } | |
159 | ||
6bb8383b | 160 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
161 | { |
162 | BUG_ON(irqs_disabled()); | |
163 | ||
15c8b6c1 | 164 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
165 | } |
166 | ||
57a6a46a TG |
167 | static void __cpa_flush_range(void *arg) |
168 | { | |
57a6a46a TG |
169 | /* |
170 | * We could optimize that further and do individual per page | |
171 | * tlb invalidates for a low number of pages. Caveat: we must | |
172 | * flush the high aliases on 64bit as well. | |
173 | */ | |
174 | __flush_tlb_all(); | |
57a6a46a TG |
175 | } |
176 | ||
6bb8383b | 177 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 178 | { |
4c61afcd IM |
179 | unsigned int i, level; |
180 | unsigned long addr; | |
181 | ||
57a6a46a | 182 | BUG_ON(irqs_disabled()); |
4c61afcd | 183 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 184 | |
15c8b6c1 | 185 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 186 | |
6bb8383b AK |
187 | if (!cache) |
188 | return; | |
189 | ||
3b233e52 TG |
190 | /* |
191 | * We only need to flush on one CPU, | |
192 | * clflush is a MESI-coherent instruction that | |
193 | * will cause all other CPUs to flush the same | |
194 | * cachelines: | |
195 | */ | |
4c61afcd IM |
196 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
197 | pte_t *pte = lookup_address(addr, &level); | |
198 | ||
199 | /* | |
200 | * Only flush present addresses: | |
201 | */ | |
7bfb72e8 | 202 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
203 | clflush_cache_range((void *) addr, PAGE_SIZE); |
204 | } | |
57a6a46a TG |
205 | } |
206 | ||
9ae28475 | 207 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
208 | int in_flags, struct page **pages) | |
d75586ad SL |
209 | { |
210 | unsigned int i, level; | |
2171787b | 211 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
212 | |
213 | BUG_ON(irqs_disabled()); | |
214 | ||
2171787b | 215 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 216 | |
2171787b | 217 | if (!cache || do_wbinvd) |
d75586ad SL |
218 | return; |
219 | ||
d75586ad SL |
220 | /* |
221 | * We only need to flush on one CPU, | |
222 | * clflush is a MESI-coherent instruction that | |
223 | * will cause all other CPUs to flush the same | |
224 | * cachelines: | |
225 | */ | |
9ae28475 | 226 | for (i = 0; i < numpages; i++) { |
227 | unsigned long addr; | |
228 | pte_t *pte; | |
229 | ||
230 | if (in_flags & CPA_PAGES_ARRAY) | |
231 | addr = (unsigned long)page_address(pages[i]); | |
232 | else | |
233 | addr = start[i]; | |
234 | ||
235 | pte = lookup_address(addr, &level); | |
d75586ad SL |
236 | |
237 | /* | |
238 | * Only flush present addresses: | |
239 | */ | |
240 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 241 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
242 | } |
243 | } | |
244 | ||
ed724be6 AV |
245 | /* |
246 | * Certain areas of memory on x86 require very specific protection flags, | |
247 | * for example the BIOS area or kernel text. Callers don't always get this | |
248 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
249 | * checks and fixes these known static required protection bits. | |
250 | */ | |
c31c7d48 TG |
251 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
252 | unsigned long pfn) | |
ed724be6 AV |
253 | { |
254 | pgprot_t forbidden = __pgprot(0); | |
255 | ||
687c4825 | 256 | /* |
ed724be6 AV |
257 | * The BIOS area between 640k and 1Mb needs to be executable for |
258 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 259 | */ |
5bd5a452 MC |
260 | #ifdef CONFIG_PCI_BIOS |
261 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 262 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 263 | #endif |
ed724be6 AV |
264 | |
265 | /* | |
266 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
267 | * Does not cover __inittext since that is gone later on. On |
268 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
269 | */ |
270 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
271 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 272 | |
cc0f21bb | 273 | /* |
c31c7d48 TG |
274 | * The .rodata section needs to be read-only. Using the pfn |
275 | * catches all aliases. | |
cc0f21bb | 276 | */ |
fc8d7826 AD |
277 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
278 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 279 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 280 | |
55ca3cc1 | 281 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 282 | /* |
502f6604 SS |
283 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
284 | * kernel text mappings for the large page aligned text, rodata sections | |
285 | * will be always read-only. For the kernel identity mappings covering | |
286 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
287 | * |
288 | * This will preserve the large page mappings for kernel text/data | |
289 | * at no extra cost. | |
290 | */ | |
502f6604 SS |
291 | if (kernel_set_to_readonly && |
292 | within(address, (unsigned long)_text, | |
281ff33b SS |
293 | (unsigned long)__end_rodata_hpage_align)) { |
294 | unsigned int level; | |
295 | ||
296 | /* | |
297 | * Don't enforce the !RW mapping for the kernel text mapping, | |
298 | * if the current mapping is already using small page mapping. | |
299 | * No need to work hard to preserve large page mappings in this | |
300 | * case. | |
301 | * | |
302 | * This also fixes the Linux Xen paravirt guest boot failure | |
303 | * (because of unexpected read-only mappings for kernel identity | |
304 | * mappings). In this paravirt guest case, the kernel text | |
305 | * mapping and the kernel identity mapping share the same | |
306 | * page-table pages. Thus we can't really use different | |
307 | * protections for the kernel text and identity mappings. Also, | |
308 | * these shared mappings are made of small page mappings. | |
309 | * Thus this don't enforce !RW mapping for small page kernel | |
310 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 311 | * as well. |
281ff33b SS |
312 | */ |
313 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
314 | pgprot_val(forbidden) |= _PAGE_RW; | |
315 | } | |
74e08179 SS |
316 | #endif |
317 | ||
ed724be6 | 318 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
319 | |
320 | return prot; | |
321 | } | |
322 | ||
426e34cc MF |
323 | /* |
324 | * Lookup the page table entry for a virtual address in a specific pgd. | |
325 | * Return a pointer to the entry and the level of the mapping. | |
326 | */ | |
327 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
328 | unsigned int *level) | |
9f4c815c | 329 | { |
1da177e4 LT |
330 | pud_t *pud; |
331 | pmd_t *pmd; | |
9f4c815c | 332 | |
30551bb3 TG |
333 | *level = PG_LEVEL_NONE; |
334 | ||
1da177e4 LT |
335 | if (pgd_none(*pgd)) |
336 | return NULL; | |
9df84993 | 337 | |
1da177e4 LT |
338 | pud = pud_offset(pgd, address); |
339 | if (pud_none(*pud)) | |
340 | return NULL; | |
c2f71ee2 AK |
341 | |
342 | *level = PG_LEVEL_1G; | |
343 | if (pud_large(*pud) || !pud_present(*pud)) | |
344 | return (pte_t *)pud; | |
345 | ||
1da177e4 LT |
346 | pmd = pmd_offset(pud, address); |
347 | if (pmd_none(*pmd)) | |
348 | return NULL; | |
30551bb3 TG |
349 | |
350 | *level = PG_LEVEL_2M; | |
9a14aefc | 351 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 352 | return (pte_t *)pmd; |
1da177e4 | 353 | |
30551bb3 | 354 | *level = PG_LEVEL_4K; |
9df84993 | 355 | |
9f4c815c IM |
356 | return pte_offset_kernel(pmd, address); |
357 | } | |
0fd64c23 BP |
358 | |
359 | /* | |
360 | * Lookup the page table entry for a virtual address. Return a pointer | |
361 | * to the entry and the level of the mapping. | |
362 | * | |
363 | * Note: We return pud and pmd either when the entry is marked large | |
364 | * or when the present bit is not set. Otherwise we would return a | |
365 | * pointer to a nonexisting mapping. | |
366 | */ | |
367 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
368 | { | |
426e34cc | 369 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 370 | } |
75bb8835 | 371 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 372 | |
0fd64c23 BP |
373 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
374 | unsigned int *level) | |
375 | { | |
376 | if (cpa->pgd) | |
426e34cc | 377 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
378 | address, level); |
379 | ||
380 | return lookup_address(address, level); | |
381 | } | |
382 | ||
792230c3 JG |
383 | /* |
384 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
385 | * or NULL if not present. | |
386 | */ | |
387 | pmd_t *lookup_pmd_address(unsigned long address) | |
388 | { | |
389 | pgd_t *pgd; | |
390 | pud_t *pud; | |
391 | ||
392 | pgd = pgd_offset_k(address); | |
393 | if (pgd_none(*pgd)) | |
394 | return NULL; | |
395 | ||
396 | pud = pud_offset(pgd, address); | |
397 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) | |
398 | return NULL; | |
399 | ||
400 | return pmd_offset(pud, address); | |
401 | } | |
402 | ||
d7656534 DH |
403 | /* |
404 | * This is necessary because __pa() does not work on some | |
405 | * kinds of memory, like vmalloc() or the alloc_remap() | |
406 | * areas on 32-bit NUMA systems. The percpu areas can | |
407 | * end up in this kind of memory, for instance. | |
408 | * | |
409 | * This could be optimized, but it is only intended to be | |
410 | * used at inititalization time, and keeping it | |
411 | * unoptimized should increase the testing coverage for | |
412 | * the more obscure platforms. | |
413 | */ | |
414 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
415 | { | |
416 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
34437e67 | 417 | unsigned long phys_addr, offset; |
d7656534 | 418 | enum pg_level level; |
d7656534 DH |
419 | pte_t *pte; |
420 | ||
421 | pte = lookup_address(virt_addr, &level); | |
422 | BUG_ON(!pte); | |
34437e67 TK |
423 | |
424 | switch (level) { | |
425 | case PG_LEVEL_1G: | |
426 | phys_addr = pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; | |
427 | offset = virt_addr & ~PUD_PAGE_MASK; | |
428 | break; | |
429 | case PG_LEVEL_2M: | |
430 | phys_addr = pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; | |
431 | offset = virt_addr & ~PMD_PAGE_MASK; | |
432 | break; | |
433 | default: | |
434 | phys_addr = pte_pfn(*pte) << PAGE_SHIFT; | |
435 | offset = virt_addr & ~PAGE_MASK; | |
436 | } | |
437 | ||
438 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
439 | } |
440 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
441 | ||
9df84993 IM |
442 | /* |
443 | * Set the new pmd in all the pgds we know about: | |
444 | */ | |
9a3dc780 | 445 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 446 | { |
9f4c815c IM |
447 | /* change init_mm */ |
448 | set_pte_atomic(kpte, pte); | |
44af6c41 | 449 | #ifdef CONFIG_X86_32 |
e4b71dcf | 450 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
451 | struct page *page; |
452 | ||
e3ed910d | 453 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
454 | pgd_t *pgd; |
455 | pud_t *pud; | |
456 | pmd_t *pmd; | |
457 | ||
458 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
459 | pud = pud_offset(pgd, address); | |
460 | pmd = pmd_offset(pud, address); | |
461 | set_pte_atomic((pte_t *)pmd, pte); | |
462 | } | |
1da177e4 | 463 | } |
44af6c41 | 464 | #endif |
1da177e4 LT |
465 | } |
466 | ||
9df84993 IM |
467 | static int |
468 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
469 | struct cpa_data *cpa) | |
65e074df | 470 | { |
a79e53d8 | 471 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn; |
65e074df | 472 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 473 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 474 | int i, do_split = 1; |
f3c4fbb6 | 475 | enum pg_level level; |
65e074df | 476 | |
c9caa02c AK |
477 | if (cpa->force_split) |
478 | return 1; | |
479 | ||
a79e53d8 | 480 | spin_lock(&pgd_lock); |
65e074df TG |
481 | /* |
482 | * Check for races, another CPU might have split this page | |
483 | * up already: | |
484 | */ | |
82f0712c | 485 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df TG |
486 | if (tmp != kpte) |
487 | goto out_unlock; | |
488 | ||
489 | switch (level) { | |
490 | case PG_LEVEL_2M: | |
f07333fd | 491 | #ifdef CONFIG_X86_64 |
65e074df | 492 | case PG_LEVEL_1G: |
f07333fd | 493 | #endif |
f3c4fbb6 DH |
494 | psize = page_level_size(level); |
495 | pmask = page_level_mask(level); | |
496 | break; | |
65e074df | 497 | default: |
beaff633 | 498 | do_split = -EINVAL; |
65e074df TG |
499 | goto out_unlock; |
500 | } | |
501 | ||
502 | /* | |
503 | * Calculate the number of pages, which fit into this large | |
504 | * page starting at address: | |
505 | */ | |
506 | nextpage_addr = (address + psize) & pmask; | |
507 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
508 | if (numpages < cpa->numpages) |
509 | cpa->numpages = numpages; | |
65e074df TG |
510 | |
511 | /* | |
512 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
513 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
514 | * up accordingly. | |
65e074df TG |
515 | */ |
516 | old_pte = *kpte; | |
f5b2831d | 517 | old_prot = req_prot = pgprot_large_2_4k(pte_pgprot(old_pte)); |
65e074df | 518 | |
64edc8ed MC |
519 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
520 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 521 | |
f5b2831d JG |
522 | /* |
523 | * req_prot is in format of 4k pages. It must be converted to large | |
524 | * page format: the caching mode includes the PAT bit located at | |
525 | * different bit positions in the two formats. | |
526 | */ | |
527 | req_prot = pgprot_4k_2_large(req_prot); | |
528 | ||
a8aed3e0 AA |
529 | /* |
530 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
531 | * set otherwise pmd_present/pmd_huge will return true even on | |
532 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
533 | * for the ancient hardware that doesn't support it. | |
534 | */ | |
f76cfa3c AA |
535 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
536 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 537 | else |
f76cfa3c | 538 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 539 | |
f76cfa3c | 540 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 541 | |
c31c7d48 TG |
542 | /* |
543 | * old_pte points to the large page base address. So we need | |
544 | * to add the offset of the virtual address: | |
545 | */ | |
546 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
547 | cpa->pfn = pfn; | |
548 | ||
64edc8ed | 549 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 550 | |
fac84939 TG |
551 | /* |
552 | * We need to check the full range, whether | |
553 | * static_protection() requires a different pgprot for one of | |
554 | * the pages in the range we try to preserve: | |
555 | */ | |
64edc8ed MC |
556 | addr = address & pmask; |
557 | pfn = pte_pfn(old_pte); | |
558 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { | |
559 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
560 | |
561 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
562 | goto out_unlock; | |
563 | } | |
564 | ||
65e074df TG |
565 | /* |
566 | * If there are no changes, return. maxpages has been updated | |
567 | * above: | |
568 | */ | |
569 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 570 | do_split = 0; |
65e074df TG |
571 | goto out_unlock; |
572 | } | |
573 | ||
574 | /* | |
575 | * We need to change the attributes. Check, whether we can | |
576 | * change the large page in one go. We request a split, when | |
577 | * the address is not aligned and the number of pages is | |
578 | * smaller than the number of pages in the large page. Note | |
579 | * that we limited the number of possible pages already to | |
580 | * the number of pages in the large page. | |
581 | */ | |
64edc8ed | 582 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
583 | /* |
584 | * The address is aligned and the number of pages | |
585 | * covers the full page. | |
586 | */ | |
a8aed3e0 | 587 | new_pte = pfn_pte(pte_pfn(old_pte), new_prot); |
65e074df | 588 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 589 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 590 | do_split = 0; |
65e074df TG |
591 | } |
592 | ||
593 | out_unlock: | |
a79e53d8 | 594 | spin_unlock(&pgd_lock); |
9df84993 | 595 | |
beaff633 | 596 | return do_split; |
65e074df TG |
597 | } |
598 | ||
5952886b | 599 | static int |
82f0712c BP |
600 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
601 | struct page *base) | |
bb5c2dbd | 602 | { |
5952886b | 603 | pte_t *pbase = (pte_t *)page_address(base); |
a79e53d8 | 604 | unsigned long pfn, pfninc = 1; |
9df84993 | 605 | unsigned int i, level; |
ae9aae9e | 606 | pte_t *tmp; |
9df84993 | 607 | pgprot_t ref_prot; |
bb5c2dbd | 608 | |
a79e53d8 | 609 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
610 | /* |
611 | * Check for races, another CPU might have split this page | |
612 | * up for us already: | |
613 | */ | |
82f0712c | 614 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
615 | if (tmp != kpte) { |
616 | spin_unlock(&pgd_lock); | |
617 | return 1; | |
618 | } | |
bb5c2dbd | 619 | |
6944a9c8 | 620 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 621 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
f5b2831d JG |
622 | |
623 | /* promote PAT bit to correct position */ | |
624 | if (level == PG_LEVEL_2M) | |
625 | ref_prot = pgprot_large_2_4k(ref_prot); | |
bb5c2dbd | 626 | |
f07333fd AK |
627 | #ifdef CONFIG_X86_64 |
628 | if (level == PG_LEVEL_1G) { | |
629 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
a8aed3e0 AA |
630 | /* |
631 | * Set the PSE flags only if the PRESENT flag is set | |
632 | * otherwise pmd_present/pmd_huge will return true | |
633 | * even on a non present pmd. | |
634 | */ | |
635 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
636 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
637 | else | |
638 | pgprot_val(ref_prot) &= ~_PAGE_PSE; | |
f07333fd AK |
639 | } |
640 | #endif | |
641 | ||
a8aed3e0 AA |
642 | /* |
643 | * Set the GLOBAL flags only if the PRESENT flag is set | |
644 | * otherwise pmd/pte_present will return true even on a non | |
645 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
646 | * for the ancient hardware that doesn't support it. | |
647 | */ | |
648 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
649 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
650 | else | |
651 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
652 | ||
63c1dcf4 TG |
653 | /* |
654 | * Get the target pfn from the original entry: | |
655 | */ | |
656 | pfn = pte_pfn(*kpte); | |
f07333fd | 657 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 658 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 659 | |
8eb5779f YL |
660 | if (pfn_range_is_mapped(PFN_DOWN(__pa(address)), |
661 | PFN_DOWN(__pa(address)) + 1)) | |
f361a450 YL |
662 | split_page_count(level); |
663 | ||
bb5c2dbd | 664 | /* |
07a66d7c | 665 | * Install the new, split up pagetable. |
4c881ca1 | 666 | * |
07a66d7c IM |
667 | * We use the standard kernel pagetable protections for the new |
668 | * pagetable protections, the actual ptes set above control the | |
669 | * primary protection behavior: | |
bb5c2dbd | 670 | */ |
07a66d7c | 671 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
672 | |
673 | /* | |
674 | * Intel Atom errata AAH41 workaround. | |
675 | * | |
676 | * The real fix should be in hw or in a microcode update, but | |
677 | * we also probabilistically try to reduce the window of having | |
678 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
679 | * going on. | |
680 | */ | |
681 | __flush_tlb_all(); | |
ae9aae9e | 682 | spin_unlock(&pgd_lock); |
211b3d03 | 683 | |
ae9aae9e WC |
684 | return 0; |
685 | } | |
bb5c2dbd | 686 | |
82f0712c BP |
687 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
688 | unsigned long address) | |
ae9aae9e | 689 | { |
ae9aae9e WC |
690 | struct page *base; |
691 | ||
692 | if (!debug_pagealloc) | |
693 | spin_unlock(&cpa_lock); | |
694 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
695 | if (!debug_pagealloc) | |
696 | spin_lock(&cpa_lock); | |
697 | if (!base) | |
698 | return -ENOMEM; | |
699 | ||
82f0712c | 700 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 701 | __free_page(base); |
bb5c2dbd | 702 | |
bb5c2dbd IM |
703 | return 0; |
704 | } | |
705 | ||
52a628fb BP |
706 | static bool try_to_free_pte_page(pte_t *pte) |
707 | { | |
708 | int i; | |
709 | ||
710 | for (i = 0; i < PTRS_PER_PTE; i++) | |
711 | if (!pte_none(pte[i])) | |
712 | return false; | |
713 | ||
714 | free_page((unsigned long)pte); | |
715 | return true; | |
716 | } | |
717 | ||
718 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
719 | { | |
720 | int i; | |
721 | ||
722 | for (i = 0; i < PTRS_PER_PMD; i++) | |
723 | if (!pmd_none(pmd[i])) | |
724 | return false; | |
725 | ||
726 | free_page((unsigned long)pmd); | |
727 | return true; | |
728 | } | |
729 | ||
42a54772 BP |
730 | static bool try_to_free_pud_page(pud_t *pud) |
731 | { | |
732 | int i; | |
733 | ||
734 | for (i = 0; i < PTRS_PER_PUD; i++) | |
735 | if (!pud_none(pud[i])) | |
736 | return false; | |
737 | ||
738 | free_page((unsigned long)pud); | |
739 | return true; | |
740 | } | |
741 | ||
52a628fb BP |
742 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) |
743 | { | |
744 | pte_t *pte = pte_offset_kernel(pmd, start); | |
745 | ||
746 | while (start < end) { | |
747 | set_pte(pte, __pte(0)); | |
748 | ||
749 | start += PAGE_SIZE; | |
750 | pte++; | |
751 | } | |
752 | ||
753 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
754 | pmd_clear(pmd); | |
755 | return true; | |
756 | } | |
757 | return false; | |
758 | } | |
759 | ||
760 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
761 | unsigned long start, unsigned long end) | |
762 | { | |
763 | if (unmap_pte_range(pmd, start, end)) | |
764 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
765 | pud_clear(pud); | |
766 | } | |
767 | ||
768 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
769 | { | |
770 | pmd_t *pmd = pmd_offset(pud, start); | |
771 | ||
772 | /* | |
773 | * Not on a 2MB page boundary? | |
774 | */ | |
775 | if (start & (PMD_SIZE - 1)) { | |
776 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
777 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
778 | ||
779 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
780 | ||
781 | start = pre_end; | |
782 | pmd++; | |
783 | } | |
784 | ||
785 | /* | |
786 | * Try to unmap in 2M chunks. | |
787 | */ | |
788 | while (end - start >= PMD_SIZE) { | |
789 | if (pmd_large(*pmd)) | |
790 | pmd_clear(pmd); | |
791 | else | |
792 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
793 | ||
794 | start += PMD_SIZE; | |
795 | pmd++; | |
796 | } | |
797 | ||
798 | /* | |
799 | * 4K leftovers? | |
800 | */ | |
801 | if (start < end) | |
802 | return __unmap_pmd_range(pud, pmd, start, end); | |
803 | ||
804 | /* | |
805 | * Try again to free the PMD page if haven't succeeded above. | |
806 | */ | |
807 | if (!pud_none(*pud)) | |
808 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
809 | pud_clear(pud); | |
810 | } | |
0bb8aeee BP |
811 | |
812 | static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end) | |
813 | { | |
814 | pud_t *pud = pud_offset(pgd, start); | |
815 | ||
816 | /* | |
817 | * Not on a GB page boundary? | |
818 | */ | |
819 | if (start & (PUD_SIZE - 1)) { | |
820 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
821 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
822 | ||
823 | unmap_pmd_range(pud, start, pre_end); | |
824 | ||
825 | start = pre_end; | |
826 | pud++; | |
827 | } | |
828 | ||
829 | /* | |
830 | * Try to unmap in 1G chunks? | |
831 | */ | |
832 | while (end - start >= PUD_SIZE) { | |
833 | ||
834 | if (pud_large(*pud)) | |
835 | pud_clear(pud); | |
836 | else | |
837 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
838 | ||
839 | start += PUD_SIZE; | |
840 | pud++; | |
841 | } | |
842 | ||
843 | /* | |
844 | * 2M leftovers? | |
845 | */ | |
846 | if (start < end) | |
847 | unmap_pmd_range(pud, start, end); | |
848 | ||
849 | /* | |
850 | * No need to try to free the PUD page because we'll free it in | |
851 | * populate_pgd's error path | |
852 | */ | |
853 | } | |
854 | ||
42a54772 BP |
855 | static void unmap_pgd_range(pgd_t *root, unsigned long addr, unsigned long end) |
856 | { | |
857 | pgd_t *pgd_entry = root + pgd_index(addr); | |
858 | ||
859 | unmap_pud_range(pgd_entry, addr, end); | |
860 | ||
861 | if (try_to_free_pud_page((pud_t *)pgd_page_vaddr(*pgd_entry))) | |
862 | pgd_clear(pgd_entry); | |
863 | } | |
864 | ||
f900a4b8 BP |
865 | static int alloc_pte_page(pmd_t *pmd) |
866 | { | |
867 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
868 | if (!pte) | |
869 | return -1; | |
870 | ||
871 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
872 | return 0; | |
873 | } | |
874 | ||
4b23538d BP |
875 | static int alloc_pmd_page(pud_t *pud) |
876 | { | |
877 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
878 | if (!pmd) | |
879 | return -1; | |
880 | ||
881 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
882 | return 0; | |
883 | } | |
884 | ||
c6b6f363 BP |
885 | static void populate_pte(struct cpa_data *cpa, |
886 | unsigned long start, unsigned long end, | |
887 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
888 | { | |
889 | pte_t *pte; | |
890 | ||
891 | pte = pte_offset_kernel(pmd, start); | |
892 | ||
893 | while (num_pages-- && start < end) { | |
894 | ||
895 | /* deal with the NX bit */ | |
896 | if (!(pgprot_val(pgprot) & _PAGE_NX)) | |
897 | cpa->pfn &= ~_PAGE_NX; | |
898 | ||
899 | set_pte(pte, pfn_pte(cpa->pfn >> PAGE_SHIFT, pgprot)); | |
900 | ||
901 | start += PAGE_SIZE; | |
902 | cpa->pfn += PAGE_SIZE; | |
903 | pte++; | |
904 | } | |
905 | } | |
f900a4b8 BP |
906 | |
907 | static int populate_pmd(struct cpa_data *cpa, | |
908 | unsigned long start, unsigned long end, | |
909 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
910 | { | |
911 | unsigned int cur_pages = 0; | |
912 | pmd_t *pmd; | |
f5b2831d | 913 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
914 | |
915 | /* | |
916 | * Not on a 2M boundary? | |
917 | */ | |
918 | if (start & (PMD_SIZE - 1)) { | |
919 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
920 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
921 | ||
922 | pre_end = min_t(unsigned long, pre_end, next_page); | |
923 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
924 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
925 | ||
926 | /* | |
927 | * Need a PTE page? | |
928 | */ | |
929 | pmd = pmd_offset(pud, start); | |
930 | if (pmd_none(*pmd)) | |
931 | if (alloc_pte_page(pmd)) | |
932 | return -1; | |
933 | ||
934 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
935 | ||
936 | start = pre_end; | |
937 | } | |
938 | ||
939 | /* | |
940 | * We mapped them all? | |
941 | */ | |
942 | if (num_pages == cur_pages) | |
943 | return cur_pages; | |
944 | ||
f5b2831d JG |
945 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
946 | ||
f900a4b8 BP |
947 | while (end - start >= PMD_SIZE) { |
948 | ||
949 | /* | |
950 | * We cannot use a 1G page so allocate a PMD page if needed. | |
951 | */ | |
952 | if (pud_none(*pud)) | |
953 | if (alloc_pmd_page(pud)) | |
954 | return -1; | |
955 | ||
956 | pmd = pmd_offset(pud, start); | |
957 | ||
f5b2831d JG |
958 | set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE | |
959 | massage_pgprot(pmd_pgprot))); | |
f900a4b8 BP |
960 | |
961 | start += PMD_SIZE; | |
962 | cpa->pfn += PMD_SIZE; | |
963 | cur_pages += PMD_SIZE >> PAGE_SHIFT; | |
964 | } | |
965 | ||
966 | /* | |
967 | * Map trailing 4K pages. | |
968 | */ | |
969 | if (start < end) { | |
970 | pmd = pmd_offset(pud, start); | |
971 | if (pmd_none(*pmd)) | |
972 | if (alloc_pte_page(pmd)) | |
973 | return -1; | |
974 | ||
975 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
976 | pmd, pgprot); | |
977 | } | |
978 | return num_pages; | |
979 | } | |
4b23538d BP |
980 | |
981 | static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd, | |
982 | pgprot_t pgprot) | |
983 | { | |
984 | pud_t *pud; | |
985 | unsigned long end; | |
986 | int cur_pages = 0; | |
f5b2831d | 987 | pgprot_t pud_pgprot; |
4b23538d BP |
988 | |
989 | end = start + (cpa->numpages << PAGE_SHIFT); | |
990 | ||
991 | /* | |
992 | * Not on a Gb page boundary? => map everything up to it with | |
993 | * smaller pages. | |
994 | */ | |
995 | if (start & (PUD_SIZE - 1)) { | |
996 | unsigned long pre_end; | |
997 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
998 | ||
999 | pre_end = min_t(unsigned long, end, next_page); | |
1000 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1001 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1002 | ||
1003 | pud = pud_offset(pgd, start); | |
1004 | ||
1005 | /* | |
1006 | * Need a PMD page? | |
1007 | */ | |
1008 | if (pud_none(*pud)) | |
1009 | if (alloc_pmd_page(pud)) | |
1010 | return -1; | |
1011 | ||
1012 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1013 | pud, pgprot); | |
1014 | if (cur_pages < 0) | |
1015 | return cur_pages; | |
1016 | ||
1017 | start = pre_end; | |
1018 | } | |
1019 | ||
1020 | /* We mapped them all? */ | |
1021 | if (cpa->numpages == cur_pages) | |
1022 | return cur_pages; | |
1023 | ||
1024 | pud = pud_offset(pgd, start); | |
f5b2831d | 1025 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1026 | |
1027 | /* | |
1028 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1029 | */ | |
1030 | while (end - start >= PUD_SIZE) { | |
f5b2831d JG |
1031 | set_pud(pud, __pud(cpa->pfn | _PAGE_PSE | |
1032 | massage_pgprot(pud_pgprot))); | |
4b23538d BP |
1033 | |
1034 | start += PUD_SIZE; | |
1035 | cpa->pfn += PUD_SIZE; | |
1036 | cur_pages += PUD_SIZE >> PAGE_SHIFT; | |
1037 | pud++; | |
1038 | } | |
1039 | ||
1040 | /* Map trailing leftover */ | |
1041 | if (start < end) { | |
1042 | int tmp; | |
1043 | ||
1044 | pud = pud_offset(pgd, start); | |
1045 | if (pud_none(*pud)) | |
1046 | if (alloc_pmd_page(pud)) | |
1047 | return -1; | |
1048 | ||
1049 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1050 | pud, pgprot); | |
1051 | if (tmp < 0) | |
1052 | return cur_pages; | |
1053 | ||
1054 | cur_pages += tmp; | |
1055 | } | |
1056 | return cur_pages; | |
1057 | } | |
f3f72966 BP |
1058 | |
1059 | /* | |
1060 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1061 | * an alternate PGD. | |
1062 | */ | |
1063 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1064 | { | |
1065 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1066 | pud_t *pud = NULL; /* shut up gcc */ |
42a54772 | 1067 | pgd_t *pgd_entry; |
f3f72966 BP |
1068 | int ret; |
1069 | ||
1070 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1071 | ||
1072 | /* | |
1073 | * Allocate a PUD page and hand it down for mapping. | |
1074 | */ | |
1075 | if (pgd_none(*pgd_entry)) { | |
1076 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
1077 | if (!pud) | |
1078 | return -1; | |
1079 | ||
1080 | set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE)); | |
f3f72966 BP |
1081 | } |
1082 | ||
1083 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1084 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1085 | ||
1086 | ret = populate_pud(cpa, addr, pgd_entry, pgprot); | |
0bb8aeee | 1087 | if (ret < 0) { |
42a54772 | 1088 | unmap_pgd_range(cpa->pgd, addr, |
0bb8aeee | 1089 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1090 | return ret; |
0bb8aeee | 1091 | } |
42a54772 | 1092 | |
f3f72966 BP |
1093 | cpa->numpages = ret; |
1094 | return 0; | |
1095 | } | |
1096 | ||
a1e46212 SS |
1097 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1098 | int primary) | |
1099 | { | |
82f0712c BP |
1100 | if (cpa->pgd) |
1101 | return populate_pgd(cpa, vaddr); | |
1102 | ||
a1e46212 SS |
1103 | /* |
1104 | * Ignore all non primary paths. | |
1105 | */ | |
1106 | if (!primary) | |
1107 | return 0; | |
1108 | ||
1109 | /* | |
1110 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1111 | * to have holes. | |
1112 | * Also set numpages to '1' indicating that we processed cpa req for | |
1113 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1114 | * on the initial value and the level returned by lookup_address(). | |
1115 | */ | |
1116 | if (within(vaddr, PAGE_OFFSET, | |
1117 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1118 | cpa->numpages = 1; | |
1119 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1120 | return 0; | |
1121 | } else { | |
1122 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1123 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1124 | *cpa->vaddr); | |
1125 | ||
1126 | return -EFAULT; | |
1127 | } | |
1128 | } | |
1129 | ||
c31c7d48 | 1130 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1131 | { |
d75586ad | 1132 | unsigned long address; |
da7bfc50 HH |
1133 | int do_split, err; |
1134 | unsigned int level; | |
c31c7d48 | 1135 | pte_t *kpte, old_pte; |
1da177e4 | 1136 | |
8523acfe TH |
1137 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1138 | struct page *page = cpa->pages[cpa->curpage]; | |
1139 | if (unlikely(PageHighMem(page))) | |
1140 | return 0; | |
1141 | address = (unsigned long)page_address(page); | |
1142 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1143 | address = cpa->vaddr[cpa->curpage]; |
1144 | else | |
1145 | address = *cpa->vaddr; | |
97f99fed | 1146 | repeat: |
82f0712c | 1147 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1148 | if (!kpte) |
a1e46212 | 1149 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1150 | |
1151 | old_pte = *kpte; | |
a1e46212 SS |
1152 | if (!pte_val(old_pte)) |
1153 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 1154 | |
30551bb3 | 1155 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1156 | pte_t new_pte; |
626c2c9d | 1157 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1158 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1159 | |
72e458df TG |
1160 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1161 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1162 | |
c31c7d48 | 1163 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 1164 | |
a8aed3e0 AA |
1165 | /* |
1166 | * Set the GLOBAL flags only if the PRESENT flag is | |
1167 | * set otherwise pte_present will return true even on | |
1168 | * a non present pte. The canon_pgprot will clear | |
1169 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
1170 | * support it. | |
1171 | */ | |
1172 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
1173 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
1174 | else | |
1175 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
1176 | ||
626c2c9d AV |
1177 | /* |
1178 | * We need to keep the pfn from the existing PTE, | |
1179 | * after all we're only going to change it's attributes | |
1180 | * not the memory it points to | |
1181 | */ | |
c31c7d48 TG |
1182 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
1183 | cpa->pfn = pfn; | |
f4ae5da0 TG |
1184 | /* |
1185 | * Do we really change anything ? | |
1186 | */ | |
1187 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1188 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1189 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1190 | } |
9b5cf48b | 1191 | cpa->numpages = 1; |
65e074df | 1192 | return 0; |
1da177e4 | 1193 | } |
65e074df TG |
1194 | |
1195 | /* | |
1196 | * Check, whether we can keep the large page intact | |
1197 | * and just change the pte: | |
1198 | */ | |
beaff633 | 1199 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
1200 | /* |
1201 | * When the range fits into the existing large page, | |
9b5cf48b | 1202 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1203 | * try_large_page: |
1204 | */ | |
87f7f8fe IM |
1205 | if (do_split <= 0) |
1206 | return do_split; | |
65e074df TG |
1207 | |
1208 | /* | |
1209 | * We have to split the large page: | |
1210 | */ | |
82f0712c | 1211 | err = split_large_page(cpa, kpte, address); |
87f7f8fe | 1212 | if (!err) { |
ad5ca55f SS |
1213 | /* |
1214 | * Do a global flush tlb after splitting the large page | |
1215 | * and before we do the actual change page attribute in the PTE. | |
1216 | * | |
1217 | * With out this, we violate the TLB application note, that says | |
1218 | * "The TLBs may contain both ordinary and large-page | |
1219 | * translations for a 4-KByte range of linear addresses. This | |
1220 | * may occur if software modifies the paging structures so that | |
1221 | * the page size used for the address range changes. If the two | |
1222 | * translations differ with respect to page frame or attributes | |
1223 | * (e.g., permissions), processor behavior is undefined and may | |
1224 | * be implementation-specific." | |
1225 | * | |
1226 | * We do this global tlb flush inside the cpa_lock, so that we | |
1227 | * don't allow any other cpu, with stale tlb entries change the | |
1228 | * page attribute in parallel, that also falls into the | |
1229 | * just split large page entry. | |
1230 | */ | |
1231 | flush_tlb_all(); | |
87f7f8fe IM |
1232 | goto repeat; |
1233 | } | |
beaff633 | 1234 | |
87f7f8fe | 1235 | return err; |
9f4c815c | 1236 | } |
1da177e4 | 1237 | |
c31c7d48 TG |
1238 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1239 | ||
1240 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1241 | { |
c31c7d48 | 1242 | struct cpa_data alias_cpa; |
992f4c1c | 1243 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1244 | unsigned long vaddr; |
992f4c1c | 1245 | int ret; |
44af6c41 | 1246 | |
8eb5779f | 1247 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1248 | return 0; |
626c2c9d | 1249 | |
f34b439f TG |
1250 | /* |
1251 | * No need to redo, when the primary call touched the direct | |
1252 | * mapping already: | |
1253 | */ | |
8523acfe TH |
1254 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1255 | struct page *page = cpa->pages[cpa->curpage]; | |
1256 | if (unlikely(PageHighMem(page))) | |
1257 | return 0; | |
1258 | vaddr = (unsigned long)page_address(page); | |
1259 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1260 | vaddr = cpa->vaddr[cpa->curpage]; |
1261 | else | |
1262 | vaddr = *cpa->vaddr; | |
1263 | ||
1264 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 1265 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1266 | |
f34b439f | 1267 | alias_cpa = *cpa; |
992f4c1c | 1268 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1269 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 1270 | |
f34b439f | 1271 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1272 | if (ret) |
1273 | return ret; | |
f34b439f | 1274 | } |
44af6c41 | 1275 | |
44af6c41 | 1276 | #ifdef CONFIG_X86_64 |
488fd995 | 1277 | /* |
992f4c1c TH |
1278 | * If the primary call didn't touch the high mapping already |
1279 | * and the physical address is inside the kernel map, we need | |
0879750f | 1280 | * to touch the high mapped kernel as well: |
488fd995 | 1281 | */ |
992f4c1c TH |
1282 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
1283 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
1284 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
1285 | __START_KERNEL_map - phys_base; | |
1286 | alias_cpa = *cpa; | |
1287 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1288 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 1289 | |
992f4c1c TH |
1290 | /* |
1291 | * The high mapping range is imprecise, so ignore the | |
1292 | * return value. | |
1293 | */ | |
1294 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1295 | } | |
488fd995 | 1296 | #endif |
992f4c1c TH |
1297 | |
1298 | return 0; | |
1da177e4 LT |
1299 | } |
1300 | ||
c31c7d48 | 1301 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1302 | { |
65e074df | 1303 | int ret, numpages = cpa->numpages; |
ff31452b | 1304 | |
65e074df TG |
1305 | while (numpages) { |
1306 | /* | |
1307 | * Store the remaining nr of pages for the large page | |
1308 | * preservation check. | |
1309 | */ | |
9b5cf48b | 1310 | cpa->numpages = numpages; |
d75586ad | 1311 | /* for array changes, we can't use large page */ |
9ae28475 | 1312 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1313 | cpa->numpages = 1; |
c31c7d48 | 1314 | |
ad5ca55f SS |
1315 | if (!debug_pagealloc) |
1316 | spin_lock(&cpa_lock); | |
c31c7d48 | 1317 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
1318 | if (!debug_pagealloc) |
1319 | spin_unlock(&cpa_lock); | |
ff31452b TG |
1320 | if (ret) |
1321 | return ret; | |
ff31452b | 1322 | |
c31c7d48 TG |
1323 | if (checkalias) { |
1324 | ret = cpa_process_alias(cpa); | |
1325 | if (ret) | |
1326 | return ret; | |
1327 | } | |
1328 | ||
65e074df TG |
1329 | /* |
1330 | * Adjust the number of pages with the result of the | |
1331 | * CPA operation. Either a large page has been | |
1332 | * preserved or a single page update happened. | |
1333 | */ | |
9b5cf48b RW |
1334 | BUG_ON(cpa->numpages > numpages); |
1335 | numpages -= cpa->numpages; | |
9ae28475 | 1336 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1337 | cpa->curpage++; |
1338 | else | |
1339 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1340 | ||
65e074df | 1341 | } |
ff31452b TG |
1342 | return 0; |
1343 | } | |
1344 | ||
d75586ad | 1345 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1346 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1347 | int force_split, int in_flag, |
1348 | struct page **pages) | |
ff31452b | 1349 | { |
72e458df | 1350 | struct cpa_data cpa; |
cacf8906 | 1351 | int ret, cache, checkalias; |
fa526d0d | 1352 | unsigned long baddr = 0; |
331e4065 | 1353 | |
82f0712c BP |
1354 | memset(&cpa, 0, sizeof(cpa)); |
1355 | ||
331e4065 TG |
1356 | /* |
1357 | * Check, if we are requested to change a not supported | |
1358 | * feature: | |
1359 | */ | |
1360 | mask_set = canon_pgprot(mask_set); | |
1361 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 1362 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1363 | return 0; |
1364 | ||
69b1415e | 1365 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1366 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1367 | int i; |
1368 | for (i = 0; i < numpages; i++) { | |
1369 | if (addr[i] & ~PAGE_MASK) { | |
1370 | addr[i] &= PAGE_MASK; | |
1371 | WARN_ON_ONCE(1); | |
1372 | } | |
1373 | } | |
9ae28475 | 1374 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1375 | /* | |
1376 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1377 | * No need to cehck in that case | |
1378 | */ | |
1379 | if (*addr & ~PAGE_MASK) { | |
1380 | *addr &= PAGE_MASK; | |
1381 | /* | |
1382 | * People should not be passing in unaligned addresses: | |
1383 | */ | |
1384 | WARN_ON_ONCE(1); | |
1385 | } | |
fa526d0d JS |
1386 | /* |
1387 | * Save address for cache flush. *addr is modified in the call | |
1388 | * to __change_page_attr_set_clr() below. | |
1389 | */ | |
1390 | baddr = *addr; | |
69b1415e TG |
1391 | } |
1392 | ||
5843d9a4 NP |
1393 | /* Must avoid aliasing mappings in the highmem code */ |
1394 | kmap_flush_unused(); | |
1395 | ||
db64fe02 NP |
1396 | vm_unmap_aliases(); |
1397 | ||
72e458df | 1398 | cpa.vaddr = addr; |
9ae28475 | 1399 | cpa.pages = pages; |
72e458df TG |
1400 | cpa.numpages = numpages; |
1401 | cpa.mask_set = mask_set; | |
1402 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1403 | cpa.flags = 0; |
1404 | cpa.curpage = 0; | |
c9caa02c | 1405 | cpa.force_split = force_split; |
72e458df | 1406 | |
9ae28475 | 1407 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1408 | cpa.flags |= in_flag; | |
d75586ad | 1409 | |
af96e443 TG |
1410 | /* No alias checking for _NX bit modifications */ |
1411 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1412 | ||
1413 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1414 | |
f4ae5da0 TG |
1415 | /* |
1416 | * Check whether we really changed something: | |
1417 | */ | |
d75586ad | 1418 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1419 | goto out; |
cacf8906 | 1420 | |
6bb8383b AK |
1421 | /* |
1422 | * No need to flush, when we did not set any of the caching | |
1423 | * attributes: | |
1424 | */ | |
c06814d8 | 1425 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1426 | |
57a6a46a | 1427 | /* |
b82ad3d3 BP |
1428 | * On success we use CLFLUSH, when the CPU supports it to |
1429 | * avoid the WBINVD. If the CPU does not support it and in the | |
f026cfa8 | 1430 | * error case we fall back to cpa_flush_all (which uses |
b82ad3d3 | 1431 | * WBINVD): |
57a6a46a | 1432 | */ |
f026cfa8 | 1433 | if (!ret && cpu_has_clflush) { |
9ae28475 | 1434 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1435 | cpa_flush_array(addr, numpages, cache, | |
1436 | cpa.flags, pages); | |
1437 | } else | |
fa526d0d | 1438 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1439 | } else |
6bb8383b | 1440 | cpa_flush_all(cache); |
cacf8906 | 1441 | |
76ebd054 | 1442 | out: |
ff31452b TG |
1443 | return ret; |
1444 | } | |
1445 | ||
d75586ad SL |
1446 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1447 | pgprot_t mask, int array) | |
75cbade8 | 1448 | { |
d75586ad | 1449 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1450 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1451 | } |
1452 | ||
d75586ad SL |
1453 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1454 | pgprot_t mask, int array) | |
72932c7a | 1455 | { |
d75586ad | 1456 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1457 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1458 | } |
1459 | ||
0f350755 | 1460 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1461 | pgprot_t mask) | |
1462 | { | |
1463 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1464 | CPA_PAGES_ARRAY, pages); | |
1465 | } | |
1466 | ||
1467 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1468 | pgprot_t mask) | |
1469 | { | |
1470 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1471 | CPA_PAGES_ARRAY, pages); | |
1472 | } | |
1473 | ||
1219333d | 1474 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1475 | { |
de33c442 SS |
1476 | /* |
1477 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1478 | * If you really need strong UC use ioremap_uc(), but note |
1479 | * that you cannot override IO areas with set_memory_*() as | |
1480 | * these helpers cannot work with IO memory. | |
de33c442 | 1481 | */ |
d75586ad | 1482 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1483 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1484 | 0); | |
75cbade8 | 1485 | } |
1219333d | 1486 | |
1487 | int set_memory_uc(unsigned long addr, int numpages) | |
1488 | { | |
9fa3ab39 | 1489 | int ret; |
1490 | ||
de33c442 SS |
1491 | /* |
1492 | * for now UC MINUS. see comments in ioremap_nocache() | |
1493 | */ | |
9fa3ab39 | 1494 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1495 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1496 | if (ret) |
1497 | goto out_err; | |
1498 | ||
1499 | ret = _set_memory_uc(addr, numpages); | |
1500 | if (ret) | |
1501 | goto out_free; | |
1502 | ||
1503 | return 0; | |
1219333d | 1504 | |
9fa3ab39 | 1505 | out_free: |
1506 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1507 | out_err: | |
1508 | return ret; | |
1219333d | 1509 | } |
75cbade8 AV |
1510 | EXPORT_SYMBOL(set_memory_uc); |
1511 | ||
2d070eff | 1512 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1513 | enum page_cache_mode new_type) |
d75586ad | 1514 | { |
623dffb2 | 1515 | enum page_cache_mode set_type; |
9fa3ab39 | 1516 | int i, j; |
1517 | int ret; | |
1518 | ||
d75586ad | 1519 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1520 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1521 | new_type, NULL); |
9fa3ab39 | 1522 | if (ret) |
1523 | goto out_free; | |
d75586ad SL |
1524 | } |
1525 | ||
623dffb2 TK |
1526 | /* If WC, set to UC- first and then WC */ |
1527 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1528 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1529 | ||
9fa3ab39 | 1530 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1531 | cachemode2pgprot(set_type), 1); |
4f646254 | 1532 | |
c06814d8 | 1533 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1534 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1535 | cachemode2pgprot( |
1536 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1537 | __pgprot(_PAGE_CACHE_MASK), |
1538 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1539 | if (ret) |
1540 | goto out_free; | |
1541 | ||
1542 | return 0; | |
1543 | ||
1544 | out_free: | |
1545 | for (j = 0; j < i; j++) | |
1546 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1547 | ||
1548 | return ret; | |
d75586ad | 1549 | } |
4f646254 PN |
1550 | |
1551 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1552 | { | |
c06814d8 | 1553 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1554 | } |
d75586ad SL |
1555 | EXPORT_SYMBOL(set_memory_array_uc); |
1556 | ||
4f646254 PN |
1557 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1558 | { | |
c06814d8 | 1559 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1560 | } |
1561 | EXPORT_SYMBOL(set_memory_array_wc); | |
1562 | ||
623dffb2 TK |
1563 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1564 | { | |
1565 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1566 | } | |
1567 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1568 | ||
ef354af4 | 1569 | int _set_memory_wc(unsigned long addr, int numpages) |
1570 | { | |
3869c4aa | 1571 | int ret; |
bdc6340f PV |
1572 | unsigned long addr_copy = addr; |
1573 | ||
3869c4aa | 1574 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1575 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1576 | 0); | |
3869c4aa | 1577 | if (!ret) { |
bdc6340f | 1578 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
c06814d8 JG |
1579 | cachemode2pgprot( |
1580 | _PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1581 | __pgprot(_PAGE_CACHE_MASK), |
1582 | 0, 0, NULL); | |
3869c4aa | 1583 | } |
1584 | return ret; | |
ef354af4 | 1585 | } |
1586 | ||
1587 | int set_memory_wc(unsigned long addr, int numpages) | |
1588 | { | |
9fa3ab39 | 1589 | int ret; |
1590 | ||
9fa3ab39 | 1591 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1592 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1593 | if (ret) |
623dffb2 | 1594 | return ret; |
ef354af4 | 1595 | |
9fa3ab39 | 1596 | ret = _set_memory_wc(addr, numpages); |
1597 | if (ret) | |
623dffb2 | 1598 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1599 | |
9fa3ab39 | 1600 | return ret; |
ef354af4 | 1601 | } |
1602 | EXPORT_SYMBOL(set_memory_wc); | |
1603 | ||
623dffb2 TK |
1604 | int _set_memory_wt(unsigned long addr, int numpages) |
1605 | { | |
1606 | return change_page_attr_set(&addr, numpages, | |
1607 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1608 | } | |
1609 | ||
1610 | int set_memory_wt(unsigned long addr, int numpages) | |
1611 | { | |
1612 | int ret; | |
1613 | ||
1614 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1615 | _PAGE_CACHE_MODE_WT, NULL); | |
1616 | if (ret) | |
1617 | return ret; | |
1618 | ||
1619 | ret = _set_memory_wt(addr, numpages); | |
1620 | if (ret) | |
1621 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1622 | ||
1623 | return ret; | |
1624 | } | |
1625 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1626 | ||
1219333d | 1627 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1628 | { |
c06814d8 | 1629 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1630 | return change_page_attr_clear(&addr, numpages, |
1631 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1632 | } |
1219333d | 1633 | |
1634 | int set_memory_wb(unsigned long addr, int numpages) | |
1635 | { | |
9fa3ab39 | 1636 | int ret; |
1637 | ||
1638 | ret = _set_memory_wb(addr, numpages); | |
1639 | if (ret) | |
1640 | return ret; | |
1641 | ||
c15238df | 1642 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1643 | return 0; |
1219333d | 1644 | } |
75cbade8 AV |
1645 | EXPORT_SYMBOL(set_memory_wb); |
1646 | ||
d75586ad SL |
1647 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1648 | { | |
1649 | int i; | |
a5593e0b | 1650 | int ret; |
1651 | ||
c06814d8 | 1652 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 1653 | ret = change_page_attr_clear(addr, addrinarray, |
1654 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1655 | if (ret) |
1656 | return ret; | |
d75586ad | 1657 | |
9fa3ab39 | 1658 | for (i = 0; i < addrinarray; i++) |
1659 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1660 | |
9fa3ab39 | 1661 | return 0; |
d75586ad SL |
1662 | } |
1663 | EXPORT_SYMBOL(set_memory_array_wb); | |
1664 | ||
75cbade8 AV |
1665 | int set_memory_x(unsigned long addr, int numpages) |
1666 | { | |
583140af PA |
1667 | if (!(__supported_pte_mask & _PAGE_NX)) |
1668 | return 0; | |
1669 | ||
d75586ad | 1670 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1671 | } |
1672 | EXPORT_SYMBOL(set_memory_x); | |
1673 | ||
1674 | int set_memory_nx(unsigned long addr, int numpages) | |
1675 | { | |
583140af PA |
1676 | if (!(__supported_pte_mask & _PAGE_NX)) |
1677 | return 0; | |
1678 | ||
d75586ad | 1679 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1680 | } |
1681 | EXPORT_SYMBOL(set_memory_nx); | |
1682 | ||
1683 | int set_memory_ro(unsigned long addr, int numpages) | |
1684 | { | |
d75586ad | 1685 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1686 | } |
75cbade8 AV |
1687 | |
1688 | int set_memory_rw(unsigned long addr, int numpages) | |
1689 | { | |
d75586ad | 1690 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1691 | } |
f62d0f00 IM |
1692 | |
1693 | int set_memory_np(unsigned long addr, int numpages) | |
1694 | { | |
d75586ad | 1695 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1696 | } |
75cbade8 | 1697 | |
c9caa02c AK |
1698 | int set_memory_4k(unsigned long addr, int numpages) |
1699 | { | |
d75586ad | 1700 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1701 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1702 | } |
1703 | ||
75cbade8 AV |
1704 | int set_pages_uc(struct page *page, int numpages) |
1705 | { | |
1706 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1707 | |
d7c8f21a | 1708 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1709 | } |
1710 | EXPORT_SYMBOL(set_pages_uc); | |
1711 | ||
4f646254 | 1712 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 1713 | enum page_cache_mode new_type) |
0f350755 | 1714 | { |
1715 | unsigned long start; | |
1716 | unsigned long end; | |
623dffb2 | 1717 | enum page_cache_mode set_type; |
0f350755 | 1718 | int i; |
1719 | int free_idx; | |
4f646254 | 1720 | int ret; |
0f350755 | 1721 | |
1722 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1723 | if (PageHighMem(pages[i])) |
1724 | continue; | |
1725 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1726 | end = start + PAGE_SIZE; |
4f646254 | 1727 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1728 | goto err_out; |
1729 | } | |
1730 | ||
623dffb2 TK |
1731 | /* If WC, set to UC- first and then WC */ |
1732 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1733 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1734 | ||
4f646254 | 1735 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 1736 | cachemode2pgprot(set_type)); |
c06814d8 | 1737 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1738 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
1739 | cachemode2pgprot( |
1740 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1741 | __pgprot(_PAGE_CACHE_MASK), |
1742 | 0, CPA_PAGES_ARRAY, pages); | |
1743 | if (ret) | |
1744 | goto err_out; | |
1745 | return 0; /* Success */ | |
0f350755 | 1746 | err_out: |
1747 | free_idx = i; | |
1748 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1749 | if (PageHighMem(pages[i])) |
1750 | continue; | |
1751 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1752 | end = start + PAGE_SIZE; |
1753 | free_memtype(start, end); | |
1754 | } | |
1755 | return -EINVAL; | |
1756 | } | |
4f646254 PN |
1757 | |
1758 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1759 | { | |
c06814d8 | 1760 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1761 | } |
0f350755 | 1762 | EXPORT_SYMBOL(set_pages_array_uc); |
1763 | ||
4f646254 PN |
1764 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1765 | { | |
c06814d8 | 1766 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1767 | } |
1768 | EXPORT_SYMBOL(set_pages_array_wc); | |
1769 | ||
623dffb2 TK |
1770 | int set_pages_array_wt(struct page **pages, int addrinarray) |
1771 | { | |
1772 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
1773 | } | |
1774 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
1775 | ||
75cbade8 AV |
1776 | int set_pages_wb(struct page *page, int numpages) |
1777 | { | |
1778 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1779 | |
d7c8f21a | 1780 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1781 | } |
1782 | EXPORT_SYMBOL(set_pages_wb); | |
1783 | ||
0f350755 | 1784 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1785 | { | |
1786 | int retval; | |
1787 | unsigned long start; | |
1788 | unsigned long end; | |
1789 | int i; | |
1790 | ||
c06814d8 | 1791 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 1792 | retval = cpa_clear_pages_array(pages, addrinarray, |
1793 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1794 | if (retval) |
1795 | return retval; | |
0f350755 | 1796 | |
1797 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1798 | if (PageHighMem(pages[i])) |
1799 | continue; | |
1800 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1801 | end = start + PAGE_SIZE; |
1802 | free_memtype(start, end); | |
1803 | } | |
1804 | ||
9fa3ab39 | 1805 | return 0; |
0f350755 | 1806 | } |
1807 | EXPORT_SYMBOL(set_pages_array_wb); | |
1808 | ||
75cbade8 AV |
1809 | int set_pages_x(struct page *page, int numpages) |
1810 | { | |
1811 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1812 | |
d7c8f21a | 1813 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1814 | } |
1815 | EXPORT_SYMBOL(set_pages_x); | |
1816 | ||
1817 | int set_pages_nx(struct page *page, int numpages) | |
1818 | { | |
1819 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1820 | |
d7c8f21a | 1821 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1822 | } |
1823 | EXPORT_SYMBOL(set_pages_nx); | |
1824 | ||
1825 | int set_pages_ro(struct page *page, int numpages) | |
1826 | { | |
1827 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1828 | |
d7c8f21a | 1829 | return set_memory_ro(addr, numpages); |
75cbade8 | 1830 | } |
75cbade8 AV |
1831 | |
1832 | int set_pages_rw(struct page *page, int numpages) | |
1833 | { | |
1834 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1835 | |
d7c8f21a | 1836 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1837 | } |
1838 | ||
1da177e4 | 1839 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1840 | |
1841 | static int __set_pages_p(struct page *page, int numpages) | |
1842 | { | |
d75586ad SL |
1843 | unsigned long tempaddr = (unsigned long) page_address(page); |
1844 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1845 | .pgd = NULL, |
72e458df TG |
1846 | .numpages = numpages, |
1847 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1848 | .mask_clr = __pgprot(0), |
1849 | .flags = 0}; | |
72932c7a | 1850 | |
55121b43 SS |
1851 | /* |
1852 | * No alias checking needed for setting present flag. otherwise, | |
1853 | * we may need to break large pages for 64-bit kernel text | |
1854 | * mappings (this adds to complexity if we want to do this from | |
1855 | * atomic context especially). Let's keep it simple! | |
1856 | */ | |
1857 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1858 | } |
1859 | ||
1860 | static int __set_pages_np(struct page *page, int numpages) | |
1861 | { | |
d75586ad SL |
1862 | unsigned long tempaddr = (unsigned long) page_address(page); |
1863 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1864 | .pgd = NULL, |
72e458df TG |
1865 | .numpages = numpages, |
1866 | .mask_set = __pgprot(0), | |
d75586ad SL |
1867 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1868 | .flags = 0}; | |
72932c7a | 1869 | |
55121b43 SS |
1870 | /* |
1871 | * No alias checking needed for setting not present flag. otherwise, | |
1872 | * we may need to break large pages for 64-bit kernel text | |
1873 | * mappings (this adds to complexity if we want to do this from | |
1874 | * atomic context especially). Let's keep it simple! | |
1875 | */ | |
1876 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1877 | } |
1878 | ||
031bc574 | 1879 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
1880 | { |
1881 | if (PageHighMem(page)) | |
1882 | return; | |
9f4c815c | 1883 | if (!enable) { |
f9b8404c IM |
1884 | debug_check_no_locks_freed(page_address(page), |
1885 | numpages * PAGE_SIZE); | |
9f4c815c | 1886 | } |
de5097c2 | 1887 | |
9f4c815c | 1888 | /* |
f8d8406b | 1889 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1890 | * Large pages for identity mappings are not used at boot time |
1891 | * and hence no memory allocations during large page split. | |
1da177e4 | 1892 | */ |
f62d0f00 IM |
1893 | if (enable) |
1894 | __set_pages_p(page, numpages); | |
1895 | else | |
1896 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1897 | |
1898 | /* | |
e4b71dcf IM |
1899 | * We should perform an IPI and flush all tlbs, |
1900 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1901 | */ |
1902 | __flush_tlb_all(); | |
26564600 BO |
1903 | |
1904 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1905 | } |
1906 | ||
8a235efa RW |
1907 | #ifdef CONFIG_HIBERNATION |
1908 | ||
1909 | bool kernel_page_present(struct page *page) | |
1910 | { | |
1911 | unsigned int level; | |
1912 | pte_t *pte; | |
1913 | ||
1914 | if (PageHighMem(page)) | |
1915 | return false; | |
1916 | ||
1917 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1918 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1919 | } | |
1920 | ||
1921 | #endif /* CONFIG_HIBERNATION */ | |
1922 | ||
1923 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 1924 | |
82f0712c BP |
1925 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
1926 | unsigned numpages, unsigned long page_flags) | |
1927 | { | |
1928 | int retval = -EINVAL; | |
1929 | ||
1930 | struct cpa_data cpa = { | |
1931 | .vaddr = &address, | |
1932 | .pfn = pfn, | |
1933 | .pgd = pgd, | |
1934 | .numpages = numpages, | |
1935 | .mask_set = __pgprot(0), | |
1936 | .mask_clr = __pgprot(0), | |
1937 | .flags = 0, | |
1938 | }; | |
1939 | ||
1940 | if (!(__supported_pte_mask & _PAGE_NX)) | |
1941 | goto out; | |
1942 | ||
1943 | if (!(page_flags & _PAGE_NX)) | |
1944 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
1945 | ||
1946 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); | |
1947 | ||
1948 | retval = __change_page_attr_set_clr(&cpa, 0); | |
1949 | __flush_tlb_all(); | |
1950 | ||
1951 | out: | |
1952 | return retval; | |
1953 | } | |
1954 | ||
42a54772 BP |
1955 | void kernel_unmap_pages_in_pgd(pgd_t *root, unsigned long address, |
1956 | unsigned numpages) | |
1957 | { | |
1958 | unmap_pgd_range(root, address, address + (numpages << PAGE_SHIFT)); | |
1959 | } | |
1960 | ||
d1028a15 AV |
1961 | /* |
1962 | * The testcases use internal knowledge of the implementation that shouldn't | |
1963 | * be exposed to the rest of the kernel. Include these directly here. | |
1964 | */ | |
1965 | #ifdef CONFIG_CPA_DEBUG | |
1966 | #include "pageattr-test.c" | |
1967 | #endif |