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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
7c0f6ba6 | 23 | #include <linux/uaccess.h> |
9f4c815c | 24 | #include <asm/pgalloc.h> |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
0fd64c23 | 33 | pgd_t *pgd; |
72e458df TG |
34 | pgprot_t mask_set; |
35 | pgprot_t mask_clr; | |
74256377 | 36 | unsigned long numpages; |
d75586ad | 37 | int flags; |
c31c7d48 | 38 | unsigned long pfn; |
c9caa02c | 39 | unsigned force_split : 1; |
d75586ad | 40 | int curpage; |
9ae28475 | 41 | struct page **pages; |
72e458df TG |
42 | }; |
43 | ||
ad5ca55f SS |
44 | /* |
45 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
46 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
47 | * entries change the page attribute in parallel to some other cpu | |
48 | * splitting a large page entry along with changing the attribute. | |
49 | */ | |
50 | static DEFINE_SPINLOCK(cpa_lock); | |
51 | ||
d75586ad SL |
52 | #define CPA_FLUSHTLB 1 |
53 | #define CPA_ARRAY 2 | |
9ae28475 | 54 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 55 | |
65280e61 | 56 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
57 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
58 | ||
65280e61 | 59 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 60 | { |
ce0c0e50 | 61 | /* Protect against CPA */ |
a79e53d8 | 62 | spin_lock(&pgd_lock); |
ce0c0e50 | 63 | direct_pages_count[level] += pages; |
a79e53d8 | 64 | spin_unlock(&pgd_lock); |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
c9e0d391 DJ |
69 | if (direct_pages_count[level] == 0) |
70 | return; | |
71 | ||
65280e61 TG |
72 | direct_pages_count[level]--; |
73 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
74 | } | |
75 | ||
e1759c21 | 76 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 77 | { |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_4K] << 2); |
80 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 11); |
83 | #else | |
b9c3bfc2 | 84 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
85 | direct_pages_count[PG_LEVEL_2M] << 12); |
86 | #endif | |
a06de630 | 87 | if (direct_gbpages) |
b9c3bfc2 | 88 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 89 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 90 | } |
65280e61 TG |
91 | #else |
92 | static inline void split_page_count(int level) { } | |
93 | #endif | |
ce0c0e50 | 94 | |
c31c7d48 TG |
95 | #ifdef CONFIG_X86_64 |
96 | ||
97 | static inline unsigned long highmap_start_pfn(void) | |
98 | { | |
fc8d7826 | 99 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
100 | } |
101 | ||
102 | static inline unsigned long highmap_end_pfn(void) | |
103 | { | |
4ff53087 TG |
104 | /* Do not reference physical address outside the kernel. */ |
105 | return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT; | |
c31c7d48 TG |
106 | } |
107 | ||
108 | #endif | |
109 | ||
ed724be6 AV |
110 | static inline int |
111 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 112 | { |
ed724be6 AV |
113 | return addr >= start && addr < end; |
114 | } | |
115 | ||
4ff53087 TG |
116 | static inline int |
117 | within_inclusive(unsigned long addr, unsigned long start, unsigned long end) | |
118 | { | |
119 | return addr >= start && addr <= end; | |
120 | } | |
121 | ||
d7c8f21a TG |
122 | /* |
123 | * Flushing functions | |
124 | */ | |
cd8ddf1a | 125 | |
cd8ddf1a TG |
126 | /** |
127 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 128 | * @vaddr: virtual start address |
cd8ddf1a TG |
129 | * @size: number of bytes to flush |
130 | * | |
8b80fd8b RZ |
131 | * clflushopt is an unordered instruction which needs fencing with mfence or |
132 | * sfence to avoid ordering issues. | |
cd8ddf1a | 133 | */ |
4c61afcd | 134 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 135 | { |
1f1a89ac CW |
136 | const unsigned long clflush_size = boot_cpu_data.x86_clflush_size; |
137 | void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1)); | |
6c434d61 | 138 | void *vend = vaddr + size; |
1f1a89ac CW |
139 | |
140 | if (p >= vend) | |
141 | return; | |
d7c8f21a | 142 | |
cd8ddf1a | 143 | mb(); |
4c61afcd | 144 | |
1f1a89ac | 145 | for (; p < vend; p += clflush_size) |
6c434d61 | 146 | clflushopt(p); |
4c61afcd | 147 | |
cd8ddf1a | 148 | mb(); |
d7c8f21a | 149 | } |
e517a5e9 | 150 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 151 | |
af1e6844 | 152 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 153 | { |
6bb8383b AK |
154 | unsigned long cache = (unsigned long)arg; |
155 | ||
d7c8f21a TG |
156 | /* |
157 | * Flush all to work around Errata in early athlons regarding | |
158 | * large page flushing. | |
159 | */ | |
160 | __flush_tlb_all(); | |
161 | ||
0b827537 | 162 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
163 | wbinvd(); |
164 | } | |
165 | ||
6bb8383b | 166 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
167 | { |
168 | BUG_ON(irqs_disabled()); | |
169 | ||
15c8b6c1 | 170 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
171 | } |
172 | ||
57a6a46a TG |
173 | static void __cpa_flush_range(void *arg) |
174 | { | |
57a6a46a TG |
175 | /* |
176 | * We could optimize that further and do individual per page | |
177 | * tlb invalidates for a low number of pages. Caveat: we must | |
178 | * flush the high aliases on 64bit as well. | |
179 | */ | |
180 | __flush_tlb_all(); | |
57a6a46a TG |
181 | } |
182 | ||
6bb8383b | 183 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 184 | { |
4c61afcd IM |
185 | unsigned int i, level; |
186 | unsigned long addr; | |
187 | ||
57a6a46a | 188 | BUG_ON(irqs_disabled()); |
4c61afcd | 189 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 190 | |
15c8b6c1 | 191 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 192 | |
6bb8383b AK |
193 | if (!cache) |
194 | return; | |
195 | ||
3b233e52 TG |
196 | /* |
197 | * We only need to flush on one CPU, | |
198 | * clflush is a MESI-coherent instruction that | |
199 | * will cause all other CPUs to flush the same | |
200 | * cachelines: | |
201 | */ | |
4c61afcd IM |
202 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
203 | pte_t *pte = lookup_address(addr, &level); | |
204 | ||
205 | /* | |
206 | * Only flush present addresses: | |
207 | */ | |
7bfb72e8 | 208 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
209 | clflush_cache_range((void *) addr, PAGE_SIZE); |
210 | } | |
57a6a46a TG |
211 | } |
212 | ||
9ae28475 | 213 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
214 | int in_flags, struct page **pages) | |
d75586ad SL |
215 | { |
216 | unsigned int i, level; | |
2171787b | 217 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
218 | |
219 | BUG_ON(irqs_disabled()); | |
220 | ||
2171787b | 221 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 222 | |
2171787b | 223 | if (!cache || do_wbinvd) |
d75586ad SL |
224 | return; |
225 | ||
d75586ad SL |
226 | /* |
227 | * We only need to flush on one CPU, | |
228 | * clflush is a MESI-coherent instruction that | |
229 | * will cause all other CPUs to flush the same | |
230 | * cachelines: | |
231 | */ | |
9ae28475 | 232 | for (i = 0; i < numpages; i++) { |
233 | unsigned long addr; | |
234 | pte_t *pte; | |
235 | ||
236 | if (in_flags & CPA_PAGES_ARRAY) | |
237 | addr = (unsigned long)page_address(pages[i]); | |
238 | else | |
239 | addr = start[i]; | |
240 | ||
241 | pte = lookup_address(addr, &level); | |
d75586ad SL |
242 | |
243 | /* | |
244 | * Only flush present addresses: | |
245 | */ | |
246 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 247 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
248 | } |
249 | } | |
250 | ||
ed724be6 AV |
251 | /* |
252 | * Certain areas of memory on x86 require very specific protection flags, | |
253 | * for example the BIOS area or kernel text. Callers don't always get this | |
254 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
255 | * checks and fixes these known static required protection bits. | |
256 | */ | |
c31c7d48 TG |
257 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
258 | unsigned long pfn) | |
ed724be6 AV |
259 | { |
260 | pgprot_t forbidden = __pgprot(0); | |
261 | ||
687c4825 | 262 | /* |
ed724be6 AV |
263 | * The BIOS area between 640k and 1Mb needs to be executable for |
264 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 265 | */ |
5bd5a452 MC |
266 | #ifdef CONFIG_PCI_BIOS |
267 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 268 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 269 | #endif |
ed724be6 AV |
270 | |
271 | /* | |
272 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
273 | * Does not cover __inittext since that is gone later on. On |
274 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
275 | */ |
276 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
277 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 278 | |
cc0f21bb | 279 | /* |
c31c7d48 TG |
280 | * The .rodata section needs to be read-only. Using the pfn |
281 | * catches all aliases. | |
cc0f21bb | 282 | */ |
fc8d7826 AD |
283 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
284 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 285 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 286 | |
9ccaf77c | 287 | #if defined(CONFIG_X86_64) |
74e08179 | 288 | /* |
502f6604 SS |
289 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
290 | * kernel text mappings for the large page aligned text, rodata sections | |
291 | * will be always read-only. For the kernel identity mappings covering | |
292 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
293 | * |
294 | * This will preserve the large page mappings for kernel text/data | |
295 | * at no extra cost. | |
296 | */ | |
502f6604 SS |
297 | if (kernel_set_to_readonly && |
298 | within(address, (unsigned long)_text, | |
281ff33b SS |
299 | (unsigned long)__end_rodata_hpage_align)) { |
300 | unsigned int level; | |
301 | ||
302 | /* | |
303 | * Don't enforce the !RW mapping for the kernel text mapping, | |
304 | * if the current mapping is already using small page mapping. | |
305 | * No need to work hard to preserve large page mappings in this | |
306 | * case. | |
307 | * | |
308 | * This also fixes the Linux Xen paravirt guest boot failure | |
309 | * (because of unexpected read-only mappings for kernel identity | |
310 | * mappings). In this paravirt guest case, the kernel text | |
311 | * mapping and the kernel identity mapping share the same | |
312 | * page-table pages. Thus we can't really use different | |
313 | * protections for the kernel text and identity mappings. Also, | |
314 | * these shared mappings are made of small page mappings. | |
315 | * Thus this don't enforce !RW mapping for small page kernel | |
316 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 317 | * as well. |
281ff33b SS |
318 | */ |
319 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
320 | pgprot_val(forbidden) |= _PAGE_RW; | |
321 | } | |
74e08179 SS |
322 | #endif |
323 | ||
ed724be6 | 324 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
325 | |
326 | return prot; | |
327 | } | |
328 | ||
426e34cc MF |
329 | /* |
330 | * Lookup the page table entry for a virtual address in a specific pgd. | |
331 | * Return a pointer to the entry and the level of the mapping. | |
332 | */ | |
333 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
334 | unsigned int *level) | |
9f4c815c | 335 | { |
1da177e4 LT |
336 | pud_t *pud; |
337 | pmd_t *pmd; | |
9f4c815c | 338 | |
30551bb3 TG |
339 | *level = PG_LEVEL_NONE; |
340 | ||
1da177e4 LT |
341 | if (pgd_none(*pgd)) |
342 | return NULL; | |
9df84993 | 343 | |
1da177e4 LT |
344 | pud = pud_offset(pgd, address); |
345 | if (pud_none(*pud)) | |
346 | return NULL; | |
c2f71ee2 AK |
347 | |
348 | *level = PG_LEVEL_1G; | |
349 | if (pud_large(*pud) || !pud_present(*pud)) | |
350 | return (pte_t *)pud; | |
351 | ||
1da177e4 LT |
352 | pmd = pmd_offset(pud, address); |
353 | if (pmd_none(*pmd)) | |
354 | return NULL; | |
30551bb3 TG |
355 | |
356 | *level = PG_LEVEL_2M; | |
9a14aefc | 357 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 358 | return (pte_t *)pmd; |
1da177e4 | 359 | |
30551bb3 | 360 | *level = PG_LEVEL_4K; |
9df84993 | 361 | |
9f4c815c IM |
362 | return pte_offset_kernel(pmd, address); |
363 | } | |
0fd64c23 BP |
364 | |
365 | /* | |
366 | * Lookup the page table entry for a virtual address. Return a pointer | |
367 | * to the entry and the level of the mapping. | |
368 | * | |
369 | * Note: We return pud and pmd either when the entry is marked large | |
370 | * or when the present bit is not set. Otherwise we would return a | |
371 | * pointer to a nonexisting mapping. | |
372 | */ | |
373 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
374 | { | |
426e34cc | 375 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 376 | } |
75bb8835 | 377 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 378 | |
0fd64c23 BP |
379 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
380 | unsigned int *level) | |
381 | { | |
382 | if (cpa->pgd) | |
426e34cc | 383 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
384 | address, level); |
385 | ||
386 | return lookup_address(address, level); | |
387 | } | |
388 | ||
792230c3 JG |
389 | /* |
390 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
391 | * or NULL if not present. | |
392 | */ | |
393 | pmd_t *lookup_pmd_address(unsigned long address) | |
394 | { | |
395 | pgd_t *pgd; | |
396 | pud_t *pud; | |
397 | ||
398 | pgd = pgd_offset_k(address); | |
399 | if (pgd_none(*pgd)) | |
400 | return NULL; | |
401 | ||
402 | pud = pud_offset(pgd, address); | |
403 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) | |
404 | return NULL; | |
405 | ||
406 | return pmd_offset(pud, address); | |
407 | } | |
408 | ||
d7656534 DH |
409 | /* |
410 | * This is necessary because __pa() does not work on some | |
411 | * kinds of memory, like vmalloc() or the alloc_remap() | |
412 | * areas on 32-bit NUMA systems. The percpu areas can | |
413 | * end up in this kind of memory, for instance. | |
414 | * | |
415 | * This could be optimized, but it is only intended to be | |
416 | * used at inititalization time, and keeping it | |
417 | * unoptimized should increase the testing coverage for | |
418 | * the more obscure platforms. | |
419 | */ | |
420 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
421 | { | |
422 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
bf70e551 DC |
423 | phys_addr_t phys_addr; |
424 | unsigned long offset; | |
d7656534 | 425 | enum pg_level level; |
d7656534 DH |
426 | pte_t *pte; |
427 | ||
428 | pte = lookup_address(virt_addr, &level); | |
429 | BUG_ON(!pte); | |
34437e67 | 430 | |
bf70e551 DC |
431 | /* |
432 | * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t | |
433 | * before being left-shifted PAGE_SHIFT bits -- this trick is to | |
434 | * make 32-PAE kernel work correctly. | |
435 | */ | |
34437e67 TK |
436 | switch (level) { |
437 | case PG_LEVEL_1G: | |
bf70e551 | 438 | phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
439 | offset = virt_addr & ~PUD_PAGE_MASK; |
440 | break; | |
441 | case PG_LEVEL_2M: | |
bf70e551 | 442 | phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; |
34437e67 TK |
443 | offset = virt_addr & ~PMD_PAGE_MASK; |
444 | break; | |
445 | default: | |
bf70e551 | 446 | phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; |
34437e67 TK |
447 | offset = virt_addr & ~PAGE_MASK; |
448 | } | |
449 | ||
450 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
451 | } |
452 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
453 | ||
9df84993 IM |
454 | /* |
455 | * Set the new pmd in all the pgds we know about: | |
456 | */ | |
9a3dc780 | 457 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 458 | { |
9f4c815c IM |
459 | /* change init_mm */ |
460 | set_pte_atomic(kpte, pte); | |
44af6c41 | 461 | #ifdef CONFIG_X86_32 |
e4b71dcf | 462 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
463 | struct page *page; |
464 | ||
e3ed910d | 465 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
466 | pgd_t *pgd; |
467 | pud_t *pud; | |
468 | pmd_t *pmd; | |
469 | ||
470 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
471 | pud = pud_offset(pgd, address); | |
472 | pmd = pmd_offset(pud, address); | |
473 | set_pte_atomic((pte_t *)pmd, pte); | |
474 | } | |
1da177e4 | 475 | } |
44af6c41 | 476 | #endif |
1da177e4 LT |
477 | } |
478 | ||
9df84993 IM |
479 | static int |
480 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
481 | struct cpa_data *cpa) | |
65e074df | 482 | { |
3a19109e | 483 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn; |
65e074df | 484 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 485 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 486 | int i, do_split = 1; |
f3c4fbb6 | 487 | enum pg_level level; |
65e074df | 488 | |
c9caa02c AK |
489 | if (cpa->force_split) |
490 | return 1; | |
491 | ||
a79e53d8 | 492 | spin_lock(&pgd_lock); |
65e074df TG |
493 | /* |
494 | * Check for races, another CPU might have split this page | |
495 | * up already: | |
496 | */ | |
82f0712c | 497 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df TG |
498 | if (tmp != kpte) |
499 | goto out_unlock; | |
500 | ||
501 | switch (level) { | |
502 | case PG_LEVEL_2M: | |
3a19109e TK |
503 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
504 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
505 | break; | |
65e074df | 506 | case PG_LEVEL_1G: |
3a19109e TK |
507 | old_prot = pud_pgprot(*(pud_t *)kpte); |
508 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
f3c4fbb6 | 509 | break; |
65e074df | 510 | default: |
beaff633 | 511 | do_split = -EINVAL; |
65e074df TG |
512 | goto out_unlock; |
513 | } | |
514 | ||
3a19109e TK |
515 | psize = page_level_size(level); |
516 | pmask = page_level_mask(level); | |
517 | ||
65e074df TG |
518 | /* |
519 | * Calculate the number of pages, which fit into this large | |
520 | * page starting at address: | |
521 | */ | |
522 | nextpage_addr = (address + psize) & pmask; | |
523 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
524 | if (numpages < cpa->numpages) |
525 | cpa->numpages = numpages; | |
65e074df TG |
526 | |
527 | /* | |
528 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
529 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
530 | * up accordingly. | |
65e074df TG |
531 | */ |
532 | old_pte = *kpte; | |
55696b1f | 533 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 534 | |
64edc8ed MC |
535 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
536 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 537 | |
f5b2831d JG |
538 | /* |
539 | * req_prot is in format of 4k pages. It must be converted to large | |
540 | * page format: the caching mode includes the PAT bit located at | |
541 | * different bit positions in the two formats. | |
542 | */ | |
543 | req_prot = pgprot_4k_2_large(req_prot); | |
544 | ||
a8aed3e0 AA |
545 | /* |
546 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
547 | * set otherwise pmd_present/pmd_huge will return true even on | |
548 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
549 | * for the ancient hardware that doesn't support it. | |
550 | */ | |
f76cfa3c AA |
551 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
552 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 553 | else |
f76cfa3c | 554 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 555 | |
f76cfa3c | 556 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 557 | |
c31c7d48 | 558 | /* |
3a19109e | 559 | * old_pfn points to the large page base pfn. So we need |
c31c7d48 TG |
560 | * to add the offset of the virtual address: |
561 | */ | |
3a19109e | 562 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
563 | cpa->pfn = pfn; |
564 | ||
64edc8ed | 565 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 566 | |
fac84939 TG |
567 | /* |
568 | * We need to check the full range, whether | |
569 | * static_protection() requires a different pgprot for one of | |
570 | * the pages in the range we try to preserve: | |
571 | */ | |
64edc8ed | 572 | addr = address & pmask; |
3a19109e | 573 | pfn = old_pfn; |
64edc8ed MC |
574 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { |
575 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
576 | |
577 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
578 | goto out_unlock; | |
579 | } | |
580 | ||
65e074df TG |
581 | /* |
582 | * If there are no changes, return. maxpages has been updated | |
583 | * above: | |
584 | */ | |
585 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 586 | do_split = 0; |
65e074df TG |
587 | goto out_unlock; |
588 | } | |
589 | ||
590 | /* | |
591 | * We need to change the attributes. Check, whether we can | |
592 | * change the large page in one go. We request a split, when | |
593 | * the address is not aligned and the number of pages is | |
594 | * smaller than the number of pages in the large page. Note | |
595 | * that we limited the number of possible pages already to | |
596 | * the number of pages in the large page. | |
597 | */ | |
64edc8ed | 598 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
599 | /* |
600 | * The address is aligned and the number of pages | |
601 | * covers the full page. | |
602 | */ | |
3a19109e | 603 | new_pte = pfn_pte(old_pfn, new_prot); |
65e074df | 604 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 605 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 606 | do_split = 0; |
65e074df TG |
607 | } |
608 | ||
609 | out_unlock: | |
a79e53d8 | 610 | spin_unlock(&pgd_lock); |
9df84993 | 611 | |
beaff633 | 612 | return do_split; |
65e074df TG |
613 | } |
614 | ||
5952886b | 615 | static int |
82f0712c BP |
616 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
617 | struct page *base) | |
bb5c2dbd | 618 | { |
5952886b | 619 | pte_t *pbase = (pte_t *)page_address(base); |
d551aaa2 | 620 | unsigned long ref_pfn, pfn, pfninc = 1; |
9df84993 | 621 | unsigned int i, level; |
ae9aae9e | 622 | pte_t *tmp; |
9df84993 | 623 | pgprot_t ref_prot; |
bb5c2dbd | 624 | |
a79e53d8 | 625 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
626 | /* |
627 | * Check for races, another CPU might have split this page | |
628 | * up for us already: | |
629 | */ | |
82f0712c | 630 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
631 | if (tmp != kpte) { |
632 | spin_unlock(&pgd_lock); | |
633 | return 1; | |
634 | } | |
bb5c2dbd | 635 | |
6944a9c8 | 636 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 637 | |
d551aaa2 TK |
638 | switch (level) { |
639 | case PG_LEVEL_2M: | |
640 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
641 | /* clear PSE and promote PAT bit to correct position */ | |
f5b2831d | 642 | ref_prot = pgprot_large_2_4k(ref_prot); |
d551aaa2 TK |
643 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
644 | break; | |
bb5c2dbd | 645 | |
d551aaa2 TK |
646 | case PG_LEVEL_1G: |
647 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
648 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 649 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
d551aaa2 | 650 | |
a8aed3e0 | 651 | /* |
d551aaa2 | 652 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
653 | * otherwise pmd_present/pmd_huge will return true |
654 | * even on a non present pmd. | |
655 | */ | |
d551aaa2 | 656 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 657 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
658 | break; |
659 | ||
660 | default: | |
661 | spin_unlock(&pgd_lock); | |
662 | return 1; | |
f07333fd | 663 | } |
f07333fd | 664 | |
a8aed3e0 AA |
665 | /* |
666 | * Set the GLOBAL flags only if the PRESENT flag is set | |
667 | * otherwise pmd/pte_present will return true even on a non | |
668 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
669 | * for the ancient hardware that doesn't support it. | |
670 | */ | |
671 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
672 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
673 | else | |
674 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
675 | ||
63c1dcf4 TG |
676 | /* |
677 | * Get the target pfn from the original entry: | |
678 | */ | |
d551aaa2 | 679 | pfn = ref_pfn; |
f07333fd | 680 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 681 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 682 | |
2c66e24d SP |
683 | if (virt_addr_valid(address)) { |
684 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
685 | ||
686 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
687 | split_page_count(level); | |
688 | } | |
f361a450 | 689 | |
bb5c2dbd | 690 | /* |
07a66d7c | 691 | * Install the new, split up pagetable. |
4c881ca1 | 692 | * |
07a66d7c IM |
693 | * We use the standard kernel pagetable protections for the new |
694 | * pagetable protections, the actual ptes set above control the | |
695 | * primary protection behavior: | |
bb5c2dbd | 696 | */ |
07a66d7c | 697 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
698 | |
699 | /* | |
700 | * Intel Atom errata AAH41 workaround. | |
701 | * | |
702 | * The real fix should be in hw or in a microcode update, but | |
703 | * we also probabilistically try to reduce the window of having | |
704 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
705 | * going on. | |
706 | */ | |
707 | __flush_tlb_all(); | |
ae9aae9e | 708 | spin_unlock(&pgd_lock); |
211b3d03 | 709 | |
ae9aae9e WC |
710 | return 0; |
711 | } | |
bb5c2dbd | 712 | |
82f0712c BP |
713 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
714 | unsigned long address) | |
ae9aae9e | 715 | { |
ae9aae9e WC |
716 | struct page *base; |
717 | ||
288cf3c6 | 718 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
719 | spin_unlock(&cpa_lock); |
720 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
288cf3c6 | 721 | if (!debug_pagealloc_enabled()) |
ae9aae9e WC |
722 | spin_lock(&cpa_lock); |
723 | if (!base) | |
724 | return -ENOMEM; | |
725 | ||
82f0712c | 726 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 727 | __free_page(base); |
bb5c2dbd | 728 | |
bb5c2dbd IM |
729 | return 0; |
730 | } | |
731 | ||
52a628fb BP |
732 | static bool try_to_free_pte_page(pte_t *pte) |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = 0; i < PTRS_PER_PTE; i++) | |
737 | if (!pte_none(pte[i])) | |
738 | return false; | |
739 | ||
740 | free_page((unsigned long)pte); | |
741 | return true; | |
742 | } | |
743 | ||
744 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
745 | { | |
746 | int i; | |
747 | ||
748 | for (i = 0; i < PTRS_PER_PMD; i++) | |
749 | if (!pmd_none(pmd[i])) | |
750 | return false; | |
751 | ||
752 | free_page((unsigned long)pmd); | |
753 | return true; | |
754 | } | |
755 | ||
756 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) | |
757 | { | |
758 | pte_t *pte = pte_offset_kernel(pmd, start); | |
759 | ||
760 | while (start < end) { | |
761 | set_pte(pte, __pte(0)); | |
762 | ||
763 | start += PAGE_SIZE; | |
764 | pte++; | |
765 | } | |
766 | ||
767 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
768 | pmd_clear(pmd); | |
769 | return true; | |
770 | } | |
771 | return false; | |
772 | } | |
773 | ||
774 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
775 | unsigned long start, unsigned long end) | |
776 | { | |
777 | if (unmap_pte_range(pmd, start, end)) | |
778 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
779 | pud_clear(pud); | |
780 | } | |
781 | ||
782 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
783 | { | |
784 | pmd_t *pmd = pmd_offset(pud, start); | |
785 | ||
786 | /* | |
787 | * Not on a 2MB page boundary? | |
788 | */ | |
789 | if (start & (PMD_SIZE - 1)) { | |
790 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
791 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
792 | ||
793 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
794 | ||
795 | start = pre_end; | |
796 | pmd++; | |
797 | } | |
798 | ||
799 | /* | |
800 | * Try to unmap in 2M chunks. | |
801 | */ | |
802 | while (end - start >= PMD_SIZE) { | |
803 | if (pmd_large(*pmd)) | |
804 | pmd_clear(pmd); | |
805 | else | |
806 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
807 | ||
808 | start += PMD_SIZE; | |
809 | pmd++; | |
810 | } | |
811 | ||
812 | /* | |
813 | * 4K leftovers? | |
814 | */ | |
815 | if (start < end) | |
816 | return __unmap_pmd_range(pud, pmd, start, end); | |
817 | ||
818 | /* | |
819 | * Try again to free the PMD page if haven't succeeded above. | |
820 | */ | |
821 | if (!pud_none(*pud)) | |
822 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
823 | pud_clear(pud); | |
824 | } | |
0bb8aeee BP |
825 | |
826 | static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end) | |
827 | { | |
828 | pud_t *pud = pud_offset(pgd, start); | |
829 | ||
830 | /* | |
831 | * Not on a GB page boundary? | |
832 | */ | |
833 | if (start & (PUD_SIZE - 1)) { | |
834 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
835 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
836 | ||
837 | unmap_pmd_range(pud, start, pre_end); | |
838 | ||
839 | start = pre_end; | |
840 | pud++; | |
841 | } | |
842 | ||
843 | /* | |
844 | * Try to unmap in 1G chunks? | |
845 | */ | |
846 | while (end - start >= PUD_SIZE) { | |
847 | ||
848 | if (pud_large(*pud)) | |
849 | pud_clear(pud); | |
850 | else | |
851 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
852 | ||
853 | start += PUD_SIZE; | |
854 | pud++; | |
855 | } | |
856 | ||
857 | /* | |
858 | * 2M leftovers? | |
859 | */ | |
860 | if (start < end) | |
861 | unmap_pmd_range(pud, start, end); | |
862 | ||
863 | /* | |
864 | * No need to try to free the PUD page because we'll free it in | |
865 | * populate_pgd's error path | |
866 | */ | |
867 | } | |
868 | ||
f900a4b8 BP |
869 | static int alloc_pte_page(pmd_t *pmd) |
870 | { | |
871 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
872 | if (!pte) | |
873 | return -1; | |
874 | ||
875 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
876 | return 0; | |
877 | } | |
878 | ||
4b23538d BP |
879 | static int alloc_pmd_page(pud_t *pud) |
880 | { | |
881 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
882 | if (!pmd) | |
883 | return -1; | |
884 | ||
885 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
886 | return 0; | |
887 | } | |
888 | ||
c6b6f363 BP |
889 | static void populate_pte(struct cpa_data *cpa, |
890 | unsigned long start, unsigned long end, | |
891 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
892 | { | |
893 | pte_t *pte; | |
894 | ||
895 | pte = pte_offset_kernel(pmd, start); | |
896 | ||
39763015 SP |
897 | /* |
898 | * Set the GLOBAL flags only if the PRESENT flag is | |
899 | * set otherwise pte_present will return true even on | |
900 | * a non present pte. The canon_pgprot will clear | |
901 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
902 | * support it. | |
903 | */ | |
904 | if (pgprot_val(pgprot) & _PAGE_PRESENT) | |
905 | pgprot_val(pgprot) |= _PAGE_GLOBAL; | |
906 | else | |
907 | pgprot_val(pgprot) &= ~_PAGE_GLOBAL; | |
c6b6f363 | 908 | |
39763015 | 909 | pgprot = canon_pgprot(pgprot); |
c6b6f363 | 910 | |
c6b6f363 | 911 | while (num_pages-- && start < end) { |
edc3b912 | 912 | set_pte(pte, pfn_pte(cpa->pfn, pgprot)); |
c6b6f363 BP |
913 | |
914 | start += PAGE_SIZE; | |
edc3b912 | 915 | cpa->pfn++; |
c6b6f363 BP |
916 | pte++; |
917 | } | |
918 | } | |
f900a4b8 | 919 | |
e535ec08 MF |
920 | static long populate_pmd(struct cpa_data *cpa, |
921 | unsigned long start, unsigned long end, | |
922 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
f900a4b8 | 923 | { |
e535ec08 | 924 | long cur_pages = 0; |
f900a4b8 | 925 | pmd_t *pmd; |
f5b2831d | 926 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
927 | |
928 | /* | |
929 | * Not on a 2M boundary? | |
930 | */ | |
931 | if (start & (PMD_SIZE - 1)) { | |
932 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
933 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
934 | ||
935 | pre_end = min_t(unsigned long, pre_end, next_page); | |
936 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
937 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
938 | ||
939 | /* | |
940 | * Need a PTE page? | |
941 | */ | |
942 | pmd = pmd_offset(pud, start); | |
943 | if (pmd_none(*pmd)) | |
944 | if (alloc_pte_page(pmd)) | |
945 | return -1; | |
946 | ||
947 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
948 | ||
949 | start = pre_end; | |
950 | } | |
951 | ||
952 | /* | |
953 | * We mapped them all? | |
954 | */ | |
955 | if (num_pages == cur_pages) | |
956 | return cur_pages; | |
957 | ||
f5b2831d JG |
958 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
959 | ||
f900a4b8 BP |
960 | while (end - start >= PMD_SIZE) { |
961 | ||
962 | /* | |
963 | * We cannot use a 1G page so allocate a PMD page if needed. | |
964 | */ | |
965 | if (pud_none(*pud)) | |
966 | if (alloc_pmd_page(pud)) | |
967 | return -1; | |
968 | ||
969 | pmd = pmd_offset(pud, start); | |
970 | ||
edc3b912 | 971 | set_pmd(pmd, __pmd(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 972 | massage_pgprot(pmd_pgprot))); |
f900a4b8 BP |
973 | |
974 | start += PMD_SIZE; | |
edc3b912 | 975 | cpa->pfn += PMD_SIZE >> PAGE_SHIFT; |
f900a4b8 BP |
976 | cur_pages += PMD_SIZE >> PAGE_SHIFT; |
977 | } | |
978 | ||
979 | /* | |
980 | * Map trailing 4K pages. | |
981 | */ | |
982 | if (start < end) { | |
983 | pmd = pmd_offset(pud, start); | |
984 | if (pmd_none(*pmd)) | |
985 | if (alloc_pte_page(pmd)) | |
986 | return -1; | |
987 | ||
988 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
989 | pmd, pgprot); | |
990 | } | |
991 | return num_pages; | |
992 | } | |
4b23538d | 993 | |
e535ec08 MF |
994 | static long populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd, |
995 | pgprot_t pgprot) | |
4b23538d BP |
996 | { |
997 | pud_t *pud; | |
998 | unsigned long end; | |
e535ec08 | 999 | long cur_pages = 0; |
f5b2831d | 1000 | pgprot_t pud_pgprot; |
4b23538d BP |
1001 | |
1002 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1003 | ||
1004 | /* | |
1005 | * Not on a Gb page boundary? => map everything up to it with | |
1006 | * smaller pages. | |
1007 | */ | |
1008 | if (start & (PUD_SIZE - 1)) { | |
1009 | unsigned long pre_end; | |
1010 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1011 | ||
1012 | pre_end = min_t(unsigned long, end, next_page); | |
1013 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1014 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1015 | ||
1016 | pud = pud_offset(pgd, start); | |
1017 | ||
1018 | /* | |
1019 | * Need a PMD page? | |
1020 | */ | |
1021 | if (pud_none(*pud)) | |
1022 | if (alloc_pmd_page(pud)) | |
1023 | return -1; | |
1024 | ||
1025 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1026 | pud, pgprot); | |
1027 | if (cur_pages < 0) | |
1028 | return cur_pages; | |
1029 | ||
1030 | start = pre_end; | |
1031 | } | |
1032 | ||
1033 | /* We mapped them all? */ | |
1034 | if (cpa->numpages == cur_pages) | |
1035 | return cur_pages; | |
1036 | ||
1037 | pud = pud_offset(pgd, start); | |
f5b2831d | 1038 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1039 | |
1040 | /* | |
1041 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1042 | */ | |
b8291adc | 1043 | while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) { |
edc3b912 | 1044 | set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE | |
f5b2831d | 1045 | massage_pgprot(pud_pgprot))); |
4b23538d BP |
1046 | |
1047 | start += PUD_SIZE; | |
edc3b912 | 1048 | cpa->pfn += PUD_SIZE >> PAGE_SHIFT; |
4b23538d BP |
1049 | cur_pages += PUD_SIZE >> PAGE_SHIFT; |
1050 | pud++; | |
1051 | } | |
1052 | ||
1053 | /* Map trailing leftover */ | |
1054 | if (start < end) { | |
e535ec08 | 1055 | long tmp; |
4b23538d BP |
1056 | |
1057 | pud = pud_offset(pgd, start); | |
1058 | if (pud_none(*pud)) | |
1059 | if (alloc_pmd_page(pud)) | |
1060 | return -1; | |
1061 | ||
1062 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1063 | pud, pgprot); | |
1064 | if (tmp < 0) | |
1065 | return cur_pages; | |
1066 | ||
1067 | cur_pages += tmp; | |
1068 | } | |
1069 | return cur_pages; | |
1070 | } | |
f3f72966 BP |
1071 | |
1072 | /* | |
1073 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1074 | * an alternate PGD. | |
1075 | */ | |
1076 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1077 | { | |
1078 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1079 | pud_t *pud = NULL; /* shut up gcc */ |
42a54772 | 1080 | pgd_t *pgd_entry; |
e535ec08 | 1081 | long ret; |
f3f72966 BP |
1082 | |
1083 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1084 | ||
1085 | /* | |
1086 | * Allocate a PUD page and hand it down for mapping. | |
1087 | */ | |
1088 | if (pgd_none(*pgd_entry)) { | |
1089 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
1090 | if (!pud) | |
1091 | return -1; | |
530dd8d4 AL |
1092 | |
1093 | set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE)); | |
f3f72966 BP |
1094 | } |
1095 | ||
1096 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1097 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1098 | ||
1099 | ret = populate_pud(cpa, addr, pgd_entry, pgprot); | |
0bb8aeee | 1100 | if (ret < 0) { |
55920d31 AL |
1101 | /* |
1102 | * Leave the PUD page in place in case some other CPU or thread | |
1103 | * already found it, but remove any useless entries we just | |
1104 | * added to it. | |
1105 | */ | |
360cb4d1 | 1106 | unmap_pud_range(pgd_entry, addr, |
0bb8aeee | 1107 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1108 | return ret; |
0bb8aeee | 1109 | } |
42a54772 | 1110 | |
f3f72966 BP |
1111 | cpa->numpages = ret; |
1112 | return 0; | |
1113 | } | |
1114 | ||
a1e46212 SS |
1115 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1116 | int primary) | |
1117 | { | |
7fc8442f MF |
1118 | if (cpa->pgd) { |
1119 | /* | |
1120 | * Right now, we only execute this code path when mapping | |
1121 | * the EFI virtual memory map regions, no other users | |
1122 | * provide a ->pgd value. This may change in the future. | |
1123 | */ | |
82f0712c | 1124 | return populate_pgd(cpa, vaddr); |
7fc8442f | 1125 | } |
82f0712c | 1126 | |
a1e46212 SS |
1127 | /* |
1128 | * Ignore all non primary paths. | |
1129 | */ | |
405e1133 JB |
1130 | if (!primary) { |
1131 | cpa->numpages = 1; | |
a1e46212 | 1132 | return 0; |
405e1133 | 1133 | } |
a1e46212 SS |
1134 | |
1135 | /* | |
1136 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1137 | * to have holes. | |
1138 | * Also set numpages to '1' indicating that we processed cpa req for | |
1139 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1140 | * on the initial value and the level returned by lookup_address(). | |
1141 | */ | |
1142 | if (within(vaddr, PAGE_OFFSET, | |
1143 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1144 | cpa->numpages = 1; | |
1145 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1146 | return 0; | |
1147 | } else { | |
1148 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1149 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1150 | *cpa->vaddr); | |
1151 | ||
1152 | return -EFAULT; | |
1153 | } | |
1154 | } | |
1155 | ||
c31c7d48 | 1156 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1157 | { |
d75586ad | 1158 | unsigned long address; |
da7bfc50 HH |
1159 | int do_split, err; |
1160 | unsigned int level; | |
c31c7d48 | 1161 | pte_t *kpte, old_pte; |
1da177e4 | 1162 | |
8523acfe TH |
1163 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1164 | struct page *page = cpa->pages[cpa->curpage]; | |
1165 | if (unlikely(PageHighMem(page))) | |
1166 | return 0; | |
1167 | address = (unsigned long)page_address(page); | |
1168 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1169 | address = cpa->vaddr[cpa->curpage]; |
1170 | else | |
1171 | address = *cpa->vaddr; | |
97f99fed | 1172 | repeat: |
82f0712c | 1173 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1174 | if (!kpte) |
a1e46212 | 1175 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1176 | |
1177 | old_pte = *kpte; | |
dcb32d99 | 1178 | if (pte_none(old_pte)) |
a1e46212 | 1179 | return __cpa_process_fault(cpa, address, primary); |
9f4c815c | 1180 | |
30551bb3 | 1181 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1182 | pte_t new_pte; |
626c2c9d | 1183 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1184 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1185 | |
72e458df TG |
1186 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1187 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1188 | |
c31c7d48 | 1189 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 1190 | |
a8aed3e0 AA |
1191 | /* |
1192 | * Set the GLOBAL flags only if the PRESENT flag is | |
1193 | * set otherwise pte_present will return true even on | |
1194 | * a non present pte. The canon_pgprot will clear | |
1195 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
1196 | * support it. | |
1197 | */ | |
1198 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
1199 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
1200 | else | |
1201 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
1202 | ||
626c2c9d AV |
1203 | /* |
1204 | * We need to keep the pfn from the existing PTE, | |
1205 | * after all we're only going to change it's attributes | |
1206 | * not the memory it points to | |
1207 | */ | |
c31c7d48 TG |
1208 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
1209 | cpa->pfn = pfn; | |
f4ae5da0 TG |
1210 | /* |
1211 | * Do we really change anything ? | |
1212 | */ | |
1213 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1214 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1215 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1216 | } |
9b5cf48b | 1217 | cpa->numpages = 1; |
65e074df | 1218 | return 0; |
1da177e4 | 1219 | } |
65e074df TG |
1220 | |
1221 | /* | |
1222 | * Check, whether we can keep the large page intact | |
1223 | * and just change the pte: | |
1224 | */ | |
beaff633 | 1225 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
1226 | /* |
1227 | * When the range fits into the existing large page, | |
9b5cf48b | 1228 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1229 | * try_large_page: |
1230 | */ | |
87f7f8fe IM |
1231 | if (do_split <= 0) |
1232 | return do_split; | |
65e074df TG |
1233 | |
1234 | /* | |
1235 | * We have to split the large page: | |
1236 | */ | |
82f0712c | 1237 | err = split_large_page(cpa, kpte, address); |
87f7f8fe | 1238 | if (!err) { |
ad5ca55f SS |
1239 | /* |
1240 | * Do a global flush tlb after splitting the large page | |
1241 | * and before we do the actual change page attribute in the PTE. | |
1242 | * | |
1243 | * With out this, we violate the TLB application note, that says | |
1244 | * "The TLBs may contain both ordinary and large-page | |
1245 | * translations for a 4-KByte range of linear addresses. This | |
1246 | * may occur if software modifies the paging structures so that | |
1247 | * the page size used for the address range changes. If the two | |
1248 | * translations differ with respect to page frame or attributes | |
1249 | * (e.g., permissions), processor behavior is undefined and may | |
1250 | * be implementation-specific." | |
1251 | * | |
1252 | * We do this global tlb flush inside the cpa_lock, so that we | |
1253 | * don't allow any other cpu, with stale tlb entries change the | |
1254 | * page attribute in parallel, that also falls into the | |
1255 | * just split large page entry. | |
1256 | */ | |
1257 | flush_tlb_all(); | |
87f7f8fe IM |
1258 | goto repeat; |
1259 | } | |
beaff633 | 1260 | |
87f7f8fe | 1261 | return err; |
9f4c815c | 1262 | } |
1da177e4 | 1263 | |
c31c7d48 TG |
1264 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1265 | ||
1266 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1267 | { |
c31c7d48 | 1268 | struct cpa_data alias_cpa; |
992f4c1c | 1269 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1270 | unsigned long vaddr; |
992f4c1c | 1271 | int ret; |
44af6c41 | 1272 | |
8eb5779f | 1273 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1274 | return 0; |
626c2c9d | 1275 | |
f34b439f TG |
1276 | /* |
1277 | * No need to redo, when the primary call touched the direct | |
1278 | * mapping already: | |
1279 | */ | |
8523acfe TH |
1280 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1281 | struct page *page = cpa->pages[cpa->curpage]; | |
1282 | if (unlikely(PageHighMem(page))) | |
1283 | return 0; | |
1284 | vaddr = (unsigned long)page_address(page); | |
1285 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1286 | vaddr = cpa->vaddr[cpa->curpage]; |
1287 | else | |
1288 | vaddr = *cpa->vaddr; | |
1289 | ||
1290 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 1291 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1292 | |
f34b439f | 1293 | alias_cpa = *cpa; |
992f4c1c | 1294 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1295 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 1296 | |
f34b439f | 1297 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1298 | if (ret) |
1299 | return ret; | |
f34b439f | 1300 | } |
44af6c41 | 1301 | |
44af6c41 | 1302 | #ifdef CONFIG_X86_64 |
488fd995 | 1303 | /* |
992f4c1c TH |
1304 | * If the primary call didn't touch the high mapping already |
1305 | * and the physical address is inside the kernel map, we need | |
0879750f | 1306 | * to touch the high mapped kernel as well: |
488fd995 | 1307 | */ |
992f4c1c | 1308 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
4ff53087 TG |
1309 | within_inclusive(cpa->pfn, highmap_start_pfn(), |
1310 | highmap_end_pfn())) { | |
992f4c1c TH |
1311 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + |
1312 | __START_KERNEL_map - phys_base; | |
1313 | alias_cpa = *cpa; | |
1314 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1315 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 1316 | |
992f4c1c TH |
1317 | /* |
1318 | * The high mapping range is imprecise, so ignore the | |
1319 | * return value. | |
1320 | */ | |
1321 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1322 | } | |
488fd995 | 1323 | #endif |
992f4c1c TH |
1324 | |
1325 | return 0; | |
1da177e4 LT |
1326 | } |
1327 | ||
c31c7d48 | 1328 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1329 | { |
e535ec08 MF |
1330 | unsigned long numpages = cpa->numpages; |
1331 | int ret; | |
ff31452b | 1332 | |
65e074df TG |
1333 | while (numpages) { |
1334 | /* | |
1335 | * Store the remaining nr of pages for the large page | |
1336 | * preservation check. | |
1337 | */ | |
9b5cf48b | 1338 | cpa->numpages = numpages; |
d75586ad | 1339 | /* for array changes, we can't use large page */ |
9ae28475 | 1340 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1341 | cpa->numpages = 1; |
c31c7d48 | 1342 | |
288cf3c6 | 1343 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1344 | spin_lock(&cpa_lock); |
c31c7d48 | 1345 | ret = __change_page_attr(cpa, checkalias); |
288cf3c6 | 1346 | if (!debug_pagealloc_enabled()) |
ad5ca55f | 1347 | spin_unlock(&cpa_lock); |
ff31452b TG |
1348 | if (ret) |
1349 | return ret; | |
ff31452b | 1350 | |
c31c7d48 TG |
1351 | if (checkalias) { |
1352 | ret = cpa_process_alias(cpa); | |
1353 | if (ret) | |
1354 | return ret; | |
1355 | } | |
1356 | ||
65e074df TG |
1357 | /* |
1358 | * Adjust the number of pages with the result of the | |
1359 | * CPA operation. Either a large page has been | |
1360 | * preserved or a single page update happened. | |
1361 | */ | |
74256377 | 1362 | BUG_ON(cpa->numpages > numpages || !cpa->numpages); |
9b5cf48b | 1363 | numpages -= cpa->numpages; |
9ae28475 | 1364 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1365 | cpa->curpage++; |
1366 | else | |
1367 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1368 | ||
65e074df | 1369 | } |
ff31452b TG |
1370 | return 0; |
1371 | } | |
1372 | ||
d75586ad | 1373 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1374 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1375 | int force_split, int in_flag, |
1376 | struct page **pages) | |
ff31452b | 1377 | { |
72e458df | 1378 | struct cpa_data cpa; |
cacf8906 | 1379 | int ret, cache, checkalias; |
fa526d0d | 1380 | unsigned long baddr = 0; |
331e4065 | 1381 | |
82f0712c BP |
1382 | memset(&cpa, 0, sizeof(cpa)); |
1383 | ||
331e4065 TG |
1384 | /* |
1385 | * Check, if we are requested to change a not supported | |
1386 | * feature: | |
1387 | */ | |
1388 | mask_set = canon_pgprot(mask_set); | |
1389 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 1390 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1391 | return 0; |
1392 | ||
69b1415e | 1393 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1394 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1395 | int i; |
1396 | for (i = 0; i < numpages; i++) { | |
1397 | if (addr[i] & ~PAGE_MASK) { | |
1398 | addr[i] &= PAGE_MASK; | |
1399 | WARN_ON_ONCE(1); | |
1400 | } | |
1401 | } | |
9ae28475 | 1402 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1403 | /* | |
1404 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1405 | * No need to cehck in that case | |
1406 | */ | |
1407 | if (*addr & ~PAGE_MASK) { | |
1408 | *addr &= PAGE_MASK; | |
1409 | /* | |
1410 | * People should not be passing in unaligned addresses: | |
1411 | */ | |
1412 | WARN_ON_ONCE(1); | |
1413 | } | |
fa526d0d JS |
1414 | /* |
1415 | * Save address for cache flush. *addr is modified in the call | |
1416 | * to __change_page_attr_set_clr() below. | |
1417 | */ | |
1418 | baddr = *addr; | |
69b1415e TG |
1419 | } |
1420 | ||
5843d9a4 NP |
1421 | /* Must avoid aliasing mappings in the highmem code */ |
1422 | kmap_flush_unused(); | |
1423 | ||
db64fe02 NP |
1424 | vm_unmap_aliases(); |
1425 | ||
72e458df | 1426 | cpa.vaddr = addr; |
9ae28475 | 1427 | cpa.pages = pages; |
72e458df TG |
1428 | cpa.numpages = numpages; |
1429 | cpa.mask_set = mask_set; | |
1430 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1431 | cpa.flags = 0; |
1432 | cpa.curpage = 0; | |
c9caa02c | 1433 | cpa.force_split = force_split; |
72e458df | 1434 | |
9ae28475 | 1435 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1436 | cpa.flags |= in_flag; | |
d75586ad | 1437 | |
af96e443 TG |
1438 | /* No alias checking for _NX bit modifications */ |
1439 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1440 | ||
1441 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1442 | |
f4ae5da0 TG |
1443 | /* |
1444 | * Check whether we really changed something: | |
1445 | */ | |
d75586ad | 1446 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1447 | goto out; |
cacf8906 | 1448 | |
6bb8383b AK |
1449 | /* |
1450 | * No need to flush, when we did not set any of the caching | |
1451 | * attributes: | |
1452 | */ | |
c06814d8 | 1453 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1454 | |
57a6a46a | 1455 | /* |
b82ad3d3 BP |
1456 | * On success we use CLFLUSH, when the CPU supports it to |
1457 | * avoid the WBINVD. If the CPU does not support it and in the | |
f026cfa8 | 1458 | * error case we fall back to cpa_flush_all (which uses |
b82ad3d3 | 1459 | * WBINVD): |
57a6a46a | 1460 | */ |
906bf7fd | 1461 | if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) { |
9ae28475 | 1462 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1463 | cpa_flush_array(addr, numpages, cache, | |
1464 | cpa.flags, pages); | |
1465 | } else | |
fa526d0d | 1466 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1467 | } else |
6bb8383b | 1468 | cpa_flush_all(cache); |
cacf8906 | 1469 | |
76ebd054 | 1470 | out: |
ff31452b TG |
1471 | return ret; |
1472 | } | |
1473 | ||
d75586ad SL |
1474 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1475 | pgprot_t mask, int array) | |
75cbade8 | 1476 | { |
d75586ad | 1477 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1478 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1479 | } |
1480 | ||
d75586ad SL |
1481 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1482 | pgprot_t mask, int array) | |
72932c7a | 1483 | { |
d75586ad | 1484 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1485 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1486 | } |
1487 | ||
0f350755 | 1488 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1489 | pgprot_t mask) | |
1490 | { | |
1491 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1492 | CPA_PAGES_ARRAY, pages); | |
1493 | } | |
1494 | ||
1495 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1496 | pgprot_t mask) | |
1497 | { | |
1498 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1499 | CPA_PAGES_ARRAY, pages); | |
1500 | } | |
1501 | ||
1219333d | 1502 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1503 | { |
de33c442 SS |
1504 | /* |
1505 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1506 | * If you really need strong UC use ioremap_uc(), but note |
1507 | * that you cannot override IO areas with set_memory_*() as | |
1508 | * these helpers cannot work with IO memory. | |
de33c442 | 1509 | */ |
d75586ad | 1510 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1511 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1512 | 0); | |
75cbade8 | 1513 | } |
1219333d | 1514 | |
1515 | int set_memory_uc(unsigned long addr, int numpages) | |
1516 | { | |
9fa3ab39 | 1517 | int ret; |
1518 | ||
de33c442 SS |
1519 | /* |
1520 | * for now UC MINUS. see comments in ioremap_nocache() | |
1521 | */ | |
9fa3ab39 | 1522 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1523 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1524 | if (ret) |
1525 | goto out_err; | |
1526 | ||
1527 | ret = _set_memory_uc(addr, numpages); | |
1528 | if (ret) | |
1529 | goto out_free; | |
1530 | ||
1531 | return 0; | |
1219333d | 1532 | |
9fa3ab39 | 1533 | out_free: |
1534 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1535 | out_err: | |
1536 | return ret; | |
1219333d | 1537 | } |
75cbade8 AV |
1538 | EXPORT_SYMBOL(set_memory_uc); |
1539 | ||
2d070eff | 1540 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1541 | enum page_cache_mode new_type) |
d75586ad | 1542 | { |
623dffb2 | 1543 | enum page_cache_mode set_type; |
9fa3ab39 | 1544 | int i, j; |
1545 | int ret; | |
1546 | ||
d75586ad | 1547 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1548 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1549 | new_type, NULL); |
9fa3ab39 | 1550 | if (ret) |
1551 | goto out_free; | |
d75586ad SL |
1552 | } |
1553 | ||
623dffb2 TK |
1554 | /* If WC, set to UC- first and then WC */ |
1555 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1556 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1557 | ||
9fa3ab39 | 1558 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1559 | cachemode2pgprot(set_type), 1); |
4f646254 | 1560 | |
c06814d8 | 1561 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1562 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1563 | cachemode2pgprot( |
1564 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1565 | __pgprot(_PAGE_CACHE_MASK), |
1566 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1567 | if (ret) |
1568 | goto out_free; | |
1569 | ||
1570 | return 0; | |
1571 | ||
1572 | out_free: | |
1573 | for (j = 0; j < i; j++) | |
1574 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1575 | ||
1576 | return ret; | |
d75586ad | 1577 | } |
4f646254 PN |
1578 | |
1579 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1580 | { | |
c06814d8 | 1581 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1582 | } |
d75586ad SL |
1583 | EXPORT_SYMBOL(set_memory_array_uc); |
1584 | ||
4f646254 PN |
1585 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1586 | { | |
c06814d8 | 1587 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1588 | } |
1589 | EXPORT_SYMBOL(set_memory_array_wc); | |
1590 | ||
623dffb2 TK |
1591 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1592 | { | |
1593 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1594 | } | |
1595 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1596 | ||
ef354af4 | 1597 | int _set_memory_wc(unsigned long addr, int numpages) |
1598 | { | |
3869c4aa | 1599 | int ret; |
bdc6340f PV |
1600 | unsigned long addr_copy = addr; |
1601 | ||
3869c4aa | 1602 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1603 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1604 | 0); | |
3869c4aa | 1605 | if (!ret) { |
bdc6340f | 1606 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
c06814d8 JG |
1607 | cachemode2pgprot( |
1608 | _PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1609 | __pgprot(_PAGE_CACHE_MASK), |
1610 | 0, 0, NULL); | |
3869c4aa | 1611 | } |
1612 | return ret; | |
ef354af4 | 1613 | } |
1614 | ||
1615 | int set_memory_wc(unsigned long addr, int numpages) | |
1616 | { | |
9fa3ab39 | 1617 | int ret; |
1618 | ||
9fa3ab39 | 1619 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1620 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1621 | if (ret) |
623dffb2 | 1622 | return ret; |
ef354af4 | 1623 | |
9fa3ab39 | 1624 | ret = _set_memory_wc(addr, numpages); |
1625 | if (ret) | |
623dffb2 | 1626 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1627 | |
9fa3ab39 | 1628 | return ret; |
ef354af4 | 1629 | } |
1630 | EXPORT_SYMBOL(set_memory_wc); | |
1631 | ||
623dffb2 TK |
1632 | int _set_memory_wt(unsigned long addr, int numpages) |
1633 | { | |
1634 | return change_page_attr_set(&addr, numpages, | |
1635 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1636 | } | |
1637 | ||
1638 | int set_memory_wt(unsigned long addr, int numpages) | |
1639 | { | |
1640 | int ret; | |
1641 | ||
1642 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1643 | _PAGE_CACHE_MODE_WT, NULL); | |
1644 | if (ret) | |
1645 | return ret; | |
1646 | ||
1647 | ret = _set_memory_wt(addr, numpages); | |
1648 | if (ret) | |
1649 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1650 | ||
1651 | return ret; | |
1652 | } | |
1653 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1654 | ||
1219333d | 1655 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1656 | { |
c06814d8 | 1657 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1658 | return change_page_attr_clear(&addr, numpages, |
1659 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1660 | } |
1219333d | 1661 | |
1662 | int set_memory_wb(unsigned long addr, int numpages) | |
1663 | { | |
9fa3ab39 | 1664 | int ret; |
1665 | ||
1666 | ret = _set_memory_wb(addr, numpages); | |
1667 | if (ret) | |
1668 | return ret; | |
1669 | ||
c15238df | 1670 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1671 | return 0; |
1219333d | 1672 | } |
75cbade8 AV |
1673 | EXPORT_SYMBOL(set_memory_wb); |
1674 | ||
d75586ad SL |
1675 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1676 | { | |
1677 | int i; | |
a5593e0b | 1678 | int ret; |
1679 | ||
c06814d8 | 1680 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 1681 | ret = change_page_attr_clear(addr, addrinarray, |
1682 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1683 | if (ret) |
1684 | return ret; | |
d75586ad | 1685 | |
9fa3ab39 | 1686 | for (i = 0; i < addrinarray; i++) |
1687 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1688 | |
9fa3ab39 | 1689 | return 0; |
d75586ad SL |
1690 | } |
1691 | EXPORT_SYMBOL(set_memory_array_wb); | |
1692 | ||
75cbade8 AV |
1693 | int set_memory_x(unsigned long addr, int numpages) |
1694 | { | |
583140af PA |
1695 | if (!(__supported_pte_mask & _PAGE_NX)) |
1696 | return 0; | |
1697 | ||
d75586ad | 1698 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1699 | } |
1700 | EXPORT_SYMBOL(set_memory_x); | |
1701 | ||
1702 | int set_memory_nx(unsigned long addr, int numpages) | |
1703 | { | |
583140af PA |
1704 | if (!(__supported_pte_mask & _PAGE_NX)) |
1705 | return 0; | |
1706 | ||
d75586ad | 1707 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1708 | } |
1709 | EXPORT_SYMBOL(set_memory_nx); | |
1710 | ||
1711 | int set_memory_ro(unsigned long addr, int numpages) | |
1712 | { | |
d75586ad | 1713 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1714 | } |
75cbade8 AV |
1715 | |
1716 | int set_memory_rw(unsigned long addr, int numpages) | |
1717 | { | |
d75586ad | 1718 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1719 | } |
f62d0f00 IM |
1720 | |
1721 | int set_memory_np(unsigned long addr, int numpages) | |
1722 | { | |
d75586ad | 1723 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1724 | } |
75cbade8 | 1725 | |
c9caa02c AK |
1726 | int set_memory_4k(unsigned long addr, int numpages) |
1727 | { | |
d75586ad | 1728 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1729 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1730 | } |
1731 | ||
75cbade8 AV |
1732 | int set_pages_uc(struct page *page, int numpages) |
1733 | { | |
1734 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1735 | |
d7c8f21a | 1736 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1737 | } |
1738 | EXPORT_SYMBOL(set_pages_uc); | |
1739 | ||
4f646254 | 1740 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 1741 | enum page_cache_mode new_type) |
0f350755 | 1742 | { |
1743 | unsigned long start; | |
1744 | unsigned long end; | |
623dffb2 | 1745 | enum page_cache_mode set_type; |
0f350755 | 1746 | int i; |
1747 | int free_idx; | |
4f646254 | 1748 | int ret; |
0f350755 | 1749 | |
1750 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1751 | if (PageHighMem(pages[i])) |
1752 | continue; | |
1753 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1754 | end = start + PAGE_SIZE; |
4f646254 | 1755 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1756 | goto err_out; |
1757 | } | |
1758 | ||
623dffb2 TK |
1759 | /* If WC, set to UC- first and then WC */ |
1760 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1761 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1762 | ||
4f646254 | 1763 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 1764 | cachemode2pgprot(set_type)); |
c06814d8 | 1765 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1766 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
1767 | cachemode2pgprot( |
1768 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1769 | __pgprot(_PAGE_CACHE_MASK), |
1770 | 0, CPA_PAGES_ARRAY, pages); | |
1771 | if (ret) | |
1772 | goto err_out; | |
1773 | return 0; /* Success */ | |
0f350755 | 1774 | err_out: |
1775 | free_idx = i; | |
1776 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1777 | if (PageHighMem(pages[i])) |
1778 | continue; | |
1779 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1780 | end = start + PAGE_SIZE; |
1781 | free_memtype(start, end); | |
1782 | } | |
1783 | return -EINVAL; | |
1784 | } | |
4f646254 PN |
1785 | |
1786 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1787 | { | |
c06814d8 | 1788 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1789 | } |
0f350755 | 1790 | EXPORT_SYMBOL(set_pages_array_uc); |
1791 | ||
4f646254 PN |
1792 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1793 | { | |
c06814d8 | 1794 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1795 | } |
1796 | EXPORT_SYMBOL(set_pages_array_wc); | |
1797 | ||
623dffb2 TK |
1798 | int set_pages_array_wt(struct page **pages, int addrinarray) |
1799 | { | |
1800 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
1801 | } | |
1802 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
1803 | ||
75cbade8 AV |
1804 | int set_pages_wb(struct page *page, int numpages) |
1805 | { | |
1806 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1807 | |
d7c8f21a | 1808 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1809 | } |
1810 | EXPORT_SYMBOL(set_pages_wb); | |
1811 | ||
0f350755 | 1812 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1813 | { | |
1814 | int retval; | |
1815 | unsigned long start; | |
1816 | unsigned long end; | |
1817 | int i; | |
1818 | ||
c06814d8 | 1819 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 1820 | retval = cpa_clear_pages_array(pages, addrinarray, |
1821 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1822 | if (retval) |
1823 | return retval; | |
0f350755 | 1824 | |
1825 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1826 | if (PageHighMem(pages[i])) |
1827 | continue; | |
1828 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1829 | end = start + PAGE_SIZE; |
1830 | free_memtype(start, end); | |
1831 | } | |
1832 | ||
9fa3ab39 | 1833 | return 0; |
0f350755 | 1834 | } |
1835 | EXPORT_SYMBOL(set_pages_array_wb); | |
1836 | ||
75cbade8 AV |
1837 | int set_pages_x(struct page *page, int numpages) |
1838 | { | |
1839 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1840 | |
d7c8f21a | 1841 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1842 | } |
1843 | EXPORT_SYMBOL(set_pages_x); | |
1844 | ||
1845 | int set_pages_nx(struct page *page, int numpages) | |
1846 | { | |
1847 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1848 | |
d7c8f21a | 1849 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1850 | } |
1851 | EXPORT_SYMBOL(set_pages_nx); | |
1852 | ||
1853 | int set_pages_ro(struct page *page, int numpages) | |
1854 | { | |
1855 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1856 | |
d7c8f21a | 1857 | return set_memory_ro(addr, numpages); |
75cbade8 | 1858 | } |
75cbade8 AV |
1859 | |
1860 | int set_pages_rw(struct page *page, int numpages) | |
1861 | { | |
1862 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1863 | |
d7c8f21a | 1864 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1865 | } |
1866 | ||
1da177e4 | 1867 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1868 | |
1869 | static int __set_pages_p(struct page *page, int numpages) | |
1870 | { | |
d75586ad SL |
1871 | unsigned long tempaddr = (unsigned long) page_address(page); |
1872 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1873 | .pgd = NULL, |
72e458df TG |
1874 | .numpages = numpages, |
1875 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1876 | .mask_clr = __pgprot(0), |
1877 | .flags = 0}; | |
72932c7a | 1878 | |
55121b43 SS |
1879 | /* |
1880 | * No alias checking needed for setting present flag. otherwise, | |
1881 | * we may need to break large pages for 64-bit kernel text | |
1882 | * mappings (this adds to complexity if we want to do this from | |
1883 | * atomic context especially). Let's keep it simple! | |
1884 | */ | |
1885 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1886 | } |
1887 | ||
1888 | static int __set_pages_np(struct page *page, int numpages) | |
1889 | { | |
d75586ad SL |
1890 | unsigned long tempaddr = (unsigned long) page_address(page); |
1891 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1892 | .pgd = NULL, |
72e458df TG |
1893 | .numpages = numpages, |
1894 | .mask_set = __pgprot(0), | |
d75586ad SL |
1895 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1896 | .flags = 0}; | |
72932c7a | 1897 | |
55121b43 SS |
1898 | /* |
1899 | * No alias checking needed for setting not present flag. otherwise, | |
1900 | * we may need to break large pages for 64-bit kernel text | |
1901 | * mappings (this adds to complexity if we want to do this from | |
1902 | * atomic context especially). Let's keep it simple! | |
1903 | */ | |
1904 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1905 | } |
1906 | ||
031bc574 | 1907 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
1908 | { |
1909 | if (PageHighMem(page)) | |
1910 | return; | |
9f4c815c | 1911 | if (!enable) { |
f9b8404c IM |
1912 | debug_check_no_locks_freed(page_address(page), |
1913 | numpages * PAGE_SIZE); | |
9f4c815c | 1914 | } |
de5097c2 | 1915 | |
9f4c815c | 1916 | /* |
f8d8406b | 1917 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1918 | * Large pages for identity mappings are not used at boot time |
1919 | * and hence no memory allocations during large page split. | |
1da177e4 | 1920 | */ |
f62d0f00 IM |
1921 | if (enable) |
1922 | __set_pages_p(page, numpages); | |
1923 | else | |
1924 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1925 | |
1926 | /* | |
e4b71dcf IM |
1927 | * We should perform an IPI and flush all tlbs, |
1928 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1929 | */ |
1930 | __flush_tlb_all(); | |
26564600 BO |
1931 | |
1932 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1933 | } |
1934 | ||
8a235efa RW |
1935 | #ifdef CONFIG_HIBERNATION |
1936 | ||
1937 | bool kernel_page_present(struct page *page) | |
1938 | { | |
1939 | unsigned int level; | |
1940 | pte_t *pte; | |
1941 | ||
1942 | if (PageHighMem(page)) | |
1943 | return false; | |
1944 | ||
1945 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1946 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1947 | } | |
1948 | ||
1949 | #endif /* CONFIG_HIBERNATION */ | |
1950 | ||
1951 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 1952 | |
82f0712c BP |
1953 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
1954 | unsigned numpages, unsigned long page_flags) | |
1955 | { | |
1956 | int retval = -EINVAL; | |
1957 | ||
1958 | struct cpa_data cpa = { | |
1959 | .vaddr = &address, | |
1960 | .pfn = pfn, | |
1961 | .pgd = pgd, | |
1962 | .numpages = numpages, | |
1963 | .mask_set = __pgprot(0), | |
1964 | .mask_clr = __pgprot(0), | |
1965 | .flags = 0, | |
1966 | }; | |
1967 | ||
1968 | if (!(__supported_pte_mask & _PAGE_NX)) | |
1969 | goto out; | |
1970 | ||
1971 | if (!(page_flags & _PAGE_NX)) | |
1972 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
1973 | ||
15f003d2 SP |
1974 | if (!(page_flags & _PAGE_RW)) |
1975 | cpa.mask_clr = __pgprot(_PAGE_RW); | |
1976 | ||
82f0712c BP |
1977 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); |
1978 | ||
1979 | retval = __change_page_attr_set_clr(&cpa, 0); | |
1980 | __flush_tlb_all(); | |
1981 | ||
1982 | out: | |
1983 | return retval; | |
1984 | } | |
1985 | ||
d1028a15 AV |
1986 | /* |
1987 | * The testcases use internal knowledge of the implementation that shouldn't | |
1988 | * be exposed to the rest of the kernel. Include these directly here. | |
1989 | */ | |
1990 | #ifdef CONFIG_CPA_DEBUG | |
1991 | #include "pageattr-test.c" | |
1992 | #endif |