[mirror_ubuntu-artful-kernel.git] / arch / x86 / oprofile / op_model_amd.c

/*
 * @file op_model_amd.c
 * athlon / K7 / K8 / Family 10h model-specific MSR operations
 *
 * @remark Copyright 2002-2009 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon
 * @author Philippe Elie
 * @author Graydon Hoare
 * @author Robert Richter <robert.richter@amd.com>
 * @author Barry Kasindorf
 */

#include <linux/oprofile.h>
#include <linux/device.h>
#include <linux/pci.h>

#include <asm/ptrace.h>
#include <asm/msr.h>
#include <asm/nmi.h>

#include "op_x86_model.h"
#include "op_counter.h"

#define NUM_COUNTERS 4
#define NUM_CONTROLS 4

#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
#define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))

#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
#define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
#define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
#define CTRL_CLEAR_LO(x) (x &= (1<<21))
#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
#define CTRL_SET_ENABLE(val) (val |= 1<<20)
#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
#define CTRL_SET_UM(val, m) (val |= (m << 8))
#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))

static unsigned long reset_value[NUM_COUNTERS];

#ifdef CONFIG_OPROFILE_IBS

/* IbsFetchCtl bits/masks */
#define IBS_FETCH_HIGH_VALID_BIT	(1UL << 17)	/* bit 49 */
#define IBS_FETCH_HIGH_ENABLE		(1UL << 16)	/* bit 48 */
#define IBS_FETCH_LOW_MAX_CNT_MASK	0x0000FFFFUL	/* MaxCnt mask */

/*IbsOpCtl bits */
#define IBS_OP_LOW_VALID_BIT		(1ULL<<18)	/* bit 18 */
#define IBS_OP_LOW_ENABLE		(1ULL<<17)	/* bit 17 */

/* Codes used in cpu_buffer.c */
/* This produces duplicate code, need to be fixed */
#define IBS_FETCH_BEGIN         (1UL << 4)
#define IBS_OP_BEGIN            (1UL << 5)

/*
 * The function interface needs to be fixed, something like add
 * data. Should then be added to linux/oprofile.h.
 */
extern void
oprofile_add_ibs_sample(struct pt_regs * const regs,
			unsigned int * const ibs_sample, int ibs_code);

struct ibs_fetch_sample {
	/* MSRC001_1031 IBS Fetch Linear Address Register */
	unsigned int ibs_fetch_lin_addr_low;
	unsigned int ibs_fetch_lin_addr_high;
	/* MSRC001_1030 IBS Fetch Control Register */
	unsigned int ibs_fetch_ctl_low;
	unsigned int ibs_fetch_ctl_high;
	/* MSRC001_1032 IBS Fetch Physical Address Register */
	unsigned int ibs_fetch_phys_addr_low;
	unsigned int ibs_fetch_phys_addr_high;
};

struct ibs_op_sample {
	/* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
	unsigned int ibs_op_rip_low;
	unsigned int ibs_op_rip_high;
	/* MSRC001_1035 IBS Op Data Register */
	unsigned int ibs_op_data1_low;
	unsigned int ibs_op_data1_high;
	/* MSRC001_1036 IBS Op Data 2 Register */
	unsigned int ibs_op_data2_low;
	unsigned int ibs_op_data2_high;
	/* MSRC001_1037 IBS Op Data 3 Register */
	unsigned int ibs_op_data3_low;
	unsigned int ibs_op_data3_high;
	/* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
	unsigned int ibs_dc_linear_low;
	unsigned int ibs_dc_linear_high;
	/* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
	unsigned int ibs_dc_phys_low;
	unsigned int ibs_dc_phys_high;
};

static int has_ibs;	/* AMD Family10h and later */

struct op_ibs_config {
	unsigned long op_enabled;
	unsigned long fetch_enabled;
	unsigned long max_cnt_fetch;
	unsigned long max_cnt_op;
	unsigned long rand_en;
	unsigned long dispatched_ops;
};

static struct op_ibs_config ibs_config;

#endif

/* functions for op_amd_spec */

static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
{
	int i;

	for (i = 0; i < NUM_COUNTERS; i++) {
		if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
			msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
		else
			msrs->counters[i].addr = 0;
	}

	for (i = 0; i < NUM_CONTROLS; i++) {
		if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
			msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
		else
			msrs->controls[i].addr = 0;
	}
}


static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;

	/* clear all counters */
	for (i = 0 ; i < NUM_CONTROLS; ++i) {
		if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
			continue;
		CTRL_READ(low, high, msrs, i);
		CTRL_CLEAR_LO(low);
		CTRL_CLEAR_HI(high);
		CTRL_WRITE(low, high, msrs, i);
	}

	/* avoid a false detection of ctr overflows in NMI handler */
	for (i = 0; i < NUM_COUNTERS; ++i) {
		if (unlikely(!CTR_IS_RESERVED(msrs, i)))
			continue;
		CTR_WRITE(1, msrs, i);
	}

	/* enable active counters */
	for (i = 0; i < NUM_COUNTERS; ++i) {
		if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
			reset_value[i] = counter_config[i].count;

			CTR_WRITE(counter_config[i].count, msrs, i);

			CTRL_READ(low, high, msrs, i);
			CTRL_CLEAR_LO(low);
			CTRL_CLEAR_HI(high);
			CTRL_SET_ENABLE(low);
			CTRL_SET_USR(low, counter_config[i].user);
			CTRL_SET_KERN(low, counter_config[i].kernel);
			CTRL_SET_UM(low, counter_config[i].unit_mask);
			CTRL_SET_EVENT_LOW(low, counter_config[i].event);
			CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
			CTRL_SET_HOST_ONLY(high, 0);
			CTRL_SET_GUEST_ONLY(high, 0);

			CTRL_WRITE(low, high, msrs, i);
		} else {
			reset_value[i] = 0;
		}
	}
}

#ifdef CONFIG_OPROFILE_IBS

static inline int
op_amd_handle_ibs(struct pt_regs * const regs,
		  struct op_msrs const * const msrs)
{
	unsigned int low, high;
	struct ibs_fetch_sample ibs_fetch;
	struct ibs_op_sample ibs_op;

	if (!has_ibs)
		return 1;

	if (ibs_config.fetch_enabled) {
		rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
		if (high & IBS_FETCH_HIGH_VALID_BIT) {
			ibs_fetch.ibs_fetch_ctl_high = high;
			ibs_fetch.ibs_fetch_ctl_low = low;
			rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
			ibs_fetch.ibs_fetch_lin_addr_high = high;
			ibs_fetch.ibs_fetch_lin_addr_low = low;
			rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
			ibs_fetch.ibs_fetch_phys_addr_high = high;
			ibs_fetch.ibs_fetch_phys_addr_low = low;

			oprofile_add_ibs_sample(regs,
						(unsigned int *)&ibs_fetch,
						IBS_FETCH_BEGIN);

			/* reenable the IRQ */
			rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
			high &= ~IBS_FETCH_HIGH_VALID_BIT;
			high |= IBS_FETCH_HIGH_ENABLE;
			low &= IBS_FETCH_LOW_MAX_CNT_MASK;
			wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
		}
	}

	if (ibs_config.op_enabled) {
		rdmsr(MSR_AMD64_IBSOPCTL, low, high);
		if (low & IBS_OP_LOW_VALID_BIT) {
			rdmsr(MSR_AMD64_IBSOPRIP, low, high);
			ibs_op.ibs_op_rip_low = low;
			ibs_op.ibs_op_rip_high = high;
			rdmsr(MSR_AMD64_IBSOPDATA, low, high);
			ibs_op.ibs_op_data1_low = low;
			ibs_op.ibs_op_data1_high = high;
			rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
			ibs_op.ibs_op_data2_low = low;
			ibs_op.ibs_op_data2_high = high;
			rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
			ibs_op.ibs_op_data3_low = low;
			ibs_op.ibs_op_data3_high = high;
			rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
			ibs_op.ibs_dc_linear_low = low;
			ibs_op.ibs_dc_linear_high = high;
			rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
			ibs_op.ibs_dc_phys_low = low;
			ibs_op.ibs_dc_phys_high = high;

			/* reenable the IRQ */
			oprofile_add_ibs_sample(regs,
						(unsigned int *)&ibs_op,
						IBS_OP_BEGIN);
			rdmsr(MSR_AMD64_IBSOPCTL, low, high);
			high = 0;
			low &= ~IBS_OP_LOW_VALID_BIT;
			low |= IBS_OP_LOW_ENABLE;
			wrmsr(MSR_AMD64_IBSOPCTL, low, high);
		}
	}

	return 1;
}

#endif

static int op_amd_check_ctrs(struct pt_regs * const regs,
			     struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;

	for (i = 0 ; i < NUM_COUNTERS; ++i) {
		if (!reset_value[i])
			continue;
		CTR_READ(low, high, msrs, i);
		if (CTR_OVERFLOWED(low)) {
			oprofile_add_sample(regs, i);
			CTR_WRITE(reset_value[i], msrs, i);
		}
	}

#ifdef CONFIG_OPROFILE_IBS
	op_amd_handle_ibs(regs, msrs);
#endif

	/* See op_model_ppro.c */
	return 1;
}

static void op_amd_start(struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;
	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
		if (reset_value[i]) {
			CTRL_READ(low, high, msrs, i);
			CTRL_SET_ACTIVE(low);
			CTRL_WRITE(low, high, msrs, i);
		}
	}

#ifdef CONFIG_OPROFILE_IBS
	if (has_ibs && ibs_config.fetch_enabled) {
		low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
		high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
			+ IBS_FETCH_HIGH_ENABLE;
		wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
	}

	if (has_ibs && ibs_config.op_enabled) {
		low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
			+ ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
			+ IBS_OP_LOW_ENABLE;
		high = 0;
		wrmsr(MSR_AMD64_IBSOPCTL, low, high);
	}
#endif
}


static void op_amd_stop(struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;

	/*
	 * Subtle: stop on all counters to avoid race with setting our
	 * pm callback
	 */
	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
		if (!reset_value[i])
			continue;
		CTRL_READ(low, high, msrs, i);
		CTRL_SET_INACTIVE(low);
		CTRL_WRITE(low, high, msrs, i);
	}

#ifdef CONFIG_OPROFILE_IBS
	if (has_ibs && ibs_config.fetch_enabled) {
		/* clear max count and enable */
		low = 0;
		high = 0;
		wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
	}

	if (has_ibs && ibs_config.op_enabled) {
		/* clear max count and enable */
		low = 0;
		high = 0;
		wrmsr(MSR_AMD64_IBSOPCTL, low, high);
	}
#endif
}

static void op_amd_shutdown(struct op_msrs const * const msrs)
{
	int i;

	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
		if (CTR_IS_RESERVED(msrs, i))
			release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
	}
	for (i = 0 ; i < NUM_CONTROLS ; ++i) {
		if (CTRL_IS_RESERVED(msrs, i))
			release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
	}
}

#ifdef CONFIG_OPROFILE_IBS

static u8 ibs_eilvt_off;

static inline void apic_init_ibs_nmi_per_cpu(void *arg)
{
	ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
}

static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
{
	setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
}

static int init_ibs_nmi(void)
{
#define IBSCTL_LVTOFFSETVAL		(1 << 8)
#define IBSCTL				0x1cc
	struct pci_dev *cpu_cfg;
	int nodes;
	u32 value = 0;

	/* per CPU setup */
	on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);

	nodes = 0;
	cpu_cfg = NULL;
	do {
		cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
					 PCI_DEVICE_ID_AMD_10H_NB_MISC,
					 cpu_cfg);
		if (!cpu_cfg)
			break;
		++nodes;
		pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
				       | IBSCTL_LVTOFFSETVAL);
		pci_read_config_dword(cpu_cfg, IBSCTL, &value);
		if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
			pci_dev_put(cpu_cfg);
			printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
				"IBSCTL = 0x%08x", value);
			return 1;
		}
	} while (1);

	if (!nodes) {
		printk(KERN_DEBUG "No CPU node configured for IBS");
		return 1;
	}

#ifdef CONFIG_NUMA
	/* Sanity check */
	/* Works only for 64bit with proper numa implementation. */
	if (nodes != num_possible_nodes()) {
		printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
			"found: %d, expected %d",
			nodes, num_possible_nodes());
		return 1;
	}
#endif
	return 0;
}

/* uninitialize the APIC for the IBS interrupts if needed */
static void clear_ibs_nmi(void)
{
	if (has_ibs)
		on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
}

/* initialize the APIC for the IBS interrupts if available */
static void ibs_init(void)
{
	has_ibs = boot_cpu_has(X86_FEATURE_IBS);

	if (!has_ibs)
		return;

	if (init_ibs_nmi()) {
		has_ibs = 0;
		return;
	}

	printk(KERN_INFO "oprofile: AMD IBS detected\n");
}

static void ibs_exit(void)
{
	if (!has_ibs)
		return;

	clear_ibs_nmi();
}

static int (*create_arch_files)(struct super_block *sb, struct dentry *root);

static int setup_ibs_files(struct super_block *sb, struct dentry *root)
{
	struct dentry *dir;
	int ret = 0;

	/* architecture specific files */
	if (create_arch_files)
		ret = create_arch_files(sb, root);

	if (ret)
		return ret;

	if (!has_ibs)
		return ret;

	/* model specific files */

	/* setup some reasonable defaults */
	ibs_config.max_cnt_fetch = 250000;
	ibs_config.fetch_enabled = 0;
	ibs_config.max_cnt_op = 250000;
	ibs_config.op_enabled = 0;
	ibs_config.dispatched_ops = 1;

	dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
	oprofilefs_create_ulong(sb, dir, "enable",
				&ibs_config.fetch_enabled);
	oprofilefs_create_ulong(sb, dir, "max_count",
				&ibs_config.max_cnt_fetch);
	oprofilefs_create_ulong(sb, dir, "rand_enable",
				&ibs_config.rand_en);

	dir = oprofilefs_mkdir(sb, root, "ibs_op");
	oprofilefs_create_ulong(sb, dir, "enable",
				&ibs_config.op_enabled);
	oprofilefs_create_ulong(sb, dir, "max_count",
				&ibs_config.max_cnt_op);
	oprofilefs_create_ulong(sb, dir, "dispatched_ops",
				&ibs_config.dispatched_ops);

	return 0;
}

static int op_amd_init(struct oprofile_operations *ops)
{
	ibs_init();
	create_arch_files = ops->create_files;
	ops->create_files = setup_ibs_files;
	return 0;
}

static void op_amd_exit(void)
{
	ibs_exit();
}

#else

/* no IBS support */

static int op_amd_init(struct oprofile_operations *ops)
{
	return 0;
}

static void op_amd_exit(void) {}

#endif /* CONFIG_OPROFILE_IBS */

struct op_x86_model_spec const op_amd_spec = {
	.init			= op_amd_init,
	.exit			= op_amd_exit,
	.num_counters		= NUM_COUNTERS,
	.num_controls		= NUM_CONTROLS,
	.fill_in_addresses	= &op_amd_fill_in_addresses,
	.setup_ctrs		= &op_amd_setup_ctrs,
	.check_ctrs		= &op_amd_check_ctrs,
	.start			= &op_amd_start,
	.stop			= &op_amd_stop,
	.shutdown		= &op_amd_shutdown
};
Commit	Line	Data
d4413732	1	/*
6852fd9b	2	* @file op_model_amd.c
bd87f1f0	3	* athlon / K7 / K8 / Family 10h model-specific MSR operations
1da177e4	4	*
ae735e99	5	* @remark Copyright 2002-2009 OProfile authors
1da177e4 LT	6	* @remark Read the file COPYING
	7	*
	8	* @author John Levon
	9	* @author Philippe Elie
	10	* @author Graydon Hoare
adf5ec0b	11	* @author Robert Richter <robert.richter@amd.com>
56784f11	12	* @author Barry Kasindorf
ae735e99	13	*/
1da177e4 LT	14
1da177e4 LT	15	#include <linux/oprofile.h>
56784f11 BK	16	#include <linux/device.h>
	17	#include <linux/pci.h>
	18
1da177e4 LT	19	#include <asm/ptrace.h>
1da177e4 LT	20	#include <asm/msr.h>
3e4ff115	21	#include <asm/nmi.h>
d4413732	22
1da177e4 LT	23	#include "op_x86_model.h"
	24	#include "op_counter.h"
	25
4c168eaf RR	26	#define NUM_COUNTERS 4
4c168eaf RR	27	#define NUM_CONTROLS 4
1da177e4	28
d4413732 PC	29	#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
	30	#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
	31	#define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
1da177e4 LT	32	#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
1da177e4 LT	33
d4413732 PC	34	#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
	35	#define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
	36	#define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
1da177e4 LT	37	#define CTRL_SET_ACTIVE(n) (n \|= (1<<22))
1da177e4 LT	38	#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
bd87f1f0 BK	39	#define CTRL_CLEAR_LO(x) (x &= (1<<21))
bd87f1f0 BK	40	#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
1da177e4	41	#define CTRL_SET_ENABLE(val) (val \|= 1<<20)
d4413732 PC	42	#define CTRL_SET_USR(val, u) (val \|= ((u & 1) << 16))
d4413732 PC	43	#define CTRL_SET_KERN(val, k) (val \|= ((k & 1) << 17))
1da177e4	44	#define CTRL_SET_UM(val, m) (val \|= (m << 8))
bd87f1f0 BK	45	#define CTRL_SET_EVENT_LOW(val, e) (val \|= (e & 0xff))
	46	#define CTRL_SET_EVENT_HIGH(val, e) (val \|= ((e >> 8) & 0xf))
	47	#define CTRL_SET_HOST_ONLY(val, h) (val \|= ((h & 1) << 9))
	48	#define CTRL_SET_GUEST_ONLY(val, h) (val \|= ((h & 1) << 8))
1da177e4	49
852402cc RR	50	static unsigned long reset_value[NUM_COUNTERS];
	51
	52	#ifdef CONFIG_OPROFILE_IBS
	53
87f0bacc RR	54	/* IbsFetchCtl bits/masks */
	55	#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
	56	#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
	57	#define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
56784f11	58
87f0bacc RR	59	/IbsOpCtl bits /
	60	#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
	61	#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
56784f11 BK	62
56784f11 BK	63	/* Codes used in cpu_buffer.c */
87f0bacc	64	/* This produces duplicate code, need to be fixed */
ae735e99 RR	65	#define IBS_FETCH_BEGIN (1UL << 4)
ae735e99 RR	66	#define IBS_OP_BEGIN (1UL << 5)
56784f11	67
fd13f6c8 RR	68	/*
	69	* The function interface needs to be fixed, something like add
	70	* data. Should then be added to linux/oprofile.h.
	71	*/
e2fee276	72	extern void
cdc1834d RR	73	oprofile_add_ibs_sample(struct pt_regs * const regs,
cdc1834d RR	74	unsigned int * const ibs_sample, int ibs_code);
90645700	75
56784f11 BK	76	struct ibs_fetch_sample {
	77	/* MSRC001_1031 IBS Fetch Linear Address Register */
	78	unsigned int ibs_fetch_lin_addr_low;
	79	unsigned int ibs_fetch_lin_addr_high;
	80	/* MSRC001_1030 IBS Fetch Control Register */
	81	unsigned int ibs_fetch_ctl_low;
	82	unsigned int ibs_fetch_ctl_high;
	83	/* MSRC001_1032 IBS Fetch Physical Address Register */
	84	unsigned int ibs_fetch_phys_addr_low;
	85	unsigned int ibs_fetch_phys_addr_high;
	86	};
	87
	88	struct ibs_op_sample {
	89	/* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
	90	unsigned int ibs_op_rip_low;
	91	unsigned int ibs_op_rip_high;
	92	/* MSRC001_1035 IBS Op Data Register */
	93	unsigned int ibs_op_data1_low;
	94	unsigned int ibs_op_data1_high;
	95	/* MSRC001_1036 IBS Op Data 2 Register */
	96	unsigned int ibs_op_data2_low;
	97	unsigned int ibs_op_data2_high;
	98	/* MSRC001_1037 IBS Op Data 3 Register */
	99	unsigned int ibs_op_data3_low;
	100	unsigned int ibs_op_data3_high;
	101	/* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
	102	unsigned int ibs_dc_linear_low;
	103	unsigned int ibs_dc_linear_high;
	104	/* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
	105	unsigned int ibs_dc_phys_low;
	106	unsigned int ibs_dc_phys_high;
	107	};
	108
fc81be8c	109	static int has_ibs; /* AMD Family10h and later */
56784f11 BK	110
	111	struct op_ibs_config {
	112	unsigned long op_enabled;
	113	unsigned long fetch_enabled;
	114	unsigned long max_cnt_fetch;
	115	unsigned long max_cnt_op;
	116	unsigned long rand_en;
	117	unsigned long dispatched_ops;
	118	};
	119
	120	static struct op_ibs_config ibs_config;
d4413732	121
852402cc RR	122	#endif
852402cc RR	123
6657fe4f	124	/* functions for op_amd_spec */
dfa15428	125
6657fe4f	126	static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
1da177e4	127	{
cb9c448c DZ	128	int i;
cb9c448c DZ	129
d4413732	130	for (i = 0; i < NUM_COUNTERS; i++) {
4c168eaf RR	131	if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
4c168eaf RR	132	msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
cb9c448c DZ	133	else
	134	msrs->counters[i].addr = 0;
	135	}
	136
d4413732	137	for (i = 0; i < NUM_CONTROLS; i++) {
4c168eaf RR	138	if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
4c168eaf RR	139	msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
cb9c448c DZ	140	else
	141	msrs->controls[i].addr = 0;
	142	}
1da177e4 LT	143	}
1da177e4 LT	144
d4413732	145
6657fe4f	146	static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
1da177e4 LT	147	{
	148	unsigned int low, high;
	149	int i;
d4413732	150
1da177e4	151	/* clear all counters */
4c168eaf	152	for (i = 0 ; i < NUM_CONTROLS; ++i) {
d4413732	153	if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
cb9c448c	154	continue;
1da177e4	155	CTRL_READ(low, high, msrs, i);
bd87f1f0 BK	156	CTRL_CLEAR_LO(low);
bd87f1f0 BK	157	CTRL_CLEAR_HI(high);
1da177e4 LT	158	CTRL_WRITE(low, high, msrs, i);
1da177e4 LT	159	}
cb9c448c	160
1da177e4	161	/* avoid a false detection of ctr overflows in NMI handler */
4c168eaf	162	for (i = 0; i < NUM_COUNTERS; ++i) {
d4413732	163	if (unlikely(!CTR_IS_RESERVED(msrs, i)))
cb9c448c	164	continue;
1da177e4 LT	165	CTR_WRITE(1, msrs, i);
	166	}
	167
	168	/* enable active counters */
4c168eaf RR	169	for (i = 0; i < NUM_COUNTERS; ++i) {
	170	if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
	171	reset_value[i] = counter_config[i].count;
	172
	173	CTR_WRITE(counter_config[i].count, msrs, i);
1da177e4 LT	174
1da177e4 LT	175	CTRL_READ(low, high, msrs, i);
bd87f1f0 BK	176	CTRL_CLEAR_LO(low);
bd87f1f0 BK	177	CTRL_CLEAR_HI(high);
1da177e4	178	CTRL_SET_ENABLE(low);
4c168eaf RR	179	CTRL_SET_USR(low, counter_config[i].user);
	180	CTRL_SET_KERN(low, counter_config[i].kernel);
	181	CTRL_SET_UM(low, counter_config[i].unit_mask);
	182	CTRL_SET_EVENT_LOW(low, counter_config[i].event);
	183	CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
bd87f1f0 BK	184	CTRL_SET_HOST_ONLY(high, 0);
	185	CTRL_SET_GUEST_ONLY(high, 0);
	186
1da177e4	187	CTRL_WRITE(low, high, msrs, i);
4c168eaf RR	188	} else {
4c168eaf RR	189	reset_value[i] = 0;
1da177e4 LT	190	}
	191	}
	192	}
	193
852402cc RR	194	#ifdef CONFIG_OPROFILE_IBS
852402cc RR	195
7939d2bf RR	196	static inline int
	197	op_amd_handle_ibs(struct pt_regs * const regs,
	198	struct op_msrs const * const msrs)
1da177e4 LT	199	{
1da177e4 LT	200	unsigned int low, high;
56784f11 BK	201	struct ibs_fetch_sample ibs_fetch;
56784f11 BK	202	struct ibs_op_sample ibs_op;
1da177e4	203
fc81be8c	204	if (!has_ibs)
7939d2bf	205	return 1;
1da177e4	206
7939d2bf	207	if (ibs_config.fetch_enabled) {
56784f11	208	rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
87f0bacc	209	if (high & IBS_FETCH_HIGH_VALID_BIT) {
56784f11 BK	210	ibs_fetch.ibs_fetch_ctl_high = high;
	211	ibs_fetch.ibs_fetch_ctl_low = low;
	212	rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
	213	ibs_fetch.ibs_fetch_lin_addr_high = high;
	214	ibs_fetch.ibs_fetch_lin_addr_low = low;
	215	rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
	216	ibs_fetch.ibs_fetch_phys_addr_high = high;
	217	ibs_fetch.ibs_fetch_phys_addr_low = low;
	218
	219	oprofile_add_ibs_sample(regs,
	220	(unsigned int *)&ibs_fetch,
	221	IBS_FETCH_BEGIN);
	222
fd13f6c8	223	/* reenable the IRQ */
56784f11	224	rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
87f0bacc RR	225	high &= ~IBS_FETCH_HIGH_VALID_BIT;
	226	high \|= IBS_FETCH_HIGH_ENABLE;
	227	low &= IBS_FETCH_LOW_MAX_CNT_MASK;
56784f11 BK	228	wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
	229	}
	230	}
	231
7939d2bf	232	if (ibs_config.op_enabled) {
56784f11	233	rdmsr(MSR_AMD64_IBSOPCTL, low, high);
87f0bacc	234	if (low & IBS_OP_LOW_VALID_BIT) {
56784f11 BK	235	rdmsr(MSR_AMD64_IBSOPRIP, low, high);
	236	ibs_op.ibs_op_rip_low = low;
	237	ibs_op.ibs_op_rip_high = high;
	238	rdmsr(MSR_AMD64_IBSOPDATA, low, high);
	239	ibs_op.ibs_op_data1_low = low;
	240	ibs_op.ibs_op_data1_high = high;
	241	rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
	242	ibs_op.ibs_op_data2_low = low;
	243	ibs_op.ibs_op_data2_high = high;
	244	rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
	245	ibs_op.ibs_op_data3_low = low;
	246	ibs_op.ibs_op_data3_high = high;
	247	rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
	248	ibs_op.ibs_dc_linear_low = low;
	249	ibs_op.ibs_dc_linear_high = high;
	250	rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
	251	ibs_op.ibs_dc_phys_low = low;
	252	ibs_op.ibs_dc_phys_high = high;
	253
	254	/* reenable the IRQ */
	255	oprofile_add_ibs_sample(regs,
	256	(unsigned int *)&ibs_op,
	257	IBS_OP_BEGIN);
	258	rdmsr(MSR_AMD64_IBSOPCTL, low, high);
543a157b	259	high = 0;
87f0bacc RR	260	low &= ~IBS_OP_LOW_VALID_BIT;
87f0bacc RR	261	low \|= IBS_OP_LOW_ENABLE;
56784f11 BK	262	wrmsr(MSR_AMD64_IBSOPCTL, low, high);
	263	}
	264	}
	265
1da177e4 LT	266	return 1;
	267	}
	268
852402cc RR	269	#endif
852402cc RR	270
7939d2bf RR	271	static int op_amd_check_ctrs(struct pt_regs * const regs,
	272	struct op_msrs const * const msrs)
	273	{
	274	unsigned int low, high;
	275	int i;
	276
4c168eaf RR	277	for (i = 0 ; i < NUM_COUNTERS; ++i) {
4c168eaf RR	278	if (!reset_value[i])
7939d2bf RR	279	continue;
	280	CTR_READ(low, high, msrs, i);
	281	if (CTR_OVERFLOWED(low)) {
4c168eaf RR	282	oprofile_add_sample(regs, i);
4c168eaf RR	283	CTR_WRITE(reset_value[i], msrs, i);
7939d2bf RR	284	}
	285	}
	286
852402cc	287	#ifdef CONFIG_OPROFILE_IBS
7939d2bf	288	op_amd_handle_ibs(regs, msrs);
852402cc	289	#endif
7939d2bf RR	290
	291	/* See op_model_ppro.c */
	292	return 1;
	293	}
d4413732	294
6657fe4f	295	static void op_amd_start(struct op_msrs const * const msrs)
1da177e4 LT	296	{
	297	unsigned int low, high;
	298	int i;
4c168eaf RR	299	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
4c168eaf RR	300	if (reset_value[i]) {
1da177e4 LT	301	CTRL_READ(low, high, msrs, i);
	302	CTRL_SET_ACTIVE(low);
	303	CTRL_WRITE(low, high, msrs, i);
	304	}
	305	}
852402cc RR	306
852402cc RR	307	#ifdef CONFIG_OPROFILE_IBS
fc81be8c	308	if (has_ibs && ibs_config.fetch_enabled) {
56784f11	309	low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
5f87dfb7 SS	310	high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
5f87dfb7 SS	311	+ IBS_FETCH_HIGH_ENABLE;
56784f11 BK	312	wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
	313	}
	314
fc81be8c	315	if (has_ibs && ibs_config.op_enabled) {
5f87dfb7 SS	316	low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
	317	+ ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
	318	+ IBS_OP_LOW_ENABLE;
56784f11 BK	319	high = 0;
	320	wrmsr(MSR_AMD64_IBSOPCTL, low, high);
	321	}
852402cc	322	#endif
1da177e4 LT	323	}
	324
	325
6657fe4f	326	static void op_amd_stop(struct op_msrs const * const msrs)
1da177e4	327	{
d4413732	328	unsigned int low, high;
1da177e4 LT	329	int i;
1da177e4 LT	330
fd13f6c8 RR	331	/*
	332	* Subtle: stop on all counters to avoid race with setting our
	333	* pm callback
	334	*/
4c168eaf RR	335	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
4c168eaf RR	336	if (!reset_value[i])
cb9c448c	337	continue;
1da177e4 LT	338	CTRL_READ(low, high, msrs, i);
	339	CTRL_SET_INACTIVE(low);
	340	CTRL_WRITE(low, high, msrs, i);
	341	}
56784f11	342
852402cc	343	#ifdef CONFIG_OPROFILE_IBS
fc81be8c	344	if (has_ibs && ibs_config.fetch_enabled) {
fd13f6c8 RR	345	/* clear max count and enable */
fd13f6c8 RR	346	low = 0;
56784f11 BK	347	high = 0;
	348	wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
	349	}
	350
fc81be8c	351	if (has_ibs && ibs_config.op_enabled) {
fd13f6c8 RR	352	/* clear max count and enable */
fd13f6c8 RR	353	low = 0;
56784f11 BK	354	high = 0;
	355	wrmsr(MSR_AMD64_IBSOPCTL, low, high);
	356	}
852402cc	357	#endif
1da177e4 LT	358	}
1da177e4 LT	359
6657fe4f	360	static void op_amd_shutdown(struct op_msrs const * const msrs)
cb9c448c DZ	361	{
	362	int i;
	363
4c168eaf	364	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
d4413732	365	if (CTR_IS_RESERVED(msrs, i))
cb9c448c DZ	366	release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
cb9c448c DZ	367	}
4c168eaf	368	for (i = 0 ; i < NUM_CONTROLS ; ++i) {
d4413732	369	if (CTRL_IS_RESERVED(msrs, i))
cb9c448c DZ	370	release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
	371	}
	372	}
1da177e4	373
9fa6812d	374	#ifdef CONFIG_OPROFILE_IBS
a4c408a4	375
7d77f2dc RR	376	static u8 ibs_eilvt_off;
7d77f2dc RR	377
56784f11 BK	378	static inline void apic_init_ibs_nmi_per_cpu(void *arg)
56784f11 BK	379	{
7d77f2dc	380	ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
56784f11 BK	381	}
	382
	383	static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
	384	{
	385	setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
	386	}
	387
fe615cbf	388	static int init_ibs_nmi(void)
7d77f2dc RR	389	{
	390	#define IBSCTL_LVTOFFSETVAL (1 << 8)
	391	#define IBSCTL 0x1cc
	392	struct pci_dev *cpu_cfg;
	393	int nodes;
	394	u32 value = 0;
	395
	396	/* per CPU setup */
ebb535de	397	on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
7d77f2dc RR	398
	399	nodes = 0;
	400	cpu_cfg = NULL;
	401	do {
	402	cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
	403	PCI_DEVICE_ID_AMD_10H_NB_MISC,
	404	cpu_cfg);
	405	if (!cpu_cfg)
	406	break;
	407	++nodes;
	408	pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
	409	\| IBSCTL_LVTOFFSETVAL);
	410	pci_read_config_dword(cpu_cfg, IBSCTL, &value);
	411	if (value != (ibs_eilvt_off \| IBSCTL_LVTOFFSETVAL)) {
83bd9243	412	pci_dev_put(cpu_cfg);
7d77f2dc RR	413	printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
	414	"IBSCTL = 0x%08x", value);
	415	return 1;
	416	}
	417	} while (1);
	418
	419	if (!nodes) {
	420	printk(KERN_DEBUG "No CPU node configured for IBS");
	421	return 1;
	422	}
	423
	424	#ifdef CONFIG_NUMA
	425	/* Sanity check */
	426	/* Works only for 64bit with proper numa implementation. */
	427	if (nodes != num_possible_nodes()) {
	428	printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
	429	"found: %d, expected %d",
	430	nodes, num_possible_nodes());
	431	return 1;
	432	}
	433	#endif
	434	return 0;
	435	}
	436
fe615cbf RR	437	/* uninitialize the APIC for the IBS interrupts if needed */
	438	static void clear_ibs_nmi(void)
	439	{
fc81be8c	440	if (has_ibs)
fe615cbf RR	441	on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
	442	}
	443
fd13f6c8	444	/* initialize the APIC for the IBS interrupts if available */
fe615cbf	445	static void ibs_init(void)
56784f11	446	{
fc81be8c	447	has_ibs = boot_cpu_has(X86_FEATURE_IBS);
56784f11	448
fc81be8c	449	if (!has_ibs)
56784f11 BK	450	return;
56784f11 BK	451
fe615cbf	452	if (init_ibs_nmi()) {
fc81be8c	453	has_ibs = 0;
852402cc RR	454	return;
	455	}
	456
	457	printk(KERN_INFO "oprofile: AMD IBS detected\n");
56784f11 BK	458	}
56784f11 BK	459
fe615cbf	460	static void ibs_exit(void)
56784f11	461	{
fc81be8c	462	if (!has_ibs)
fe615cbf RR	463	return;
	464
	465	clear_ibs_nmi();
56784f11 BK	466	}
56784f11 BK	467
25ad2913	468	static int (create_arch_files)(struct super_block sb, struct dentry *root);
270d3e1a	469
25ad2913	470	static int setup_ibs_files(struct super_block sb, struct dentry root)
56784f11	471	{
56784f11	472	struct dentry *dir;
270d3e1a RR	473	int ret = 0;
	474
	475	/* architecture specific files */
	476	if (create_arch_files)
	477	ret = create_arch_files(sb, root);
	478
	479	if (ret)
	480	return ret;
56784f11	481
fc81be8c	482	if (!has_ibs)
270d3e1a RR	483	return ret;
	484
	485	/* model specific files */
56784f11 BK	486
	487	/* setup some reasonable defaults */
	488	ibs_config.max_cnt_fetch = 250000;
	489	ibs_config.fetch_enabled = 0;
	490	ibs_config.max_cnt_op = 250000;
	491	ibs_config.op_enabled = 0;
	492	ibs_config.dispatched_ops = 1;
2d55a478 RR	493
2d55a478 RR	494	dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
56784f11	495	oprofilefs_create_ulong(sb, dir, "enable",
2d55a478	496	&ibs_config.fetch_enabled);
56784f11	497	oprofilefs_create_ulong(sb, dir, "max_count",
2d55a478 RR	498	&ibs_config.max_cnt_fetch);
	499	oprofilefs_create_ulong(sb, dir, "rand_enable",
	500	&ibs_config.rand_en);
	501
ccd755c2	502	dir = oprofilefs_mkdir(sb, root, "ibs_op");
56784f11	503	oprofilefs_create_ulong(sb, dir, "enable",
2d55a478	504	&ibs_config.op_enabled);
56784f11	505	oprofilefs_create_ulong(sb, dir, "max_count",
2d55a478	506	&ibs_config.max_cnt_op);
56784f11	507	oprofilefs_create_ulong(sb, dir, "dispatched_ops",
2d55a478	508	&ibs_config.dispatched_ops);
fc2bd734 RR	509
fc2bd734 RR	510	return 0;
56784f11 BK	511	}
56784f11 BK	512
adf5ec0b RR	513	static int op_amd_init(struct oprofile_operations *ops)
adf5ec0b RR	514	{
fe615cbf	515	ibs_init();
270d3e1a RR	516	create_arch_files = ops->create_files;
270d3e1a RR	517	ops->create_files = setup_ibs_files;
adf5ec0b RR	518	return 0;
	519	}
	520
	521	static void op_amd_exit(void)
	522	{
fe615cbf	523	ibs_exit();
adf5ec0b RR	524	}
adf5ec0b RR	525
9fa6812d RR	526	#else
	527
	528	/* no IBS support */
	529
	530	static int op_amd_init(struct oprofile_operations *ops)
	531	{
	532	return 0;
	533	}
	534
	535	static void op_amd_exit(void) {}
	536
	537	#endif /* CONFIG_OPROFILE_IBS */
a4c408a4	538
6657fe4f	539	struct op_x86_model_spec const op_amd_spec = {
c92960fc RR	540	.init = op_amd_init,
	541	.exit = op_amd_exit,
	542	.num_counters = NUM_COUNTERS,
	543	.num_controls = NUM_CONTROLS,
	544	.fill_in_addresses = &op_amd_fill_in_addresses,
	545	.setup_ctrs = &op_amd_setup_ctrs,
	546	.check_ctrs = &op_amd_check_ctrs,
	547	.start = &op_amd_start,
	548	.stop = &op_amd_stop,
	549	.shutdown = &op_amd_shutdown
1da177e4	550	};