[mirror_ubuntu-artful-kernel.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <linux/range.h>

#include <asm/amd_nb.h>
#include <asm/pci_x86.h>

#include <asm/pci-direct.h>

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

#define RANGE_NUM 16

static struct pci_root_info __init *find_pci_root_info(int node, int link)
{
	struct pci_root_info *info;

	/* find the position */
	list_for_each_entry(info, &pci_root_infos, list)
		if (info->node == node && info->link == link)
			return info;

	return NULL;
}

static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node)
{
#ifdef CONFIG_NUMA
	int j;

	for (j = min_bus; j <= max_bus; j++)
		set_mp_bus_to_node(j, node);
#endif
}
/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	u64 start;
	u64 end;
	struct range range[RANGE_NUM];
	u64 val;
	u32 address;
	bool found;
	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	u64 fam10h_mmconf_start;
	u64 fam10h_mmconf_end;

	if (!early_pci_allowed())
		return -1;

	found = false;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = true;
			break;
		}
	}

	if (!found)
		return 0;

	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
		set_mp_bus_range_to_node(min_bus, max_bus, node);
		link = (reg >> 8) & 0x03;

		info = alloc_pci_root_info(min_bus, max_bus, node, link);
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		info = find_pci_root_info(node, link);
		if (!info)
			continue; /* not found */

		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, start, end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	info = find_pci_root_info(def_node, def_link);
	if (info) {
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end - 1,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	end = cap_resource((0xfdULL<<32) - 1);
	end++;
	add_range(range, RANGE_NUM, 0, 0, end);

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
	if (end < (1ULL<<32))
		subtract_range(range, RANGE_NUM, 0, end);

	/* get mmconfig */
	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
	/* need to take out mmconf range */
	if (fam10h_mmconf) {
		printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
		fam10h_mmconf_start = fam10h_mmconf->start;
		fam10h_mmconf_end = fam10h_mmconf->end;
		subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
				 fam10h_mmconf_end + 1);
	} else {
		fam10h_mmconf_start = 0;
		fam10h_mmconf_end = 0;
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		info = find_pci_root_info(node, link);

		if (!info)
			continue;

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, start, end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				subtract_range(range, RANGE_NUM, start,
						 endx + 1);
				printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, cap_resource(start), cap_resource(end),
				 IORESOURCE_MEM, 1);
		subtract_range(range, RANGE_NUM, start, end + 1);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
		subtract_range(range, RANGE_NUM, 1ULL<<32, end);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	info = find_pci_root_info(def_node, def_link);
	if (info) {
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, cap_resource(range[i].start),
				   cap_resource(range[i].end - 1),
				   IORESOURCE_MEM, 1);
		}
	}

	list_for_each_entry(info, &pci_root_infos, list) {
		int busnum;
		struct pci_root_res *root_res;

		busnum = info->busn.start;
		printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
		       &info->busn, info->node, info->link);
		list_for_each_entry(root_res, &info->resources, list)
			printk(KERN_DEBUG "bus: %02x %pR\n",
				       busnum, &root_res->res);
	}

	return 0;
}

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int amd_cpu_notify(struct notifier_block *self, unsigned long action,
			  void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static void __init pci_enable_pci_io_ecs(void)
{
#ifdef CONFIG_AMD_NB
	unsigned int i, n;

	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
		u8 bus = amd_nb_bus_dev_ranges[i].bus;
		u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
		u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;

		for (; slot < limit; ++slot) {
			u32 val = read_pci_config(bus, slot, 3, 0);

			if (!early_is_amd_nb(val))
				continue;

			val = read_pci_config(bus, slot, 3, 0x8c);
			if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
				val |= ENABLE_CF8_EXT_CFG >> 32;
				write_pci_config(bus, slot, 3, 0x8c, val);
			}
			++n;
		}
	}
#endif
}

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	/* Try the PCI method first. */
	if (early_pci_allowed())
		pci_enable_pci_io_ecs();

	register_cpu_notifier(&amd_cpu_notifier);
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
27811d8c YL	5	#include <linux/range.h>
27811d8c YL	6
24d9b70b	7	#include <asm/amd_nb.h>
82487711	8	#include <asm/pci_x86.h>
3a27dd1c	9
871d5f8d	10	#include <asm/pci-direct.h>
1da177e4	11
99935a7a YL	12	#include "bus_numa.h"
99935a7a YL	13
1da177e4 LT	14	/*
1da177e4 LT	15	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	16	* also get peer root bus resource for io,mmio
1da177e4 LT	17	*/
1da177e4 LT	18
30a18d6c YL	19	struct pci_hostbridge_probe {
	20	u32 bus;
	21	u32 slot;
	22	u32 vendor;
	23	u32 device;
	24	};
	25
	26	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	27	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	28	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	29	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	30	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	31	};
	32
27811d8c YL	33	#define RANGE_NUM 16
27811d8c YL	34
d28e5ac2 YL	35	static struct pci_root_info __init *find_pci_root_info(int node, int link)
	36	{
	37	struct pci_root_info *info;
	38
	39	/* find the position */
	40	list_for_each_entry(info, &pci_root_infos, list)
	41	if (info->node == node && info->link == link)
	42	return info;
	43
	44	return NULL;
	45	}
	46
0f1103e4 YL	47	static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node)
	48	{
	49	#ifdef CONFIG_NUMA
	50	int j;
	51
	52	for (j = min_bus; j <= max_bus; j++)
	53	set_mp_bus_to_node(j, node);
	54	#endif
	55	}
1da177e4	56	/**
871d5f8d YL	57	* early_fill_mp_bus_to_node()
871d5f8d YL	58	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	59	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	60	* Registers found in the K8 northbridge
	61	*/
30a18d6c	62	static int __init early_fill_mp_bus_info(void)
1da177e4	63	{
30a18d6c	64	int i;
30a18d6c	65	unsigned bus;
871d5f8d	66	unsigned slot;
35ddd068	67	int node;
30a18d6c YL	68	int link;
	69	int def_node;
	70	int def_link;
	71	struct pci_root_info *info;
	72	u32 reg;
97445c3b YL	73	u64 start;
97445c3b YL	74	u64 end;
27811d8c	75	struct range range[RANGE_NUM];
30a18d6c YL	76	u64 val;
30a18d6c YL	77	u32 address;
3e3da00c	78	bool found;
24d25dbf BH	79	struct resource fam10h_mmconf_res, *fam10h_mmconf;
	80	u64 fam10h_mmconf_start;
	81	u64 fam10h_mmconf_end;
1da177e4	82
871d5f8d YL	83	if (!early_pci_allowed())
	84	return -1;
	85
3e3da00c	86	found = false;
30a18d6c YL	87	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	88	u32 id;
	89	u16 device;
	90	u16 vendor;
35ddd068	91
30a18d6c YL	92	bus = pci_probes[i].bus;
	93	slot = pci_probes[i].slot;
	94	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	95
30a18d6c YL	96	vendor = id & 0xffff;
	97	device = (id>>16) & 0xffff;
	98	if (pci_probes[i].vendor == vendor &&
	99	pci_probes[i].device == device) {
3e3da00c	100	found = true;
30a18d6c YL	101	break;
	102	}
	103	}
	104
3e3da00c	105	if (!found)
30a18d6c	106	return 0;
35ddd068	107
30a18d6c YL	108	for (i = 0; i < 4; i++) {
	109	int min_bus;
	110	int max_bus;
	111	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	112
35ddd068 YL	113	/* Check if that register is enabled for bus range */
30a18d6c	114	if ((reg & 7) != 3)
35ddd068 YL	115	continue;
35ddd068 YL	116
30a18d6c YL	117	min_bus = (reg >> 16) & 0xff;
	118	max_bus = (reg >> 24) & 0xff;
	119	node = (reg >> 4) & 0x07;
0f1103e4	120	set_mp_bus_range_to_node(min_bus, max_bus, node);
30a18d6c YL	121	link = (reg >> 8) & 0x03;
30a18d6c YL	122
d28e5ac2	123	info = alloc_pci_root_info(min_bus, max_bus, node, link);
1da177e4 LT	124	}
1da177e4 LT	125
30a18d6c YL	126	/* get the default node and link for left over res */
	127	reg = read_pci_config(bus, slot, 0, 0x60);
	128	def_node = (reg >> 8) & 0x07;
	129	reg = read_pci_config(bus, slot, 0, 0x64);
	130	def_link = (reg >> 8) & 0x03;
	131
	132	memset(range, 0, sizeof(range));
e9a0064a	133	add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
30a18d6c YL	134	/* io port resource */
	135	for (i = 0; i < 4; i++) {
	136	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	137	if (!(reg & 3))
	138	continue;
	139
	140	start = reg & 0xfff000;
	141	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	142	node = reg & 0x07;
	143	link = (reg >> 4) & 0x03;
	144	end = (reg & 0xfff000) \| 0xfff;
	145
d28e5ac2 YL	146	info = find_pci_root_info(node, link);
d28e5ac2 YL	147	if (!info)
30a18d6c YL	148	continue; /* not found */
30a18d6c YL	149
6e184f29	150	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
97445c3b	151	node, link, start, end);
e8ee6f0a YL	152
	153	/* kernel only handle 16 bit only */
	154	if (end > 0xffff)
	155	end = 0xffff;
	156	update_res(info, start, end, IORESOURCE_IO, 1);
e9a0064a	157	subtract_range(range, RANGE_NUM, start, end + 1);
30a18d6c YL	158	}
	159	/* add left over io port range to def node/link, [0, 0xffff] */
	160	/* find the position */
d28e5ac2 YL	161	info = find_pci_root_info(def_node, def_link);
d28e5ac2 YL	162	if (info) {
30a18d6c YL	163	for (i = 0; i < RANGE_NUM; i++) {
	164	if (!range[i].end)
	165	continue;
	166
e9a0064a	167	update_res(info, range[i].start, range[i].end - 1,
30a18d6c YL	168	IORESOURCE_IO, 1);
	169	}
	170	}
	171
	172	memset(range, 0, sizeof(range));
	173	/* 0xfd00000000-0xffffffffff for HT */
e9a0064a YL	174	end = cap_resource((0xfdULL<<32) - 1);
	175	end++;
	176	add_range(range, RANGE_NUM, 0, 0, end);
30a18d6c YL	177
	178	/* need to take out [0, TOM) for RAM*/
	179	address = MSR_K8_TOP_MEM1;
	180	rdmsrl(address, val);
8004dd96	181	end = (val & 0xffffff800000ULL);
97445c3b	182	printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
30a18d6c	183	if (end < (1ULL<<32))
e9a0064a	184	subtract_range(range, RANGE_NUM, 0, end);
30a18d6c	185
6e184f29	186	/* get mmconfig */
24d25dbf	187	fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
6e184f29	188	/* need to take out mmconf range */
24d25dbf BH	189	if (fam10h_mmconf) {
	190	printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
	191	fam10h_mmconf_start = fam10h_mmconf->start;
	192	fam10h_mmconf_end = fam10h_mmconf->end;
e9a0064a YL	193	subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
e9a0064a YL	194	fam10h_mmconf_end + 1);
24d25dbf BH	195	} else {
	196	fam10h_mmconf_start = 0;
	197	fam10h_mmconf_end = 0;
6e184f29 YL	198	}
6e184f29 YL	199
30a18d6c YL	200	/* mmio resource */
	201	for (i = 0; i < 8; i++) {
	202	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	203	if (!(reg & 3))
	204	continue;
	205
	206	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	207	start <<= 8;
	208	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	209	node = reg & 0x07;
	210	link = (reg >> 4) & 0x03;
	211	end = (reg & 0xffffff00);
	212	end <<= 8;
	213	end \|= 0xffff;
	214
d28e5ac2	215	info = find_pci_root_info(node, link);
30a18d6c	216
d28e5ac2 YL	217	if (!info)
d28e5ac2 YL	218	continue;
6e184f29 YL	219
6e184f29 YL	220	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
97445c3b	221	node, link, start, end);
6e184f29 YL	222	/*
	223	* some sick allocation would have range overlap with fam10h
	224	* mmconf range, so need to update start and end.
	225	*/
	226	if (fam10h_mmconf_end) {
	227	int changed = 0;
	228	u64 endx = 0;
	229	if (start >= fam10h_mmconf_start &&
	230	start <= fam10h_mmconf_end) {
	231	start = fam10h_mmconf_end + 1;
	232	changed = 1;
	233	}
	234
	235	if (end >= fam10h_mmconf_start &&
	236	end <= fam10h_mmconf_end) {
	237	end = fam10h_mmconf_start - 1;
	238	changed = 1;
	239	}
	240
	241	if (start < fam10h_mmconf_start &&
	242	end > fam10h_mmconf_end) {
	243	/* we got a hole */
	244	endx = fam10h_mmconf_start - 1;
	245	update_res(info, start, endx, IORESOURCE_MEM, 0);
e9a0064a YL	246	subtract_range(range, RANGE_NUM, start,
e9a0064a YL	247	endx + 1);
97445c3b	248	printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
6e184f29 YL	249	start = fam10h_mmconf_end + 1;
	250	changed = 1;
	251	}
	252	if (changed) {
	253	if (start <= end) {
97445c3b	254	printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
6e184f29 YL	255	} else {
	256	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	257	continue;
	258	}
	259	}
	260	}
	261
9ad3f2c7 YL	262	update_res(info, cap_resource(start), cap_resource(end),
9ad3f2c7 YL	263	IORESOURCE_MEM, 1);
e9a0064a	264	subtract_range(range, RANGE_NUM, start, end + 1);
6e184f29	265	printk(KERN_CONT "\n");
30a18d6c YL	266	}
	267
	268	/* need to take out [4G, TOM2) for RAM*/
	269	/* SYS_CFG */
	270	address = MSR_K8_SYSCFG;
	271	rdmsrl(address, val);
	272	/* TOP_MEM2 is enabled? */
	273	if (val & (1<<21)) {
	274	/* TOP_MEM2 */
	275	address = MSR_K8_TOP_MEM2;
	276	rdmsrl(address, val);
8004dd96	277	end = (val & 0xffffff800000ULL);
97445c3b	278	printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
e9a0064a	279	subtract_range(range, RANGE_NUM, 1ULL<<32, end);
30a18d6c YL	280	}
	281
	282	/*
	283	* add left over mmio range to def node/link ?
	284	* that is tricky, just record range in from start_min to 4G
	285	*/
d28e5ac2 YL	286	info = find_pci_root_info(def_node, def_link);
d28e5ac2 YL	287	if (info) {
30a18d6c YL	288	for (i = 0; i < RANGE_NUM; i++) {
	289	if (!range[i].end)
	290	continue;
	291
9ad3f2c7	292	update_res(info, cap_resource(range[i].start),
e9a0064a	293	cap_resource(range[i].end - 1),
30a18d6c YL	294	IORESOURCE_MEM, 1);
	295	}
	296	}
	297
d28e5ac2	298	list_for_each_entry(info, &pci_root_infos, list) {
30a18d6c	299	int busnum;
d28e5ac2	300	struct pci_root_res *root_res;
30a18d6c	301
a10bb128 YL	302	busnum = info->busn.start;
	303	printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
	304	&info->busn, info->node, info->link);
d28e5ac2 YL	305	list_for_each_entry(root_res, &info->resources, list)
	306	printk(KERN_DEBUG "bus: %02x %pR\n",
	307	busnum, &root_res->res);
30a18d6c YL	308	}
30a18d6c YL	309
1da177e4 LT	310	return 0;
	311	}
	312
3a27dd1c RR	313	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
3a27dd1c RR	314
148f9bb8	315	static void enable_pci_io_ecs(void *unused)
3a27dd1c RR	316	{
	317	u64 reg;
	318	rdmsrl(MSR_AMD64_NB_CFG, reg);
	319	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	320	reg \|= ENABLE_CF8_EXT_CFG;
	321	wrmsrl(MSR_AMD64_NB_CFG, reg);
	322	}
	323	}
	324
148f9bb8 PG	325	static int amd_cpu_notify(struct notifier_block *self, unsigned long action,
148f9bb8 PG	326	void *hcpu)
3a27dd1c	327	{
91ede005	328	int cpu = (long)hcpu;
ed21763e	329	switch (action) {
91ede005 RR	330	case CPU_ONLINE:
	331	case CPU_ONLINE_FROZEN:
	332	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	333	break;
	334	default:
	335	break;
	336	}
	337	return NOTIFY_OK;
	338	}
	339
148f9bb8	340	static struct notifier_block amd_cpu_notifier = {
91ede005 RR	341	.notifier_call = amd_cpu_notify,
	342	};
	343
24d9b70b JB	344	static void __init pci_enable_pci_io_ecs(void)
	345	{
	346	#ifdef CONFIG_AMD_NB
	347	unsigned int i, n;
	348
	349	for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
	350	u8 bus = amd_nb_bus_dev_ranges[i].bus;
	351	u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
	352	u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
	353
	354	for (; slot < limit; ++slot) {
	355	u32 val = read_pci_config(bus, slot, 3, 0);
	356
	357	if (!early_is_amd_nb(val))
	358	continue;
	359
	360	val = read_pci_config(bus, slot, 3, 0x8c);
	361	if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
	362	val \|= ENABLE_CF8_EXT_CFG >> 32;
	363	write_pci_config(bus, slot, 3, 0x8c, val);
	364	}
	365	++n;
	366	}
	367	}
24d9b70b JB	368	#endif
	369	}
	370
91ede005 RR	371	static int __init pci_io_ecs_init(void)
	372	{
	373	int cpu;
	374
3a27dd1c RR	375	/* assume all cpus from fam10h have IO ECS */
	376	if (boot_cpu_data.x86 < 0x10)
	377	return 0;
91ede005	378
24d9b70b JB	379	/* Try the PCI method first. */
	380	if (early_pci_allowed())
	381	pci_enable_pci_io_ecs();
	382
91ede005 RR	383	register_cpu_notifier(&amd_cpu_notifier);
	384	for_each_online_cpu(cpu)
	385	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	386	(void *)(long)cpu);
3a27dd1c	387	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	388
3a27dd1c RR	389	return 0;
	390	}
	391
9b4e27b5 RR	392	static int __init amd_postcore_init(void)
	393	{
	394	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	395	return 0;
	396
	397	early_fill_mp_bus_info();
91ede005	398	pci_io_ecs_init();
9b4e27b5 RR	399
	400	return 0;
	401	}
	402
	403	postcore_initcall(amd_postcore_init);