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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * Exceptions for specific devices. Usually work-arounds for fatal design flaws. | |
4 | */ | |
5 | ||
f8977d0a JB |
6 | #include <linux/delay.h> |
7 | #include <linux/dmi.h> | |
1da177e4 | 8 | #include <linux/pci.h> |
db2e034d | 9 | #include <linux/vgaarb.h> |
44c8bdbe | 10 | #include <asm/hpet.h> |
82487711 | 11 | #include <asm/pci_x86.h> |
1da177e4 | 12 | |
a18e3690 | 13 | static void pci_fixup_i450nx(struct pci_dev *d) |
1da177e4 LT |
14 | { |
15 | /* | |
16 | * i450NX -- Find and scan all secondary buses on all PXB's. | |
17 | */ | |
18 | int pxb, reg; | |
19 | u8 busno, suba, subb; | |
20 | ||
9ed88554 | 21 | dev_warn(&d->dev, "Searching for i450NX host bridges\n"); |
1da177e4 | 22 | reg = 0xd0; |
938f6671 | 23 | for(pxb = 0; pxb < 2; pxb++) { |
1da177e4 LT |
24 | pci_read_config_byte(d, reg++, &busno); |
25 | pci_read_config_byte(d, reg++, &suba); | |
26 | pci_read_config_byte(d, reg++, &subb); | |
12c0b20f BH |
27 | dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, |
28 | suba, subb); | |
1da177e4 | 29 | if (busno) |
8d7d8186 | 30 | pcibios_scan_root(busno); /* Bus A */ |
1da177e4 | 31 | if (suba < subb) |
8d7d8186 | 32 | pcibios_scan_root(suba+1); /* Bus B */ |
1da177e4 LT |
33 | } |
34 | pcibios_last_bus = -1; | |
35 | } | |
36 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); | |
37 | ||
a18e3690 | 38 | static void pci_fixup_i450gx(struct pci_dev *d) |
1da177e4 LT |
39 | { |
40 | /* | |
41 | * i450GX and i450KX -- Find and scan all secondary buses. | |
42 | * (called separately for each PCI bridge found) | |
43 | */ | |
44 | u8 busno; | |
45 | pci_read_config_byte(d, 0x4a, &busno); | |
9ed88554 | 46 | dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); |
8d7d8186 | 47 | pcibios_scan_root(busno); |
1da177e4 LT |
48 | pcibios_last_bus = -1; |
49 | } | |
50 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); | |
51 | ||
a18e3690 | 52 | static void pci_fixup_umc_ide(struct pci_dev *d) |
1da177e4 LT |
53 | { |
54 | /* | |
55 | * UM8886BF IDE controller sets region type bits incorrectly, | |
56 | * therefore they look like memory despite of them being I/O. | |
57 | */ | |
58 | int i; | |
59 | ||
9ed88554 | 60 | dev_warn(&d->dev, "Fixing base address flags\n"); |
938f6671 | 61 | for(i = 0; i < 4; i++) |
1da177e4 LT |
62 | d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; |
63 | } | |
64 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); | |
65 | ||
a18e3690 | 66 | static void pci_fixup_latency(struct pci_dev *d) |
1da177e4 LT |
67 | { |
68 | /* | |
69 | * SiS 5597 and 5598 chipsets require latency timer set to | |
70 | * at most 32 to avoid lockups. | |
71 | */ | |
9ed88554 | 72 | dev_dbg(&d->dev, "Setting max latency to 32\n"); |
1da177e4 LT |
73 | pcibios_max_latency = 32; |
74 | } | |
75 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); | |
76 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); | |
77 | ||
a18e3690 | 78 | static void pci_fixup_piix4_acpi(struct pci_dev *d) |
1da177e4 LT |
79 | { |
80 | /* | |
81 | * PIIX4 ACPI device: hardwired IRQ9 | |
82 | */ | |
83 | d->irq = 9; | |
84 | } | |
85 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); | |
86 | ||
87 | /* | |
88 | * Addresses issues with problems in the memory write queue timer in | |
89 | * certain VIA Northbridges. This bugfix is per VIA's specifications, | |
90 | * except for the KL133/KM133: clearing bit 5 on those Northbridges seems | |
91 | * to trigger a bug in its integrated ProSavage video card, which | |
92 | * causes screen corruption. We only clear bits 6 and 7 for that chipset, | |
93 | * until VIA can provide us with definitive information on why screen | |
94 | * corruption occurs, and what exactly those bits do. | |
95 | * | |
96 | * VIA 8363,8622,8361 Northbridges: | |
97 | * - bits 5, 6, 7 at offset 0x55 need to be turned off | |
98 | * VIA 8367 (KT266x) Northbridges: | |
99 | * - bits 5, 6, 7 at offset 0x95 need to be turned off | |
100 | * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: | |
101 | * - bits 6, 7 at offset 0x55 need to be turned off | |
102 | */ | |
103 | ||
104 | #define VIA_8363_KL133_REVISION_ID 0x81 | |
105 | #define VIA_8363_KM133_REVISION_ID 0x84 | |
106 | ||
1597cacb | 107 | static void pci_fixup_via_northbridge_bug(struct pci_dev *d) |
1da177e4 LT |
108 | { |
109 | u8 v; | |
1da177e4 LT |
110 | int where = 0x55; |
111 | int mask = 0x1f; /* clear bits 5, 6, 7 by default */ | |
112 | ||
1da177e4 LT |
113 | if (d->device == PCI_DEVICE_ID_VIA_8367_0) { |
114 | /* fix pci bus latency issues resulted by NB bios error | |
115 | it appears on bug free^Wreduced kt266x's bios forces | |
116 | NB latency to zero */ | |
117 | pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); | |
118 | ||
938f6671 | 119 | where = 0x95; /* the memory write queue timer register is |
1da177e4 LT |
120 | different for the KT266x's: 0x95 not 0x55 */ |
121 | } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && | |
44c10138 AK |
122 | (d->revision == VIA_8363_KL133_REVISION_ID || |
123 | d->revision == VIA_8363_KM133_REVISION_ID)) { | |
1da177e4 LT |
124 | mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 |
125 | causes screen corruption on the KL133/KM133 */ | |
126 | } | |
127 | ||
128 | pci_read_config_byte(d, where, &v); | |
129 | if (v & ~mask) { | |
9ed88554 | 130 | dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ |
44c10138 | 131 | d->device, d->revision, where, v, mask, v & mask); |
1da177e4 LT |
132 | v &= mask; |
133 | pci_write_config_byte(d, where, v); | |
134 | } | |
135 | } | |
136 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); | |
137 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); | |
138 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); | |
139 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); | |
1597cacb AC |
140 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); |
141 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); | |
142 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); | |
143 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); | |
1da177e4 LT |
144 | |
145 | /* | |
146 | * For some reasons Intel decided that certain parts of their | |
147 | * 815, 845 and some other chipsets must look like PCI-to-PCI bridges | |
148 | * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, | |
149 | * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according | |
150 | * to Intel terminology. These devices do forward all addresses from | |
151 | * system to PCI bus no matter what are their window settings, so they are | |
152 | * "transparent" (or subtractive decoding) from programmers point of view. | |
153 | */ | |
a18e3690 | 154 | static void pci_fixup_transparent_bridge(struct pci_dev *dev) |
1da177e4 | 155 | { |
4082cf2d | 156 | if ((dev->device & 0xff00) == 0x2400) |
1da177e4 LT |
157 | dev->transparent = 1; |
158 | } | |
4082cf2d YL |
159 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
160 | PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge); | |
1da177e4 LT |
161 | |
162 | /* | |
163 | * Fixup for C1 Halt Disconnect problem on nForce2 systems. | |
164 | * | |
165 | * From information provided by "Allen Martin" <AMartin@nvidia.com>: | |
166 | * | |
167 | * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle | |
168 | * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. | |
169 | * This allows the state-machine and timer to return to a proper state within | |
170 | * 80 ns of the CONNECT and probe appearing together. Since the CPU will not | |
171 | * issue another HALT within 80 ns of the initial HALT, the failure condition | |
172 | * is avoided. | |
173 | */ | |
1597cacb | 174 | static void pci_fixup_nforce2(struct pci_dev *dev) |
1da177e4 LT |
175 | { |
176 | u32 val; | |
177 | ||
178 | /* | |
179 | * Chip Old value New value | |
180 | * C17 0x1F0FFF01 0x1F01FF01 | |
181 | * C18D 0x9F0FFF01 0x9F01FF01 | |
182 | * | |
183 | * Northbridge chip version may be determined by | |
184 | * reading the PCI revision ID (0xC1 or greater is C18D). | |
185 | */ | |
186 | pci_read_config_dword(dev, 0x6c, &val); | |
187 | ||
188 | /* | |
189 | * Apply fixup if needed, but don't touch disconnect state | |
190 | */ | |
191 | if ((val & 0x00FF0000) != 0x00010000) { | |
9ed88554 | 192 | dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); |
1da177e4 LT |
193 | pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); |
194 | } | |
195 | } | |
196 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); | |
1597cacb | 197 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); |
1da177e4 LT |
198 | |
199 | /* Max PCI Express root ports */ | |
200 | #define MAX_PCIEROOT 6 | |
201 | static int quirk_aspm_offset[MAX_PCIEROOT << 3]; | |
202 | ||
ff0d2f90 | 203 | #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7)) |
1da177e4 LT |
204 | |
205 | static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | |
206 | { | |
b6ce068a MW |
207 | return raw_pci_read(pci_domain_nr(bus), bus->number, |
208 | devfn, where, size, value); | |
1da177e4 LT |
209 | } |
210 | ||
211 | /* | |
212 | * Replace the original pci bus ops for write with a new one that will filter | |
213 | * the request to insure ASPM cannot be enabled. | |
214 | */ | |
215 | static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | |
216 | { | |
217 | u8 offset; | |
218 | ||
219 | offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; | |
220 | ||
221 | if ((offset) && (where == offset)) | |
f8a26fe6 | 222 | value = value & ~PCI_EXP_LNKCTL_ASPMC; |
938f6671 | 223 | |
b6ce068a MW |
224 | return raw_pci_write(pci_domain_nr(bus), bus->number, |
225 | devfn, where, size, value); | |
1da177e4 LT |
226 | } |
227 | ||
228 | static struct pci_ops quirk_pcie_aspm_ops = { | |
229 | .read = quirk_pcie_aspm_read, | |
230 | .write = quirk_pcie_aspm_write, | |
231 | }; | |
232 | ||
233 | /* | |
234 | * Prevents PCI Express ASPM (Active State Power Management) being enabled. | |
235 | * | |
236 | * Save the register offset, where the ASPM control bits are located, | |
237 | * for each PCI Express device that is in the device list of | |
238 | * the root port in an array for fast indexing. Replace the bus ops | |
239 | * with the modified one. | |
240 | */ | |
241 | static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) | |
242 | { | |
f8a26fe6 | 243 | int i; |
1da177e4 LT |
244 | struct pci_bus *pbus; |
245 | struct pci_dev *dev; | |
246 | ||
247 | if ((pbus = pdev->subordinate) == NULL) | |
248 | return; | |
249 | ||
250 | /* | |
251 | * Check if the DID of pdev matches one of the six root ports. This | |
252 | * check is needed in the case this function is called directly by the | |
253 | * hot-plug driver. | |
254 | */ | |
255 | if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) || | |
256 | (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) | |
257 | return; | |
258 | ||
259 | if (list_empty(&pbus->devices)) { | |
260 | /* | |
261 | * If no device is attached to the root port at power-up or | |
262 | * after hot-remove, the pbus->devices is empty and this code | |
263 | * will set the offsets to zero and the bus ops to parent's bus | |
264 | * ops, which is unmodified. | |
938f6671 PC |
265 | */ |
266 | for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) | |
1da177e4 LT |
267 | quirk_aspm_offset[i] = 0; |
268 | ||
f8a26fe6 | 269 | pci_bus_set_ops(pbus, pbus->parent->ops); |
1da177e4 LT |
270 | } else { |
271 | /* | |
272 | * If devices are attached to the root port at power-up or | |
273 | * after hot-add, the code loops through the device list of | |
274 | * each root port to save the register offsets and replace the | |
275 | * bus ops. | |
276 | */ | |
f8a26fe6 | 277 | list_for_each_entry(dev, &pbus->devices, bus_list) |
1da177e4 | 278 | /* There are 0 to 8 devices attached to this bus */ |
f8a26fe6 YW |
279 | quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = |
280 | dev->pcie_cap + PCI_EXP_LNKCTL; | |
281 | ||
282 | pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops); | |
283 | dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n"); | |
1da177e4 | 284 | } |
f8a26fe6 | 285 | |
1da177e4 | 286 | } |
938f6671 PC |
287 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); |
288 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); | |
289 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk); | |
290 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk); | |
291 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk); | |
292 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk); | |
1da177e4 | 293 | |
6b5c76b8 EO |
294 | /* |
295 | * Fixup to mark boot BIOS video selected by BIOS before it changes | |
296 | * | |
297 | * From information provided by "Jon Smirl" <jonsmirl@gmail.com> | |
298 | * | |
299 | * The standard boot ROM sequence for an x86 machine uses the BIOS | |
300 | * to select an initial video card for boot display. This boot video | |
0c0e0736 | 301 | * card will have its BIOS copied to 0xC0000 in system RAM. |
6b5c76b8 EO |
302 | * IORESOURCE_ROM_SHADOW is used to associate the boot video |
303 | * card with this copy. On laptops this copy has to be used since | |
304 | * the main ROM may be compressed or combined with another image. | |
d8801e4d SE |
305 | * See pci_map_rom() for use of this flag. Before marking the device |
306 | * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set | |
0c0e0736 BH |
307 | * by either arch code or vga-arbitration; if so only apply the fixup to this |
308 | * already-determined primary video card. | |
6b5c76b8 EO |
309 | */ |
310 | ||
a18e3690 | 311 | static void pci_fixup_video(struct pci_dev *pdev) |
6b5c76b8 EO |
312 | { |
313 | struct pci_dev *bridge; | |
314 | struct pci_bus *bus; | |
315 | u16 config; | |
0c0e0736 | 316 | struct resource *res; |
6b5c76b8 | 317 | |
6b5c76b8 EO |
318 | /* Is VGA routed to us? */ |
319 | bus = pdev->bus; | |
320 | while (bus) { | |
321 | bridge = bus->self; | |
322 | ||
323 | /* | |
324 | * From information provided by | |
325 | * "David Miller" <davem@davemloft.net> | |
326 | * The bridge control register is valid for PCI header | |
327 | * type BRIDGE, or CARDBUS. Host to PCI controllers use | |
328 | * PCI header type NORMAL. | |
329 | */ | |
56a41f99 | 330 | if (bridge && (pci_is_bridge(bridge))) { |
6b5c76b8 EO |
331 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, |
332 | &config); | |
333 | if (!(config & PCI_BRIDGE_CTL_VGA)) | |
334 | return; | |
335 | } | |
336 | bus = bus->parent; | |
337 | } | |
d8801e4d SE |
338 | if (!vga_default_device() || pdev == vga_default_device()) { |
339 | pci_read_config_word(pdev, PCI_COMMAND, &config); | |
340 | if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | |
0c0e0736 BH |
341 | res = &pdev->resource[PCI_ROM_RESOURCE]; |
342 | ||
343 | pci_disable_rom(pdev); | |
344 | if (res->parent) | |
345 | release_resource(res); | |
346 | ||
347 | res->start = 0xC0000; | |
348 | res->end = res->start + 0x20000 - 1; | |
349 | res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW | | |
350 | IORESOURCE_PCI_FIXED; | |
351 | dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n", | |
352 | res); | |
d8801e4d | 353 | } |
6b5c76b8 EO |
354 | } |
355 | } | |
73e3b590 YL |
356 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
357 | PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video); | |
6b5c76b8 | 358 | |
346ca04d | 359 | |
a18e3690 | 360 | static const struct dmi_system_id msi_k8t_dmi_table[] = { |
346ca04d JG |
361 | { |
362 | .ident = "MSI-K8T-Neo2Fir", | |
363 | .matches = { | |
364 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
365 | DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"), | |
366 | }, | |
367 | }, | |
368 | {} | |
369 | }; | |
370 | ||
371 | /* | |
372 | * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound | |
373 | * card if a PCI-soundcard is added. | |
374 | * | |
375 | * The BIOS only gives options "DISABLED" and "AUTO". This code sets | |
376 | * the corresponding register-value to enable the soundcard. | |
377 | * | |
378 | * The soundcard is only enabled, if the mainborad is identified | |
379 | * via DMI-tables and the soundcard is detected to be off. | |
380 | */ | |
a18e3690 | 381 | static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) |
346ca04d JG |
382 | { |
383 | unsigned char val; | |
384 | if (!dmi_check_system(msi_k8t_dmi_table)) | |
385 | return; /* only applies to MSI K8T Neo2-FIR */ | |
386 | ||
387 | pci_read_config_byte(dev, 0x50, &val); | |
388 | if (val & 0x40) { | |
389 | pci_write_config_byte(dev, 0x50, val & (~0x40)); | |
390 | ||
391 | /* verify the change for status output */ | |
392 | pci_read_config_byte(dev, 0x50, &val); | |
393 | if (val & 0x40) | |
9ed88554 | 394 | dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
346ca04d JG |
395 | "can't enable onboard soundcard!\n"); |
396 | else | |
9ed88554 | 397 | dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
398 | "enabled onboard soundcard\n"); | |
346ca04d JG |
399 | } |
400 | } | |
401 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, | |
402 | pci_fixup_msi_k8t_onboard_sound); | |
403 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, | |
404 | pci_fixup_msi_k8t_onboard_sound); | |
405 | ||
f8977d0a JB |
406 | /* |
407 | * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. | |
408 | * | |
409 | * We pretend to bring them out of full D3 state, and restore the proper | |
410 | * IRQ, PCI cache line size, and BARs, otherwise the device won't function | |
411 | * properly. In some cases, the device will generate an interrupt on | |
4b3f686d | 412 | * the wrong IRQ line, causing any devices sharing the line it's |
f8977d0a JB |
413 | * *supposed* to use to be disabled by the kernel's IRQ debug code. |
414 | */ | |
415 | static u16 toshiba_line_size; | |
416 | ||
a18e3690 | 417 | static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = { |
f8977d0a JB |
418 | { |
419 | .ident = "Toshiba PS5 based laptop", | |
420 | .matches = { | |
421 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
422 | DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"), | |
423 | }, | |
424 | }, | |
425 | { | |
426 | .ident = "Toshiba PSM4 based laptop", | |
427 | .matches = { | |
428 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
429 | DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"), | |
430 | }, | |
431 | }, | |
19272684 JB |
432 | { |
433 | .ident = "Toshiba A40 based laptop", | |
434 | .matches = { | |
435 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
436 | DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"), | |
437 | }, | |
438 | }, | |
f8977d0a JB |
439 | { } |
440 | }; | |
441 | ||
a18e3690 | 442 | static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) |
f8977d0a JB |
443 | { |
444 | if (!dmi_check_system(toshiba_ohci1394_dmi_table)) | |
445 | return; /* only applies to certain Toshibas (so far) */ | |
446 | ||
447 | dev->current_state = PCI_D3cold; | |
448 | pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size); | |
449 | } | |
450 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, | |
451 | pci_pre_fixup_toshiba_ohci1394); | |
452 | ||
a18e3690 | 453 | static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) |
f8977d0a JB |
454 | { |
455 | if (!dmi_check_system(toshiba_ohci1394_dmi_table)) | |
456 | return; /* only applies to certain Toshibas (so far) */ | |
457 | ||
458 | /* Restore config space on Toshiba laptops */ | |
f8977d0a | 459 | pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); |
6e6ece5d | 460 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq); |
f8977d0a JB |
461 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, |
462 | pci_resource_start(dev, 0)); | |
463 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, | |
464 | pci_resource_start(dev, 1)); | |
465 | } | |
466 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, | |
467 | pci_post_fixup_toshiba_ohci1394); | |
a80da738 DV |
468 | |
469 | ||
470 | /* | |
471 | * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device | |
472 | * configuration space. | |
473 | */ | |
1597cacb | 474 | static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) |
a80da738 DV |
475 | { |
476 | u8 r; | |
477 | /* clear 'F4 Video Configuration Trap' bit */ | |
478 | pci_read_config_byte(dev, 0x42, &r); | |
479 | r &= 0xfd; | |
480 | pci_write_config_byte(dev, 0x42, r); | |
481 | } | |
482 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, | |
483 | pci_early_fixup_cyrix_5530); | |
1597cacb AC |
484 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, |
485 | pci_early_fixup_cyrix_5530); | |
73a74ed3 IK |
486 | |
487 | /* | |
488 | * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: | |
489 | * prevent update of the BAR0, which doesn't look like a normal BAR. | |
490 | */ | |
a18e3690 | 491 | static void pci_siemens_interrupt_controller(struct pci_dev *dev) |
73a74ed3 IK |
492 | { |
493 | dev->resource[0].flags |= IORESOURCE_PCI_FIXED; | |
494 | } | |
495 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, | |
496 | pci_siemens_interrupt_controller); | |
57741a77 | 497 | |
d7451fca JC |
498 | /* |
499 | * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from | |
500 | * confusing the PCI engine: | |
501 | */ | |
502 | static void sb600_disable_hpet_bar(struct pci_dev *dev) | |
503 | { | |
504 | u8 val; | |
505 | ||
506 | /* | |
507 | * The SB600 and SB700 both share the same device | |
508 | * ID, but the PM register 0x55 does something different | |
509 | * for the SB700, so make sure we are dealing with the | |
510 | * SB600 before touching the bit: | |
511 | */ | |
512 | ||
513 | pci_read_config_byte(dev, 0x08, &val); | |
514 | ||
515 | if (val < 0x2F) { | |
516 | outb(0x55, 0xCD6); | |
517 | val = inb(0xCD7); | |
518 | ||
519 | /* Set bit 7 in PM register 0x55 */ | |
520 | outb(0x55, 0xCD6); | |
521 | outb(val | 0x80, 0xCD7); | |
522 | } | |
523 | } | |
524 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); | |
80b3e557 | 525 | |
44c8bdbe BH |
526 | #ifdef CONFIG_HPET_TIMER |
527 | static void sb600_hpet_quirk(struct pci_dev *dev) | |
528 | { | |
529 | struct resource *r = &dev->resource[1]; | |
530 | ||
531 | if (r->flags & IORESOURCE_MEM && r->start == hpet_address) { | |
532 | r->flags |= IORESOURCE_PCI_FIXED; | |
533 | dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n"); | |
534 | } | |
535 | } | |
536 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk); | |
537 | #endif | |
538 | ||
80b3e557 AC |
539 | /* |
540 | * Twinhead H12Y needs us to block out a region otherwise we map devices | |
541 | * there and any access kills the box. | |
542 | * | |
543 | * See: https://bugzilla.kernel.org/show_bug.cgi?id=10231 | |
544 | * | |
545 | * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor) | |
546 | */ | |
a18e3690 | 547 | static void twinhead_reserve_killing_zone(struct pci_dev *dev) |
80b3e557 AC |
548 | { |
549 | if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) { | |
550 | pr_info("Reserving memory on Twinhead H12Y\n"); | |
551 | request_mem_region(0xFFB00000, 0x100000, "twinhead"); | |
552 | } | |
553 | } | |
554 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone); | |
b8941571 | 555 | |
da77b671 | 556 | /* |
6af7e4f7 BH |
557 | * Device [8086:2fc0] |
558 | * Erratum HSE43 | |
559 | * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset | |
560 | * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html | |
da77b671 | 561 | * |
6af7e4f7 BH |
562 | * Devices [8086:6f60,6fa0,6fc0] |
563 | * Erratum BDF2 | |
564 | * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration | |
565 | * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html | |
da77b671 | 566 | */ |
6af7e4f7 | 567 | static void pci_invalid_bar(struct pci_dev *dev) |
b8941571 BH |
568 | { |
569 | dev->non_compliant_bars = 1; | |
570 | } | |
6af7e4f7 BH |
571 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar); |
572 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar); | |
573 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar); | |
574 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar); | |
0bf3730b KHF |
575 | |
576 | /* | |
577 | * Device [1022:7808] | |
578 | * 23. USB Wake on Connect/Disconnect with Low Speed Devices | |
579 | * https://support.amd.com/TechDocs/46837.pdf | |
580 | * Appendix A2 | |
581 | * https://support.amd.com/TechDocs/42413.pdf | |
582 | */ | |
583 | static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) | |
584 | { | |
585 | dev_info(&dev->dev, "PME# does not work under D3, disabling it\n"); | |
586 | dev->pme_support &= ~((PCI_PM_CAP_PME_D3 | PCI_PM_CAP_PME_D3cold) | |
587 | >> PCI_PM_CAP_PME_SHIFT); | |
588 | } | |
589 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); | |
8cd93850 | 590 | |
13cfc732 BH |
591 | /* |
592 | * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] | |
593 | * | |
594 | * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to | |
595 | * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used | |
596 | * for soft poweroff and suspend-to-RAM. | |
597 | * | |
598 | * As far as we know, this is related to the address space, not to the Root | |
599 | * Port itself. Attaching the quirk to the Root Port is a convenience, but | |
600 | * it could probably also be a standalone DMI quirk. | |
601 | * | |
602 | * https://bugzilla.kernel.org/show_bug.cgi?id=103211 | |
603 | */ | |
604 | static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) | |
605 | { | |
606 | struct device *dev = &pdev->dev; | |
607 | struct resource *res; | |
608 | ||
609 | if ((!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") && | |
610 | !dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) || | |
611 | pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0)) | |
612 | return; | |
613 | ||
614 | res = request_mem_region(0x7fa00000, 0x200000, | |
615 | "MacBook Pro poweroff workaround"); | |
616 | if (res) | |
617 | dev_info(dev, "claimed %s %pR\n", res->name, res); | |
618 | else | |
619 | dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); | |
620 | } | |
621 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); | |
f1b0e54e JD |
622 | |
623 | /* | |
624 | * VMD-enabled root ports will change the source ID for all messages | |
625 | * to the VMD device. Rather than doing device matching with the source | |
626 | * ID, the AER driver should traverse the child device tree, reading | |
627 | * AER registers to find the faulting device. | |
628 | */ | |
629 | static void quirk_no_aersid(struct pci_dev *pdev) | |
630 | { | |
631 | /* VMD Domain */ | |
c37f23d4 | 632 | if (is_vmd(pdev->bus)) |
f1b0e54e JD |
633 | pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID; |
634 | } | |
635 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid); | |
636 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid); | |
637 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid); | |
638 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid); | |
fa564ad9 CK |
639 | |
640 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
641 | ||
642 | #define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) | |
643 | #define AMD_141b_MMIO_BASE_RE_MASK BIT(0) | |
644 | #define AMD_141b_MMIO_BASE_WE_MASK BIT(1) | |
645 | #define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) | |
646 | ||
647 | #define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) | |
648 | #define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) | |
649 | ||
650 | #define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) | |
651 | #define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) | |
652 | #define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 | |
653 | #define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) | |
654 | ||
655 | /* | |
656 | * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow | |
657 | * configuring host bridge windows using the _PRS and _SRS methods. | |
658 | * | |
659 | * But this is rarely implemented, so we manually enable a large 64bit BAR for | |
660 | * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors | |
661 | * here. | |
662 | */ | |
663 | static void pci_amd_enable_64bit_bar(struct pci_dev *dev) | |
664 | { | |
fa564ad9 | 665 | u32 base, limit, high; |
a19e2696 | 666 | struct pci_dev *other; |
03a55173 UCCB |
667 | struct resource *res; |
668 | unsigned i; | |
669 | int r; | |
a19e2696 | 670 | |
f32ab754 UCCB |
671 | if (!(pci_probe & PCI_BIG_ROOT_WINDOW)) |
672 | return; | |
673 | ||
a19e2696 CK |
674 | /* Check that we are the only device of that type */ |
675 | other = pci_get_device(dev->vendor, dev->device, NULL); | |
676 | if (other != dev || | |
677 | (other = pci_get_device(dev->vendor, dev->device, other))) { | |
678 | /* This is a multi-socket system, don't touch it for now */ | |
679 | pci_dev_put(other); | |
680 | return; | |
681 | } | |
fa564ad9 CK |
682 | |
683 | for (i = 0; i < 8; i++) { | |
684 | pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); | |
685 | pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); | |
686 | ||
687 | /* Is this slot free? */ | |
688 | if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | | |
689 | AMD_141b_MMIO_BASE_WE_MASK))) | |
690 | break; | |
691 | ||
692 | base >>= 8; | |
693 | base |= high << 24; | |
694 | ||
695 | /* Abort if a slot already configures a 64bit BAR. */ | |
696 | if (base > 0x10000) | |
697 | return; | |
698 | } | |
699 | if (i == 8) | |
700 | return; | |
701 | ||
702 | res = kzalloc(sizeof(*res), GFP_KERNEL); | |
703 | if (!res) | |
704 | return; | |
705 | ||
03a55173 UCCB |
706 | /* |
707 | * Allocate a 256GB window directly below the 0xfd00000000 hardware | |
708 | * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6). | |
709 | */ | |
fa564ad9 CK |
710 | res->name = "PCI Bus 0000:00"; |
711 | res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | | |
712 | IORESOURCE_MEM_64 | IORESOURCE_WINDOW; | |
03a55173 | 713 | res->start = 0xbd00000000ull; |
fa564ad9 CK |
714 | res->end = 0xfd00000000ull - 1; |
715 | ||
03a55173 UCCB |
716 | r = request_resource(&iomem_resource, res); |
717 | if (r) { | |
718 | kfree(res); | |
719 | return; | |
470195f8 | 720 | } |
fa564ad9 | 721 | |
f32ab754 UCCB |
722 | dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n", |
723 | res); | |
724 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
fa564ad9 CK |
725 | |
726 | base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | | |
727 | AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; | |
728 | limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; | |
729 | high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | | |
730 | ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) | |
731 | & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); | |
732 | ||
733 | pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); | |
734 | pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); | |
735 | pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); | |
736 | ||
737 | pci_bus_add_resource(dev->bus, res, 0); | |
738 | } | |
a19e2696 CK |
739 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); |
740 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); | |
741 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); | |
742 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); | |
743 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); | |
fa564ad9 CK |
744 | |
745 | #endif |