[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <asm/e820.h>

#include "pci.h"

/* aperture is up to 256MB but BIOS may reserve less */
#define MMCONFIG_APER_MIN	(2 * 1024*1024)
#define MMCONFIG_APER_MAX	(256 * 1024*1024)

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);

	win = win & 0xf000;
	if(win == 0x0000 || win == 0xf000)
		pci_mmcfg_config_num = 0;
	else {
		pci_mmcfg_config_num = 1;
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = win << 16;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = 255;
	}

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	pci_mmcfg_config_num = 1;

	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		pci_mmcfg_config_num = 0;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		pci_mmcfg_config_num = 0;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		pci_mmcfg_config_num = 0;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		pci_mmcfg_config_num = 0;

	if (pci_mmcfg_config_num) {
		pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
		if (!pci_mmcfg_config)
			return NULL;
		pci_mmcfg_config[0].address = pciexbar & mask;
		pci_mmcfg_config[0].pci_segment = 0;
		pci_mmcfg_config[0].start_bus_number = 0;
		pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	}

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
	u32 low, high, address;
	u64 base, msr;
	int i;
	unsigned segnbits = 0, busnbits;

	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	if (rdmsr_safe(address, &low, &high))
		return NULL;

	msr = high;
	msr <<= 32;
	msr |= low;

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	/*
	 * only handle bus 0 ?
	 * need to skip it
	 */
	if (!busnbits)
		return NULL;

	if (busnbits > 8) {
		segnbits = busnbits - 8;
		busnbits = 8;
	}

	pci_mmcfg_config_num = (1 << segnbits);
	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
				   pci_mmcfg_config_num, GFP_KERNEL);
	if (!pci_mmcfg_config)
		return NULL;

	for (i = 0; i < (1 << segnbits); i++) {
		pci_mmcfg_config[i].address = base + (1<<28) * i;
		pci_mmcfg_config[i].pci_segment = i;
		pci_mmcfg_config[i].start_bus_number = 0;
		pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	}

	return "AMD Family 10h NB";
}

struct pci_mmcfg_hostbridge_probe {
	u32 bus;
	u32 devfn;
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
};

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u32 bus, devfn;
	u16 vendor, device;
	int i;
	const char *name;

	if (!raw_pci_ops)
		return 0;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;
	name = NULL;

	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		bus =  pci_mmcfg_probes[i].bus;
		devfn = pci_mmcfg_probes[i].devfn;
		raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();
	}

	if (name) {
		printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
		       name, pci_mmcfg_config_num ? "with" : "without");
	}

	return name != NULL;
}

static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
			 cfg->pci_segment);
		res->start = cfg->address;
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | resource_flags;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end < (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end < (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(unsigned long start, unsigned long end)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

static void __init pci_mmcfg_reject_broken(int early)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	cfg = &pci_mmcfg_config[0];

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		int valid = 0;
		u32 size = (cfg->end_bus_number + 1) << 20;
		cfg = &pci_mmcfg_config[i];
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);

		if (!early &&
		    is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
			printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
			       "in ACPI motherboard resources\n",
			       cfg->address);
			valid = 1;
		}

		if (valid)
			continue;

		if (!early)
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);
		/* Don't try to do this check unless configuration
		   type 1 is available. how about type 2 ?*/
		if (raw_pci_ops && e820_all_mapped(cfg->address,
						  cfg->address + size - 1,
						  E820_RESERVED)) {
			printk(KERN_NOTICE
			       "PCI: MCFG area at %Lx reserved in E820\n",
			       cfg->address);
			valid = 1;
		}

		if (!valid)
			goto reject;
	}

	return;

reject:
	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
	pci_mmcfg_arch_free();
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

static int __initdata known_bridge;

static void __init __pci_mmcfg_init(int early)
{
	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	/* for late to exit */
	if (known_bridge)
		return;

	if (early) {
		if (pci_mmcfg_check_hostbridge())
			known_bridge = 1;
	}

	if (!known_bridge) {
		acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
		pci_mmcfg_reject_broken(early);
	}

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init()) {
		if (known_bridge)
			pci_mmcfg_insert_resources(IORESOURCE_BUSY);
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	} else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

void __init pci_mmcfg_early_init(void)
{
	__pci_mmcfg_init(1);
}

void __init pci_mmcfg_late_init(void)
{
	__pci_mmcfg_init(0);
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources(0);

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
	16	#include <linux/bitmap.h>
	17	#include <asm/e820.h>
	18
	19	#include "pci.h"
	20
	21	/* aperture is up to 256MB but BIOS may reserve less */
	22	#define MMCONFIG_APER_MIN (2 * 1024*1024)
	23	#define MMCONFIG_APER_MAX (256 * 1024*1024)
	24
a5ba7971 AD	25	/* Indicate if the mmcfg resources have been placed into the resource table. */
	26	static int __initdata pci_mmcfg_resources_inserted;
	27
429d512e	28	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	29	{
9358c693 OG	30	u32 win;
bb63b421	31	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
9358c693	32
b5229dbb OG	33	win = win & 0xf000;
	34	if(win == 0x0000 \|\| win == 0xf000)
	35	pci_mmcfg_config_num = 0;
	36	else {
	37	pci_mmcfg_config_num = 1;
	38	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	39	if (!pci_mmcfg_config)
	40	return NULL;
	41	pci_mmcfg_config[0].address = win << 16;
	42	pci_mmcfg_config[0].pci_segment = 0;
	43	pci_mmcfg_config[0].start_bus_number = 0;
	44	pci_mmcfg_config[0].end_bus_number = 255;
	45	}
9358c693 OG	46
	47	return "Intel Corporation E7520 Memory Controller Hub";
	48	}
	49
429d512e	50	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	51	{
	52	u32 pciexbar, mask = 0, len = 0;
	53
	54	pci_mmcfg_config_num = 1;
	55
bb63b421	56	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
9358c693 OG	57
	58	/* Enable bit */
	59	if (!(pciexbar & 1))
	60	pci_mmcfg_config_num = 0;
	61
	62	/* Size bits */
	63	switch ((pciexbar >> 1) & 3) {
	64	case 0:
	65	mask = 0xf0000000U;
	66	len = 0x10000000U;
	67	break;
	68	case 1:
	69	mask = 0xf8000000U;
	70	len = 0x08000000U;
	71	break;
	72	case 2:
	73	mask = 0xfc000000U;
	74	len = 0x04000000U;
	75	break;
	76	default:
	77	pci_mmcfg_config_num = 0;
	78	}
	79
	80	/* Errata #2, things break when not aligned on a 256Mb boundary */
	81	/* Can only happen in 64M/128M mode */
	82
	83	if ((pciexbar & mask) & 0x0fffffffU)
	84	pci_mmcfg_config_num = 0;
	85
b5229dbb OG	86	/* Don't hit the APIC registers and their friends */
	87	if ((pciexbar & mask) >= 0xf0000000U)
	88	pci_mmcfg_config_num = 0;
	89
9358c693 OG	90	if (pci_mmcfg_config_num) {
	91	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
	92	if (!pci_mmcfg_config)
	93	return NULL;
	94	pci_mmcfg_config[0].address = pciexbar & mask;
	95	pci_mmcfg_config[0].pci_segment = 0;
	96	pci_mmcfg_config[0].start_bus_number = 0;
	97	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
	98	}
	99
	100	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	101	}
	102
7fd0da40 YL	103	static const char __init *pci_mmcfg_amd_fam10h(void)
	104	{
	105	u32 low, high, address;
	106	u64 base, msr;
	107	int i;
	108	unsigned segnbits = 0, busnbits;
	109
5f0b2976 YL	110	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
	111	return NULL;
	112
7fd0da40 YL	113	address = MSR_FAM10H_MMIO_CONF_BASE;
	114	if (rdmsr_safe(address, &low, &high))
	115	return NULL;
	116
	117	msr = high;
	118	msr <<= 32;
	119	msr \|= low;
	120
	121	/* mmconfig is not enable */
	122	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	123	return NULL;
	124
	125	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	126
	127	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	128	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	129
	130	/*
	131	* only handle bus 0 ?
	132	* need to skip it
	133	*/
	134	if (!busnbits)
	135	return NULL;
	136
	137	if (busnbits > 8) {
	138	segnbits = busnbits - 8;
	139	busnbits = 8;
	140	}
	141
	142	pci_mmcfg_config_num = (1 << segnbits);
	143	pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
	144	pci_mmcfg_config_num, GFP_KERNEL);
	145	if (!pci_mmcfg_config)
	146	return NULL;
	147
	148	for (i = 0; i < (1 << segnbits); i++) {
	149	pci_mmcfg_config[i].address = base + (1<<28) * i;
	150	pci_mmcfg_config[i].pci_segment = i;
	151	pci_mmcfg_config[i].start_bus_number = 0;
	152	pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
	153	}
	154
	155	return "AMD Family 10h NB";
	156	}
	157
9358c693	158	struct pci_mmcfg_hostbridge_probe {
7fd0da40 YL	159	u32 bus;
7fd0da40 YL	160	u32 devfn;
9358c693 OG	161	u32 vendor;
	162	u32 device;
	163	const char (probe)(void);
	164	};
	165
429d512e	166	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
7fd0da40 YL	167	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	168	PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	169	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	170	PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	171	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	172	0x1200, pci_mmcfg_amd_fam10h },
	173	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	174	0x1200, pci_mmcfg_amd_fam10h },
9358c693 OG	175	};
	176
	177	static int __init pci_mmcfg_check_hostbridge(void)
	178	{
	179	u32 l;
7fd0da40	180	u32 bus, devfn;
9358c693 OG	181	u16 vendor, device;
	182	int i;
	183	const char *name;
	184
bb63b421 YL	185	if (!raw_pci_ops)
	186	return 0;
	187
9358c693 OG	188	pci_mmcfg_config_num = 0;
	189	pci_mmcfg_config = NULL;
	190	name = NULL;
	191
429d512e	192	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40 YL	193	bus = pci_mmcfg_probes[i].bus;
7fd0da40 YL	194	devfn = pci_mmcfg_probes[i].devfn;
bb63b421	195	raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
7fd0da40 YL	196	vendor = l & 0xffff;
	197	device = (l >> 16) & 0xffff;
	198
429d512e OH	199	if (pci_mmcfg_probes[i].vendor == vendor &&
429d512e OH	200	pci_mmcfg_probes[i].device == device)
9358c693	201	name = pci_mmcfg_probes[i].probe();
429d512e	202	}
9358c693 OG	203
9358c693 OG	204	if (name) {
429d512e OH	205	printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
429d512e OH	206	name, pci_mmcfg_config_num ? "with" : "without");
9358c693 OG	207	}
	208
	209	return name != NULL;
	210	}
	211
a5ba7971	212	static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
6a0668fc OG	213	{
	214	#define PCI_MMCFG_RESOURCE_NAME_LEN 19
	215	int i;
	216	struct resource *res;
	217	char *names;
	218	unsigned num_buses;
	219
	220	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	221	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	222	if (!res) {
	223	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	224	return;
	225	}
	226
	227	names = (void *)&res[pci_mmcfg_config_num];
	228	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	229	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	230	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc OG	231	res->name = names;
6a0668fc OG	232	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
429d512e OH	233	cfg->pci_segment);
429d512e OH	234	res->start = cfg->address;
6a0668fc	235	res->end = res->start + (num_buses << 20) - 1;
a5ba7971	236	res->flags = IORESOURCE_MEM \| resource_flags;
6a0668fc OG	237	insert_resource(&iomem_resource, res);
	238	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	239	}
a5ba7971 AD	240
	241	/* Mark that the resources have been inserted. */
	242	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	243	}
6a0668fc OG	244
7752d5cf RH	245	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	246	void *data)
	247	{
	248	struct resource *mcfg_res = data;
	249	struct acpi_resource_address64 address;
	250	acpi_status status;
	251
	252	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	253	struct acpi_resource_fixed_memory32 *fixmem32 =
	254	&res->data.fixed_memory32;
	255	if (!fixmem32)
	256	return AE_OK;
	257	if ((mcfg_res->start >= fixmem32->address) &&
	258	(mcfg_res->end < (fixmem32->address +
	259	fixmem32->address_length))) {
	260	mcfg_res->flags = 1;
	261	return AE_CTRL_TERMINATE;
	262	}
	263	}
	264	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	265	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	266	return AE_OK;
	267
	268	status = acpi_resource_to_address64(res, &address);
	269	if (ACPI_FAILURE(status) \|\|
	270	(address.address_length <= 0) \|\|
	271	(address.resource_type != ACPI_MEMORY_RANGE))
	272	return AE_OK;
	273
	274	if ((mcfg_res->start >= address.minimum) &&
	275	(mcfg_res->end < (address.minimum + address.address_length))) {
	276	mcfg_res->flags = 1;
	277	return AE_CTRL_TERMINATE;
	278	}
	279	return AE_OK;
	280	}
	281
	282	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	283	void context, void *rv)
	284	{
	285	struct resource *mcfg_res = context;
	286
	287	acpi_walk_resources(handle, METHOD_NAME__CRS,
	288	check_mcfg_resource, context);
	289
	290	if (mcfg_res->flags)
	291	return AE_CTRL_TERMINATE;
	292
	293	return AE_OK;
	294	}
	295
	296	static int __init is_acpi_reserved(unsigned long start, unsigned long end)
	297	{
	298	struct resource mcfg_res;
	299
	300	mcfg_res.start = start;
	301	mcfg_res.end = end;
	302	mcfg_res.flags = 0;
	303
	304	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	305
	306	if (!mcfg_res.flags)
	307	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	308	NULL);
309
310	return mcfg_res.flags;
311	}
312
bb63b421	313	static void __init pci_mmcfg_reject_broken(int early)
44de0203	314	{
26054ed0	315	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	316	int i;
26054ed0 OH	317
	318	if ((pci_mmcfg_config_num == 0) \|\|
	319	(pci_mmcfg_config == NULL) \|\|
	320	(pci_mmcfg_config[0].address == 0))
	321	return;
	322
	323	cfg = &pci_mmcfg_config[0];
44de0203	324
7752d5cf	325	for (i = 0; i < pci_mmcfg_config_num; i++) {
05c58b8a	326	int valid = 0;
7752d5cf RH	327	u32 size = (cfg->end_bus_number + 1) << 20;
7752d5cf RH	328	cfg = &pci_mmcfg_config[i];
05c58b8a	329	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
7752d5cf RH	330	"segment %hu buses %u - %u\n",
	331	i, (unsigned long)cfg->address, cfg->pci_segment,
	332	(unsigned int)cfg->start_bus_number,
	333	(unsigned int)cfg->end_bus_number);
05c58b8a YL	334
	335	if (!early &&
	336	is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
7752d5cf RH	337	printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
	338	"in ACPI motherboard resources\n",
	339	cfg->address);
05c58b8a YL	340	valid = 1;
	341	}
	342
	343	if (valid)
	344	continue;
	345
	346	if (!early)
7752d5cf RH	347	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	348	" reserved in ACPI motherboard resources\n",
	349	cfg->address);
05c58b8a	350	/* Don't try to do this check unless configuration
bb63b421 YL	351	type 1 is available. how about type 2 ?*/
bb63b421 YL	352	if (raw_pci_ops && e820_all_mapped(cfg->address,
05c58b8a YL	353	cfg->address + size - 1,
	354	E820_RESERVED)) {
	355	printk(KERN_NOTICE
	356	"PCI: MCFG area at %Lx reserved in E820\n",
	357	cfg->address);
	358	valid = 1;
7752d5cf	359	}
05c58b8a YL	360
	361	if (!valid)
	362	goto reject;
44de0203	363	}
7752d5cf	364
26054ed0 OH	365	return;
	366
	367	reject:
	368	printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
0b64ad71	369	pci_mmcfg_arch_free();
26054ed0 OH	370	kfree(pci_mmcfg_config);
	371	pci_mmcfg_config = NULL;
	372	pci_mmcfg_config_num = 0;
44de0203 OH	373	}
44de0203 OH	374
05c58b8a	375	static int __initdata known_bridge;
7752d5cf	376
968cbfad	377	static void __init __pci_mmcfg_init(int early)
b7867394	378	{
7752d5cf	379	/* MMCONFIG disabled */
b7867394 OG	380	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	381	return;
	382
7752d5cf	383	/* MMCONFIG already enabled */
05c58b8a	384	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
7752d5cf	385	return;
9358c693	386
05c58b8a YL	387	/* for late to exit */
	388	if (known_bridge)
	389	return;
7752d5cf	390
bb63b421	391	if (early) {
05c58b8a YL	392	if (pci_mmcfg_check_hostbridge())
	393	known_bridge = 1;
	394	}
	395
	396	if (!known_bridge) {
	397	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
bb63b421	398	pci_mmcfg_reject_broken(early);
05c58b8a	399	}
b7867394 OG	400
	401	if ((pci_mmcfg_config_num == 0) \|\|
	402	(pci_mmcfg_config == NULL) \|\|
	403	(pci_mmcfg_config[0].address == 0))
	404	return;
	405
b7867394	406	if (pci_mmcfg_arch_init()) {
6a0668fc	407	if (known_bridge)
a5ba7971	408	pci_mmcfg_insert_resources(IORESOURCE_BUSY);
b7867394	409	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
a5ba7971 AD	410	} else {
	411	/*
	412	* Signal not to attempt to insert mmcfg resources because
	413	* the architecture mmcfg setup could not initialize.
	414	*/
	415	pci_mmcfg_resources_inserted = 1;
b7867394 OG	416	}
b7867394 OG	417	}
a5ba7971	418
bb63b421	419	void __init pci_mmcfg_early_init(void)
05c58b8a	420	{
bb63b421	421	__pci_mmcfg_init(1);
05c58b8a YL	422	}
	423
	424	void __init pci_mmcfg_late_init(void)
	425	{
bb63b421	426	__pci_mmcfg_init(0);
05c58b8a YL	427	}
05c58b8a YL	428
a5ba7971 AD	429	static int __init pci_mmcfg_late_insert_resources(void)
	430	{
	431	/*
	432	* If resources are already inserted or we are not using MMCONFIG,
	433	* don't insert the resources.
	434	*/
	435	if ((pci_mmcfg_resources_inserted == 1) \|\|
	436	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	437	(pci_mmcfg_config_num == 0) \|\|
	438	(pci_mmcfg_config == NULL) \|\|
	439	(pci_mmcfg_config[0].address == 0))
	440	return 1;
	441
	442	/*
	443	* Attempt to insert the mmcfg resources but not with the busy flag
	444	* marked so it won't cause request errors when __request_region is
	445	* called.
	446	*/
	447	pci_mmcfg_insert_resources(0);
	448
	449	return 0;
	450	}
	451
	452	/*
	453	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	454	* misprogrammed MCFG tables that state larger sizes but actually conflict
	455	* with other system resources.
	456	*/
	457	late_initcall(pci_mmcfg_late_insert_resources);