[mirror_ubuntu-artful-kernel.git] / arch / x86 / pci / mmconfig_32.c

/*
 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
 * Copyright (C) 2004 Intel Corp.
 *
 * This code is released under the GNU General Public License version 2.
 */

/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <asm/e820.h>
#include "pci.h"

/* Assume systems with more busses have correct MCFG */
#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))

/* The base address of the last MMCONFIG device accessed */
static u32 mmcfg_last_accessed_device;
static int mmcfg_last_accessed_cpu;

/*
 * Functions for accessing PCI configuration space with MMCONFIG accesses
 */
static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
{
	struct acpi_mcfg_allocation *cfg;
	int cfg_num;

	for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
		cfg = &pci_mmcfg_config[cfg_num];
		if (cfg->pci_segment == seg &&
		    (cfg->start_bus_number <= bus) &&
		    (cfg->end_bus_number >= bus))
			return cfg->address;
	}

	/* Fall back to type 0 */
	return 0;
}

/*
 * This is always called under pci_config_lock
 */
static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
{
	u32 dev_base = base | (bus << 20) | (devfn << 12);
	int cpu = smp_processor_id();
	if (dev_base != mmcfg_last_accessed_device ||
	    cpu != mmcfg_last_accessed_cpu) {
		mmcfg_last_accessed_device = dev_base;
		mmcfg_last_accessed_cpu = cpu;
		set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	}
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
err:		*value = -1;
		return -EINVAL;
	}

	if (reg < 256)
		return pci_conf1_read(seg,bus,devfn,reg,len,value);

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		goto err;

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		*value = mmio_config_readb(mmcfg_virt_addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(mmcfg_virt_addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(mmcfg_virt_addr + reg);
		break;
	}
	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	unsigned long flags;
	u32 base;

	if ((bus > 255) || (devfn > 255) || (reg > 4095))
		return -EINVAL;

	if (reg < 256)
		return pci_conf1_write(seg,bus,devfn,reg,len,value);

	base = get_base_addr(seg, bus, devfn);
	if (!base)
		return -EINVAL;

	spin_lock_irqsave(&pci_config_lock, flags);

	pci_exp_set_dev_base(base, bus, devfn);

	switch (len) {
	case 1:
		mmio_config_writeb(mmcfg_virt_addr + reg, value);
		break;
	case 2:
		mmio_config_writew(mmcfg_virt_addr + reg, value);
		break;
	case 4:
		mmio_config_writel(mmcfg_virt_addr + reg, value);
		break;
	}
	spin_unlock_irqrestore(&pci_config_lock, flags);

	return 0;
}

static struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

int __init pci_mmcfg_arch_init(void)
{
	printk(KERN_INFO "PCI: Using MMCONFIG\n");
	raw_pci_ops = &pci_mmcfg;
	return 1;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
	3	* Copyright (C) 2004 Intel Corp.
	4	*
	5	* This code is released under the GNU General Public License version 2.
	6	*/
	7
	8	/*
	9	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
	10	*/
	11
	12	#include <linux/pci.h>
	13	#include <linux/init.h>
54549391	14	#include <linux/acpi.h>
946f2ee5	15	#include <asm/e820.h>
1da177e4 LT	16	#include "pci.h"
1da177e4 LT	17
8c30b1a7	18	/* Assume systems with more busses have correct MCFG */
1da177e4 LT	19	#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
	20
	21	/* The base address of the last MMCONFIG device accessed */
	22	static u32 mmcfg_last_accessed_device;
8d1c4819	23	static int mmcfg_last_accessed_cpu;
1da177e4 LT	24
	25	/*
	26	* Functions for accessing PCI configuration space with MMCONFIG accesses
	27	*/
d6ece549	28	static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
d57e26ce	29	{
15a58ed1	30	struct acpi_mcfg_allocation *cfg;
429d512e	31	int cfg_num;
d57e26ce	32
429d512e	33	for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
d57e26ce	34	cfg = &pci_mmcfg_config[cfg_num];
429d512e OH	35	if (cfg->pci_segment == seg &&
429d512e OH	36	(cfg->start_bus_number <= bus) &&
d57e26ce	37	(cfg->end_bus_number >= bus))
15a58ed1	38	return cfg->address;
d57e26ce	39	}
3103039c	40
3103039c AK	41	/* Fall back to type 0 */
3103039c AK	42	return 0;
d57e26ce	43	}
1da177e4	44
be5b7a89 AM	45	/*
	46	* This is always called under pci_config_lock
	47	*/
	48	static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
1da177e4	49	{
928cf8c6	50	u32 dev_base = base \| (bus << 20) \| (devfn << 12);
8d1c4819 OH	51	int cpu = smp_processor_id();
	52	if (dev_base != mmcfg_last_accessed_device \|\|
	53	cpu != mmcfg_last_accessed_cpu) {
1da177e4	54	mmcfg_last_accessed_device = dev_base;
8d1c4819	55	mmcfg_last_accessed_cpu = cpu;
1da177e4 LT	56	set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
	57	}
	58	}
	59
	60	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	61	unsigned int devfn, int reg, int len, u32 *value)
	62	{
	63	unsigned long flags;
928cf8c6	64	u32 base;
1da177e4	65
ecc16ba9	66	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)) {
a0ca9909	67	err: *value = -1;
1da177e4	68	return -EINVAL;
49c93e84	69	}
1da177e4	70
a0ca9909 IK	71	if (reg < 256)
	72	return pci_conf1_read(seg,bus,devfn,reg,len,value);
	73
d6ece549	74	base = get_base_addr(seg, bus, devfn);
928cf8c6	75	if (!base)
a0ca9909	76	goto err;
928cf8c6	77
1da177e4 LT	78	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	79
928cf8c6	80	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	81
	82	switch (len) {
	83	case 1:
3320ad99	84	*value = mmio_config_readb(mmcfg_virt_addr + reg);
1da177e4 LT	85	break;
1da177e4 LT	86	case 2:
3320ad99	87	*value = mmio_config_readw(mmcfg_virt_addr + reg);
1da177e4 LT	88	break;
1da177e4 LT	89	case 4:
3320ad99	90	*value = mmio_config_readl(mmcfg_virt_addr + reg);
1da177e4 LT	91	break;
1da177e4 LT	92	}
1da177e4 LT	93	spin_unlock_irqrestore(&pci_config_lock, flags);
	94
	95	return 0;
	96	}
	97
	98	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	99	unsigned int devfn, int reg, int len, u32 value)
	100	{
	101	unsigned long flags;
928cf8c6	102	u32 base;
1da177e4	103
15a58ed1	104	if ((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))
1da177e4 LT	105	return -EINVAL;
1da177e4 LT	106
a0ca9909 IK	107	if (reg < 256)
	108	return pci_conf1_write(seg,bus,devfn,reg,len,value);
	109
d6ece549	110	base = get_base_addr(seg, bus, devfn);
928cf8c6	111	if (!base)
a0ca9909	112	return -EINVAL;
928cf8c6	113
1da177e4 LT	114	spin_lock_irqsave(&pci_config_lock, flags);
1da177e4 LT	115
928cf8c6	116	pci_exp_set_dev_base(base, bus, devfn);
1da177e4 LT	117
	118	switch (len) {
	119	case 1:
c1502e28	120	mmio_config_writeb(mmcfg_virt_addr + reg, value);
1da177e4 LT	121	break;
1da177e4 LT	122	case 2:
c1502e28	123	mmio_config_writew(mmcfg_virt_addr + reg, value);
1da177e4 LT	124	break;
1da177e4 LT	125	case 4:
c1502e28	126	mmio_config_writel(mmcfg_virt_addr + reg, value);
1da177e4 LT	127	break;
1da177e4 LT	128	}
1da177e4 LT	129	spin_unlock_irqrestore(&pci_config_lock, flags);
	130
	131	return 0;
	132	}
	133
	134	static struct pci_raw_ops pci_mmcfg = {
	135	.read = pci_mmcfg_read,
	136	.write = pci_mmcfg_write,
	137	};
	138
b7867394	139	int __init pci_mmcfg_arch_init(void)
d6ece549	140	{
1da177e4 LT	141	printk(KERN_INFO "PCI: Using MMCONFIG\n");
1da177e4 LT	142	raw_pci_ops = &pci_mmcfg;
b7867394	143	return 1;
1da177e4	144	}