[mirror_ubuntu-focal-kernel.git] / arch / x86 / pci / mmconfig_64.c

// SPDX-License-Identifier: GPL-2.0
/*
 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
 *
 * This is an 64bit optimized version that always keeps the full mmconfig
 * space mapped. This allows lockless config space operation.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/bitmap.h>
#include <linux/rcupdate.h>
#include <asm/e820/api.h>
#include <asm/pci_x86.h>

#define PREFIX "PCI: "

static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
{
	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);

	if (cfg && cfg->virt)
		return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
	return NULL;
}

static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			  unsigned int devfn, int reg, int len, u32 *value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
err:		*value = -1;
		return -EINVAL;
	}

	rcu_read_lock();
	addr = pci_dev_base(seg, bus, devfn);
	if (!addr) {
		rcu_read_unlock();
		goto err;
	}

	switch (len) {
	case 1:
		*value = mmio_config_readb(addr + reg);
		break;
	case 2:
		*value = mmio_config_readw(addr + reg);
		break;
	case 4:
		*value = mmio_config_readl(addr + reg);
		break;
	}
	rcu_read_unlock();

	return 0;
}

static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			   unsigned int devfn, int reg, int len, u32 value)
{
	char __iomem *addr;

	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
	if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
		return -EINVAL;

	rcu_read_lock();
	addr = pci_dev_base(seg, bus, devfn);
	if (!addr) {
		rcu_read_unlock();
		return -EINVAL;
	}

	switch (len) {
	case 1:
		mmio_config_writeb(addr + reg, value);
		break;
	case 2:
		mmio_config_writew(addr + reg, value);
		break;
	case 4:
		mmio_config_writel(addr + reg, value);
		break;
	}
	rcu_read_unlock();

	return 0;
}

const struct pci_raw_ops pci_mmcfg = {
	.read =		pci_mmcfg_read,
	.write =	pci_mmcfg_write,
};

static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg)
{
	void __iomem *addr;
	u64 start, size;
	int num_buses;

	start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
	num_buses = cfg->end_bus - cfg->start_bus + 1;
	size = PCI_MMCFG_BUS_OFFSET(num_buses);
	addr = ioremap_nocache(start, size);
	if (addr)
		addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
	return addr;
}

int __init pci_mmcfg_arch_init(void)
{
	struct pci_mmcfg_region *cfg;

	list_for_each_entry(cfg, &pci_mmcfg_list, list)
		if (pci_mmcfg_arch_map(cfg)) {
			pci_mmcfg_arch_free();
			return 0;
		}

	raw_pci_ext_ops = &pci_mmcfg;

	return 1;
}

void __init pci_mmcfg_arch_free(void)
{
	struct pci_mmcfg_region *cfg;

	list_for_each_entry(cfg, &pci_mmcfg_list, list)
		pci_mmcfg_arch_unmap(cfg);
}

int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
{
	cfg->virt = mcfg_ioremap(cfg);
	if (!cfg->virt) {
		pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
		return -ENOMEM;
	}

	return 0;
}

void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
{
	if (cfg && cfg->virt) {
		iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
		cfg->virt = NULL;
	}
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
1da177e4 LT	3	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
15a58ed1	4	*
1da177e4 LT	5	* This is an 64bit optimized version that always keeps the full mmconfig
	6	* space mapped. This allows lockless config space operation.
	7	*/
	8
	9	#include <linux/pci.h>
	10	#include <linux/init.h>
54549391	11	#include <linux/acpi.h>
d6ece549	12	#include <linux/bitmap.h>
376f70ac	13	#include <linux/rcupdate.h>
66441bd3	14	#include <asm/e820/api.h>
82487711	15	#include <asm/pci_x86.h>
1da177e4	16
8c57786a BH	17	#define PREFIX "PCI: "
8c57786a BH	18
8b8a4e33	19	static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
1cde8a16	20	{
f6e1d8cc	21	struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
a0ca9909	22
f6e1d8cc BH	23	if (cfg && cfg->virt)
	24	return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) \| (devfn << 12));
	25	return NULL;
1da177e4 LT	26	}
	27
	28	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
	29	unsigned int devfn, int reg, int len, u32 *value)
	30	{
8b8a4e33	31	char __iomem *addr;
1da177e4	32
928cf8c6	33	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
ecc16ba9	34	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095))) {
a0ca9909	35	err: *value = -1;
1da177e4	36	return -EINVAL;
49c93e84	37	}
1da177e4	38
376f70ac	39	rcu_read_lock();
928cf8c6	40	addr = pci_dev_base(seg, bus, devfn);
376f70ac JL	41	if (!addr) {
376f70ac JL	42	rcu_read_unlock();
a0ca9909	43	goto err;
376f70ac	44	}
928cf8c6	45
1da177e4 LT	46	switch (len) {
1da177e4 LT	47	case 1:
3320ad99	48	*value = mmio_config_readb(addr + reg);
1da177e4 LT	49	break;
1da177e4 LT	50	case 2:
3320ad99	51	*value = mmio_config_readw(addr + reg);
1da177e4 LT	52	break;
1da177e4 LT	53	case 4:
3320ad99	54	*value = mmio_config_readl(addr + reg);
1da177e4 LT	55	break;
1da177e4 LT	56	}
376f70ac	57	rcu_read_unlock();
1da177e4 LT	58
	59	return 0;
	60	}
	61
	62	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
	63	unsigned int devfn, int reg, int len, u32 value)
	64	{
8b8a4e33	65	char __iomem *addr;
1da177e4	66
928cf8c6	67	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
1da177e4 LT	68	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
	69	return -EINVAL;
	70
376f70ac	71	rcu_read_lock();
928cf8c6	72	addr = pci_dev_base(seg, bus, devfn);
376f70ac JL	73	if (!addr) {
376f70ac JL	74	rcu_read_unlock();
a0ca9909	75	return -EINVAL;
376f70ac	76	}
928cf8c6	77
1da177e4 LT	78	switch (len) {
1da177e4 LT	79	case 1:
3320ad99	80	mmio_config_writeb(addr + reg, value);
1da177e4 LT	81	break;
1da177e4 LT	82	case 2:
3320ad99	83	mmio_config_writew(addr + reg, value);
1da177e4 LT	84	break;
1da177e4 LT	85	case 4:
3320ad99	86	mmio_config_writel(addr + reg, value);
1da177e4 LT	87	break;
1da177e4 LT	88	}
376f70ac	89	rcu_read_unlock();
1da177e4 LT	90
	91	return 0;
	92	}
	93
c0fa4078	94	const struct pci_raw_ops pci_mmcfg = {
1da177e4 LT	95	.read = pci_mmcfg_read,
	96	.write = pci_mmcfg_write,
	97	};
	98
a18e3690	99	static void __iomem mcfg_ioremap(struct pci_mmcfg_region cfg)
44de0203 OH	100	{
44de0203 OH	101	void __iomem *addr;
068258bc	102	u64 start, size;
df5eb1d6	103	int num_buses;
068258bc	104
d7e6b66f BH	105	start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
d7e6b66f BH	106	num_buses = cfg->end_bus - cfg->start_bus + 1;
df5eb1d6	107	size = PCI_MMCFG_BUS_OFFSET(num_buses);
068258bc	108	addr = ioremap_nocache(start, size);
8c57786a	109	if (addr)
d7e6b66f	110	addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
44de0203 OH	111	return addr;
	112	}
	113
b7867394	114	int __init pci_mmcfg_arch_init(void)
1da177e4	115	{
3f0f5503	116	struct pci_mmcfg_region *cfg;
b7867394	117
9cf0105d JL	118	list_for_each_entry(cfg, &pci_mmcfg_list, list)
9cf0105d JL	119	if (pci_mmcfg_arch_map(cfg)) {
0b64ad71	120	pci_mmcfg_arch_free();
b7867394	121	return 0;
1cde8a16	122	}
9cf0105d	123
b6ce068a	124	raw_pci_ext_ops = &pci_mmcfg;
9cf0105d	125
b7867394	126	return 1;
1da177e4	127	}
0b64ad71 YL	128
	129	void __init pci_mmcfg_arch_free(void)
	130	{
3f0f5503	131	struct pci_mmcfg_region *cfg;
0b64ad71	132
9cf0105d JL	133	list_for_each_entry(cfg, &pci_mmcfg_list, list)
	134	pci_mmcfg_arch_unmap(cfg);
	135	}
	136
a18e3690	137	int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
9cf0105d JL	138	{
	139	cfg->virt = mcfg_ioremap(cfg);
	140	if (!cfg->virt) {
24c97f04	141	pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
9cf0105d JL	142	return -ENOMEM;
	143	}
	144
	145	return 0;
	146	}
	147
	148	void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
	149	{
	150	if (cfg && cfg->virt) {
	151	iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
	152	cfg->virt = NULL;
0b64ad71	153	}
0b64ad71	154	}