[mirror_ubuntu-bionic-kernel.git] / arch / x86 / pci / visws.c

/*
 *	Low-Level PCI Support for SGI Visual Workstation
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>

#include <asm/setup.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/lithium.h>

#include "pci.h"

static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
static void pci_visws_disable_irq(struct pci_dev *dev) { }

/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */

/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */


unsigned int pci_bus0, pci_bus1;

static inline u8 bridge_swizzle(u8 pin, u8 slot) 
{
	return (((pin - 1) + slot) % 4) + 1;
}

static u8 __init visws_swizzle(struct pci_dev *dev, u8 *pinp)
{
	u8 pin = *pinp;

	while (dev->bus->self) {	/* Move up the chain of bridges. */
		pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
		dev = dev->bus->self;
	}
	*pinp = pin;

	return PCI_SLOT(dev->devfn);
}

static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq, bus = dev->bus->number;

	pin--;

	/* Nothing useful at PIIX4 pin 1 */
	if (bus == pci_bus0 && slot == 4 && pin == 0)
		return -1;

	/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
	if (bus == pci_bus0 && slot == 4 && pin == 3) {
		irq = CO_IRQ(CO_APIC_PIIX4_USB);
		goto out;
	}

	/* First pin spread down 1 APIC entry per slot */
	if (pin == 0) {
		irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
						CO_APIC_PCIA_BASE0) + slot);
		goto out;
	}

	/* lines 1,2,3 from any slot is shared in this twirly pattern */
	if (bus == pci_bus1) {
		/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
		irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
	} else { /* bus == pci_bus0 */
		/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
		if (slot == 0)
			slot = 3; /* same pattern */
		irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
	}
out:
	printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
	return irq;
}

void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

static int __init pci_visws_init(void)
{
	/* The VISWS supports configuration access type 1 only */
	pci_probe = (pci_probe | PCI_PROBE_CONF1) &
		    ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);

	pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
	pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;

	printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
		"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);

	raw_pci_ops = &pci_direct_conf1;
	pci_scan_bus_with_sysdata(pci_bus0);
	pci_scan_bus_with_sysdata(pci_bus1);
	pci_fixup_irqs(visws_swizzle, visws_map_irq);
	pcibios_resource_survey();
	return 0;
}

static __init int pci_subsys_init(void)
{
	if (!is_visws_box())
		return -1;

	pcibios_enable_irq = &pci_visws_enable_irq;
	pcibios_disable_irq = &pci_visws_disable_irq;

	pci_visws_init();
	pcibios_init();

	return 0;
}
subsys_initcall(pci_subsys_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for SGI Visual Workstation
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
1da177e4 LT	7	#include <linux/kernel.h>
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
	10
5548ed11	11	#include <asm/setup.h>
b4b86416 IM	12	#include <asm/visws/cobalt.h>
b4b86416 IM	13	#include <asm/visws/lithium.h>
1da177e4 LT	14
	15	#include "pci.h"
	16
1da177e4	17	static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
46bdac99	18	static void pci_visws_disable_irq(struct pci_dev *dev) { }
1da177e4	19
22d5c67c IM	20	/* int (pcibios_enable_irq)(struct pci_dev dev) = &pci_visws_enable_irq; */
22d5c67c IM	21	/* void (pcibios_disable_irq)(struct pci_dev dev) = &pci_visws_disable_irq; */
1da177e4	22
22d5c67c	23	/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
1da177e4 LT	24
	25
	26	unsigned int pci_bus0, pci_bus1;
	27
	28	static inline u8 bridge_swizzle(u8 pin, u8 slot)
	29	{
	30	return (((pin - 1) + slot) % 4) + 1;
	31	}
	32
	33	static u8 __init visws_swizzle(struct pci_dev dev, u8 pinp)
	34	{
	35	u8 pin = *pinp;
	36
	37	while (dev->bus->self) { /* Move up the chain of bridges. */
	38	pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
	39	dev = dev->bus->self;
	40	}
	41	*pinp = pin;
	42
	43	return PCI_SLOT(dev->devfn);
	44	}
	45
	46	static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	47	{
	48	int irq, bus = dev->bus->number;
	49
	50	pin--;
	51
	52	/* Nothing useful at PIIX4 pin 1 */
	53	if (bus == pci_bus0 && slot == 4 && pin == 0)
	54	return -1;
	55
	56	/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
	57	if (bus == pci_bus0 && slot == 4 && pin == 3) {
	58	irq = CO_IRQ(CO_APIC_PIIX4_USB);
	59	goto out;
	60	}
	61
	62	/* First pin spread down 1 APIC entry per slot */
	63	if (pin == 0) {
	64	irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
	65	CO_APIC_PCIA_BASE0) + slot);
	66	goto out;
	67	}
	68
	69	/* lines 1,2,3 from any slot is shared in this twirly pattern */
	70	if (bus == pci_bus1) {
	71	/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
	72	irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
	73	} else { /* bus == pci_bus0 */
	74	/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
	75	if (slot == 0)
	76	slot = 3; /* same pattern */
	77	irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
	78	}
	79	out:
	80	printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
	81	return irq;
	82	}
	83
	84	void __init pcibios_update_irq(struct pci_dev *dev, int irq)
	85	{
	86	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	87	}
88
ae28d705	89	static int __init pci_visws_init(void)
1da177e4 LT	90	{
	91	/* The VISWS supports configuration access type 1 only */
	92	pci_probe = (pci_probe \| PCI_PROBE_CONF1) &
	93	~(PCI_PROBE_BIOS \| PCI_PROBE_CONF2);
	94
	95	pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
	96	pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
	97
	98	printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
	99	"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
	100
	101	raw_pci_ops = &pci_direct_conf1;
73c59afc MBY	102	pci_scan_bus_with_sysdata(pci_bus0);
73c59afc MBY	103	pci_scan_bus_with_sysdata(pci_bus1);
1da177e4 LT	104	pci_fixup_irqs(visws_swizzle, visws_map_irq);
	105	pcibios_resource_survey();
	106	return 0;
	107	}
	108
8dd779b1 RR	109	static __init int pci_subsys_init(void)
8dd779b1 RR	110	{
5548ed11 IM	111	if (!is_visws_box())
	112	return -1;
	113
	114	pcibios_enable_irq = &pci_visws_enable_irq;
	115	pcibios_disable_irq = &pci_visws_disable_irq;
31ac409a	116
8dd779b1 RR	117	pci_visws_init();
8dd779b1 RR	118	pcibios_init();
31ac409a IM	119
31ac409a IM	120	return 0;
8dd779b1 RR	121	}
8dd779b1 RR	122	subsys_initcall(pci_subsys_init);