[mirror_ubuntu-artful-kernel.git] / arch / x86 / pci / xen.c

/*
 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
 * 0xcf8 PCI configuration read/write.
 *
 *   Author: Ryan Wilson <hap9@epoch.ncsc.mil>
 *           Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 *           Stefano Stabellini <stefano.stabellini@eu.citrix.com>
 */
#include <linux/export.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/acpi.h>

#include <linux/io.h>
#include <asm/io_apic.h>
#include <asm/pci_x86.h>

#include <asm/xen/hypervisor.h>

#include <xen/features.h>
#include <xen/events.h>
#include <asm/xen/pci.h>
#include <asm/xen/cpuid.h>
#include <asm/apic.h>
#include <asm/i8259.h>

static int xen_pcifront_enable_irq(struct pci_dev *dev)
{
	int rc;
	int share = 1;
	int pirq;
	u8 gsi;

	rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
	if (rc < 0) {
		dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
			 rc);
		return rc;
	}
	/* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
	pirq = gsi;

	if (gsi < nr_legacy_irqs())
		share = 0;

	rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
	if (rc < 0) {
		dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
			 gsi, pirq, rc);
		return rc;
	}

	dev->irq = rc;
	dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
	return 0;
}

#ifdef CONFIG_ACPI
static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
			     bool set_pirq)
{
	int rc, pirq = -1, irq = -1;
	struct physdev_map_pirq map_irq;
	int shareable = 0;
	char *name;

	irq = xen_irq_from_gsi(gsi);
	if (irq > 0)
		return irq;

	if (set_pirq)
		pirq = gsi;

	map_irq.domid = DOMID_SELF;
	map_irq.type = MAP_PIRQ_TYPE_GSI;
	map_irq.index = gsi;
	map_irq.pirq = pirq;

	rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
	if (rc) {
		printk(KERN_WARNING "xen map irq failed %d\n", rc);
		return -1;
	}

	if (triggering == ACPI_EDGE_SENSITIVE) {
		shareable = 0;
		name = "ioapic-edge";
	} else {
		shareable = 1;
		name = "ioapic-level";
	}

	if (gsi_override >= 0)
		gsi = gsi_override;

	irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
	if (irq < 0)
		goto out;

	printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
out:
	return irq;
}

static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
				     int trigger, int polarity)
{
	if (!xen_hvm_domain())
		return -1;

	return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
				 false /* no mapping of GSI to PIRQ */);
}

#ifdef CONFIG_XEN_DOM0
static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
{
	int rc, irq;
	struct physdev_setup_gsi setup_gsi;

	if (!xen_pv_domain())
		return -1;

	printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
			gsi, triggering, polarity);

	irq = xen_register_pirq(gsi, gsi_override, triggering, true);

	setup_gsi.gsi = gsi;
	setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
	setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);

	rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
	if (rc == -EEXIST)
		printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
	else if (rc) {
		printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
				gsi, rc);
	}

	return irq;
}

static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
				 int trigger, int polarity)
{
	return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
}
#endif
#endif

#if defined(CONFIG_PCI_MSI)
#include <linux/msi.h>
#include <asm/msidef.h>

struct xen_pci_frontend_ops *xen_pci_frontend;
EXPORT_SYMBOL_GPL(xen_pci_frontend);

static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int irq, ret, i;
	struct msi_desc *msidesc;
	int *v;

	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;

	v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
	if (!v)
		return -ENOMEM;

	if (type == PCI_CAP_ID_MSIX)
		ret = xen_pci_frontend_enable_msix(dev, v, nvec);
	else
		ret = xen_pci_frontend_enable_msi(dev, v);
	if (ret)
		goto error;
	i = 0;
	for_each_pci_msi_entry(msidesc, dev) {
		irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
					       (type == PCI_CAP_ID_MSI) ? nvec : 1,
					       (type == PCI_CAP_ID_MSIX) ?
					       "pcifront-msi-x" :
					       "pcifront-msi",
						DOMID_SELF);
		if (irq < 0) {
			ret = irq;
			goto free;
		}
		i++;
	}
	kfree(v);
	return 0;

error:
	if (ret == -ENOSYS)
		dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
	else if (ret)
		dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
free:
	kfree(v);
	return ret;
}

#define XEN_PIRQ_MSI_DATA  (MSI_DATA_TRIGGER_EDGE | \
		MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))

static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
		struct msi_msg *msg)
{
	/* We set vector == 0 to tell the hypervisor we don't care about it,
	 * but we want a pirq setup instead.
	 * We use the dest_id field to pass the pirq that we want. */
	msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
	msg->address_lo =
		MSI_ADDR_BASE_LO |
		MSI_ADDR_DEST_MODE_PHYSICAL |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DEST_ID(pirq);

	msg->data = XEN_PIRQ_MSI_DATA;
}

static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int irq, pirq;
	struct msi_desc *msidesc;
	struct msi_msg msg;

	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;

	for_each_pci_msi_entry(msidesc, dev) {
		pirq = xen_allocate_pirq_msi(dev, msidesc);
		if (pirq < 0) {
			irq = -ENODEV;
			goto error;
		}
		xen_msi_compose_msg(dev, pirq, &msg);
		__pci_write_msi_msg(msidesc, &msg);
		dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
		irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
					       (type == PCI_CAP_ID_MSI) ? nvec : 1,
					       (type == PCI_CAP_ID_MSIX) ?
					       "msi-x" : "msi",
					       DOMID_SELF);
		if (irq < 0)
			goto error;
		dev_dbg(&dev->dev,
			"xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
	}
	return 0;

error:
	dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
		type == PCI_CAP_ID_MSI ? "" : "-X", irq);
	return irq;
}

#ifdef CONFIG_XEN_DOM0
static bool __read_mostly pci_seg_supported = true;

static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int ret = 0;
	struct msi_desc *msidesc;

	for_each_pci_msi_entry(msidesc, dev) {
		struct physdev_map_pirq map_irq;
		domid_t domid;

		domid = ret = xen_find_device_domain_owner(dev);
		/* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
		 * hence check ret value for < 0. */
		if (ret < 0)
			domid = DOMID_SELF;

		memset(&map_irq, 0, sizeof(map_irq));
		map_irq.domid = domid;
		map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
		map_irq.index = -1;
		map_irq.pirq = -1;
		map_irq.bus = dev->bus->number |
			      (pci_domain_nr(dev->bus) << 16);
		map_irq.devfn = dev->devfn;

		if (type == PCI_CAP_ID_MSI && nvec > 1) {
			map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
			map_irq.entry_nr = nvec;
		} else if (type == PCI_CAP_ID_MSIX) {
			int pos;
			unsigned long flags;
			u32 table_offset, bir;

			pos = dev->msix_cap;
			pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
					      &table_offset);
			bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
			flags = pci_resource_flags(dev, bir);
			if (!flags || (flags & IORESOURCE_UNSET))
				return -EINVAL;

			map_irq.table_base = pci_resource_start(dev, bir);
			map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
		}

		ret = -EINVAL;
		if (pci_seg_supported)
			ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
						    &map_irq);
		if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
			/*
			 * If MAP_PIRQ_TYPE_MULTI_MSI is not available
			 * there's nothing else we can do in this case.
			 * Just set ret > 0 so driver can retry with
			 * single MSI.
			 */
			ret = 1;
			goto out;
		}
		if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
			map_irq.type = MAP_PIRQ_TYPE_MSI;
			map_irq.index = -1;
			map_irq.pirq = -1;
			map_irq.bus = dev->bus->number;
			ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
						    &map_irq);
			if (ret != -EINVAL)
				pci_seg_supported = false;
		}
		if (ret) {
			dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
				 ret, domid);
			goto out;
		}

		ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
		                               (type == PCI_CAP_ID_MSI) ? nvec : 1,
		                               (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
		                               domid);
		if (ret < 0)
			goto out;
	}
	ret = 0;
out:
	return ret;
}

static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
{
	int ret = 0;

	if (pci_seg_supported) {
		struct physdev_pci_device restore_ext;

		restore_ext.seg = pci_domain_nr(dev->bus);
		restore_ext.bus = dev->bus->number;
		restore_ext.devfn = dev->devfn;
		ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
					&restore_ext);
		if (ret == -ENOSYS)
			pci_seg_supported = false;
		WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
	}
	if (!pci_seg_supported) {
		struct physdev_restore_msi restore;

		restore.bus = dev->bus->number;
		restore.devfn = dev->devfn;
		ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
		WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
	}
}
#endif

static void xen_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *msidesc;

	msidesc = first_pci_msi_entry(dev);
	if (msidesc->msi_attrib.is_msix)
		xen_pci_frontend_disable_msix(dev);
	else
		xen_pci_frontend_disable_msi(dev);

	/* Free the IRQ's and the msidesc using the generic code. */
	default_teardown_msi_irqs(dev);
}

static void xen_teardown_msi_irq(unsigned int irq)
{
	xen_destroy_irq(irq);
}

#endif

int __init pci_xen_init(void)
{
	if (!xen_pv_domain() || xen_initial_domain())
		return -ENODEV;

	printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");

	pcibios_set_cache_line_size();

	pcibios_enable_irq = xen_pcifront_enable_irq;
	pcibios_disable_irq = NULL;

#ifdef CONFIG_ACPI
	/* Keep ACPI out of the picture */
	acpi_noirq = 1;
#endif

#ifdef CONFIG_PCI_MSI
	x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
	pci_msi_ignore_mask = 1;
#endif
	return 0;
}

#ifdef CONFIG_PCI_MSI
void __init xen_msi_init(void)
{
	if (!disable_apic) {
		/*
		 * If hardware supports (x2)APIC virtualization (as indicated
		 * by hypervisor's leaf 4) then we don't need to use pirqs/
		 * event channels for MSI handling and instead use regular
		 * APIC processing
		 */
		uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);

		if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
		    ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
			return;
	}

	x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
}
#endif

int __init pci_xen_hvm_init(void)
{
	if (!xen_feature(XENFEAT_hvm_pirqs))
		return 0;

#ifdef CONFIG_ACPI
	/*
	 * We don't want to change the actual ACPI delivery model,
	 * just how GSIs get registered.
	 */
	__acpi_register_gsi = acpi_register_gsi_xen_hvm;
	__acpi_unregister_gsi = NULL;
#endif

#ifdef CONFIG_PCI_MSI
	/*
	 * We need to wait until after x2apic is initialized
	 * before we can set MSI IRQ ops.
	 */
	x86_platform.apic_post_init = xen_msi_init;
#endif
	return 0;
}

#ifdef CONFIG_XEN_DOM0
int __init pci_xen_initial_domain(void)
{
	int irq;

#ifdef CONFIG_PCI_MSI
	x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
	pci_msi_ignore_mask = 1;
#endif
	__acpi_register_gsi = acpi_register_gsi_xen;
	__acpi_unregister_gsi = NULL;
	/*
	 * Pre-allocate the legacy IRQs.  Use NR_LEGACY_IRQS here
	 * because we don't have a PIC and thus nr_legacy_irqs() is zero.
	 */
	for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
		int trigger, polarity;

		if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
			continue;

		xen_register_pirq(irq, -1 /* no GSI override */,
			trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
			true /* Map GSI to PIRQ */);
	}
	if (0 == nr_ioapics) {
		for (irq = 0; irq < nr_legacy_irqs(); irq++)
			xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
	}
	return 0;
}

struct xen_device_domain_owner {
	domid_t domain;
	struct pci_dev *dev;
	struct list_head list;
};

static DEFINE_SPINLOCK(dev_domain_list_spinlock);
static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);

static struct xen_device_domain_owner *find_device(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;

	list_for_each_entry(owner, &dev_domain_list, list) {
		if (owner->dev == dev)
			return owner;
	}
	return NULL;
}

int xen_find_device_domain_owner(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;
	int domain = -ENODEV;

	spin_lock(&dev_domain_list_spinlock);
	owner = find_device(dev);
	if (owner)
		domain = owner->domain;
	spin_unlock(&dev_domain_list_spinlock);
	return domain;
}
EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);

int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
{
	struct xen_device_domain_owner *owner;

	owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
	if (!owner)
		return -ENODEV;

	spin_lock(&dev_domain_list_spinlock);
	if (find_device(dev)) {
		spin_unlock(&dev_domain_list_spinlock);
		kfree(owner);
		return -EEXIST;
	}
	owner->domain = domain;
	owner->dev = dev;
	list_add_tail(&owner->list, &dev_domain_list);
	spin_unlock(&dev_domain_list_spinlock);
	return 0;
}
EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);

int xen_unregister_device_domain_owner(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;

	spin_lock(&dev_domain_list_spinlock);
	owner = find_device(dev);
	if (!owner) {
		spin_unlock(&dev_domain_list_spinlock);
		return -ENODEV;
	}
	list_del(&owner->list);
	spin_unlock(&dev_domain_list_spinlock);
	kfree(owner);
	return 0;
}
EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
#endif
Commit	Line	Data
b5401a96	1	/*
996c34ae KRW	2	* Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
	3	* initial domain support. We also handle the DSDT _PRT callbacks for GSI's
	4	* used in HVM and initial domain mode (PV does not parse ACPI, so it has no
	5	* concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
	6	* 0xcf8 PCI configuration read/write.
b5401a96 AN	7	*
b5401a96 AN	8	* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
996c34ae KRW	9	* Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
996c34ae KRW	10	* Stefano Stabellini <stefano.stabellini@eu.citrix.com>
b5401a96	11	*/
eb008eb6	12	#include <linux/export.h>
b5401a96 AN	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/acpi.h>
	16
	17	#include <linux/io.h>
0e058e52	18	#include <asm/io_apic.h>
b5401a96 AN	19	#include <asm/pci_x86.h>
	20
	21	#include <asm/xen/hypervisor.h>
	22
3942b740	23	#include <xen/features.h>
b5401a96 AN	24	#include <xen/events.h>
b5401a96 AN	25	#include <asm/xen/pci.h>
14520c92 BO	26	#include <asm/xen/cpuid.h>
14520c92 BO	27	#include <asm/apic.h>
95d76acc	28	#include <asm/i8259.h>
b5401a96	29
fef6e262 KRW	30	static int xen_pcifront_enable_irq(struct pci_dev *dev)
	31	{
	32	int rc;
	33	int share = 1;
	34	int pirq;
	35	u8 gsi;
	36
	37	rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
	38	if (rc < 0) {
	39	dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
	40	rc);
	41	return rc;
	42	}
78316ada KRW	43	/* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
78316ada KRW	44	pirq = gsi;
fef6e262	45
95d76acc	46	if (gsi < nr_legacy_irqs())
fef6e262 KRW	47	share = 0;
	48
	49	rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
	50	if (rc < 0) {
	51	dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
	52	gsi, pirq, rc);
	53	return rc;
	54	}
	55
	56	dev->irq = rc;
	57	dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
	58	return 0;
	59	}
	60
42a1de56	61	#ifdef CONFIG_ACPI
ed89eb63	62	static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
78316ada	63	bool set_pirq)
42a1de56	64	{
ed89eb63	65	int rc, pirq = -1, irq = -1;
42a1de56 SS	66	struct physdev_map_pirq map_irq;
	67	int shareable = 0;
	68	char *name;
	69
68c2c39a SS	70	irq = xen_irq_from_gsi(gsi);
	71	if (irq > 0)
	72	return irq;
	73
78316ada KRW	74	if (set_pirq)
	75	pirq = gsi;
	76
fef6e262 KRW	77	map_irq.domid = DOMID_SELF;
	78	map_irq.type = MAP_PIRQ_TYPE_GSI;
	79	map_irq.index = gsi;
	80	map_irq.pirq = pirq;
	81
	82	rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
	83	if (rc) {
	84	printk(KERN_WARNING "xen map irq failed %d\n", rc);
	85	return -1;
	86	}
	87
30bd35ed KRW	88	if (triggering == ACPI_EDGE_SENSITIVE) {
	89	shareable = 0;
	90	name = "ioapic-edge";
	91	} else {
	92	shareable = 1;
	93	name = "ioapic-level";
	94	}
	95
	96	if (gsi_override >= 0)
	97	gsi = gsi_override;
	98
ed89eb63	99	irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
30bd35ed KRW	100	if (irq < 0)
	101	goto out;
	102
ed89eb63	103	printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
fef6e262 KRW	104	out:
	105	return irq;
	106	}
	107
ed89eb63 KRW	108	static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
	109	int trigger, int polarity)
	110	{
	111	if (!xen_hvm_domain())
	112	return -1;
	113
78316ada KRW	114	return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
78316ada KRW	115	false /* no mapping of GSI to PIRQ */);
ed89eb63 KRW	116	}
	117
	118	#ifdef CONFIG_XEN_DOM0
fef6e262 KRW	119	static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
	120	{
	121	int rc, irq;
	122	struct physdev_setup_gsi setup_gsi;
	123
	124	if (!xen_pv_domain())
	125	return -1;
	126
	127	printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
	128	gsi, triggering, polarity);
	129
ed89eb63	130	irq = xen_register_pirq(gsi, gsi_override, triggering, true);
fef6e262 KRW	131
	132	setup_gsi.gsi = gsi;
	133	setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
	134	setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
	135
	136	rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
	137	if (rc == -EEXIST)
	138	printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
	139	else if (rc) {
	140	printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
	141	gsi, rc);
	142	}
	143
	144	return irq;
	145	}
	146
	147	static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
	148	int trigger, int polarity)
	149	{
	150	return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
	151	}
	152	#endif
d92edd81	153	#endif
fef6e262	154
b5401a96 AN	155	#if defined(CONFIG_PCI_MSI)
b5401a96 AN	156	#include <linux/msi.h>
809f9267	157	#include <asm/msidef.h>
b5401a96 AN	158
	159	struct xen_pci_frontend_ops *xen_pci_frontend;
	160	EXPORT_SYMBOL_GPL(xen_pci_frontend);
	161
fef6e262 KRW	162	static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	163	{
	164	int irq, ret, i;
	165	struct msi_desc *msidesc;
	166	int *v;
	167
884ac297 KRW	168	if (type == PCI_CAP_ID_MSI && nvec > 1)
	169	return 1;
	170
fef6e262 KRW	171	v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
	172	if (!v)
	173	return -ENOMEM;
	174
	175	if (type == PCI_CAP_ID_MSIX)
	176	ret = xen_pci_frontend_enable_msix(dev, v, nvec);
	177	else
	178	ret = xen_pci_frontend_enable_msi(dev, v);
	179	if (ret)
	180	goto error;
	181	i = 0;
39118e31	182	for_each_pci_msi_entry(msidesc, dev) {
dec02dea	183	irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
4892c9b4	184	(type == PCI_CAP_ID_MSI) ? nvec : 1,
fef6e262 KRW	185	(type == PCI_CAP_ID_MSIX) ?
	186	"pcifront-msi-x" :
	187	"pcifront-msi",
	188	DOMID_SELF);
e6599225 KRW	189	if (irq < 0) {
e6599225 KRW	190	ret = irq;
fef6e262	191	goto free;
e6599225	192	}
fef6e262 KRW	193	i++;
	194	}
	195	kfree(v);
	196	return 0;
	197
	198	error:
2cfec6a2 KRW	199	if (ret == -ENOSYS)
	200	dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
	201	else if (ret)
	202	dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
fef6e262 KRW	203	free:
	204	kfree(v);
	205	return ret;
	206	}
	207
af42b8d1 SS	208	#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE \| \
	209	MSI_DATA_LEVEL_ASSERT \| (3 << 8) \| MSI_DATA_VECTOR(0))
	210
809f9267 SS	211	static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
	212	struct msi_msg *msg)
	213	{
	214	/* We set vector == 0 to tell the hypervisor we don't care about it,
	215	* but we want a pirq setup instead.
	216	* We use the dest_id field to pass the pirq that we want. */
	217	msg->address_hi = MSI_ADDR_BASE_HI \| MSI_ADDR_EXT_DEST_ID(pirq);
	218	msg->address_lo =
	219	MSI_ADDR_BASE_LO \|
	220	MSI_ADDR_DEST_MODE_PHYSICAL \|
	221	MSI_ADDR_REDIRECTION_CPU \|
	222	MSI_ADDR_DEST_ID(pirq);
	223
af42b8d1	224	msg->data = XEN_PIRQ_MSI_DATA;
809f9267 SS	225	}
	226
	227	static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	228	{
bf480d95	229	int irq, pirq;
809f9267 SS	230	struct msi_desc *msidesc;
	231	struct msi_msg msg;
	232
884ac297 KRW	233	if (type == PCI_CAP_ID_MSI && nvec > 1)
	234	return 1;
	235
39118e31	236	for_each_pci_msi_entry(msidesc, dev) {
c74fd80f DS	237	pirq = xen_allocate_pirq_msi(dev, msidesc);
	238	if (pirq < 0) {
	239	irq = -ENODEV;
	240	goto error;
af42b8d1	241	}
c74fd80f DS	242	xen_msi_compose_msg(dev, pirq, &msg);
	243	__pci_write_msi_msg(msidesc, &msg);
	244	dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
dec02dea	245	irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
4892c9b4	246	(type == PCI_CAP_ID_MSI) ? nvec : 1,
bf480d95	247	(type == PCI_CAP_ID_MSIX) ?
beafbdc1 KRW	248	"msi-x" : "msi",
beafbdc1 KRW	249	DOMID_SELF);
bf480d95	250	if (irq < 0)
809f9267	251	goto error;
bf480d95 IC	252	dev_dbg(&dev->dev,
bf480d95 IC	253	"xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
809f9267 SS	254	}
	255	return 0;
	256
809f9267	257	error:
577f79e4 KRW	258	dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
577f79e4 KRW	259	type == PCI_CAP_ID_MSI ? "" : "-X", irq);
e6599225	260	return irq;
809f9267 SS	261	}
809f9267 SS	262
260a7d4c	263	#ifdef CONFIG_XEN_DOM0
55e901fc JB	264	static bool __read_mostly pci_seg_supported = true;
55e901fc JB	265
f731e3ef QH	266	static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
f731e3ef QH	267	{
71eef7d1	268	int ret = 0;
f731e3ef QH	269	struct msi_desc *msidesc;
f731e3ef QH	270
39118e31	271	for_each_pci_msi_entry(msidesc, dev) {
71eef7d1	272	struct physdev_map_pirq map_irq;
beafbdc1 KRW	273	domid_t domid;
	274
	275	domid = ret = xen_find_device_domain_owner(dev);
	276	/* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
	277	* hence check ret value for < 0. */
	278	if (ret < 0)
	279	domid = DOMID_SELF;
71eef7d1 IC	280
71eef7d1 IC	281	memset(&map_irq, 0, sizeof(map_irq));
beafbdc1	282	map_irq.domid = domid;
55e901fc	283	map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
71eef7d1 IC	284	map_irq.index = -1;
71eef7d1 IC	285	map_irq.pirq = -1;
55e901fc JB	286	map_irq.bus = dev->bus->number \|
55e901fc JB	287	(pci_domain_nr(dev->bus) << 16);
71eef7d1 IC	288	map_irq.devfn = dev->devfn;
71eef7d1 IC	289
4892c9b4 RPM	290	if (type == PCI_CAP_ID_MSI && nvec > 1) {
	291	map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
	292	map_irq.entry_nr = nvec;
	293	} else if (type == PCI_CAP_ID_MSIX) {
71eef7d1	294	int pos;
6a878e50	295	unsigned long flags;
71eef7d1 IC	296	u32 table_offset, bir;
71eef7d1 IC	297
7c86617d	298	pos = dev->msix_cap;
71eef7d1 IC	299	pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
71eef7d1 IC	300	&table_offset);
4be6bfe2	301	bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
6a878e50 YW	302	flags = pci_resource_flags(dev, bir);
	303	if (!flags \|\| (flags & IORESOURCE_UNSET))
	304	return -EINVAL;
71eef7d1 IC	305
	306	map_irq.table_base = pci_resource_start(dev, bir);
	307	map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
	308	}
	309
55e901fc JB	310	ret = -EINVAL;
	311	if (pci_seg_supported)
	312	ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
	313	&map_irq);
4892c9b4 RPM	314	if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
	315	/*
	316	* If MAP_PIRQ_TYPE_MULTI_MSI is not available
	317	* there's nothing else we can do in this case.
	318	* Just set ret > 0 so driver can retry with
	319	* single MSI.
	320	*/
	321	ret = 1;
	322	goto out;
	323	}
55e901fc JB	324	if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
	325	map_irq.type = MAP_PIRQ_TYPE_MSI;
	326	map_irq.index = -1;
	327	map_irq.pirq = -1;
	328	map_irq.bus = dev->bus->number;
	329	ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
	330	&map_irq);
	331	if (ret != -EINVAL)
	332	pci_seg_supported = false;
	333	}
71eef7d1	334	if (ret) {
beafbdc1 KRW	335	dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
beafbdc1 KRW	336	ret, domid);
71eef7d1 IC	337	goto out;
	338	}
	339
4892c9b4 RPM	340	ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
	341	(type == PCI_CAP_ID_MSI) ? nvec : 1,
	342	(type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
	343	domid);
71eef7d1 IC	344	if (ret < 0)
71eef7d1 IC	345	goto out;
f731e3ef	346	}
71eef7d1 IC	347	ret = 0;
	348	out:
	349	return ret;
f731e3ef	350	}
8605c684	351
ac8344c4	352	static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
8605c684 TL	353	{
	354	int ret = 0;
	355
	356	if (pci_seg_supported) {
	357	struct physdev_pci_device restore_ext;
	358
	359	restore_ext.seg = pci_domain_nr(dev->bus);
	360	restore_ext.bus = dev->bus->number;
	361	restore_ext.devfn = dev->devfn;
	362	ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
	363	&restore_ext);
	364	if (ret == -ENOSYS)
	365	pci_seg_supported = false;
	366	WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
	367	}
	368	if (!pci_seg_supported) {
	369	struct physdev_restore_msi restore;
	370
	371	restore.bus = dev->bus->number;
	372	restore.devfn = dev->devfn;
	373	ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
	374	WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
	375	}
	376	}
b5401a96 AN	377	#endif
b5401a96 AN	378
fef6e262	379	static void xen_teardown_msi_irqs(struct pci_dev *dev)
b5401a96	380	{
fef6e262	381	struct msi_desc *msidesc;
b5401a96	382
39118e31	383	msidesc = first_pci_msi_entry(dev);
fef6e262 KRW	384	if (msidesc->msi_attrib.is_msix)
	385	xen_pci_frontend_disable_msix(dev);
	386	else
	387	xen_pci_frontend_disable_msi(dev);
b5401a96	388
fef6e262 KRW	389	/* Free the IRQ's and the msidesc using the generic code. */
	390	default_teardown_msi_irqs(dev);
	391	}
f4d0635b	392
fef6e262 KRW	393	static void xen_teardown_msi_irq(unsigned int irq)
	394	{
	395	xen_destroy_irq(irq);
	396	}
03f56e42	397
fef6e262	398	#endif
3f2a230c	399
b5401a96 AN	400	int __init pci_xen_init(void)
	401	{
	402	if (!xen_pv_domain() \|\| xen_initial_domain())
	403	return -ENODEV;
	404
	405	printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
	406
	407	pcibios_set_cache_line_size();
	408
	409	pcibios_enable_irq = xen_pcifront_enable_irq;
	410	pcibios_disable_irq = NULL;
	411
	412	#ifdef CONFIG_ACPI
	413	/* Keep ACPI out of the picture */
	414	acpi_noirq = 1;
	415	#endif
	416
b5401a96 AN	417	#ifdef CONFIG_PCI_MSI
	418	x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
	419	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	420	x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
38737d82	421	pci_msi_ignore_mask = 1;
b5401a96 AN	422	#endif
	423	return 0;
	424	}
3942b740	425
066d79e4 BO	426	#ifdef CONFIG_PCI_MSI
	427	void __init xen_msi_init(void)
	428	{
14520c92 BO	429	if (!disable_apic) {
	430	/*
	431	* If hardware supports (x2)APIC virtualization (as indicated
	432	* by hypervisor's leaf 4) then we don't need to use pirqs/
	433	* event channels for MSI handling and instead use regular
	434	* APIC processing
	435	*/
	436	uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
	437
	438	if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) \|\|
93984fbd	439	((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
14520c92 BO	440	return;
	441	}
	442
066d79e4 BO	443	x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
	444	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	445	}
	446	#endif
	447
3942b740 SS	448	int __init pci_xen_hvm_init(void)
3942b740 SS	449	{
72a9b186	450	if (!xen_feature(XENFEAT_hvm_pirqs))
3942b740 SS	451	return 0;
	452
	453	#ifdef CONFIG_ACPI
	454	/*
	455	* We don't want to change the actual ACPI delivery model,
	456	* just how GSIs get registered.
	457	*/
	458	__acpi_register_gsi = acpi_register_gsi_xen_hvm;
8abb850a	459	__acpi_unregister_gsi = NULL;
3942b740	460	#endif
809f9267 SS	461
809f9267 SS	462	#ifdef CONFIG_PCI_MSI
066d79e4 BO	463	/*
	464	* We need to wait until after x2apic is initialized
	465	* before we can set MSI IRQ ops.
	466	*/
	467	x86_platform.apic_post_init = xen_msi_init;
809f9267	468	#endif
3942b740 SS	469	return 0;
3942b740 SS	470	}
38aa66fc JF	471
38aa66fc JF	472	#ifdef CONFIG_XEN_DOM0
a0ee0567	473	int __init pci_xen_initial_domain(void)
38aa66fc	474	{
78316ada	475	int irq;
a0ee0567	476
f731e3ef QH	477	#ifdef CONFIG_PCI_MSI
	478	x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
	479	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
8605c684	480	x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
38737d82	481	pci_msi_ignore_mask = 1;
f731e3ef	482	#endif
38aa66fc	483	__acpi_register_gsi = acpi_register_gsi_xen;
8abb850a	484	__acpi_unregister_gsi = NULL;
702f9260 SS	485	/*
	486	* Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here
	487	* because we don't have a PIC and thus nr_legacy_irqs() is zero.
	488	*/
	489	for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
38aa66fc JF	490	int trigger, polarity;
	491
	492	if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
	493	continue;
	494
ee339fe6	495	xen_register_pirq(irq, -1 /* no GSI override */,
ed89eb63	496	trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
78316ada	497	true /* Map GSI to PIRQ */);
38aa66fc	498	}
9b6519db	499	if (0 == nr_ioapics) {
95d76acc	500	for (irq = 0; irq < nr_legacy_irqs(); irq++)
78316ada	501	xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
9b6519db	502	}
a0ee0567	503	return 0;
38aa66fc	504	}
c55fa78b KRW	505
	506	struct xen_device_domain_owner {
	507	domid_t domain;
	508	struct pci_dev *dev;
	509	struct list_head list;
	510	};
	511
	512	static DEFINE_SPINLOCK(dev_domain_list_spinlock);
	513	static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);
	514
	515	static struct xen_device_domain_owner find_device(struct pci_dev dev)
	516	{
	517	struct xen_device_domain_owner *owner;
	518
	519	list_for_each_entry(owner, &dev_domain_list, list) {
	520	if (owner->dev == dev)
	521	return owner;
	522	}
	523	return NULL;
	524	}
	525
	526	int xen_find_device_domain_owner(struct pci_dev *dev)
	527	{
	528	struct xen_device_domain_owner *owner;
	529	int domain = -ENODEV;
	530
	531	spin_lock(&dev_domain_list_spinlock);
	532	owner = find_device(dev);
	533	if (owner)
	534	domain = owner->domain;
	535	spin_unlock(&dev_domain_list_spinlock);
	536	return domain;
	537	}
	538	EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);
	539
	540	int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
	541	{
	542	struct xen_device_domain_owner *owner;
	543
	544	owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
	545	if (!owner)
	546	return -ENODEV;
	547
	548	spin_lock(&dev_domain_list_spinlock);
	549	if (find_device(dev)) {
	550	spin_unlock(&dev_domain_list_spinlock);
	551	kfree(owner);
	552	return -EEXIST;
	553	}
	554	owner->domain = domain;
	555	owner->dev = dev;
	556	list_add_tail(&owner->list, &dev_domain_list);
	557	spin_unlock(&dev_domain_list_spinlock);
	558	return 0;
	559	}
	560	EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);
	561
	562	int xen_unregister_device_domain_owner(struct pci_dev *dev)
	563	{
	564	struct xen_device_domain_owner *owner;
	565
	566	spin_lock(&dev_domain_list_spinlock);
	567	owner = find_device(dev);
	568	if (!owner) {
569	spin_unlock(&dev_domain_list_spinlock);
570	return -ENODEV;
571	}
572	list_del(&owner->list);
573	spin_unlock(&dev_domain_list_spinlock);
574	kfree(owner);
575	return 0;
576	}
577	EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
7c1bfd68	578	#endif