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Commit | Line | Data |
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3f4110a4 | 1 | /* |
05454c26 | 2 | * intel-mid.c: Intel MID platform setup code |
3f4110a4 | 3 | * |
05454c26 | 4 | * (C) Copyright 2008, 2012 Intel Corporation |
3f4110a4 | 5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) |
05454c26 | 6 | * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> |
3f4110a4 TG |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; version 2 | |
11 | * of the License. | |
12 | */ | |
1da4b1c6 | 13 | |
712b6aa8 | 14 | #define pr_fmt(fmt) "intel_mid: " fmt |
1da4b1c6 | 15 | |
3f4110a4 | 16 | #include <linux/init.h> |
16ab5395 | 17 | #include <linux/kernel.h> |
efe3ed98 FT |
18 | #include <linux/interrupt.h> |
19 | #include <linux/scatterlist.h> | |
16ab5395 JP |
20 | #include <linux/sfi.h> |
21 | #include <linux/irq.h> | |
cf089455 | 22 | #include <linux/module.h> |
42c2544b | 23 | #include <linux/notifier.h> |
3f4110a4 TG |
24 | |
25 | #include <asm/setup.h> | |
16ab5395 JP |
26 | #include <asm/mpspec_def.h> |
27 | #include <asm/hw_irq.h> | |
28 | #include <asm/apic.h> | |
29 | #include <asm/io_apic.h> | |
05454c26 KS |
30 | #include <asm/intel-mid.h> |
31 | #include <asm/intel_mid_vrtc.h> | |
5b78b672 JP |
32 | #include <asm/io.h> |
33 | #include <asm/i8259.h> | |
1da4b1c6 | 34 | #include <asm/intel_scu_ipc.h> |
3746c6b6 | 35 | #include <asm/apb_timer.h> |
cfb505a7 | 36 | #include <asm/reboot.h> |
3f4110a4 | 37 | |
ecd6910d DC |
38 | #include "intel_mid_weak_decls.h" |
39 | ||
a875c019 JP |
40 | /* |
41 | * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, | |
712b6aa8 | 42 | * cmdline option x86_intel_mid_timer can be used to override the configuration |
a875c019 JP |
43 | * to prefer one or the other. |
44 | * at runtime, there are basically three timer configurations: | |
45 | * 1. per cpu apbt clock only | |
46 | * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only | |
47 | * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. | |
48 | * | |
49 | * by default (without cmdline option), platform code first detects cpu type | |
50 | * to see if we are on lincroft or penwell, then set up both lapic or apbt | |
51 | * clocks accordingly. | |
52 | * i.e. by default, medfield uses configuration #2, moorestown uses #1. | |
53 | * config #3 is supported but not recommended on medfield. | |
54 | * | |
55 | * rating and feature summary: | |
56 | * lapic (with C3STOP) --------- 100 | |
57 | * apbt (always-on) ------------ 110 | |
58 | * lapic (always-on,ARAT) ------ 150 | |
59 | */ | |
60 | ||
712b6aa8 | 61 | enum intel_mid_timer_options intel_mid_timer_options; |
a875c019 | 62 | |
85611e3f KS |
63 | /* intel_mid_ops to store sub arch ops */ |
64 | struct intel_mid_ops *intel_mid_ops; | |
65 | /* getter function for sub arch ops*/ | |
66 | static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; | |
712b6aa8 KS |
67 | enum intel_mid_cpu_type __intel_mid_cpu_chip; |
68 | EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); | |
a0c173bd | 69 | |
85611e3f KS |
70 | static void intel_mid_power_off(void) |
71 | { | |
72 | }; | |
73 | ||
712b6aa8 | 74 | static void intel_mid_reboot(void) |
48bc5562 | 75 | { |
1a8359e4 | 76 | intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); |
48bc5562 JP |
77 | } |
78 | ||
85611e3f KS |
79 | static unsigned long __init intel_mid_calibrate_tsc(void) |
80 | { | |
81 | return 0; | |
82 | } | |
83 | ||
712b6aa8 | 84 | static void __init intel_mid_time_init(void) |
3746c6b6 | 85 | { |
7f05dec3 | 86 | sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); |
712b6aa8 KS |
87 | switch (intel_mid_timer_options) { |
88 | case INTEL_MID_TIMER_APBT_ONLY: | |
a875c019 | 89 | break; |
712b6aa8 | 90 | case INTEL_MID_TIMER_LAPIC_APBT: |
a875c019 JP |
91 | x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; |
92 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; | |
93 | break; | |
94 | default: | |
95 | if (!boot_cpu_has(X86_FEATURE_ARAT)) | |
96 | break; | |
97 | x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; | |
98 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; | |
99 | return; | |
100 | } | |
101 | /* we need at least one APB timer */ | |
3746c6b6 JP |
102 | pre_init_apic_IRQ0(); |
103 | apbt_time_init(); | |
104 | } | |
105 | ||
aeeca404 | 106 | static void intel_mid_arch_setup(void) |
3746c6b6 | 107 | { |
85611e3f | 108 | if (boot_cpu_data.x86 != 6) { |
1a8359e4 | 109 | pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", |
a0c173bd | 110 | boot_cpu_data.x86, boot_cpu_data.x86_model); |
712b6aa8 | 111 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; |
85611e3f KS |
112 | goto out; |
113 | } | |
114 | ||
115 | switch (boot_cpu_data.x86_model) { | |
116 | case 0x35: | |
117 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; | |
118 | break; | |
bc20aa48 DC |
119 | case 0x3C: |
120 | case 0x4A: | |
121 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; | |
122 | break; | |
85611e3f KS |
123 | case 0x27: |
124 | default: | |
125 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; | |
126 | break; | |
a0c173bd | 127 | } |
85611e3f KS |
128 | |
129 | if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) | |
130 | intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); | |
131 | else { | |
132 | intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); | |
579deee5 | 133 | pr_info("ARCH: Unknown SoC, assuming PENWELL!\n"); |
85611e3f KS |
134 | } |
135 | ||
136 | out: | |
137 | if (intel_mid_ops->arch_setup) | |
138 | intel_mid_ops->arch_setup(); | |
a0c173bd | 139 | } |
3746c6b6 | 140 | |
6d2cce62 | 141 | /* MID systems don't have i8042 controller */ |
712b6aa8 | 142 | static int intel_mid_i8042_detect(void) |
6d2cce62 FT |
143 | { |
144 | return 0; | |
145 | } | |
146 | ||
064a59b6 JP |
147 | /* |
148 | * Moorestown does not have external NMI source nor port 0x61 to report | |
149 | * NMI status. The possible NMI sources are from pmu as a result of NMI | |
150 | * watchdog or lock debug. Reading io port 0x61 results in 0xff which | |
151 | * misled NMI handler. | |
152 | */ | |
712b6aa8 | 153 | static unsigned char intel_mid_get_nmi_reason(void) |
064a59b6 JP |
154 | { |
155 | return 0; | |
156 | } | |
157 | ||
3f4110a4 TG |
158 | /* |
159 | * Moorestown specific x86_init function overrides and early setup | |
160 | * calls. | |
161 | */ | |
712b6aa8 | 162 | void __init x86_intel_mid_early_setup(void) |
3f4110a4 TG |
163 | { |
164 | x86_init.resources.probe_roms = x86_init_noop; | |
165 | x86_init.resources.reserve_resources = x86_init_noop; | |
5b78b672 | 166 | |
712b6aa8 | 167 | x86_init.timers.timer_init = intel_mid_time_init; |
a875c019 | 168 | x86_init.timers.setup_percpu_clockev = x86_init_noop; |
3746c6b6 JP |
169 | |
170 | x86_init.irqs.pre_vector_init = x86_init_noop; | |
171 | ||
712b6aa8 | 172 | x86_init.oem.arch_setup = intel_mid_arch_setup; |
a0c173bd | 173 | |
a875c019 | 174 | x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; |
3746c6b6 | 175 | |
712b6aa8 KS |
176 | x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; |
177 | x86_platform.i8042_detect = intel_mid_i8042_detect; | |
178 | x86_init.timers.wallclock_init = intel_mid_rtc_init; | |
179 | x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; | |
064a59b6 | 180 | |
712b6aa8 | 181 | x86_init.pci.init = intel_mid_pci_init; |
af2730f6 JP |
182 | x86_init.pci.fixup_irqs = x86_init_noop; |
183 | ||
5b78b672 | 184 | legacy_pic = &null_legacy_pic; |
fea24e28 | 185 | |
712b6aa8 KS |
186 | pm_power_off = intel_mid_power_off; |
187 | machine_ops.emergency_restart = intel_mid_reboot; | |
cfb505a7 | 188 | |
fea24e28 JP |
189 | /* Avoid searching for BIOS MP tables */ |
190 | x86_init.mpparse.find_smp_config = x86_init_noop; | |
191 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; | |
9d90e49d | 192 | set_bit(MP_BUS_ISA, mp_bus_not_pci); |
3f4110a4 | 193 | } |
a875c019 JP |
194 | |
195 | /* | |
196 | * if user does not want to use per CPU apb timer, just give it a lower rating | |
197 | * than local apic timer and skip the late per cpu timer init. | |
198 | */ | |
712b6aa8 | 199 | static inline int __init setup_x86_intel_mid_timer(char *arg) |
a875c019 JP |
200 | { |
201 | if (!arg) | |
202 | return -EINVAL; | |
203 | ||
204 | if (strcmp("apbt_only", arg) == 0) | |
712b6aa8 | 205 | intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; |
a875c019 | 206 | else if (strcmp("lapic_and_apbt", arg) == 0) |
712b6aa8 | 207 | intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; |
a875c019 | 208 | else { |
712b6aa8 KS |
209 | pr_warn("X86 INTEL_MID timer option %s not recognised" |
210 | " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", | |
a875c019 JP |
211 | arg); |
212 | return -EINVAL; | |
213 | } | |
214 | return 0; | |
215 | } | |
712b6aa8 | 216 | __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); |
1da4b1c6 | 217 |