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Commit | Line | Data |
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3f4110a4 TG |
1 | /* |
2 | * mrst.c: Intel Moorestown platform specific setup code | |
3 | * | |
4 | * (C) Copyright 2008 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
1da4b1c6 FT |
12 | |
13 | #define pr_fmt(fmt) "mrst: " fmt | |
14 | ||
3f4110a4 | 15 | #include <linux/init.h> |
16ab5395 | 16 | #include <linux/kernel.h> |
efe3ed98 FT |
17 | #include <linux/interrupt.h> |
18 | #include <linux/scatterlist.h> | |
16ab5395 | 19 | #include <linux/sfi.h> |
1da4b1c6 FT |
20 | #include <linux/intel_pmic_gpio.h> |
21 | #include <linux/spi/spi.h> | |
22 | #include <linux/i2c.h> | |
23 | #include <linux/i2c/pca953x.h> | |
24 | #include <linux/gpio_keys.h> | |
25 | #include <linux/input.h> | |
26 | #include <linux/platform_device.h> | |
16ab5395 | 27 | #include <linux/irq.h> |
cf089455 | 28 | #include <linux/module.h> |
42c2544b | 29 | #include <linux/notifier.h> |
360545c1 | 30 | #include <linux/mfd/intel_msic.h> |
3f4110a4 TG |
31 | |
32 | #include <asm/setup.h> | |
16ab5395 JP |
33 | #include <asm/mpspec_def.h> |
34 | #include <asm/hw_irq.h> | |
35 | #include <asm/apic.h> | |
36 | #include <asm/io_apic.h> | |
5b78b672 | 37 | #include <asm/mrst.h> |
168202c7 | 38 | #include <asm/mrst-vrtc.h> |
5b78b672 JP |
39 | #include <asm/io.h> |
40 | #include <asm/i8259.h> | |
1da4b1c6 | 41 | #include <asm/intel_scu_ipc.h> |
3746c6b6 | 42 | #include <asm/apb_timer.h> |
cfb505a7 | 43 | #include <asm/reboot.h> |
3f4110a4 | 44 | |
a875c019 JP |
45 | /* |
46 | * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, | |
47 | * cmdline option x86_mrst_timer can be used to override the configuration | |
48 | * to prefer one or the other. | |
49 | * at runtime, there are basically three timer configurations: | |
50 | * 1. per cpu apbt clock only | |
51 | * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only | |
52 | * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. | |
53 | * | |
54 | * by default (without cmdline option), platform code first detects cpu type | |
55 | * to see if we are on lincroft or penwell, then set up both lapic or apbt | |
56 | * clocks accordingly. | |
57 | * i.e. by default, medfield uses configuration #2, moorestown uses #1. | |
58 | * config #3 is supported but not recommended on medfield. | |
59 | * | |
60 | * rating and feature summary: | |
61 | * lapic (with C3STOP) --------- 100 | |
62 | * apbt (always-on) ------------ 110 | |
63 | * lapic (always-on,ARAT) ------ 150 | |
64 | */ | |
65 | ||
14671386 | 66 | __cpuinitdata enum mrst_timer_options mrst_timer_options; |
a875c019 | 67 | |
16ab5395 JP |
68 | static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM]; |
69 | static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; | |
a75af580 PA |
70 | enum mrst_cpu_type __mrst_cpu_chip; |
71 | EXPORT_SYMBOL_GPL(__mrst_cpu_chip); | |
a0c173bd | 72 | |
16ab5395 JP |
73 | int sfi_mtimer_num; |
74 | ||
cf089455 FT |
75 | struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; |
76 | EXPORT_SYMBOL_GPL(sfi_mrtc_array); | |
77 | int sfi_mrtc_num; | |
78 | ||
16ab5395 JP |
79 | /* parse all the mtimer info to a static mtimer array */ |
80 | static int __init sfi_parse_mtmr(struct sfi_table_header *table) | |
81 | { | |
82 | struct sfi_table_simple *sb; | |
83 | struct sfi_timer_table_entry *pentry; | |
84 | struct mpc_intsrc mp_irq; | |
85 | int totallen; | |
86 | ||
87 | sb = (struct sfi_table_simple *)table; | |
88 | if (!sfi_mtimer_num) { | |
89 | sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb, | |
90 | struct sfi_timer_table_entry); | |
91 | pentry = (struct sfi_timer_table_entry *) sb->pentry; | |
92 | totallen = sfi_mtimer_num * sizeof(*pentry); | |
93 | memcpy(sfi_mtimer_array, pentry, totallen); | |
94 | } | |
95 | ||
1da4b1c6 | 96 | pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num); |
16ab5395 JP |
97 | pentry = sfi_mtimer_array; |
98 | for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) { | |
1da4b1c6 | 99 | pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz," |
16ab5395 JP |
100 | " irq = %d\n", totallen, (u32)pentry->phys_addr, |
101 | pentry->freq_hz, pentry->irq); | |
102 | if (!pentry->irq) | |
103 | continue; | |
9d90e49d | 104 | mp_irq.type = MP_INTSRC; |
16ab5395 JP |
105 | mp_irq.irqtype = mp_INT; |
106 | /* triggering mode edge bit 2-3, active high polarity bit 0-1 */ | |
107 | mp_irq.irqflag = 5; | |
9d90e49d | 108 | mp_irq.srcbus = MP_BUS_ISA; |
16ab5395 JP |
109 | mp_irq.srcbusirq = pentry->irq; /* IRQ */ |
110 | mp_irq.dstapic = MP_APIC_ALL; | |
111 | mp_irq.dstirq = pentry->irq; | |
2d8009ba | 112 | mp_save_irq(&mp_irq); |
16ab5395 JP |
113 | } |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | struct sfi_timer_table_entry *sfi_get_mtmr(int hint) | |
119 | { | |
120 | int i; | |
121 | if (hint < sfi_mtimer_num) { | |
122 | if (!sfi_mtimer_usage[hint]) { | |
123 | pr_debug("hint taken for timer %d irq %d\n",\ | |
124 | hint, sfi_mtimer_array[hint].irq); | |
125 | sfi_mtimer_usage[hint] = 1; | |
126 | return &sfi_mtimer_array[hint]; | |
127 | } | |
128 | } | |
129 | /* take the first timer available */ | |
130 | for (i = 0; i < sfi_mtimer_num;) { | |
131 | if (!sfi_mtimer_usage[i]) { | |
132 | sfi_mtimer_usage[i] = 1; | |
133 | return &sfi_mtimer_array[i]; | |
134 | } | |
135 | i++; | |
136 | } | |
137 | return NULL; | |
138 | } | |
139 | ||
140 | void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr) | |
141 | { | |
142 | int i; | |
143 | for (i = 0; i < sfi_mtimer_num;) { | |
144 | if (mtmr->irq == sfi_mtimer_array[i].irq) { | |
145 | sfi_mtimer_usage[i] = 0; | |
146 | return; | |
147 | } | |
148 | i++; | |
149 | } | |
150 | } | |
151 | ||
cf089455 FT |
152 | /* parse all the mrtc info to a global mrtc array */ |
153 | int __init sfi_parse_mrtc(struct sfi_table_header *table) | |
154 | { | |
155 | struct sfi_table_simple *sb; | |
156 | struct sfi_rtc_table_entry *pentry; | |
157 | struct mpc_intsrc mp_irq; | |
158 | ||
159 | int totallen; | |
160 | ||
161 | sb = (struct sfi_table_simple *)table; | |
162 | if (!sfi_mrtc_num) { | |
163 | sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb, | |
164 | struct sfi_rtc_table_entry); | |
165 | pentry = (struct sfi_rtc_table_entry *)sb->pentry; | |
166 | totallen = sfi_mrtc_num * sizeof(*pentry); | |
167 | memcpy(sfi_mrtc_array, pentry, totallen); | |
168 | } | |
169 | ||
1da4b1c6 | 170 | pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num); |
cf089455 FT |
171 | pentry = sfi_mrtc_array; |
172 | for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) { | |
1da4b1c6 | 173 | pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n", |
cf089455 | 174 | totallen, (u32)pentry->phys_addr, pentry->irq); |
9d90e49d | 175 | mp_irq.type = MP_INTSRC; |
cf089455 | 176 | mp_irq.irqtype = mp_INT; |
6f207e9b | 177 | mp_irq.irqflag = 0xf; /* level trigger and active low */ |
9d90e49d | 178 | mp_irq.srcbus = MP_BUS_ISA; |
cf089455 FT |
179 | mp_irq.srcbusirq = pentry->irq; /* IRQ */ |
180 | mp_irq.dstapic = MP_APIC_ALL; | |
181 | mp_irq.dstirq = pentry->irq; | |
2d8009ba | 182 | mp_save_irq(&mp_irq); |
cf089455 FT |
183 | } |
184 | return 0; | |
185 | } | |
186 | ||
3746c6b6 JP |
187 | static unsigned long __init mrst_calibrate_tsc(void) |
188 | { | |
189 | unsigned long flags, fast_calibrate; | |
190 | ||
191 | local_irq_save(flags); | |
192 | fast_calibrate = apbt_quick_calibrate(); | |
193 | local_irq_restore(flags); | |
194 | ||
195 | if (fast_calibrate) | |
196 | return fast_calibrate; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
8fab6af2 | 201 | static void __init mrst_time_init(void) |
3746c6b6 | 202 | { |
7f05dec3 | 203 | sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); |
a875c019 JP |
204 | switch (mrst_timer_options) { |
205 | case MRST_TIMER_APBT_ONLY: | |
206 | break; | |
207 | case MRST_TIMER_LAPIC_APBT: | |
208 | x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; | |
209 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; | |
210 | break; | |
211 | default: | |
212 | if (!boot_cpu_has(X86_FEATURE_ARAT)) | |
213 | break; | |
214 | x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; | |
215 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; | |
216 | return; | |
217 | } | |
218 | /* we need at least one APB timer */ | |
3746c6b6 JP |
219 | pre_init_apic_IRQ0(); |
220 | apbt_time_init(); | |
221 | } | |
222 | ||
8fab6af2 | 223 | static void __cpuinit mrst_arch_setup(void) |
3746c6b6 | 224 | { |
a0c173bd | 225 | if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27) |
a75af580 | 226 | __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL; |
a0c173bd | 227 | else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26) |
a75af580 | 228 | __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; |
a0c173bd JP |
229 | else { |
230 | pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n", | |
231 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
a75af580 | 232 | __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT; |
a0c173bd JP |
233 | } |
234 | pr_debug("Moorestown CPU %s identified\n", | |
a75af580 | 235 | (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ? |
a0c173bd JP |
236 | "Lincroft" : "Penwell"); |
237 | } | |
3746c6b6 | 238 | |
6d2cce62 FT |
239 | /* MID systems don't have i8042 controller */ |
240 | static int mrst_i8042_detect(void) | |
241 | { | |
242 | return 0; | |
243 | } | |
244 | ||
cfb505a7 AD |
245 | /* Reboot and power off are handled by the SCU on a MID device */ |
246 | static void mrst_power_off(void) | |
247 | { | |
248 | intel_scu_ipc_simple_command(0xf1, 1); | |
249 | } | |
250 | ||
251 | static void mrst_reboot(void) | |
252 | { | |
253 | intel_scu_ipc_simple_command(0xf1, 0); | |
254 | } | |
255 | ||
3f4110a4 TG |
256 | /* |
257 | * Moorestown specific x86_init function overrides and early setup | |
258 | * calls. | |
259 | */ | |
260 | void __init x86_mrst_early_setup(void) | |
261 | { | |
262 | x86_init.resources.probe_roms = x86_init_noop; | |
263 | x86_init.resources.reserve_resources = x86_init_noop; | |
5b78b672 | 264 | |
3746c6b6 | 265 | x86_init.timers.timer_init = mrst_time_init; |
a875c019 | 266 | x86_init.timers.setup_percpu_clockev = x86_init_noop; |
3746c6b6 JP |
267 | |
268 | x86_init.irqs.pre_vector_init = x86_init_noop; | |
269 | ||
a0c173bd JP |
270 | x86_init.oem.arch_setup = mrst_arch_setup; |
271 | ||
a875c019 | 272 | x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; |
3746c6b6 JP |
273 | |
274 | x86_platform.calibrate_tsc = mrst_calibrate_tsc; | |
6d2cce62 | 275 | x86_platform.i8042_detect = mrst_i8042_detect; |
168202c7 | 276 | x86_init.timers.wallclock_init = mrst_rtc_init; |
af2730f6 JP |
277 | x86_init.pci.init = pci_mrst_init; |
278 | x86_init.pci.fixup_irqs = x86_init_noop; | |
279 | ||
5b78b672 | 280 | legacy_pic = &null_legacy_pic; |
fea24e28 | 281 | |
cfb505a7 AD |
282 | /* Moorestown specific power_off/restart method */ |
283 | pm_power_off = mrst_power_off; | |
284 | machine_ops.emergency_restart = mrst_reboot; | |
285 | ||
fea24e28 JP |
286 | /* Avoid searching for BIOS MP tables */ |
287 | x86_init.mpparse.find_smp_config = x86_init_noop; | |
288 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; | |
9d90e49d | 289 | set_bit(MP_BUS_ISA, mp_bus_not_pci); |
3f4110a4 | 290 | } |
a875c019 JP |
291 | |
292 | /* | |
293 | * if user does not want to use per CPU apb timer, just give it a lower rating | |
294 | * than local apic timer and skip the late per cpu timer init. | |
295 | */ | |
296 | static inline int __init setup_x86_mrst_timer(char *arg) | |
297 | { | |
298 | if (!arg) | |
299 | return -EINVAL; | |
300 | ||
301 | if (strcmp("apbt_only", arg) == 0) | |
302 | mrst_timer_options = MRST_TIMER_APBT_ONLY; | |
303 | else if (strcmp("lapic_and_apbt", arg) == 0) | |
304 | mrst_timer_options = MRST_TIMER_LAPIC_APBT; | |
305 | else { | |
306 | pr_warning("X86 MRST timer option %s not recognised" | |
307 | " use x86_mrst_timer=apbt_only or lapic_and_apbt\n", | |
308 | arg); | |
309 | return -EINVAL; | |
310 | } | |
311 | return 0; | |
312 | } | |
313 | __setup("x86_mrst_timer=", setup_x86_mrst_timer); | |
1da4b1c6 FT |
314 | |
315 | /* | |
316 | * Parsing GPIO table first, since the DEVS table will need this table | |
317 | * to map the pin name to the actual pin. | |
318 | */ | |
319 | static struct sfi_gpio_table_entry *gpio_table; | |
320 | static int gpio_num_entry; | |
321 | ||
322 | static int __init sfi_parse_gpio(struct sfi_table_header *table) | |
323 | { | |
324 | struct sfi_table_simple *sb; | |
325 | struct sfi_gpio_table_entry *pentry; | |
326 | int num, i; | |
327 | ||
328 | if (gpio_table) | |
329 | return 0; | |
330 | sb = (struct sfi_table_simple *)table; | |
331 | num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry); | |
332 | pentry = (struct sfi_gpio_table_entry *)sb->pentry; | |
333 | ||
334 | gpio_table = (struct sfi_gpio_table_entry *) | |
335 | kmalloc(num * sizeof(*pentry), GFP_KERNEL); | |
336 | if (!gpio_table) | |
337 | return -1; | |
338 | memcpy(gpio_table, pentry, num * sizeof(*pentry)); | |
339 | gpio_num_entry = num; | |
340 | ||
341 | pr_debug("GPIO pin info:\n"); | |
342 | for (i = 0; i < num; i++, pentry++) | |
343 | pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s," | |
344 | " pin = %d\n", i, | |
345 | pentry->controller_name, | |
346 | pentry->pin_name, | |
347 | pentry->pin_no); | |
348 | return 0; | |
349 | } | |
350 | ||
351 | static int get_gpio_by_name(const char *name) | |
352 | { | |
353 | struct sfi_gpio_table_entry *pentry = gpio_table; | |
354 | int i; | |
355 | ||
356 | if (!pentry) | |
357 | return -1; | |
358 | for (i = 0; i < gpio_num_entry; i++, pentry++) { | |
359 | if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN)) | |
360 | return pentry->pin_no; | |
361 | } | |
362 | return -1; | |
363 | } | |
364 | ||
365 | /* | |
366 | * Here defines the array of devices platform data that IAFW would export | |
367 | * through SFI "DEVS" table, we use name and type to match the device and | |
368 | * its platform data. | |
369 | */ | |
370 | struct devs_id { | |
371 | char name[SFI_NAME_LEN + 1]; | |
372 | u8 type; | |
373 | u8 delay; | |
374 | void *(*get_platform_data)(void *info); | |
375 | }; | |
376 | ||
377 | /* the offset for the mapping of global gpio pin to irq */ | |
378 | #define MRST_IRQ_OFFSET 0x100 | |
379 | ||
380 | static void __init *pmic_gpio_platform_data(void *info) | |
381 | { | |
382 | static struct intel_pmic_gpio_platform_data pmic_gpio_pdata; | |
383 | int gpio_base = get_gpio_by_name("pmic_gpio_base"); | |
384 | ||
385 | if (gpio_base == -1) | |
386 | gpio_base = 64; | |
387 | pmic_gpio_pdata.gpio_base = gpio_base; | |
388 | pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET; | |
389 | pmic_gpio_pdata.gpiointr = 0xffffeff8; | |
390 | ||
391 | return &pmic_gpio_pdata; | |
392 | } | |
393 | ||
394 | static void __init *max3111_platform_data(void *info) | |
395 | { | |
396 | struct spi_board_info *spi_info = info; | |
397 | int intr = get_gpio_by_name("max3111_int"); | |
398 | ||
efe3ed98 | 399 | spi_info->mode = SPI_MODE_0; |
1da4b1c6 FT |
400 | if (intr == -1) |
401 | return NULL; | |
402 | spi_info->irq = intr + MRST_IRQ_OFFSET; | |
403 | return NULL; | |
404 | } | |
405 | ||
406 | /* we have multiple max7315 on the board ... */ | |
407 | #define MAX7315_NUM 2 | |
408 | static void __init *max7315_platform_data(void *info) | |
409 | { | |
410 | static struct pca953x_platform_data max7315_pdata[MAX7315_NUM]; | |
411 | static int nr; | |
412 | struct pca953x_platform_data *max7315 = &max7315_pdata[nr]; | |
413 | struct i2c_board_info *i2c_info = info; | |
414 | int gpio_base, intr; | |
415 | char base_pin_name[SFI_NAME_LEN + 1]; | |
416 | char intr_pin_name[SFI_NAME_LEN + 1]; | |
417 | ||
418 | if (nr == MAX7315_NUM) { | |
419 | pr_err("too many max7315s, we only support %d\n", | |
420 | MAX7315_NUM); | |
421 | return NULL; | |
422 | } | |
423 | /* we have several max7315 on the board, we only need load several | |
424 | * instances of the same pca953x driver to cover them | |
425 | */ | |
426 | strcpy(i2c_info->type, "max7315"); | |
427 | if (nr++) { | |
428 | sprintf(base_pin_name, "max7315_%d_base", nr); | |
429 | sprintf(intr_pin_name, "max7315_%d_int", nr); | |
430 | } else { | |
431 | strcpy(base_pin_name, "max7315_base"); | |
432 | strcpy(intr_pin_name, "max7315_int"); | |
433 | } | |
434 | ||
435 | gpio_base = get_gpio_by_name(base_pin_name); | |
436 | intr = get_gpio_by_name(intr_pin_name); | |
437 | ||
438 | if (gpio_base == -1) | |
439 | return NULL; | |
440 | max7315->gpio_base = gpio_base; | |
441 | if (intr != -1) { | |
442 | i2c_info->irq = intr + MRST_IRQ_OFFSET; | |
443 | max7315->irq_base = gpio_base + MRST_IRQ_OFFSET; | |
444 | } else { | |
445 | i2c_info->irq = -1; | |
446 | max7315->irq_base = -1; | |
447 | } | |
448 | return max7315; | |
449 | } | |
450 | ||
451 | static void __init *emc1403_platform_data(void *info) | |
452 | { | |
453 | static short intr2nd_pdata; | |
454 | struct i2c_board_info *i2c_info = info; | |
455 | int intr = get_gpio_by_name("thermal_int"); | |
456 | int intr2nd = get_gpio_by_name("thermal_alert"); | |
457 | ||
458 | if (intr == -1 || intr2nd == -1) | |
459 | return NULL; | |
460 | ||
461 | i2c_info->irq = intr + MRST_IRQ_OFFSET; | |
462 | intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET; | |
463 | ||
464 | return &intr2nd_pdata; | |
465 | } | |
466 | ||
467 | static void __init *lis331dl_platform_data(void *info) | |
468 | { | |
469 | static short intr2nd_pdata; | |
470 | struct i2c_board_info *i2c_info = info; | |
471 | int intr = get_gpio_by_name("accel_int"); | |
472 | int intr2nd = get_gpio_by_name("accel_2"); | |
473 | ||
474 | if (intr == -1 || intr2nd == -1) | |
475 | return NULL; | |
476 | ||
477 | i2c_info->irq = intr + MRST_IRQ_OFFSET; | |
478 | intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET; | |
479 | ||
480 | return &intr2nd_pdata; | |
481 | } | |
482 | ||
86071535 VK |
483 | static void __init *no_platform_data(void *info) |
484 | { | |
485 | return NULL; | |
486 | } | |
487 | ||
360545c1 MW |
488 | static struct resource msic_resources[] = { |
489 | { | |
490 | .start = INTEL_MSIC_IRQ_PHYS_BASE, | |
491 | .end = INTEL_MSIC_IRQ_PHYS_BASE + 64 - 1, | |
492 | .flags = IORESOURCE_MEM, | |
493 | }, | |
494 | }; | |
495 | ||
496 | static struct intel_msic_platform_data msic_pdata; | |
497 | ||
498 | static struct platform_device msic_device = { | |
499 | .name = "intel_msic", | |
500 | .id = -1, | |
501 | .dev = { | |
502 | .platform_data = &msic_pdata, | |
503 | }, | |
504 | .num_resources = ARRAY_SIZE(msic_resources), | |
505 | .resource = msic_resources, | |
506 | }; | |
507 | ||
508 | static inline bool mrst_has_msic(void) | |
509 | { | |
510 | return mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL; | |
511 | } | |
512 | ||
513 | static int msic_scu_status_change(struct notifier_block *nb, | |
514 | unsigned long code, void *data) | |
515 | { | |
516 | if (code == SCU_DOWN) { | |
517 | platform_device_unregister(&msic_device); | |
518 | return 0; | |
519 | } | |
520 | ||
521 | return platform_device_register(&msic_device); | |
522 | } | |
523 | ||
524 | static int __init msic_init(void) | |
525 | { | |
526 | static struct notifier_block msic_scu_notifier = { | |
527 | .notifier_call = msic_scu_status_change, | |
528 | }; | |
529 | ||
530 | /* | |
531 | * We need to be sure that the SCU IPC is ready before MSIC device | |
532 | * can be registered. | |
533 | */ | |
534 | if (mrst_has_msic()) | |
535 | intel_scu_notifier_add(&msic_scu_notifier); | |
536 | ||
537 | return 0; | |
538 | } | |
539 | arch_initcall(msic_init); | |
540 | ||
541 | /* | |
542 | * msic_generic_platform_data - sets generic platform data for the block | |
543 | * @info: pointer to the SFI device table entry for this block | |
544 | * @block: MSIC block | |
545 | * | |
546 | * Function sets IRQ number from the SFI table entry for given device to | |
547 | * the MSIC platform data. | |
548 | */ | |
549 | static void *msic_generic_platform_data(void *info, enum intel_msic_block block) | |
550 | { | |
551 | struct sfi_device_table_entry *entry = info; | |
552 | ||
553 | BUG_ON(block < 0 || block >= INTEL_MSIC_BLOCK_LAST); | |
554 | msic_pdata.irq[block] = entry->irq; | |
555 | ||
556 | return no_platform_data(info); | |
557 | } | |
558 | ||
559 | static void *msic_battery_platform_data(void *info) | |
560 | { | |
561 | return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY); | |
562 | } | |
563 | ||
564 | static void *msic_gpio_platform_data(void *info) | |
565 | { | |
566 | static struct intel_msic_gpio_pdata pdata; | |
567 | int gpio = get_gpio_by_name("msic_gpio_base"); | |
568 | ||
569 | if (gpio < 0) | |
570 | return NULL; | |
571 | ||
572 | pdata.gpio_base = gpio; | |
573 | msic_pdata.gpio = &pdata; | |
574 | ||
575 | return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_GPIO); | |
576 | } | |
577 | ||
578 | static void *msic_audio_platform_data(void *info) | |
579 | { | |
580 | struct platform_device *pdev; | |
581 | ||
582 | pdev = platform_device_register_simple("sst-platform", -1, NULL, 0); | |
583 | if (IS_ERR(pdev)) { | |
584 | pr_err("failed to create audio platform device\n"); | |
585 | return NULL; | |
586 | } | |
587 | ||
588 | return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_AUDIO); | |
589 | } | |
590 | ||
591 | static void *msic_power_btn_platform_data(void *info) | |
592 | { | |
593 | return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_POWER_BTN); | |
594 | } | |
595 | ||
596 | static void *msic_ocd_platform_data(void *info) | |
597 | { | |
598 | static struct intel_msic_ocd_pdata pdata; | |
599 | int gpio = get_gpio_by_name("ocd_gpio"); | |
600 | ||
601 | if (gpio < 0) | |
602 | return NULL; | |
603 | ||
604 | pdata.gpio = gpio; | |
605 | msic_pdata.ocd = &pdata; | |
606 | ||
607 | return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD); | |
608 | } | |
609 | ||
1da4b1c6 FT |
610 | static const struct devs_id __initconst device_ids[] = { |
611 | {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data}, | |
612 | {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data}, | |
613 | {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data}, | |
614 | {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data}, | |
615 | {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data}, | |
616 | {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data}, | |
86071535 | 617 | {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data}, |
360545c1 MW |
618 | |
619 | /* MSIC subdevices */ | |
620 | {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data}, | |
621 | {"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data}, | |
622 | {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data}, | |
623 | {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data}, | |
624 | {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data}, | |
625 | ||
1da4b1c6 FT |
626 | {}, |
627 | }; | |
628 | ||
629 | #define MAX_IPCDEVS 24 | |
630 | static struct platform_device *ipc_devs[MAX_IPCDEVS]; | |
631 | static int ipc_next_dev; | |
632 | ||
633 | #define MAX_SCU_SPI 24 | |
634 | static struct spi_board_info *spi_devs[MAX_SCU_SPI]; | |
635 | static int spi_next_dev; | |
636 | ||
637 | #define MAX_SCU_I2C 24 | |
638 | static struct i2c_board_info *i2c_devs[MAX_SCU_I2C]; | |
639 | static int i2c_bus[MAX_SCU_I2C]; | |
640 | static int i2c_next_dev; | |
641 | ||
642 | static void __init intel_scu_device_register(struct platform_device *pdev) | |
643 | { | |
644 | if(ipc_next_dev == MAX_IPCDEVS) | |
645 | pr_err("too many SCU IPC devices"); | |
646 | else | |
647 | ipc_devs[ipc_next_dev++] = pdev; | |
648 | } | |
649 | ||
650 | static void __init intel_scu_spi_device_register(struct spi_board_info *sdev) | |
651 | { | |
652 | struct spi_board_info *new_dev; | |
653 | ||
654 | if (spi_next_dev == MAX_SCU_SPI) { | |
655 | pr_err("too many SCU SPI devices"); | |
656 | return; | |
657 | } | |
658 | ||
659 | new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL); | |
660 | if (!new_dev) { | |
661 | pr_err("failed to alloc mem for delayed spi dev %s\n", | |
662 | sdev->modalias); | |
663 | return; | |
664 | } | |
665 | memcpy(new_dev, sdev, sizeof(*sdev)); | |
666 | ||
667 | spi_devs[spi_next_dev++] = new_dev; | |
668 | } | |
669 | ||
670 | static void __init intel_scu_i2c_device_register(int bus, | |
671 | struct i2c_board_info *idev) | |
672 | { | |
673 | struct i2c_board_info *new_dev; | |
674 | ||
675 | if (i2c_next_dev == MAX_SCU_I2C) { | |
676 | pr_err("too many SCU I2C devices"); | |
677 | return; | |
678 | } | |
679 | ||
680 | new_dev = kzalloc(sizeof(*idev), GFP_KERNEL); | |
681 | if (!new_dev) { | |
682 | pr_err("failed to alloc mem for delayed i2c dev %s\n", | |
683 | idev->type); | |
684 | return; | |
685 | } | |
686 | memcpy(new_dev, idev, sizeof(*idev)); | |
687 | ||
688 | i2c_bus[i2c_next_dev] = bus; | |
689 | i2c_devs[i2c_next_dev++] = new_dev; | |
690 | } | |
691 | ||
42c2544b AC |
692 | BLOCKING_NOTIFIER_HEAD(intel_scu_notifier); |
693 | EXPORT_SYMBOL_GPL(intel_scu_notifier); | |
694 | ||
1da4b1c6 FT |
695 | /* Called by IPC driver */ |
696 | void intel_scu_devices_create(void) | |
697 | { | |
698 | int i; | |
699 | ||
700 | for (i = 0; i < ipc_next_dev; i++) | |
701 | platform_device_add(ipc_devs[i]); | |
702 | ||
703 | for (i = 0; i < spi_next_dev; i++) | |
704 | spi_register_board_info(spi_devs[i], 1); | |
705 | ||
706 | for (i = 0; i < i2c_next_dev; i++) { | |
707 | struct i2c_adapter *adapter; | |
708 | struct i2c_client *client; | |
709 | ||
710 | adapter = i2c_get_adapter(i2c_bus[i]); | |
711 | if (adapter) { | |
712 | client = i2c_new_device(adapter, i2c_devs[i]); | |
713 | if (!client) | |
714 | pr_err("can't create i2c device %s\n", | |
715 | i2c_devs[i]->type); | |
716 | } else | |
717 | i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); | |
718 | } | |
42c2544b | 719 | intel_scu_notifier_post(SCU_AVAILABLE, 0L); |
1da4b1c6 FT |
720 | } |
721 | EXPORT_SYMBOL_GPL(intel_scu_devices_create); | |
722 | ||
723 | /* Called by IPC driver */ | |
724 | void intel_scu_devices_destroy(void) | |
725 | { | |
726 | int i; | |
727 | ||
42c2544b AC |
728 | intel_scu_notifier_post(SCU_DOWN, 0L); |
729 | ||
1da4b1c6 FT |
730 | for (i = 0; i < ipc_next_dev; i++) |
731 | platform_device_del(ipc_devs[i]); | |
732 | } | |
733 | EXPORT_SYMBOL_GPL(intel_scu_devices_destroy); | |
734 | ||
735 | static void __init install_irq_resource(struct platform_device *pdev, int irq) | |
736 | { | |
737 | /* Single threaded */ | |
738 | static struct resource __initdata res = { | |
739 | .name = "IRQ", | |
740 | .flags = IORESOURCE_IRQ, | |
741 | }; | |
742 | res.start = irq; | |
743 | platform_device_add_resources(pdev, &res, 1); | |
744 | } | |
745 | ||
360545c1 | 746 | static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry) |
1da4b1c6 FT |
747 | { |
748 | const struct devs_id *dev = device_ids; | |
360545c1 | 749 | struct platform_device *pdev; |
1da4b1c6 FT |
750 | void *pdata = NULL; |
751 | ||
752 | while (dev->name[0]) { | |
753 | if (dev->type == SFI_DEV_TYPE_IPC && | |
360545c1 MW |
754 | !strncmp(dev->name, entry->name, SFI_NAME_LEN)) { |
755 | pdata = dev->get_platform_data(entry); | |
1da4b1c6 FT |
756 | break; |
757 | } | |
758 | dev++; | |
759 | } | |
360545c1 MW |
760 | |
761 | /* | |
762 | * On Medfield the platform device creation is handled by the MSIC | |
763 | * MFD driver so we don't need to do it here. | |
764 | */ | |
765 | if (mrst_has_msic()) | |
766 | return; | |
767 | ||
768 | /* ID as IRQ is a hack that will go away */ | |
769 | pdev = platform_device_alloc(entry->name, entry->irq); | |
770 | if (pdev == NULL) { | |
771 | pr_err("out of memory for SFI platform device '%s'.\n", | |
772 | entry->name); | |
773 | return; | |
774 | } | |
775 | install_irq_resource(pdev, entry->irq); | |
776 | ||
1da4b1c6 FT |
777 | pdev->dev.platform_data = pdata; |
778 | intel_scu_device_register(pdev); | |
779 | } | |
780 | ||
781 | static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info) | |
782 | { | |
783 | const struct devs_id *dev = device_ids; | |
784 | void *pdata = NULL; | |
785 | ||
786 | while (dev->name[0]) { | |
787 | if (dev->type == SFI_DEV_TYPE_SPI && | |
788 | !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) { | |
789 | pdata = dev->get_platform_data(spi_info); | |
790 | break; | |
791 | } | |
792 | dev++; | |
793 | } | |
794 | spi_info->platform_data = pdata; | |
795 | if (dev->delay) | |
796 | intel_scu_spi_device_register(spi_info); | |
797 | else | |
798 | spi_register_board_info(spi_info, 1); | |
799 | } | |
800 | ||
801 | static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info) | |
802 | { | |
803 | const struct devs_id *dev = device_ids; | |
804 | void *pdata = NULL; | |
805 | ||
806 | while (dev->name[0]) { | |
807 | if (dev->type == SFI_DEV_TYPE_I2C && | |
808 | !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) { | |
809 | pdata = dev->get_platform_data(i2c_info); | |
810 | break; | |
811 | } | |
812 | dev++; | |
813 | } | |
814 | i2c_info->platform_data = pdata; | |
815 | ||
816 | if (dev->delay) | |
817 | intel_scu_i2c_device_register(bus, i2c_info); | |
818 | else | |
819 | i2c_register_board_info(bus, i2c_info, 1); | |
820 | } | |
821 | ||
822 | ||
823 | static int __init sfi_parse_devs(struct sfi_table_header *table) | |
824 | { | |
825 | struct sfi_table_simple *sb; | |
826 | struct sfi_device_table_entry *pentry; | |
827 | struct spi_board_info spi_info; | |
828 | struct i2c_board_info i2c_info; | |
1da4b1c6 FT |
829 | int num, i, bus; |
830 | int ioapic; | |
831 | struct io_apic_irq_attr irq_attr; | |
832 | ||
833 | sb = (struct sfi_table_simple *)table; | |
834 | num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry); | |
835 | pentry = (struct sfi_device_table_entry *)sb->pentry; | |
836 | ||
837 | for (i = 0; i < num; i++, pentry++) { | |
153b19a3 MW |
838 | int irq = pentry->irq; |
839 | ||
840 | if (irq != (u8)0xff) { /* native RTE case */ | |
1da4b1c6 FT |
841 | /* these SPI2 devices are not exposed to system as PCI |
842 | * devices, but they have separate RTE entry in IOAPIC | |
843 | * so we have to enable them one by one here | |
844 | */ | |
153b19a3 | 845 | ioapic = mp_find_ioapic(irq); |
1da4b1c6 | 846 | irq_attr.ioapic = ioapic; |
153b19a3 | 847 | irq_attr.ioapic_pin = irq; |
1da4b1c6 FT |
848 | irq_attr.trigger = 1; |
849 | irq_attr.polarity = 1; | |
153b19a3 | 850 | io_apic_set_pci_routing(NULL, irq, &irq_attr); |
a94cc4e6 | 851 | } else |
153b19a3 | 852 | irq = 0; /* No irq */ |
a94cc4e6 | 853 | |
1da4b1c6 FT |
854 | switch (pentry->type) { |
855 | case SFI_DEV_TYPE_IPC: | |
1da4b1c6 | 856 | pr_debug("info[%2d]: IPC bus, name = %16.16s, " |
360545c1 MW |
857 | "irq = 0x%2x\n", i, pentry->name, pentry->irq); |
858 | sfi_handle_ipc_dev(pentry); | |
1da4b1c6 FT |
859 | break; |
860 | case SFI_DEV_TYPE_SPI: | |
861 | memset(&spi_info, 0, sizeof(spi_info)); | |
862 | strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN); | |
153b19a3 | 863 | spi_info.irq = irq; |
1da4b1c6 FT |
864 | spi_info.bus_num = pentry->host_num; |
865 | spi_info.chip_select = pentry->addr; | |
866 | spi_info.max_speed_hz = pentry->max_freq; | |
867 | pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, " | |
868 | "irq = 0x%2x, max_freq = %d, cs = %d\n", i, | |
869 | spi_info.bus_num, | |
870 | spi_info.modalias, | |
871 | spi_info.irq, | |
872 | spi_info.max_speed_hz, | |
873 | spi_info.chip_select); | |
874 | sfi_handle_spi_dev(&spi_info); | |
875 | break; | |
876 | case SFI_DEV_TYPE_I2C: | |
877 | memset(&i2c_info, 0, sizeof(i2c_info)); | |
878 | bus = pentry->host_num; | |
879 | strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN); | |
153b19a3 | 880 | i2c_info.irq = irq; |
1da4b1c6 FT |
881 | i2c_info.addr = pentry->addr; |
882 | pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, " | |
883 | "irq = 0x%2x, addr = 0x%x\n", i, bus, | |
884 | i2c_info.type, | |
885 | i2c_info.irq, | |
886 | i2c_info.addr); | |
887 | sfi_handle_i2c_dev(bus, &i2c_info); | |
888 | break; | |
889 | case SFI_DEV_TYPE_UART: | |
890 | case SFI_DEV_TYPE_HSI: | |
891 | default: | |
892 | ; | |
893 | } | |
894 | } | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static int __init mrst_platform_init(void) | |
899 | { | |
900 | sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio); | |
901 | sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs); | |
902 | return 0; | |
903 | } | |
904 | arch_initcall(mrst_platform_init); | |
905 | ||
906 | /* | |
907 | * we will search these buttons in SFI GPIO table (by name) | |
908 | * and register them dynamically. Please add all possible | |
909 | * buttons here, we will shrink them if no GPIO found. | |
910 | */ | |
911 | static struct gpio_keys_button gpio_button[] = { | |
912 | {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000}, | |
913 | {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20}, | |
914 | {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20}, | |
915 | {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20}, | |
916 | {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20}, | |
917 | {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20}, | |
918 | {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20}, | |
919 | {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20}, | |
920 | {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20}, | |
921 | {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20}, | |
922 | }; | |
923 | ||
924 | static struct gpio_keys_platform_data mrst_gpio_keys = { | |
925 | .buttons = gpio_button, | |
926 | .rep = 1, | |
927 | .nbuttons = -1, /* will fill it after search */ | |
928 | }; | |
929 | ||
930 | static struct platform_device pb_device = { | |
931 | .name = "gpio-keys", | |
932 | .id = -1, | |
933 | .dev = { | |
934 | .platform_data = &mrst_gpio_keys, | |
935 | }, | |
936 | }; | |
937 | ||
938 | /* | |
939 | * Shrink the non-existent buttons, register the gpio button | |
940 | * device if there is some | |
941 | */ | |
942 | static int __init pb_keys_init(void) | |
943 | { | |
944 | struct gpio_keys_button *gb = gpio_button; | |
945 | int i, num, good = 0; | |
946 | ||
947 | num = sizeof(gpio_button) / sizeof(struct gpio_keys_button); | |
948 | for (i = 0; i < num; i++) { | |
949 | gb[i].gpio = get_gpio_by_name(gb[i].desc); | |
950 | if (gb[i].gpio == -1) | |
951 | continue; | |
952 | ||
953 | if (i != good) | |
954 | gb[good] = gb[i]; | |
955 | good++; | |
956 | } | |
957 | ||
958 | if (good) { | |
959 | mrst_gpio_keys.nbuttons = good; | |
960 | return platform_device_register(&pb_device); | |
961 | } | |
962 | return 0; | |
963 | } | |
964 | late_initcall(pb_keys_init); |