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1812924b
CW
1/*
2 * SGI UltraViolet TLB flush routines.
3 *
a26fd719 4 * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
1812924b
CW
5 *
6 * This code is released under the GNU General Public License version 2 or
7 * later.
8 */
aef8f5b8 9#include <linux/seq_file.h>
1812924b 10#include <linux/proc_fs.h>
e8e5e8a8 11#include <linux/debugfs.h>
1812924b 12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
ca444564 14#include <linux/delay.h>
1812924b 15
1812924b 16#include <asm/mmu_context.h>
bdbcdd48 17#include <asm/uv/uv.h>
1812924b 18#include <asm/uv/uv_mmrs.h>
b4c286e6 19#include <asm/uv/uv_hub.h>
1812924b 20#include <asm/uv/uv_bau.h>
7b6aa335 21#include <asm/apic.h>
b4c286e6 22#include <asm/idle.h>
b194b120 23#include <asm/tsc.h>
99dd8713 24#include <asm/irq_vectors.h>
b8f7fb13 25#include <asm/timer.h>
1812924b 26
12a6611f
CW
27/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
28static int timeout_base_ns[] = {
29 20,
30 160,
31 1280,
32 10240,
33 81920,
34 655360,
35 5242880,
36 167772160
37};
f073cc8f 38
12a6611f 39static int timeout_us;
e8e5e8a8 40static int nobau;
26ef8577 41static int nobau_perm;
50fb55ac 42static cycles_t congested_cycles;
12a6611f 43
e8e5e8a8 44/* tunables: */
f073cc8f
CW
45static int max_concurr = MAX_BAU_CONCURRENT;
46static int max_concurr_const = MAX_BAU_CONCURRENT;
47static int plugged_delay = PLUGGED_DELAY;
48static int plugsb4reset = PLUGSB4RESET;
8b6e511e 49static int giveup_limit = GIVEUP_LIMIT;
f073cc8f
CW
50static int timeoutsb4reset = TIMEOUTSB4RESET;
51static int ipi_reset_limit = IPI_RESET_LIMIT;
52static int complete_threshold = COMPLETE_THRESHOLD;
53static int congested_respns_us = CONGESTED_RESPONSE_US;
54static int congested_reps = CONGESTED_REPS;
8b6e511e 55static int disabled_period = DISABLED_PERIOD;
f073cc8f
CW
56
57static struct tunables tunables[] = {
58 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
59 {&plugged_delay, PLUGGED_DELAY},
60 {&plugsb4reset, PLUGSB4RESET},
61 {&timeoutsb4reset, TIMEOUTSB4RESET},
62 {&ipi_reset_limit, IPI_RESET_LIMIT},
63 {&complete_threshold, COMPLETE_THRESHOLD},
64 {&congested_respns_us, CONGESTED_RESPONSE_US},
65 {&congested_reps, CONGESTED_REPS},
8b6e511e
CW
66 {&disabled_period, DISABLED_PERIOD},
67 {&giveup_limit, GIVEUP_LIMIT}
f073cc8f
CW
68};
69
e8e5e8a8
CW
70static struct dentry *tunables_dir;
71static struct dentry *tunables_file;
b4c286e6 72
f073cc8f
CW
73/* these correspond to the statistics printed by ptc_seq_show() */
74static char *stat_description[] = {
75 "sent: number of shootdown messages sent",
76 "stime: time spent sending messages",
77 "numuvhubs: number of hubs targeted with shootdown",
78 "numuvhubs16: number times 16 or more hubs targeted",
79 "numuvhubs8: number times 8 or more hubs targeted",
80 "numuvhubs4: number times 4 or more hubs targeted",
81 "numuvhubs2: number times 2 or more hubs targeted",
82 "numuvhubs1: number times 1 hub targeted",
83 "numcpus: number of cpus targeted with shootdown",
84 "dto: number of destination timeouts",
85 "retries: destination timeout retries sent",
86 "rok: : destination timeouts successfully retried",
87 "resetp: ipi-style resource resets for plugs",
88 "resett: ipi-style resource resets for timeouts",
89 "giveup: fall-backs to ipi-style shootdowns",
90 "sto: number of source timeouts",
91 "bz: number of stay-busy's",
92 "throt: number times spun in throttle",
93 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
94 "recv: shootdown messages received",
95 "rtime: time spent processing messages",
96 "all: shootdown all-tlb messages",
97 "one: shootdown one-tlb messages",
98 "mult: interrupts that found multiple messages",
99 "none: interrupts that found no messages",
100 "retry: number of retry messages processed",
101 "canc: number messages canceled by retries",
102 "nocan: number retries that found nothing to cancel",
103 "reset: number of ipi-style reset requests processed",
104 "rcan: number messages canceled by reset requests",
105 "disable: number times use of the BAU was disabled",
106 "enable: number times use of the BAU was re-enabled"
107};
108
109static int __init
110setup_nobau(char *arg)
b8f7fb13
CW
111{
112 nobau = 1;
113 return 0;
114}
115early_param("nobau", setup_nobau);
b4c286e6 116
b8f7fb13 117/* base pnode in this partition */
f073cc8f 118static int uv_base_pnode __read_mostly;
1812924b 119
dc163a41
IM
120static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
121static DEFINE_PER_CPU(struct bau_control, bau_control);
b8f7fb13
CW
122static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
123
26ef8577
CW
124static void
125set_bau_on(void)
126{
127 int cpu;
128 struct bau_control *bcp;
129
130 if (nobau_perm) {
131 pr_info("BAU not initialized; cannot be turned on\n");
132 return;
133 }
134 nobau = 0;
135 for_each_present_cpu(cpu) {
136 bcp = &per_cpu(bau_control, cpu);
137 bcp->nobau = 0;
138 }
139 pr_info("BAU turned on\n");
140 return;
141}
142
143static void
144set_bau_off(void)
145{
146 int cpu;
147 struct bau_control *bcp;
148
149 nobau = 1;
150 for_each_present_cpu(cpu) {
151 bcp = &per_cpu(bau_control, cpu);
152 bcp->nobau = 1;
153 }
154 pr_info("BAU turned off\n");
155 return;
156}
157
9674f35b 158/*
b8f7fb13
CW
159 * Determine the first node on a uvhub. 'Nodes' are used for kernel
160 * memory allocation.
9674f35b 161 */
b8f7fb13 162static int __init uvhub_to_first_node(int uvhub)
9674f35b
CW
163{
164 int node, b;
165
166 for_each_online_node(node) {
167 b = uv_node_to_blade_id(node);
b8f7fb13 168 if (uvhub == b)
9674f35b
CW
169 return node;
170 }
b8f7fb13 171 return -1;
9674f35b
CW
172}
173
174/*
b8f7fb13 175 * Determine the apicid of the first cpu on a uvhub.
9674f35b 176 */
b8f7fb13 177static int __init uvhub_to_first_apicid(int uvhub)
9674f35b
CW
178{
179 int cpu;
180
181 for_each_present_cpu(cpu)
b8f7fb13 182 if (uvhub == uv_cpu_to_blade_id(cpu))
9674f35b
CW
183 return per_cpu(x86_cpu_to_apicid, cpu);
184 return -1;
185}
186
1812924b
CW
187/*
188 * Free a software acknowledge hardware resource by clearing its Pending
189 * bit. This will return a reply to the sender.
190 * If the message has timed out, a reply has already been sent by the
191 * hardware but the resource has not been released. In that case our
192 * clear of the Timeout bit (as well) will free the resource. No reply will
193 * be sent (the hardware will only do one reply per message).
194 */
c5d35d39
CW
195static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
196 int do_acknowledge)
1812924b 197{
b194b120 198 unsigned long dw;
f073cc8f 199 struct bau_pq_entry *msg;
1812924b 200
b8f7fb13 201 msg = mdp->msg;
c5d35d39 202 if (!msg->canceled && do_acknowledge) {
f073cc8f
CW
203 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
204 write_mmr_sw_ack(dw);
b8f7fb13 205 }
1812924b 206 msg->replied_to = 1;
f073cc8f 207 msg->swack_vec = 0;
1812924b
CW
208}
209
210/*
b8f7fb13 211 * Process the receipt of a RETRY message
1812924b 212 */
f073cc8f
CW
213static void bau_process_retry_msg(struct msg_desc *mdp,
214 struct bau_control *bcp)
1812924b 215{
b8f7fb13
CW
216 int i;
217 int cancel_count = 0;
b8f7fb13
CW
218 unsigned long msg_res;
219 unsigned long mmr = 0;
f073cc8f
CW
220 struct bau_pq_entry *msg = mdp->msg;
221 struct bau_pq_entry *msg2;
222 struct ptc_stats *stat = bcp->statp;
1812924b 223
b8f7fb13
CW
224 stat->d_retries++;
225 /*
226 * cancel any message from msg+1 to the retry itself
227 */
228 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
f073cc8f
CW
229 if (msg2 > mdp->queue_last)
230 msg2 = mdp->queue_first;
b8f7fb13
CW
231 if (msg2 == msg)
232 break;
233
f073cc8f 234 /* same conditions for cancellation as do_reset */
b8f7fb13 235 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
f073cc8f
CW
236 (msg2->swack_vec) && ((msg2->swack_vec &
237 msg->swack_vec) == 0) &&
b8f7fb13
CW
238 (msg2->sending_cpu == msg->sending_cpu) &&
239 (msg2->msg_type != MSG_NOOP)) {
f073cc8f
CW
240 mmr = read_mmr_sw_ack();
241 msg_res = msg2->swack_vec;
b8f7fb13
CW
242 /*
243 * This is a message retry; clear the resources held
244 * by the previous message only if they timed out.
245 * If it has not timed out we have an unexpected
246 * situation to report.
247 */
39847e7f 248 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
f073cc8f 249 unsigned long mr;
b8f7fb13 250 /*
c5d35d39
CW
251 * Is the resource timed out?
252 * Make everyone ignore the cancelled message.
b8f7fb13
CW
253 */
254 msg2->canceled = 1;
255 stat->d_canceled++;
256 cancel_count++;
f073cc8f
CW
257 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
258 write_mmr_sw_ack(mr);
39847e7f 259 }
b8f7fb13
CW
260 }
261 }
262 if (!cancel_count)
263 stat->d_nocanceled++;
264}
1812924b 265
b8f7fb13
CW
266/*
267 * Do all the things a cpu should do for a TLB shootdown message.
268 * Other cpu's may come here at the same time for this message.
269 */
c5d35d39
CW
270static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
271 int do_acknowledge)
b8f7fb13 272{
b8f7fb13 273 short socket_ack_count = 0;
f073cc8f
CW
274 short *sp;
275 struct atomic_short *asp;
276 struct ptc_stats *stat = bcp->statp;
277 struct bau_pq_entry *msg = mdp->msg;
b8f7fb13 278 struct bau_control *smaster = bcp->socket_master;
1812924b 279
b8f7fb13
CW
280 /*
281 * This must be a normal message, or retry of a normal message
282 */
1812924b
CW
283 if (msg->address == TLB_FLUSH_ALL) {
284 local_flush_tlb();
b8f7fb13 285 stat->d_alltlb++;
1812924b
CW
286 } else {
287 __flush_tlb_one(msg->address);
b8f7fb13 288 stat->d_onetlb++;
1812924b 289 }
b8f7fb13
CW
290 stat->d_requestee++;
291
292 /*
293 * One cpu on each uvhub has the additional job on a RETRY
294 * of releasing the resource held by the message that is
295 * being retried. That message is identified by sending
296 * cpu number.
297 */
298 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
f073cc8f 299 bau_process_retry_msg(mdp, bcp);
1812924b 300
b8f7fb13 301 /*
f073cc8f 302 * This is a swack message, so we have to reply to it.
b8f7fb13
CW
303 * Count each responding cpu on the socket. This avoids
304 * pinging the count's cache line back and forth between
305 * the sockets.
306 */
f073cc8f
CW
307 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
308 asp = (struct atomic_short *)sp;
309 socket_ack_count = atom_asr(1, asp);
b8f7fb13 310 if (socket_ack_count == bcp->cpus_in_socket) {
f073cc8f 311 int msg_ack_count;
b8f7fb13
CW
312 /*
313 * Both sockets dump their completed count total into
314 * the message's count.
315 */
8b6e511e 316 *sp = 0;
f073cc8f
CW
317 asp = (struct atomic_short *)&msg->acknowledge_count;
318 msg_ack_count = atom_asr(socket_ack_count, asp);
b8f7fb13
CW
319
320 if (msg_ack_count == bcp->cpus_in_uvhub) {
321 /*
322 * All cpus in uvhub saw it; reply
c5d35d39 323 * (unless we are in the UV2 workaround)
b8f7fb13 324 */
c5d35d39 325 reply_to_message(mdp, bcp, do_acknowledge);
b8f7fb13
CW
326 }
327 }
1812924b 328
b8f7fb13 329 return;
1812924b
CW
330}
331
332/*
485f07d3 333 * Determine the first cpu on a pnode.
b8f7fb13 334 */
485f07d3 335static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
b8f7fb13
CW
336{
337 int cpu;
485f07d3 338 struct hub_and_pnode *hpp;
339
340 for_each_present_cpu(cpu) {
341 hpp = &smaster->thp[cpu];
342 if (pnode == hpp->pnode)
b8f7fb13 343 return cpu;
485f07d3 344 }
b8f7fb13
CW
345 return -1;
346}
347
348/*
349 * Last resort when we get a large number of destination timeouts is
350 * to clear resources held by a given cpu.
351 * Do this with IPI so that all messages in the BAU message queue
f073cc8f 352 * can be identified by their nonzero swack_vec field.
1812924b 353 *
b8f7fb13
CW
354 * This is entered for a single cpu on the uvhub.
355 * The sender want's this uvhub to free a specific message's
f073cc8f 356 * swack resources.
1812924b 357 */
f073cc8f 358static void do_reset(void *ptr)
1812924b 359{
b4c286e6 360 int i;
f073cc8f
CW
361 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
362 struct reset_args *rap = (struct reset_args *)ptr;
363 struct bau_pq_entry *msg;
364 struct ptc_stats *stat = bcp->statp;
1812924b 365
b8f7fb13 366 stat->d_resets++;
b8f7fb13
CW
367 /*
368 * We're looking for the given sender, and
f073cc8f 369 * will free its swack resource.
b8f7fb13
CW
370 * If all cpu's finally responded after the timeout, its
371 * message 'replied_to' was set.
372 */
f073cc8f
CW
373 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
374 unsigned long msg_res;
375 /* do_reset: same conditions for cancellation as
376 bau_process_retry_msg() */
b8f7fb13
CW
377 if ((msg->replied_to == 0) &&
378 (msg->canceled == 0) &&
379 (msg->sending_cpu == rap->sender) &&
f073cc8f 380 (msg->swack_vec) &&
b8f7fb13 381 (msg->msg_type != MSG_NOOP)) {
f073cc8f
CW
382 unsigned long mmr;
383 unsigned long mr;
b8f7fb13
CW
384 /*
385 * make everyone else ignore this message
386 */
387 msg->canceled = 1;
b8f7fb13
CW
388 /*
389 * only reset the resource if it is still pending
390 */
f073cc8f
CW
391 mmr = read_mmr_sw_ack();
392 msg_res = msg->swack_vec;
393 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
b8f7fb13
CW
394 if (mmr & msg_res) {
395 stat->d_rcanceled++;
f073cc8f 396 write_mmr_sw_ack(mr);
dc163a41 397 }
dc163a41
IM
398 }
399 }
b8f7fb13 400 return;
dc163a41
IM
401}
402
403/*
b8f7fb13
CW
404 * Use IPI to get all target uvhubs to release resources held by
405 * a given sending cpu number.
dc163a41 406 */
a456eaab 407static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
dc163a41 408{
485f07d3 409 int pnode;
410 int apnode;
f073cc8f 411 int maskbits;
485f07d3 412 int sender = bcp->cpu;
442d3924 413 cpumask_t *mask = bcp->uvhub_master->cpumask;
485f07d3 414 struct bau_control *smaster = bcp->socket_master;
b8f7fb13 415 struct reset_args reset_args;
dc163a41 416
b8f7fb13 417 reset_args.sender = sender;
442d3924 418 cpus_clear(*mask);
b8f7fb13 419 /* find a single cpu for each uvhub in this distribution mask */
a456eaab 420 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
485f07d3 421 /* each bit is a pnode relative to the partition base pnode */
422 for (pnode = 0; pnode < maskbits; pnode++) {
f073cc8f 423 int cpu;
485f07d3 424 if (!bau_uvhub_isset(pnode, distribution))
b194b120 425 continue;
485f07d3 426 apnode = pnode + bcp->partition_base_pnode;
427 cpu = pnode_to_first_cpu(apnode, smaster);
442d3924 428 cpu_set(cpu, *mask);
1812924b 429 }
f073cc8f
CW
430
431 /* IPI all cpus; preemption is already disabled */
442d3924 432 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
b8f7fb13
CW
433 return;
434}
435
20d1c86a
PZ
436/*
437 * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
438 * number, not an absolute. It converts a duration in cycles to a duration in
439 * ns.
440 */
441static inline unsigned long long cycles_2_ns(unsigned long long cyc)
b8f7fb13 442{
20d1c86a 443 struct cyc2ns_data *data = cyc2ns_read_begin();
b8f7fb13 444 unsigned long long ns;
f073cc8f 445
20d1c86a
PZ
446 ns = mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
447
448 cyc2ns_read_end(data);
449 return ns;
450}
451
452/*
453 * The reverse of the above; converts a duration in ns to a duration in cycles.
a26fd719 454 */
20d1c86a
PZ
455static inline unsigned long long ns_2_cycles(unsigned long long ns)
456{
457 struct cyc2ns_data *data = cyc2ns_read_begin();
458 unsigned long long cyc;
459
460 cyc = (ns << data->cyc2ns_shift) / data->cyc2ns_mul;
461
462 cyc2ns_read_end(data);
463 return cyc;
464}
465
466static inline unsigned long cycles_2_us(unsigned long long cyc)
467{
468 return cycles_2_ns(cyc) / NSEC_PER_USEC;
469}
470
471static inline cycles_t sec_2_cycles(unsigned long sec)
472{
473 return ns_2_cycles(sec * NSEC_PER_SEC);
474}
475
476static inline unsigned long long usec_2_cycles(unsigned long usec)
477{
478 return ns_2_cycles(usec * NSEC_PER_USEC);
1812924b
CW
479}
480
b194b120 481/*
b8f7fb13
CW
482 * wait for all cpus on this hub to finish their sends and go quiet
483 * leaves uvhub_quiesce set so that no new broadcasts are started by
484 * bau_flush_send_and_wait()
485 */
f073cc8f 486static inline void quiesce_local_uvhub(struct bau_control *hmaster)
b8f7fb13 487{
f073cc8f 488 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
b8f7fb13
CW
489}
490
491/*
492 * mark this quiet-requestor as done
493 */
f073cc8f 494static inline void end_uvhub_quiesce(struct bau_control *hmaster)
b8f7fb13 495{
f073cc8f
CW
496 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
497}
498
499static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
500{
501 unsigned long descriptor_status;
502
503 descriptor_status = uv_read_local_mmr(mmr_offset);
504 descriptor_status >>= right_shift;
505 descriptor_status &= UV_ACT_STATUS_MASK;
506 return descriptor_status;
b8f7fb13
CW
507}
508
509/*
510 * Wait for completion of a broadcast software ack message
511 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
b194b120 512 */
2a919596 513static int uv1_wait_completion(struct bau_desc *bau_desc,
f073cc8f
CW
514 unsigned long mmr_offset, int right_shift,
515 struct bau_control *bcp, long try)
b194b120 516{
b194b120 517 unsigned long descriptor_status;
f073cc8f 518 cycles_t ttm;
712157aa 519 struct ptc_stats *stat = bcp->statp;
b194b120 520
f073cc8f 521 descriptor_status = uv1_read_status(mmr_offset, right_shift);
b8f7fb13 522 /* spin on the status MMR, waiting for it to go idle */
f073cc8f 523 while ((descriptor_status != DS_IDLE)) {
b194b120 524 /*
2a919596
JS
525 * Our software ack messages may be blocked because
526 * there are no swack resources available. As long
527 * as none of them has timed out hardware will NACK
528 * our message and its state will stay IDLE.
b194b120 529 */
f073cc8f 530 if (descriptor_status == DS_SOURCE_TIMEOUT) {
b8f7fb13
CW
531 stat->s_stimeout++;
532 return FLUSH_GIVEUP;
f073cc8f 533 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
2a919596 534 stat->s_dtimeout++;
f073cc8f 535 ttm = get_cycles();
2a919596
JS
536
537 /*
538 * Our retries may be blocked by all destination
539 * swack resources being consumed, and a timeout
540 * pending. In that case hardware returns the
541 * ERROR that looks like a destination timeout.
542 */
f073cc8f 543 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
2a919596
JS
544 bcp->conseccompletes = 0;
545 return FLUSH_RETRY_PLUGGED;
546 }
547
548 bcp->conseccompletes = 0;
549 return FLUSH_RETRY_TIMEOUT;
550 } else {
551 /*
552 * descriptor_status is still BUSY
553 */
554 cpu_relax();
555 }
f073cc8f 556 descriptor_status = uv1_read_status(mmr_offset, right_shift);
2a919596
JS
557 }
558 bcp->conseccompletes++;
559 return FLUSH_COMPLETE;
560}
561
f073cc8f 562/*
8b6e511e
CW
563 * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
564 * But not currently used.
f073cc8f 565 */
a26fd719 566static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
2a919596
JS
567{
568 unsigned long descriptor_status;
f073cc8f 569
8b6e511e
CW
570 descriptor_status =
571 ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
f073cc8f
CW
572 return descriptor_status;
573}
574
c5d35d39
CW
575/*
576 * Return whether the status of the descriptor that is normally used for this
577 * cpu (the one indexed by its hub-relative cpu number) is busy.
578 * The status of the original 32 descriptors is always reflected in the 64
579 * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0.
580 * The bit provided by the activation_status_2 register is irrelevant to
581 * the status if it is only being tested for busy or not busy.
582 */
583int normal_busy(struct bau_control *bcp)
584{
585 int cpu = bcp->uvhub_cpu;
586 int mmr_offset;
587 int right_shift;
588
589 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
590 right_shift = cpu * UV_ACT_STATUS_SIZE;
591 return (((((read_lmmr(mmr_offset) >> right_shift) &
592 UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY);
593}
594
595/*
596 * Entered when a bau descriptor has gone into a permanent busy wait because
597 * of a hardware bug.
598 * Workaround the bug.
599 */
600int handle_uv2_busy(struct bau_control *bcp)
601{
c5d35d39 602 struct ptc_stats *stat = bcp->statp;
c5d35d39
CW
603
604 stat->s_uv2_wars++;
8b6e511e
CW
605 bcp->busy = 1;
606 return FLUSH_GIVEUP;
c5d35d39
CW
607}
608
a26fd719 609static int uv2_3_wait_completion(struct bau_desc *bau_desc,
f073cc8f
CW
610 unsigned long mmr_offset, int right_shift,
611 struct bau_control *bcp, long try)
612{
613 unsigned long descriptor_stat;
614 cycles_t ttm;
8b6e511e 615 int desc = bcp->uvhub_cpu;
c5d35d39 616 long busy_reps = 0;
2a919596
JS
617 struct ptc_stats *stat = bcp->statp;
618
a26fd719 619 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
f073cc8f 620
2a919596 621 /* spin on the status MMR, waiting for it to go idle */
f073cc8f 622 while (descriptor_stat != UV2H_DESC_IDLE) {
8b6e511e
CW
623 if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
624 /*
625 * A h/w bug on the destination side may
626 * have prevented the message being marked
627 * pending, thus it doesn't get replied to
628 * and gets continually nacked until it times
629 * out with a SOURCE_TIMEOUT.
630 */
2a919596
JS
631 stat->s_stimeout++;
632 return FLUSH_GIVEUP;
f073cc8f 633 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
8b6e511e
CW
634 ttm = get_cycles();
635
636 /*
637 * Our retries may be blocked by all destination
638 * swack resources being consumed, and a timeout
639 * pending. In that case hardware returns the
640 * ERROR that looks like a destination timeout.
641 * Without using the extended status we have to
642 * deduce from the short time that this was a
643 * strong nack.
644 */
645 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
646 bcp->conseccompletes = 0;
647 stat->s_plugged++;
648 /* FLUSH_RETRY_PLUGGED causes hang on boot */
649 return FLUSH_GIVEUP;
650 }
b8f7fb13 651 stat->s_dtimeout++;
b8f7fb13 652 bcp->conseccompletes = 0;
8b6e511e
CW
653 /* FLUSH_RETRY_TIMEOUT causes hang on boot */
654 return FLUSH_GIVEUP;
b8f7fb13 655 } else {
c5d35d39
CW
656 busy_reps++;
657 if (busy_reps > 1000000) {
658 /* not to hammer on the clock */
659 busy_reps = 0;
660 ttm = get_cycles();
a26fd719 661 if ((ttm - bcp->send_message) > bcp->timeout_interval)
c5d35d39 662 return handle_uv2_busy(bcp);
c5d35d39 663 }
b8f7fb13 664 /*
f073cc8f 665 * descriptor_stat is still BUSY
b8f7fb13
CW
666 */
667 cpu_relax();
b194b120 668 }
a26fd719 669 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
b194b120 670 }
b8f7fb13 671 bcp->conseccompletes++;
b194b120
CW
672 return FLUSH_COMPLETE;
673}
674
f073cc8f
CW
675/*
676 * There are 2 status registers; each and array[32] of 2 bits. Set up for
677 * which register to read and position in that register based on cpu in
678 * current hub.
679 */
a26fd719 680static int wait_completion(struct bau_desc *bau_desc, struct bau_control *bcp, long try)
2a919596 681{
f073cc8f
CW
682 int right_shift;
683 unsigned long mmr_offset;
8b6e511e 684 int desc = bcp->uvhub_cpu;
f073cc8f 685
c5d35d39 686 if (desc < UV_CPUS_PER_AS) {
f073cc8f 687 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
c5d35d39 688 right_shift = desc * UV_ACT_STATUS_SIZE;
f073cc8f
CW
689 } else {
690 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
c5d35d39 691 right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
f073cc8f
CW
692 }
693
da87c937 694 if (bcp->uvhub_version == 1)
a26fd719 695 return uv1_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
2a919596 696 else
a26fd719 697 return uv2_3_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
2a919596
JS
698}
699
b8f7fb13 700/*
f073cc8f 701 * Our retries are blocked by all destination sw ack resources being
f6d8a566
CW
702 * in use, and a timeout is pending. In that case hardware immediately
703 * returns the ERROR that looks like a destination timeout.
704 */
f073cc8f
CW
705static void destination_plugged(struct bau_desc *bau_desc,
706 struct bau_control *bcp,
f6d8a566
CW
707 struct bau_control *hmaster, struct ptc_stats *stat)
708{
709 udelay(bcp->plugged_delay);
710 bcp->plugged_tries++;
f073cc8f 711
f6d8a566
CW
712 if (bcp->plugged_tries >= bcp->plugsb4reset) {
713 bcp->plugged_tries = 0;
f073cc8f 714
f6d8a566 715 quiesce_local_uvhub(hmaster);
f073cc8f 716
f6d8a566 717 spin_lock(&hmaster->queue_lock);
485f07d3 718 reset_with_ipi(&bau_desc->distribution, bcp);
f6d8a566 719 spin_unlock(&hmaster->queue_lock);
f073cc8f 720
f6d8a566 721 end_uvhub_quiesce(hmaster);
f073cc8f 722
f6d8a566
CW
723 bcp->ipi_attempts++;
724 stat->s_resets_plug++;
725 }
726}
727
f073cc8f
CW
728static void destination_timeout(struct bau_desc *bau_desc,
729 struct bau_control *bcp, struct bau_control *hmaster,
730 struct ptc_stats *stat)
f6d8a566 731{
f073cc8f 732 hmaster->max_concurr = 1;
f6d8a566
CW
733 bcp->timeout_tries++;
734 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
735 bcp->timeout_tries = 0;
f073cc8f 736
f6d8a566 737 quiesce_local_uvhub(hmaster);
f073cc8f 738
f6d8a566 739 spin_lock(&hmaster->queue_lock);
485f07d3 740 reset_with_ipi(&bau_desc->distribution, bcp);
f6d8a566 741 spin_unlock(&hmaster->queue_lock);
f073cc8f 742
f6d8a566 743 end_uvhub_quiesce(hmaster);
f073cc8f 744
f6d8a566
CW
745 bcp->ipi_attempts++;
746 stat->s_resets_timeout++;
747 }
748}
749
50fb55ac 750/*
8b6e511e
CW
751 * Stop all cpus on a uvhub from using the BAU for a period of time.
752 * This is reversed by check_enable.
50fb55ac 753 */
8b6e511e 754static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
50fb55ac 755{
8b6e511e
CW
756 int tcpu;
757 struct bau_control *tbcp;
758 struct bau_control *hmaster;
759 cycles_t tm1;
760
761 hmaster = bcp->uvhub_master;
762 spin_lock(&hmaster->disable_lock);
763 if (!bcp->baudisabled) {
50fb55ac 764 stat->s_bau_disabled++;
8b6e511e 765 tm1 = get_cycles();
50fb55ac
CW
766 for_each_present_cpu(tcpu) {
767 tbcp = &per_cpu(bau_control, tcpu);
8b6e511e
CW
768 if (tbcp->uvhub_master == hmaster) {
769 tbcp->baudisabled = 1;
770 tbcp->set_bau_on_time =
771 tm1 + bcp->disabled_period;
772 }
50fb55ac
CW
773 }
774 }
8b6e511e 775 spin_unlock(&hmaster->disable_lock);
50fb55ac
CW
776}
777
f073cc8f
CW
778static void count_max_concurr(int stat, struct bau_control *bcp,
779 struct bau_control *hmaster)
780{
781 bcp->plugged_tries = 0;
782 bcp->timeout_tries = 0;
783 if (stat != FLUSH_COMPLETE)
784 return;
785 if (bcp->conseccompletes <= bcp->complete_threshold)
786 return;
787 if (hmaster->max_concurr >= hmaster->max_concurr_const)
788 return;
789 hmaster->max_concurr++;
790}
791
792static void record_send_stats(cycles_t time1, cycles_t time2,
793 struct bau_control *bcp, struct ptc_stats *stat,
794 int completion_status, int try)
795{
796 cycles_t elapsed;
797
798 if (time2 > time1) {
799 elapsed = time2 - time1;
800 stat->s_time += elapsed;
801
802 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
803 bcp->period_requests++;
804 bcp->period_time += elapsed;
805 if ((elapsed > congested_cycles) &&
8b6e511e
CW
806 (bcp->period_requests > bcp->cong_reps) &&
807 ((bcp->period_time / bcp->period_requests) >
808 congested_cycles)) {
809 stat->s_congested++;
810 disable_for_period(bcp, stat);
811 }
f073cc8f
CW
812 }
813 } else
814 stat->s_requestor--;
815
816 if (completion_status == FLUSH_COMPLETE && try > 1)
817 stat->s_retriesok++;
8b6e511e 818 else if (completion_status == FLUSH_GIVEUP) {
f073cc8f 819 stat->s_giveup++;
8b6e511e
CW
820 if (get_cycles() > bcp->period_end)
821 bcp->period_giveups = 0;
822 bcp->period_giveups++;
823 if (bcp->period_giveups == 1)
824 bcp->period_end = get_cycles() + bcp->disabled_period;
825 if (bcp->period_giveups > bcp->giveup_limit) {
826 disable_for_period(bcp, stat);
827 stat->s_giveuplimit++;
828 }
829 }
f073cc8f
CW
830}
831
832/*
833 * Because of a uv1 hardware bug only a limited number of concurrent
834 * requests can be made.
835 */
836static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
837{
838 spinlock_t *lock = &hmaster->uvhub_lock;
839 atomic_t *v;
840
841 v = &hmaster->active_descriptor_count;
842 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
843 stat->s_throttles++;
844 do {
845 cpu_relax();
846 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
847 }
848}
849
850/*
851 * Handle the completion status of a message send.
852 */
853static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
854 struct bau_control *bcp, struct bau_control *hmaster,
855 struct ptc_stats *stat)
856{
857 if (completion_status == FLUSH_RETRY_PLUGGED)
858 destination_plugged(bau_desc, bcp, hmaster, stat);
859 else if (completion_status == FLUSH_RETRY_TIMEOUT)
860 destination_timeout(bau_desc, bcp, hmaster, stat);
861}
862
863/*
b8f7fb13 864 * Send a broadcast and wait for it to complete.
b194b120 865 *
f6d8a566 866 * The flush_mask contains the cpus the broadcast is to be sent to including
b8f7fb13 867 * cpus that are on the local uvhub.
b194b120 868 *
450a007e
CW
869 * Returns 0 if all flushing represented in the mask was done.
870 * Returns 1 if it gives up entirely and the original cpu mask is to be
871 * returned to the kernel.
b194b120 872 */
8b6e511e
CW
873int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
874 struct bau_desc *bau_desc)
b194b120 875{
b8f7fb13 876 int seq_number = 0;
f073cc8f 877 int completion_stat = 0;
da87c937 878 int uv1 = 0;
b8f7fb13 879 long try = 0;
b4c286e6 880 unsigned long index;
b194b120
CW
881 cycles_t time1;
882 cycles_t time2;
712157aa 883 struct ptc_stats *stat = bcp->statp;
b8f7fb13 884 struct bau_control *hmaster = bcp->uvhub_master;
da87c937 885 struct uv1_bau_msg_header *uv1_hdr = NULL;
a26fd719 886 struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
b8f7fb13 887
8b6e511e
CW
888 if (bcp->uvhub_version == 1) {
889 uv1 = 1;
f073cc8f 890 uv1_throttle(hmaster, stat);
8b6e511e 891 }
f073cc8f 892
b8f7fb13
CW
893 while (hmaster->uvhub_quiesce)
894 cpu_relax();
b194b120 895
b194b120 896 time1 = get_cycles();
8b6e511e
CW
897 if (uv1)
898 uv1_hdr = &bau_desc->header.uv1_hdr;
899 else
a26fd719
CW
900 /* uv2 and uv3 */
901 uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
8b6e511e 902
b194b120 903 do {
8b6e511e 904 if (try == 0) {
da87c937
CW
905 if (uv1)
906 uv1_hdr->msg_type = MSG_REGULAR;
907 else
a26fd719 908 uv2_3_hdr->msg_type = MSG_REGULAR;
b8f7fb13
CW
909 seq_number = bcp->message_number++;
910 } else {
da87c937
CW
911 if (uv1)
912 uv1_hdr->msg_type = MSG_RETRY;
913 else
a26fd719 914 uv2_3_hdr->msg_type = MSG_RETRY;
b8f7fb13
CW
915 stat->s_retry_messages++;
916 }
f073cc8f 917
da87c937
CW
918 if (uv1)
919 uv1_hdr->sequence = seq_number;
920 else
a26fd719 921 uv2_3_hdr->sequence = seq_number;
8b6e511e 922 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
b8f7fb13 923 bcp->send_message = get_cycles();
f073cc8f
CW
924
925 write_mmr_activation(index);
926
b8f7fb13 927 try++;
f073cc8f
CW
928 completion_stat = wait_completion(bau_desc, bcp, try);
929
930 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
b8f7fb13 931
e8e5e8a8 932 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
b8f7fb13 933 bcp->ipi_attempts = 0;
8b6e511e 934 stat->s_overipilimit++;
f073cc8f 935 completion_stat = FLUSH_GIVEUP;
b8f7fb13
CW
936 break;
937 }
938 cpu_relax();
f073cc8f
CW
939 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
940 (completion_stat == FLUSH_RETRY_TIMEOUT));
941
b194b120 942 time2 = get_cycles();
f073cc8f
CW
943
944 count_max_concurr(completion_stat, bcp, hmaster);
945
b8f7fb13
CW
946 while (hmaster->uvhub_quiesce)
947 cpu_relax();
f073cc8f 948
b8f7fb13 949 atomic_dec(&hmaster->active_descriptor_count);
f073cc8f
CW
950
951 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
952
953 if (completion_stat == FLUSH_GIVEUP)
c5d35d39 954 /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
f073cc8f
CW
955 return 1;
956 return 0;
957}
958
959/*
8b6e511e
CW
960 * The BAU is disabled for this uvhub. When the disabled time period has
961 * expired re-enable it.
962 * Return 0 if it is re-enabled for all cpus on this uvhub.
f073cc8f
CW
963 */
964static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
965{
966 int tcpu;
967 struct bau_control *tbcp;
8b6e511e 968 struct bau_control *hmaster;
f073cc8f 969
8b6e511e
CW
970 hmaster = bcp->uvhub_master;
971 spin_lock(&hmaster->disable_lock);
972 if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
973 stat->s_bau_reenabled++;
974 for_each_present_cpu(tcpu) {
975 tbcp = &per_cpu(bau_control, tcpu);
976 if (tbcp->uvhub_master == hmaster) {
f073cc8f
CW
977 tbcp->baudisabled = 0;
978 tbcp->period_requests = 0;
979 tbcp->period_time = 0;
8b6e511e 980 tbcp->period_giveups = 0;
50fb55ac
CW
981 }
982 }
8b6e511e
CW
983 spin_unlock(&hmaster->disable_lock);
984 return 0;
f073cc8f 985 }
8b6e511e 986 spin_unlock(&hmaster->disable_lock);
f073cc8f
CW
987 return -1;
988}
989
990static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
991 int remotes, struct bau_desc *bau_desc)
992{
993 stat->s_requestor++;
994 stat->s_ntargcpu += remotes + locals;
995 stat->s_ntargremotes += remotes;
996 stat->s_ntarglocals += locals;
997
998 /* uvhub statistics */
999 hubs = bau_uvhub_weight(&bau_desc->distribution);
1000 if (locals) {
1001 stat->s_ntarglocaluvhub++;
1002 stat->s_ntargremoteuvhub += (hubs - 1);
e8e5e8a8 1003 } else
f073cc8f
CW
1004 stat->s_ntargremoteuvhub += hubs;
1005
1006 stat->s_ntarguvhub += hubs;
1007
1008 if (hubs >= 16)
1009 stat->s_ntarguvhub16++;
1010 else if (hubs >= 8)
1011 stat->s_ntarguvhub8++;
1012 else if (hubs >= 4)
1013 stat->s_ntarguvhub4++;
1014 else if (hubs >= 2)
1015 stat->s_ntarguvhub2++;
1016 else
1017 stat->s_ntarguvhub1++;
1018}
1019
1020/*
1021 * Translate a cpu mask to the uvhub distribution mask in the BAU
1022 * activation descriptor.
1023 */
1024static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1025 struct bau_desc *bau_desc, int *localsp, int *remotesp)
1026{
1027 int cpu;
1028 int pnode;
1029 int cnt = 0;
1030 struct hub_and_pnode *hpp;
1031
1032 for_each_cpu(cpu, flush_mask) {
1033 /*
1034 * The distribution vector is a bit map of pnodes, relative
1035 * to the partition base pnode (and the partition base nasid
1036 * in the header).
1037 * Translate cpu to pnode and hub using a local memory array.
1038 */
1039 hpp = &bcp->socket_master->thp[cpu];
1040 pnode = hpp->pnode - bcp->partition_base_pnode;
1041 bau_uvhub_set(pnode, &bau_desc->distribution);
1042 cnt++;
1043 if (hpp->uvhub == bcp->uvhub)
1044 (*localsp)++;
1045 else
1046 (*remotesp)++;
b194b120 1047 }
f073cc8f
CW
1048 if (!cnt)
1049 return 1;
450a007e 1050 return 0;
b194b120
CW
1051}
1052
f073cc8f
CW
1053/*
1054 * globally purge translation cache of a virtual address or all TLB's
bdbcdd48 1055 * @cpumask: mask of all cpu's in which the address is to be removed
1812924b 1056 * @mm: mm_struct containing virtual address range
57c4f430
AS
1057 * @start: start virtual address to be removed from TLB
1058 * @end: end virtual address to be remove from TLB
bdbcdd48 1059 * @cpu: the current cpu
1812924b
CW
1060 *
1061 * This is the entry point for initiating any UV global TLB shootdown.
1062 *
1063 * Purges the translation caches of all specified processors of the given
1064 * virtual address, or purges all TLB's on specified processors.
1065 *
bdbcdd48
TH
1066 * The caller has derived the cpumask from the mm_struct. This function
1067 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1812924b 1068 *
b8f7fb13
CW
1069 * The cpumask is converted into a uvhubmask of the uvhubs containing
1070 * those cpus.
b194b120 1071 *
bdbcdd48
TH
1072 * Note that this function should be called with preemption disabled.
1073 *
1074 * Returns NULL if all remote flushing was done.
1075 * Returns pointer to cpumask if some remote flushing remains to be
1076 * done. The returned pointer is valid till preemption is re-enabled.
1812924b 1077 */
bdbcdd48 1078const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
a26fd719
CW
1079 struct mm_struct *mm,
1080 unsigned long start,
1081 unsigned long end,
1082 unsigned int cpu)
1812924b 1083{
b194b120 1084 int locals = 0;
450a007e
CW
1085 int remotes = 0;
1086 int hubs = 0;
dc163a41 1087 struct bau_desc *bau_desc;
b8f7fb13
CW
1088 struct cpumask *flush_mask;
1089 struct ptc_stats *stat;
1090 struct bau_control *bcp;
8b6e511e
CW
1091 unsigned long descriptor_status;
1092 unsigned long status;
bdbcdd48 1093
b8f7fb13 1094 bcp = &per_cpu(bau_control, cpu);
26ef8577
CW
1095
1096 if (bcp->nobau)
1097 return cpumask;
50fb55ac 1098
3eae49ca 1099 stat = bcp->statp;
1100 stat->s_enters++;
1101
8b6e511e
CW
1102 if (bcp->busy) {
1103 descriptor_status =
1104 read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1105 status = ((descriptor_status >> (bcp->uvhub_cpu *
1106 UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1107 if (status == UV2H_DESC_BUSY)
1108 return cpumask;
1109 bcp->busy = 0;
1110 }
1111
50fb55ac
CW
1112 /* bau was disabled due to slow response */
1113 if (bcp->baudisabled) {
8b6e511e
CW
1114 if (check_enable(bcp, stat)) {
1115 stat->s_ipifordisabled++;
f073cc8f 1116 return cpumask;
8b6e511e 1117 }
50fb55ac 1118 }
e8e5e8a8 1119
b8f7fb13
CW
1120 /*
1121 * Each sending cpu has a per-cpu mask which it fills from the caller's
450a007e
CW
1122 * cpu mask. All cpus are converted to uvhubs and copied to the
1123 * activation descriptor.
b8f7fb13
CW
1124 */
1125 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
450a007e 1126 /* don't actually do a shootdown of the local cpu */
b8f7fb13 1127 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
f073cc8f 1128
b8f7fb13 1129 if (cpu_isset(cpu, *cpumask))
450a007e 1130 stat->s_ntargself++;
1812924b 1131
b8f7fb13 1132 bau_desc = bcp->descriptor_base;
8b6e511e 1133 bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
b8f7fb13 1134 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
f073cc8f 1135 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
450a007e 1136 return NULL;
450a007e 1137
f073cc8f 1138 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1812924b 1139
57c4f430
AS
1140 if (!end || (end - start) <= PAGE_SIZE)
1141 bau_desc->payload.address = start;
1142 else
1143 bau_desc->payload.address = TLB_FLUSH_ALL;
bdbcdd48 1144 bau_desc->payload.sending_cpu = cpu;
b8f7fb13 1145 /*
450a007e
CW
1146 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1147 * or 1 if it gave up and the original cpumask should be returned.
b8f7fb13 1148 */
8b6e511e 1149 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
450a007e
CW
1150 return NULL;
1151 else
1152 return cpumask;
1812924b
CW
1153}
1154
c5d35d39 1155/*
8b6e511e
CW
1156 * Search the message queue for any 'other' unprocessed message with the
1157 * same software acknowledge resource bit vector as the 'msg' message.
c5d35d39
CW
1158 */
1159struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
8b6e511e 1160 struct bau_control *bcp)
c5d35d39
CW
1161{
1162 struct bau_pq_entry *msg_next = msg + 1;
8b6e511e 1163 unsigned char swack_vec = msg->swack_vec;
c5d35d39
CW
1164
1165 if (msg_next > bcp->queue_last)
1166 msg_next = bcp->queue_first;
8b6e511e
CW
1167 while (msg_next != msg) {
1168 if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1169 (msg_next->swack_vec == swack_vec))
c5d35d39
CW
1170 return msg_next;
1171 msg_next++;
1172 if (msg_next > bcp->queue_last)
1173 msg_next = bcp->queue_first;
1174 }
1175 return NULL;
1176}
1177
1178/*
1179 * UV2 needs to work around a bug in which an arriving message has not
1180 * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1181 * Such a message must be ignored.
1182 */
1183void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1184{
1185 unsigned long mmr_image;
1186 unsigned char swack_vec;
1187 struct bau_pq_entry *msg = mdp->msg;
1188 struct bau_pq_entry *other_msg;
1189
1190 mmr_image = read_mmr_sw_ack();
1191 swack_vec = msg->swack_vec;
1192
1193 if ((swack_vec & mmr_image) == 0) {
1194 /*
1195 * This message was assigned a swack resource, but no
1196 * reserved acknowlegment is pending.
1197 * The bug has prevented this message from setting the MMR.
c5d35d39 1198 */
c5d35d39 1199 /*
8b6e511e
CW
1200 * Some message has set the MMR 'pending' bit; it might have
1201 * been another message. Look for that message.
c5d35d39 1202 */
8b6e511e
CW
1203 other_msg = find_another_by_swack(msg, bcp);
1204 if (other_msg) {
1205 /*
1206 * There is another. Process this one but do not
1207 * ack it.
1208 */
1209 bau_process_message(mdp, bcp, 0);
1210 /*
1211 * Let the natural processing of that other message
1212 * acknowledge it. Don't get the processing of sw_ack's
1213 * out of order.
1214 */
1215 return;
1216 }
c5d35d39
CW
1217 }
1218
1219 /*
8b6e511e
CW
1220 * Either the MMR shows this one pending a reply or there is no
1221 * other message using this sw_ack, so it is safe to acknowledge it.
c5d35d39
CW
1222 */
1223 bau_process_message(mdp, bcp, 1);
1224
1225 return;
1226}
1227
1812924b
CW
1228/*
1229 * The BAU message interrupt comes here. (registered by set_intr_gate)
1230 * See entry_64.S
1231 *
1232 * We received a broadcast assist message.
1233 *
b8f7fb13 1234 * Interrupts are disabled; this interrupt could represent
1812924b
CW
1235 * the receipt of several messages.
1236 *
b8f7fb13
CW
1237 * All cores/threads on this hub get this interrupt.
1238 * The last one to see it does the software ack.
1812924b 1239 * (the resource will not be freed until noninterruptable cpus see this
b8f7fb13 1240 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1812924b 1241 */
b194b120 1242void uv_bau_message_interrupt(struct pt_regs *regs)
1812924b 1243{
1812924b 1244 int count = 0;
b8f7fb13 1245 cycles_t time_start;
f073cc8f 1246 struct bau_pq_entry *msg;
b8f7fb13
CW
1247 struct bau_control *bcp;
1248 struct ptc_stats *stat;
1249 struct msg_desc msgdesc;
1250
88ed9dd7 1251 ack_APIC_irq();
b8f7fb13 1252 time_start = get_cycles();
f073cc8f 1253
b8f7fb13 1254 bcp = &per_cpu(bau_control, smp_processor_id());
712157aa 1255 stat = bcp->statp;
f073cc8f
CW
1256
1257 msgdesc.queue_first = bcp->queue_first;
1258 msgdesc.queue_last = bcp->queue_last;
1259
b8f7fb13 1260 msg = bcp->bau_msg_head;
f073cc8f 1261 while (msg->swack_vec) {
1812924b 1262 count++;
f073cc8f
CW
1263
1264 msgdesc.msg_slot = msg - msgdesc.queue_first;
b8f7fb13 1265 msgdesc.msg = msg;
c5d35d39
CW
1266 if (bcp->uvhub_version == 2)
1267 process_uv2_message(&msgdesc, bcp);
1268 else
a26fd719 1269 /* no error workaround for uv1 or uv3 */
c5d35d39 1270 bau_process_message(&msgdesc, bcp, 1);
f073cc8f 1271
1812924b 1272 msg++;
f073cc8f
CW
1273 if (msg > msgdesc.queue_last)
1274 msg = msgdesc.queue_first;
b8f7fb13 1275 bcp->bau_msg_head = msg;
1812924b 1276 }
b8f7fb13 1277 stat->d_time += (get_cycles() - time_start);
1812924b 1278 if (!count)
b8f7fb13 1279 stat->d_nomsg++;
1812924b 1280 else if (count > 1)
b8f7fb13 1281 stat->d_multmsg++;
1812924b
CW
1282}
1283
c4c4688f 1284/*
f073cc8f 1285 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
c4c4688f
CW
1286 * shootdown message timeouts enabled. The timeout does not cause
1287 * an interrupt, but causes an error message to be returned to
1288 * the sender.
1289 */
f073cc8f 1290static void __init enable_timeouts(void)
1812924b 1291{
b8f7fb13
CW
1292 int uvhub;
1293 int nuvhubs;
1812924b 1294 int pnode;
c4c4688f 1295 unsigned long mmr_image;
1812924b 1296
b8f7fb13 1297 nuvhubs = uv_num_possible_blades();
1812924b 1298
b8f7fb13
CW
1299 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1300 if (!uv_blade_nr_possible_cpus(uvhub))
1812924b 1301 continue;
c4c4688f 1302
b8f7fb13 1303 pnode = uv_blade_to_pnode(uvhub);
f073cc8f 1304 mmr_image = read_mmr_misc_control(pnode);
c4c4688f
CW
1305 /*
1306 * Set the timeout period and then lock it in, in three
1307 * steps; captures and locks in the period.
1308 *
1309 * To program the period, the SOFT_ACK_MODE must be off.
1310 */
f073cc8f
CW
1311 mmr_image &= ~(1L << SOFTACK_MSHIFT);
1312 write_mmr_misc_control(pnode, mmr_image);
c4c4688f
CW
1313 /*
1314 * Set the 4-bit period.
1315 */
f073cc8f
CW
1316 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1317 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1318 write_mmr_misc_control(pnode, mmr_image);
c4c4688f 1319 /*
2a919596 1320 * UV1:
c4c4688f
CW
1321 * Subsequent reversals of the timebase bit (3) cause an
1322 * immediate timeout of one or all INTD resources as
1323 * indicated in bits 2:0 (7 causes all of them to timeout).
1324 */
f073cc8f 1325 mmr_image |= (1L << SOFTACK_MSHIFT);
2a919596 1326 if (is_uv2_hub()) {
a26fd719 1327 /* do not touch the legacy mode bit */
8b6e511e
CW
1328 /* hw bug workaround; do not use extended status */
1329 mmr_image &= ~(1L << UV2_EXT_SHFT);
a26fd719
CW
1330 } else if (is_uv3_hub()) {
1331 mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
1332 mmr_image |= (1L << SB_STATUS_SHFT);
2a919596 1333 }
f073cc8f 1334 write_mmr_misc_control(pnode, mmr_image);
1812924b 1335 }
1812924b
CW
1336}
1337
f073cc8f 1338static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1812924b
CW
1339{
1340 if (*offset < num_possible_cpus())
1341 return offset;
1342 return NULL;
1343}
1344
f073cc8f 1345static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1812924b
CW
1346{
1347 (*offset)++;
1348 if (*offset < num_possible_cpus())
1349 return offset;
1350 return NULL;
1351}
1352
f073cc8f 1353static void ptc_seq_stop(struct seq_file *file, void *data)
1812924b
CW
1354{
1355}
1356
1357/*
f073cc8f 1358 * Display the statistics thru /proc/sgi_uv/ptc_statistics
b8f7fb13 1359 * 'data' points to the cpu number
f073cc8f 1360 * Note: see the descriptions in stat_description[].
1812924b 1361 */
f073cc8f 1362static int ptc_seq_show(struct seq_file *file, void *data)
1812924b
CW
1363{
1364 struct ptc_stats *stat;
26ef8577 1365 struct bau_control *bcp;
1812924b
CW
1366 int cpu;
1367
1368 cpu = *(loff_t *)data;
1812924b
CW
1369 if (!cpu) {
1370 seq_printf(file,
8b6e511e 1371 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
450a007e
CW
1372 seq_printf(file,
1373 "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1812924b 1374 seq_printf(file,
8b6e511e
CW
1375 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1376 seq_printf(file,
1377 "rok resetp resett giveup sto bz throt disable ");
b8f7fb13 1378 seq_printf(file,
8b6e511e 1379 "enable wars warshw warwaits enters ipidis plugged ");
b8f7fb13 1380 seq_printf(file,
8b6e511e 1381 "ipiover glim cong swack recv rtime all one mult ");
50fb55ac 1382 seq_printf(file,
8b6e511e 1383 "none retry canc nocan reset rcan\n");
1812924b
CW
1384 }
1385 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
26ef8577
CW
1386 bcp = &per_cpu(bau_control, cpu);
1387 stat = bcp->statp;
b8f7fb13
CW
1388 /* source side statistics */
1389 seq_printf(file,
8b6e511e 1390 "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
26ef8577
CW
1391 cpu, bcp->nobau, stat->s_requestor,
1392 cycles_2_us(stat->s_time),
450a007e
CW
1393 stat->s_ntargself, stat->s_ntarglocals,
1394 stat->s_ntargremotes, stat->s_ntargcpu,
1395 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1396 stat->s_ntarguvhub, stat->s_ntarguvhub16);
b54bd9be 1397 seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
b8f7fb13
CW
1398 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1399 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
b54bd9be 1400 stat->s_dtimeout, stat->s_strongnacks);
8b6e511e 1401 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
b8f7fb13
CW
1402 stat->s_retry_messages, stat->s_retriesok,
1403 stat->s_resets_plug, stat->s_resets_timeout,
1404 stat->s_giveup, stat->s_stimeout,
8b6e511e
CW
1405 stat->s_busy, stat->s_throttles);
1406 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1407 stat->s_bau_disabled, stat->s_bau_reenabled,
1408 stat->s_uv2_wars, stat->s_uv2_wars_hw,
1409 stat->s_uv2_war_waits, stat->s_enters,
1410 stat->s_ipifordisabled, stat->s_plugged,
1411 stat->s_overipilimit, stat->s_giveuplimit,
1412 stat->s_congested);
e8e5e8a8 1413
b8f7fb13
CW
1414 /* destination side statistics */
1415 seq_printf(file,
8b6e511e 1416 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
f073cc8f 1417 read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
b8f7fb13
CW
1418 stat->d_requestee, cycles_2_us(stat->d_time),
1419 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1420 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1421 stat->d_nocanceled, stat->d_resets,
1422 stat->d_rcanceled);
1812924b 1423 }
1812924b
CW
1424 return 0;
1425}
1426
e8e5e8a8
CW
1427/*
1428 * Display the tunables thru debugfs
1429 */
1430static ssize_t tunables_read(struct file *file, char __user *userbuf,
f073cc8f 1431 size_t count, loff_t *ppos)
e8e5e8a8 1432{
b365a85c 1433 char *buf;
e8e5e8a8
CW
1434 int ret;
1435
8b6e511e
CW
1436 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1437 "max_concur plugged_delay plugsb4reset timeoutsb4reset",
1438 "ipi_reset_limit complete_threshold congested_response_us",
1439 "congested_reps disabled_period giveup_limit",
f073cc8f 1440 max_concurr, plugged_delay, plugsb4reset,
e8e5e8a8 1441 timeoutsb4reset, ipi_reset_limit, complete_threshold,
8b6e511e
CW
1442 congested_respns_us, congested_reps, disabled_period,
1443 giveup_limit);
e8e5e8a8 1444
b365a85c
DC
1445 if (!buf)
1446 return -ENOMEM;
1447
1448 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1449 kfree(buf);
1450 return ret;
e8e5e8a8
CW
1451}
1452
1812924b 1453/*
f073cc8f
CW
1454 * handle a write to /proc/sgi_uv/ptc_statistics
1455 * -1: reset the statistics
1812924b 1456 * 0: display meaning of the statistics
1812924b 1457 */
f073cc8f
CW
1458static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1459 size_t count, loff_t *data)
1812924b 1460{
b8f7fb13 1461 int cpu;
f073cc8f
CW
1462 int i;
1463 int elements;
b8f7fb13 1464 long input_arg;
1812924b 1465 char optstr[64];
b8f7fb13 1466 struct ptc_stats *stat;
1812924b 1467
e7eb8726 1468 if (count == 0 || count > sizeof(optstr))
cef53278 1469 return -EINVAL;
1812924b
CW
1470 if (copy_from_user(optstr, user, count))
1471 return -EFAULT;
1472 optstr[count - 1] = '\0';
f073cc8f 1473
26ef8577
CW
1474 if (!strcmp(optstr, "on")) {
1475 set_bau_on();
1476 return count;
1477 } else if (!strcmp(optstr, "off")) {
1478 set_bau_off();
1479 return count;
1480 }
1481
164109e3 1482 if (kstrtol(optstr, 10, &input_arg) < 0) {
1812924b
CW
1483 printk(KERN_DEBUG "%s is invalid\n", optstr);
1484 return -EINVAL;
1485 }
1486
b8f7fb13 1487 if (input_arg == 0) {
64441745 1488 elements = ARRAY_SIZE(stat_description);
1812924b 1489 printk(KERN_DEBUG "# cpu: cpu number\n");
b8f7fb13 1490 printk(KERN_DEBUG "Sender statistics:\n");
f073cc8f
CW
1491 for (i = 0; i < elements; i++)
1492 printk(KERN_DEBUG "%s\n", stat_description[i]);
b8f7fb13
CW
1493 } else if (input_arg == -1) {
1494 for_each_present_cpu(cpu) {
1495 stat = &per_cpu(ptcstats, cpu);
1496 memset(stat, 0, sizeof(struct ptc_stats));
1497 }
e8e5e8a8
CW
1498 }
1499
1500 return count;
1501}
1502
1503static int local_atoi(const char *name)
1504{
1505 int val = 0;
1506
1507 for (;; name++) {
1508 switch (*name) {
1509 case '0' ... '9':
1510 val = 10*val+(*name-'0');
1511 break;
1512 default:
1513 return val;
b8f7fb13 1514 }
1812924b 1515 }
e8e5e8a8
CW
1516}
1517
1518/*
f073cc8f
CW
1519 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1520 * Zero values reset them to defaults.
e8e5e8a8 1521 */
f073cc8f
CW
1522static int parse_tunables_write(struct bau_control *bcp, char *instr,
1523 int count)
e8e5e8a8 1524{
e8e5e8a8
CW
1525 char *p;
1526 char *q;
f073cc8f
CW
1527 int cnt = 0;
1528 int val;
64441745 1529 int e = ARRAY_SIZE(tunables);
e8e5e8a8 1530
e8e5e8a8
CW
1531 p = instr + strspn(instr, WHITESPACE);
1532 q = p;
1533 for (; *p; p = q + strspn(q, WHITESPACE)) {
1534 q = p + strcspn(p, WHITESPACE);
1535 cnt++;
1536 if (q == p)
1537 break;
1538 }
f073cc8f
CW
1539 if (cnt != e) {
1540 printk(KERN_INFO "bau tunable error: should be %d values\n", e);
e8e5e8a8
CW
1541 return -EINVAL;
1542 }
1543
1544 p = instr + strspn(instr, WHITESPACE);
1545 q = p;
1546 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1547 q = p + strcspn(p, WHITESPACE);
1548 val = local_atoi(p);
1549 switch (cnt) {
1550 case 0:
1551 if (val == 0) {
f073cc8f
CW
1552 max_concurr = MAX_BAU_CONCURRENT;
1553 max_concurr_const = MAX_BAU_CONCURRENT;
e8e5e8a8
CW
1554 continue;
1555 }
e8e5e8a8
CW
1556 if (val < 1 || val > bcp->cpus_in_uvhub) {
1557 printk(KERN_DEBUG
1558 "Error: BAU max concurrent %d is invalid\n",
1559 val);
1560 return -EINVAL;
1561 }
f073cc8f
CW
1562 max_concurr = val;
1563 max_concurr_const = val;
e8e5e8a8 1564 continue;
f073cc8f 1565 default:
e8e5e8a8 1566 if (val == 0)
f073cc8f 1567 *tunables[cnt].tunp = tunables[cnt].deflt;
e8e5e8a8 1568 else
f073cc8f 1569 *tunables[cnt].tunp = val;
e8e5e8a8
CW
1570 continue;
1571 }
1572 if (q == p)
1573 break;
1574 }
f073cc8f
CW
1575 return 0;
1576}
1577
1578/*
1579 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1580 */
1581static ssize_t tunables_write(struct file *file, const char __user *user,
1582 size_t count, loff_t *data)
1583{
1584 int cpu;
1585 int ret;
1586 char instr[100];
1587 struct bau_control *bcp;
1588
1589 if (count == 0 || count > sizeof(instr)-1)
1590 return -EINVAL;
1591 if (copy_from_user(instr, user, count))
1592 return -EFAULT;
1593
1594 instr[count] = '\0';
1595
00b30cf0 1596 cpu = get_cpu();
1597 bcp = &per_cpu(bau_control, cpu);
f073cc8f 1598 ret = parse_tunables_write(bcp, instr, count);
00b30cf0 1599 put_cpu();
f073cc8f
CW
1600 if (ret)
1601 return ret;
1602
e8e5e8a8
CW
1603 for_each_present_cpu(cpu) {
1604 bcp = &per_cpu(bau_control, cpu);
f073cc8f
CW
1605 bcp->max_concurr = max_concurr;
1606 bcp->max_concurr_const = max_concurr;
1607 bcp->plugged_delay = plugged_delay;
1608 bcp->plugsb4reset = plugsb4reset;
1609 bcp->timeoutsb4reset = timeoutsb4reset;
1610 bcp->ipi_reset_limit = ipi_reset_limit;
1611 bcp->complete_threshold = complete_threshold;
1612 bcp->cong_response_us = congested_respns_us;
1613 bcp->cong_reps = congested_reps;
8b6e511e
CW
1614 bcp->disabled_period = sec_2_cycles(disabled_period);
1615 bcp->giveup_limit = giveup_limit;
e8e5e8a8 1616 }
1812924b
CW
1617 return count;
1618}
1619
1620static const struct seq_operations uv_ptc_seq_ops = {
f073cc8f
CW
1621 .start = ptc_seq_start,
1622 .next = ptc_seq_next,
1623 .stop = ptc_seq_stop,
1624 .show = ptc_seq_show
1812924b
CW
1625};
1626
f073cc8f 1627static int ptc_proc_open(struct inode *inode, struct file *file)
1812924b
CW
1628{
1629 return seq_open(file, &uv_ptc_seq_ops);
1630}
1631
e8e5e8a8
CW
1632static int tunables_open(struct inode *inode, struct file *file)
1633{
1634 return 0;
1635}
1636
1812924b 1637static const struct file_operations proc_uv_ptc_operations = {
f073cc8f 1638 .open = ptc_proc_open,
b194b120 1639 .read = seq_read,
f073cc8f 1640 .write = ptc_proc_write,
b194b120
CW
1641 .llseek = seq_lseek,
1642 .release = seq_release,
1812924b
CW
1643};
1644
e8e5e8a8
CW
1645static const struct file_operations tunables_fops = {
1646 .open = tunables_open,
1647 .read = tunables_read,
1648 .write = tunables_write,
6038f373 1649 .llseek = default_llseek,
e8e5e8a8
CW
1650};
1651
b194b120 1652static int __init uv_ptc_init(void)
1812924b 1653{
b194b120 1654 struct proc_dir_entry *proc_uv_ptc;
1812924b
CW
1655
1656 if (!is_uv_system())
1657 return 0;
1658
10f02d11
AD
1659 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1660 &proc_uv_ptc_operations);
1812924b
CW
1661 if (!proc_uv_ptc) {
1662 printk(KERN_ERR "unable to create %s proc entry\n",
1663 UV_PTC_BASENAME);
1664 return -EINVAL;
1665 }
e8e5e8a8
CW
1666
1667 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1668 if (!tunables_dir) {
1669 printk(KERN_ERR "unable to create debugfs directory %s\n",
1670 UV_BAU_TUNABLES_DIR);
1671 return -EINVAL;
1672 }
1673 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
f073cc8f 1674 tunables_dir, NULL, &tunables_fops);
e8e5e8a8
CW
1675 if (!tunables_file) {
1676 printk(KERN_ERR "unable to create debugfs file %s\n",
1677 UV_BAU_TUNABLES_FILE);
1678 return -EINVAL;
1679 }
1812924b
CW
1680 return 0;
1681}
1682
1812924b 1683/*
77ed23f8 1684 * Initialize the sending side's sending buffers.
1812924b 1685 */
f073cc8f 1686static void activation_descriptor_init(int node, int pnode, int base_pnode)
1812924b
CW
1687{
1688 int i;
b8f7fb13 1689 int cpu;
da87c937 1690 int uv1 = 0;
6a469e46 1691 unsigned long gpa;
1812924b 1692 unsigned long m;
b194b120 1693 unsigned long n;
f073cc8f 1694 size_t dsize;
b8f7fb13
CW
1695 struct bau_desc *bau_desc;
1696 struct bau_desc *bd2;
da87c937 1697 struct uv1_bau_msg_header *uv1_hdr;
a26fd719 1698 struct uv2_3_bau_msg_header *uv2_3_hdr;
b8f7fb13 1699 struct bau_control *bcp;
b194b120 1700
0e2595cd 1701 /*
f073cc8f
CW
1702 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1703 * per cpu; and one per cpu on the uvhub (ADP_SZ)
0e2595cd 1704 */
f073cc8f
CW
1705 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1706 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
b8f7fb13 1707 BUG_ON(!bau_desc);
b4c286e6 1708
6a469e46
JS
1709 gpa = uv_gpa(bau_desc);
1710 n = uv_gpa_to_gnode(gpa);
1711 m = uv_gpa_to_offset(gpa);
da87c937
CW
1712 if (is_uv1_hub())
1713 uv1 = 1;
b4c286e6 1714
77ed23f8 1715 /* the 14-bit pnode */
f073cc8f 1716 write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
0e2595cd 1717 /*
f073cc8f 1718 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
0e2595cd 1719 * cpu even though we only use the first one; one descriptor can
b8f7fb13 1720 * describe a broadcast to 256 uv hubs.
0e2595cd 1721 */
f073cc8f 1722 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
b8f7fb13 1723 memset(bd2, 0, sizeof(struct bau_desc));
da87c937
CW
1724 if (uv1) {
1725 uv1_hdr = &bd2->header.uv1_hdr;
1726 uv1_hdr->swack_flag = 1;
1727 /*
1728 * The base_dest_nasid set in the message header
1729 * is the nasid of the first uvhub in the partition.
1730 * The bit map will indicate destination pnode numbers
1731 * relative to that base. They may not be consecutive
1732 * if nasid striding is being used.
1733 */
1734 uv1_hdr->base_dest_nasid =
1735 UV_PNODE_TO_NASID(base_pnode);
1736 uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1737 uv1_hdr->command = UV_NET_ENDPOINT_INTD;
1738 uv1_hdr->int_both = 1;
1739 /*
1740 * all others need to be set to zero:
1741 * fairness chaining multilevel count replied_to
1742 */
1743 } else {
8b6e511e 1744 /*
a26fd719 1745 * BIOS uses legacy mode, but uv2 and uv3 hardware always
8b6e511e
CW
1746 * uses native mode for selective broadcasts.
1747 */
a26fd719
CW
1748 uv2_3_hdr = &bd2->header.uv2_3_hdr;
1749 uv2_3_hdr->swack_flag = 1;
1750 uv2_3_hdr->base_dest_nasid =
da87c937 1751 UV_PNODE_TO_NASID(base_pnode);
a26fd719
CW
1752 uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1753 uv2_3_hdr->command = UV_NET_ENDPOINT_INTD;
da87c937 1754 }
b194b120 1755 }
b8f7fb13
CW
1756 for_each_present_cpu(cpu) {
1757 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1758 continue;
1759 bcp = &per_cpu(bau_control, cpu);
1760 bcp->descriptor_base = bau_desc;
1761 }
b194b120
CW
1762}
1763
1764/*
1765 * initialize the destination side's receiving buffers
b8f7fb13
CW
1766 * entered for each uvhub in the partition
1767 * - node is first node (kernel memory notion) on the uvhub
1768 * - pnode is the uvhub's physical identifier
b194b120 1769 */
f073cc8f 1770static void pq_init(int node, int pnode)
b194b120 1771{
b8f7fb13 1772 int cpu;
f073cc8f 1773 size_t plsize;
b4c286e6 1774 char *cp;
f073cc8f
CW
1775 void *vp;
1776 unsigned long pn;
1777 unsigned long first;
1778 unsigned long pn_first;
1779 unsigned long last;
1780 struct bau_pq_entry *pqp;
b8f7fb13 1781 struct bau_control *bcp;
1812924b 1782
f073cc8f
CW
1783 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1784 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1785 pqp = (struct bau_pq_entry *)vp;
dc163a41 1786 BUG_ON(!pqp);
b4c286e6 1787
b194b120 1788 cp = (char *)pqp + 31;
f073cc8f 1789 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
b8f7fb13
CW
1790
1791 for_each_present_cpu(cpu) {
1792 if (pnode != uv_cpu_to_pnode(cpu))
1793 continue;
1794 /* for every cpu on this pnode: */
1795 bcp = &per_cpu(bau_control, cpu);
f073cc8f
CW
1796 bcp->queue_first = pqp;
1797 bcp->bau_msg_head = pqp;
1798 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
b8f7fb13 1799 }
4ea3c51d 1800 /*
6a469e46 1801 * need the gnode of where the memory was really allocated
4ea3c51d 1802 */
6a469e46 1803 pn = uv_gpa_to_gnode(uv_gpa(pqp));
f073cc8f
CW
1804 first = uv_physnodeaddr(pqp);
1805 pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
1806 last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
1807 write_mmr_payload_first(pnode, pn_first);
1808 write_mmr_payload_tail(pnode, first);
1809 write_mmr_payload_last(pnode, last);
c5d35d39 1810 write_gmmr_sw_ack(pnode, 0xffffUL);
f073cc8f 1811
b8f7fb13 1812 /* in effect, all msg_type's are set to MSG_NOOP */
f073cc8f 1813 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
b194b120 1814}
1812924b 1815
b194b120 1816/*
b8f7fb13 1817 * Initialization of each UV hub's structures
b194b120 1818 */
f073cc8f 1819static void __init init_uvhub(int uvhub, int vector, int base_pnode)
b194b120 1820{
9674f35b 1821 int node;
b194b120 1822 int pnode;
b194b120 1823 unsigned long apicid;
b8f7fb13
CW
1824
1825 node = uvhub_to_first_node(uvhub);
1826 pnode = uv_blade_to_pnode(uvhub);
f073cc8f
CW
1827
1828 activation_descriptor_init(node, pnode, base_pnode);
1829
1830 pq_init(node, pnode);
b194b120 1831 /*
77ed23f8
CW
1832 * The below initialization can't be in firmware because the
1833 * messaging IRQ will be determined by the OS.
b194b120 1834 */
8191c9f6 1835 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
f073cc8f 1836 write_mmr_data_config(pnode, ((apicid << 32) | vector));
b8f7fb13
CW
1837}
1838
12a6611f
CW
1839/*
1840 * We will set BAU_MISC_CONTROL with a timeout period.
1841 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
f073cc8f 1842 * So the destination timeout period has to be calculated from them.
12a6611f 1843 */
f073cc8f 1844static int calculate_destination_timeout(void)
12a6611f
CW
1845{
1846 unsigned long mmr_image;
1847 int mult1;
1848 int mult2;
1849 int index;
1850 int base;
1851 int ret;
1852 unsigned long ts_ns;
1853
2a919596 1854 if (is_uv1_hub()) {
f073cc8f 1855 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
2a919596
JS
1856 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1857 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1858 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1859 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
11cab711
CW
1860 ts_ns = timeout_base_ns[index];
1861 ts_ns *= (mult1 * mult2);
2a919596
JS
1862 ret = ts_ns / 1000;
1863 } else {
a26fd719 1864 /* same destination timeout for uv2 and uv3 */
d059f9fa
CW
1865 /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
1866 mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
2a919596 1867 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
f073cc8f 1868 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
d059f9fa 1869 base = 80;
2a919596 1870 else
d059f9fa
CW
1871 base = 10;
1872 mult1 = mmr_image & UV2_ACK_MASK;
2a919596
JS
1873 ret = mult1 * base;
1874 }
12a6611f
CW
1875 return ret;
1876}
1877
f073cc8f
CW
1878static void __init init_per_cpu_tunables(void)
1879{
1880 int cpu;
1881 struct bau_control *bcp;
1882
1883 for_each_present_cpu(cpu) {
1884 bcp = &per_cpu(bau_control, cpu);
1885 bcp->baudisabled = 0;
26ef8577
CW
1886 if (nobau)
1887 bcp->nobau = 1;
f073cc8f
CW
1888 bcp->statp = &per_cpu(ptcstats, cpu);
1889 /* time interval to catch a hardware stay-busy bug */
1890 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1891 bcp->max_concurr = max_concurr;
1892 bcp->max_concurr_const = max_concurr;
1893 bcp->plugged_delay = plugged_delay;
1894 bcp->plugsb4reset = plugsb4reset;
1895 bcp->timeoutsb4reset = timeoutsb4reset;
1896 bcp->ipi_reset_limit = ipi_reset_limit;
1897 bcp->complete_threshold = complete_threshold;
1898 bcp->cong_response_us = congested_respns_us;
1899 bcp->cong_reps = congested_reps;
8b6e511e
CW
1900 bcp->disabled_period = sec_2_cycles(disabled_period);
1901 bcp->giveup_limit = giveup_limit;
d2ebc71d
CW
1902 spin_lock_init(&bcp->queue_lock);
1903 spin_lock_init(&bcp->uvhub_lock);
8b6e511e 1904 spin_lock_init(&bcp->disable_lock);
f073cc8f
CW
1905 }
1906}
1907
b8f7fb13 1908/*
f073cc8f 1909 * Scan all cpus to collect blade and socket summaries.
b8f7fb13 1910 */
f073cc8f
CW
1911static int __init get_cpu_topology(int base_pnode,
1912 struct uvhub_desc *uvhub_descs,
1913 unsigned char *uvhub_mask)
b8f7fb13 1914{
b8f7fb13
CW
1915 int cpu;
1916 int pnode;
1917 int uvhub;
f073cc8f 1918 int socket;
b8f7fb13
CW
1919 struct bau_control *bcp;
1920 struct uvhub_desc *bdp;
1921 struct socket_desc *sdp;
b8f7fb13 1922
b8f7fb13
CW
1923 for_each_present_cpu(cpu) {
1924 bcp = &per_cpu(bau_control, cpu);
f073cc8f 1925
b8f7fb13 1926 memset(bcp, 0, sizeof(struct bau_control));
f073cc8f 1927
b8f7fb13 1928 pnode = uv_cpu_hub_info(cpu)->pnode;
f073cc8f 1929 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
77ed23f8
CW
1930 printk(KERN_EMERG
1931 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
f073cc8f 1932 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
77ed23f8
CW
1933 return 1;
1934 }
f073cc8f 1935
77ed23f8 1936 bcp->osnode = cpu_to_node(cpu);
f073cc8f
CW
1937 bcp->partition_base_pnode = base_pnode;
1938
b8f7fb13 1939 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
c4026cfd 1940 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
b8f7fb13 1941 bdp = &uvhub_descs[uvhub];
f073cc8f 1942
b8f7fb13
CW
1943 bdp->num_cpus++;
1944 bdp->uvhub = uvhub;
1945 bdp->pnode = pnode;
f073cc8f 1946
a8328ee5
CW
1947 /* kludge: 'assuming' one node per socket, and assuming that
1948 disabling a socket just leaves a gap in node numbers */
77ed23f8 1949 socket = bcp->osnode & 1;
a8328ee5 1950 bdp->socket_mask |= (1 << socket);
b8f7fb13
CW
1951 sdp = &bdp->socket[socket];
1952 sdp->cpu_number[sdp->num_cpus] = cpu;
1953 sdp->num_cpus++;
cfa60917 1954 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
f073cc8f
CW
1955 printk(KERN_EMERG "%d cpus per socket invalid\n",
1956 sdp->num_cpus);
cfa60917
CW
1957 return 1;
1958 }
b8f7fb13 1959 }
f073cc8f
CW
1960 return 0;
1961}
1962
1963/*
1964 * Each socket is to get a local array of pnodes/hubs.
1965 */
1966static void make_per_cpu_thp(struct bau_control *smaster)
1967{
1968 int cpu;
1969 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
1970
1971 smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
1972 memset(smaster->thp, 0, hpsz);
1973 for_each_present_cpu(cpu) {
1974 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
1975 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1976 }
1977}
1978
442d3924 1979/*
1980 * Each uvhub is to get a local cpumask.
1981 */
1982static void make_per_hub_cpumask(struct bau_control *hmaster)
1983{
1984 int sz = sizeof(cpumask_t);
1985
1986 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
1987}
1988
f073cc8f
CW
1989/*
1990 * Initialize all the per_cpu information for the cpu's on a given socket,
1991 * given what has been gathered into the socket_desc struct.
1992 * And reports the chosen hub and socket masters back to the caller.
1993 */
1994static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
1995 struct bau_control **smasterp,
1996 struct bau_control **hmasterp)
1997{
1998 int i;
1999 int cpu;
2000 struct bau_control *bcp;
2001
2002 for (i = 0; i < sdp->num_cpus; i++) {
2003 cpu = sdp->cpu_number[i];
2004 bcp = &per_cpu(bau_control, cpu);
2005 bcp->cpu = cpu;
2006 if (i == 0) {
2007 *smasterp = bcp;
2008 if (!(*hmasterp))
2009 *hmasterp = bcp;
2010 }
2011 bcp->cpus_in_uvhub = bdp->num_cpus;
2012 bcp->cpus_in_socket = sdp->num_cpus;
2013 bcp->socket_master = *smasterp;
2014 bcp->uvhub = bdp->uvhub;
da87c937
CW
2015 if (is_uv1_hub())
2016 bcp->uvhub_version = 1;
2017 else if (is_uv2_hub())
2018 bcp->uvhub_version = 2;
a26fd719
CW
2019 else if (is_uv3_hub())
2020 bcp->uvhub_version = 3;
da87c937 2021 else {
a26fd719 2022 printk(KERN_EMERG "uvhub version not 1, 2 or 3\n");
da87c937
CW
2023 return 1;
2024 }
f073cc8f
CW
2025 bcp->uvhub_master = *hmasterp;
2026 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
2027 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2028 printk(KERN_EMERG "%d cpus per uvhub invalid\n",
2029 bcp->uvhub_cpu);
2030 return 1;
2031 }
2032 }
2033 return 0;
2034}
2035
2036/*
2037 * Summarize the blade and socket topology into the per_cpu structures.
2038 */
2039static int __init summarize_uvhub_sockets(int nuvhubs,
2040 struct uvhub_desc *uvhub_descs,
2041 unsigned char *uvhub_mask)
2042{
2043 int socket;
2044 int uvhub;
2045 unsigned short socket_mask;
2046
c4026cfd 2047 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
f073cc8f
CW
2048 struct uvhub_desc *bdp;
2049 struct bau_control *smaster = NULL;
2050 struct bau_control *hmaster = NULL;
2051
c4026cfd
CW
2052 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2053 continue;
f073cc8f 2054
b8f7fb13 2055 bdp = &uvhub_descs[uvhub];
a8328ee5
CW
2056 socket_mask = bdp->socket_mask;
2057 socket = 0;
2058 while (socket_mask) {
f073cc8f
CW
2059 struct socket_desc *sdp;
2060 if ((socket_mask & 1)) {
2061 sdp = &bdp->socket[socket];
2062 if (scan_sock(sdp, bdp, &smaster, &hmaster))
cfa60917 2063 return 1;
9c9153db 2064 make_per_cpu_thp(smaster);
b8f7fb13
CW
2065 }
2066 socket++;
a8328ee5 2067 socket_mask = (socket_mask >> 1);
b8f7fb13 2068 }
442d3924 2069 make_per_hub_cpumask(hmaster);
b8f7fb13 2070 }
f073cc8f
CW
2071 return 0;
2072}
2073
2074/*
2075 * initialize the bau_control structure for each cpu
2076 */
2077static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2078{
2079 unsigned char *uvhub_mask;
2080 void *vp;
2081 struct uvhub_desc *uvhub_descs;
2082
2083 timeout_us = calculate_destination_timeout();
2084
2085 vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
2086 uvhub_descs = (struct uvhub_desc *)vp;
2087 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
2088 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2089
2090 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
bbd270e6 2091 goto fail;
f073cc8f
CW
2092
2093 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
bbd270e6 2094 goto fail;
f073cc8f 2095
b8f7fb13 2096 kfree(uvhub_descs);
c4026cfd 2097 kfree(uvhub_mask);
f073cc8f 2098 init_per_cpu_tunables();
cfa60917 2099 return 0;
bbd270e6 2100
2101fail:
2102 kfree(uvhub_descs);
2103 kfree(uvhub_mask);
2104 return 1;
b194b120
CW
2105}
2106
2107/*
2108 * Initialization of BAU-related structures
2109 */
2110static int __init uv_bau_init(void)
2111{
b8f7fb13
CW
2112 int uvhub;
2113 int pnode;
2114 int nuvhubs;
2c74d666 2115 int cur_cpu;
f073cc8f 2116 int cpus;
b8f7fb13 2117 int vector;
f073cc8f 2118 cpumask_var_t *mask;
b194b120
CW
2119
2120 if (!is_uv_system())
2121 return 0;
1812924b 2122
f073cc8f
CW
2123 for_each_possible_cpu(cur_cpu) {
2124 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2125 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2126 }
76ba0ecd 2127
b8f7fb13 2128 nuvhubs = uv_num_possible_blades();
f073cc8f 2129 congested_cycles = usec_2_cycles(congested_respns_us);
9674f35b 2130
f073cc8f 2131 uv_base_pnode = 0x7fffffff;
77ed23f8 2132 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
f073cc8f
CW
2133 cpus = uv_blade_nr_possible_cpus(uvhub);
2134 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2135 uv_base_pnode = uv_blade_to_pnode(uvhub);
77ed23f8
CW
2136 }
2137
d059f9fa
CW
2138 enable_timeouts();
2139
f073cc8f 2140 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
26ef8577
CW
2141 set_bau_off();
2142 nobau_perm = 1;
77ed23f8
CW
2143 return 0;
2144 }
b8f7fb13
CW
2145
2146 vector = UV_BAU_MESSAGE;
a26fd719 2147 for_each_possible_blade(uvhub) {
b8f7fb13 2148 if (uv_blade_nr_possible_cpus(uvhub))
f073cc8f 2149 init_uvhub(uvhub, vector, uv_base_pnode);
a26fd719 2150 }
b8f7fb13 2151
b8f7fb13
CW
2152 alloc_intr_gate(vector, uv_bau_message_intr1);
2153
2154 for_each_possible_blade(uvhub) {
93a7ca0c 2155 if (uv_blade_nr_possible_cpus(uvhub)) {
f073cc8f
CW
2156 unsigned long val;
2157 unsigned long mmr;
93a7ca0c
CW
2158 pnode = uv_blade_to_pnode(uvhub);
2159 /* INIT the bau */
f073cc8f
CW
2160 val = 1L << 63;
2161 write_gmmr_activation(pnode, val);
93a7ca0c 2162 mmr = 1; /* should be 1 to broadcast to both sockets */
da87c937
CW
2163 if (!is_uv1_hub())
2164 write_mmr_data_broadcast(pnode, mmr);
93a7ca0c 2165 }
b8f7fb13 2166 }
b4c286e6 2167
1812924b
CW
2168 return 0;
2169}
b8f7fb13 2170core_initcall(uv_bau_init);
e8e5e8a8 2171fs_initcall(uv_ptc_init);