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Commit | Line | Data |
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1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
a26fd719 | 4 | * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI. |
1812924b CW |
5 | * |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b | 10 | #include <linux/proc_fs.h> |
e8e5e8a8 | 11 | #include <linux/debugfs.h> |
1812924b | 12 | #include <linux/kernel.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
ca444564 | 14 | #include <linux/delay.h> |
1812924b | 15 | |
1812924b | 16 | #include <asm/mmu_context.h> |
bdbcdd48 | 17 | #include <asm/uv/uv.h> |
1812924b | 18 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 19 | #include <asm/uv/uv_hub.h> |
1812924b | 20 | #include <asm/uv/uv_bau.h> |
7b6aa335 | 21 | #include <asm/apic.h> |
b194b120 | 22 | #include <asm/tsc.h> |
99dd8713 | 23 | #include <asm/irq_vectors.h> |
b8f7fb13 | 24 | #include <asm/timer.h> |
1812924b | 25 | |
5e4f96fe AB |
26 | static struct bau_operations ops; |
27 | ||
28 | static struct bau_operations uv123_bau_ops = { | |
29 | .bau_gpa_to_offset = uv_gpa_to_offset, | |
30 | .read_l_sw_ack = read_mmr_sw_ack, | |
31 | .read_g_sw_ack = read_gmmr_sw_ack, | |
32 | .write_l_sw_ack = write_mmr_sw_ack, | |
33 | .write_g_sw_ack = write_gmmr_sw_ack, | |
34 | .write_payload_first = write_mmr_payload_first, | |
35 | .write_payload_last = write_mmr_payload_last, | |
36 | }; | |
37 | ||
4f059d51 AB |
38 | static struct bau_operations uv4_bau_ops = { |
39 | .bau_gpa_to_offset = uv_gpa_to_soc_phys_ram, | |
40 | .read_l_sw_ack = read_mmr_proc_sw_ack, | |
41 | .read_g_sw_ack = read_gmmr_proc_sw_ack, | |
42 | .write_l_sw_ack = write_mmr_proc_sw_ack, | |
43 | .write_g_sw_ack = write_gmmr_proc_sw_ack, | |
44 | .write_payload_first = write_mmr_proc_payload_first, | |
45 | .write_payload_last = write_mmr_proc_payload_last, | |
46 | }; | |
47 | ||
48 | ||
12a6611f CW |
49 | /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */ |
50 | static int timeout_base_ns[] = { | |
51 | 20, | |
52 | 160, | |
53 | 1280, | |
54 | 10240, | |
55 | 81920, | |
56 | 655360, | |
57 | 5242880, | |
58 | 167772160 | |
59 | }; | |
f073cc8f | 60 | |
12a6611f | 61 | static int timeout_us; |
1c532e00 | 62 | static bool nobau = true; |
26ef8577 | 63 | static int nobau_perm; |
50fb55ac | 64 | static cycles_t congested_cycles; |
12a6611f | 65 | |
e8e5e8a8 | 66 | /* tunables: */ |
f073cc8f CW |
67 | static int max_concurr = MAX_BAU_CONCURRENT; |
68 | static int max_concurr_const = MAX_BAU_CONCURRENT; | |
69 | static int plugged_delay = PLUGGED_DELAY; | |
70 | static int plugsb4reset = PLUGSB4RESET; | |
8b6e511e | 71 | static int giveup_limit = GIVEUP_LIMIT; |
f073cc8f CW |
72 | static int timeoutsb4reset = TIMEOUTSB4RESET; |
73 | static int ipi_reset_limit = IPI_RESET_LIMIT; | |
74 | static int complete_threshold = COMPLETE_THRESHOLD; | |
75 | static int congested_respns_us = CONGESTED_RESPONSE_US; | |
76 | static int congested_reps = CONGESTED_REPS; | |
8b6e511e | 77 | static int disabled_period = DISABLED_PERIOD; |
f073cc8f CW |
78 | |
79 | static struct tunables tunables[] = { | |
67492c86 AB |
80 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ |
81 | {&plugged_delay, PLUGGED_DELAY}, | |
82 | {&plugsb4reset, PLUGSB4RESET}, | |
83 | {&timeoutsb4reset, TIMEOUTSB4RESET}, | |
84 | {&ipi_reset_limit, IPI_RESET_LIMIT}, | |
85 | {&complete_threshold, COMPLETE_THRESHOLD}, | |
86 | {&congested_respns_us, CONGESTED_RESPONSE_US}, | |
87 | {&congested_reps, CONGESTED_REPS}, | |
88 | {&disabled_period, DISABLED_PERIOD}, | |
89 | {&giveup_limit, GIVEUP_LIMIT} | |
f073cc8f CW |
90 | }; |
91 | ||
e8e5e8a8 CW |
92 | static struct dentry *tunables_dir; |
93 | static struct dentry *tunables_file; | |
b4c286e6 | 94 | |
f073cc8f CW |
95 | /* these correspond to the statistics printed by ptc_seq_show() */ |
96 | static char *stat_description[] = { | |
97 | "sent: number of shootdown messages sent", | |
98 | "stime: time spent sending messages", | |
99 | "numuvhubs: number of hubs targeted with shootdown", | |
100 | "numuvhubs16: number times 16 or more hubs targeted", | |
101 | "numuvhubs8: number times 8 or more hubs targeted", | |
102 | "numuvhubs4: number times 4 or more hubs targeted", | |
103 | "numuvhubs2: number times 2 or more hubs targeted", | |
104 | "numuvhubs1: number times 1 hub targeted", | |
105 | "numcpus: number of cpus targeted with shootdown", | |
106 | "dto: number of destination timeouts", | |
107 | "retries: destination timeout retries sent", | |
108 | "rok: : destination timeouts successfully retried", | |
109 | "resetp: ipi-style resource resets for plugs", | |
110 | "resett: ipi-style resource resets for timeouts", | |
111 | "giveup: fall-backs to ipi-style shootdowns", | |
112 | "sto: number of source timeouts", | |
113 | "bz: number of stay-busy's", | |
114 | "throt: number times spun in throttle", | |
115 | "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE", | |
116 | "recv: shootdown messages received", | |
117 | "rtime: time spent processing messages", | |
118 | "all: shootdown all-tlb messages", | |
119 | "one: shootdown one-tlb messages", | |
120 | "mult: interrupts that found multiple messages", | |
121 | "none: interrupts that found no messages", | |
122 | "retry: number of retry messages processed", | |
123 | "canc: number messages canceled by retries", | |
124 | "nocan: number retries that found nothing to cancel", | |
125 | "reset: number of ipi-style reset requests processed", | |
126 | "rcan: number messages canceled by reset requests", | |
127 | "disable: number times use of the BAU was disabled", | |
128 | "enable: number times use of the BAU was re-enabled" | |
129 | }; | |
130 | ||
1c532e00 | 131 | static int __init setup_bau(char *arg) |
b8f7fb13 | 132 | { |
1c532e00 AT |
133 | int result; |
134 | ||
135 | if (!arg) | |
136 | return -EINVAL; | |
137 | ||
138 | result = strtobool(arg, &nobau); | |
139 | if (result) | |
140 | return result; | |
141 | ||
142 | /* we need to flip the logic here, so that bau=y sets nobau to false */ | |
143 | nobau = !nobau; | |
144 | ||
145 | if (!nobau) | |
146 | pr_info("UV BAU Enabled\n"); | |
147 | else | |
148 | pr_info("UV BAU Disabled\n"); | |
149 | ||
b8f7fb13 CW |
150 | return 0; |
151 | } | |
1c532e00 | 152 | early_param("bau", setup_bau); |
b4c286e6 | 153 | |
b8f7fb13 | 154 | /* base pnode in this partition */ |
f073cc8f | 155 | static int uv_base_pnode __read_mostly; |
1812924b | 156 | |
dc163a41 IM |
157 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
158 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
b8f7fb13 CW |
159 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); |
160 | ||
26ef8577 CW |
161 | static void |
162 | set_bau_on(void) | |
163 | { | |
164 | int cpu; | |
165 | struct bau_control *bcp; | |
166 | ||
167 | if (nobau_perm) { | |
168 | pr_info("BAU not initialized; cannot be turned on\n"); | |
169 | return; | |
170 | } | |
1c532e00 | 171 | nobau = false; |
26ef8577 CW |
172 | for_each_present_cpu(cpu) { |
173 | bcp = &per_cpu(bau_control, cpu); | |
1c532e00 | 174 | bcp->nobau = false; |
26ef8577 CW |
175 | } |
176 | pr_info("BAU turned on\n"); | |
177 | return; | |
178 | } | |
179 | ||
180 | static void | |
181 | set_bau_off(void) | |
182 | { | |
183 | int cpu; | |
184 | struct bau_control *bcp; | |
185 | ||
1c532e00 | 186 | nobau = true; |
26ef8577 CW |
187 | for_each_present_cpu(cpu) { |
188 | bcp = &per_cpu(bau_control, cpu); | |
1c532e00 | 189 | bcp->nobau = true; |
26ef8577 CW |
190 | } |
191 | pr_info("BAU turned off\n"); | |
192 | return; | |
193 | } | |
194 | ||
9674f35b | 195 | /* |
b8f7fb13 CW |
196 | * Determine the first node on a uvhub. 'Nodes' are used for kernel |
197 | * memory allocation. | |
9674f35b | 198 | */ |
b8f7fb13 | 199 | static int __init uvhub_to_first_node(int uvhub) |
9674f35b CW |
200 | { |
201 | int node, b; | |
202 | ||
203 | for_each_online_node(node) { | |
204 | b = uv_node_to_blade_id(node); | |
b8f7fb13 | 205 | if (uvhub == b) |
9674f35b CW |
206 | return node; |
207 | } | |
b8f7fb13 | 208 | return -1; |
9674f35b CW |
209 | } |
210 | ||
211 | /* | |
b8f7fb13 | 212 | * Determine the apicid of the first cpu on a uvhub. |
9674f35b | 213 | */ |
b8f7fb13 | 214 | static int __init uvhub_to_first_apicid(int uvhub) |
9674f35b CW |
215 | { |
216 | int cpu; | |
217 | ||
218 | for_each_present_cpu(cpu) | |
b8f7fb13 | 219 | if (uvhub == uv_cpu_to_blade_id(cpu)) |
9674f35b CW |
220 | return per_cpu(x86_cpu_to_apicid, cpu); |
221 | return -1; | |
222 | } | |
223 | ||
1812924b CW |
224 | /* |
225 | * Free a software acknowledge hardware resource by clearing its Pending | |
226 | * bit. This will return a reply to the sender. | |
227 | * If the message has timed out, a reply has already been sent by the | |
228 | * hardware but the resource has not been released. In that case our | |
229 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
230 | * be sent (the hardware will only do one reply per message). | |
231 | */ | |
c5d35d39 CW |
232 | static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp, |
233 | int do_acknowledge) | |
1812924b | 234 | { |
b194b120 | 235 | unsigned long dw; |
f073cc8f | 236 | struct bau_pq_entry *msg; |
1812924b | 237 | |
b8f7fb13 | 238 | msg = mdp->msg; |
c5d35d39 | 239 | if (!msg->canceled && do_acknowledge) { |
f073cc8f | 240 | dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; |
21e3f12f | 241 | ops.write_l_sw_ack(dw); |
b8f7fb13 | 242 | } |
1812924b | 243 | msg->replied_to = 1; |
f073cc8f | 244 | msg->swack_vec = 0; |
1812924b CW |
245 | } |
246 | ||
247 | /* | |
b8f7fb13 | 248 | * Process the receipt of a RETRY message |
1812924b | 249 | */ |
f073cc8f CW |
250 | static void bau_process_retry_msg(struct msg_desc *mdp, |
251 | struct bau_control *bcp) | |
1812924b | 252 | { |
b8f7fb13 CW |
253 | int i; |
254 | int cancel_count = 0; | |
b8f7fb13 CW |
255 | unsigned long msg_res; |
256 | unsigned long mmr = 0; | |
f073cc8f CW |
257 | struct bau_pq_entry *msg = mdp->msg; |
258 | struct bau_pq_entry *msg2; | |
259 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 260 | |
b8f7fb13 CW |
261 | stat->d_retries++; |
262 | /* | |
263 | * cancel any message from msg+1 to the retry itself | |
264 | */ | |
265 | for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { | |
f073cc8f CW |
266 | if (msg2 > mdp->queue_last) |
267 | msg2 = mdp->queue_first; | |
b8f7fb13 CW |
268 | if (msg2 == msg) |
269 | break; | |
270 | ||
f073cc8f | 271 | /* same conditions for cancellation as do_reset */ |
b8f7fb13 | 272 | if ((msg2->replied_to == 0) && (msg2->canceled == 0) && |
f073cc8f CW |
273 | (msg2->swack_vec) && ((msg2->swack_vec & |
274 | msg->swack_vec) == 0) && | |
b8f7fb13 CW |
275 | (msg2->sending_cpu == msg->sending_cpu) && |
276 | (msg2->msg_type != MSG_NOOP)) { | |
21e3f12f | 277 | mmr = ops.read_l_sw_ack(); |
f073cc8f | 278 | msg_res = msg2->swack_vec; |
b8f7fb13 CW |
279 | /* |
280 | * This is a message retry; clear the resources held | |
281 | * by the previous message only if they timed out. | |
282 | * If it has not timed out we have an unexpected | |
283 | * situation to report. | |
284 | */ | |
39847e7f | 285 | if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { |
f073cc8f | 286 | unsigned long mr; |
b8f7fb13 | 287 | /* |
c5d35d39 CW |
288 | * Is the resource timed out? |
289 | * Make everyone ignore the cancelled message. | |
b8f7fb13 CW |
290 | */ |
291 | msg2->canceled = 1; | |
292 | stat->d_canceled++; | |
293 | cancel_count++; | |
f073cc8f | 294 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; |
21e3f12f | 295 | ops.write_l_sw_ack(mr); |
39847e7f | 296 | } |
b8f7fb13 CW |
297 | } |
298 | } | |
299 | if (!cancel_count) | |
300 | stat->d_nocanceled++; | |
301 | } | |
1812924b | 302 | |
b8f7fb13 CW |
303 | /* |
304 | * Do all the things a cpu should do for a TLB shootdown message. | |
305 | * Other cpu's may come here at the same time for this message. | |
306 | */ | |
c5d35d39 CW |
307 | static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp, |
308 | int do_acknowledge) | |
b8f7fb13 | 309 | { |
b8f7fb13 | 310 | short socket_ack_count = 0; |
f073cc8f CW |
311 | short *sp; |
312 | struct atomic_short *asp; | |
313 | struct ptc_stats *stat = bcp->statp; | |
314 | struct bau_pq_entry *msg = mdp->msg; | |
b8f7fb13 | 315 | struct bau_control *smaster = bcp->socket_master; |
1812924b | 316 | |
b8f7fb13 CW |
317 | /* |
318 | * This must be a normal message, or retry of a normal message | |
319 | */ | |
1812924b CW |
320 | if (msg->address == TLB_FLUSH_ALL) { |
321 | local_flush_tlb(); | |
b8f7fb13 | 322 | stat->d_alltlb++; |
1812924b CW |
323 | } else { |
324 | __flush_tlb_one(msg->address); | |
b8f7fb13 | 325 | stat->d_onetlb++; |
1812924b | 326 | } |
b8f7fb13 CW |
327 | stat->d_requestee++; |
328 | ||
329 | /* | |
330 | * One cpu on each uvhub has the additional job on a RETRY | |
331 | * of releasing the resource held by the message that is | |
332 | * being retried. That message is identified by sending | |
333 | * cpu number. | |
334 | */ | |
335 | if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) | |
f073cc8f | 336 | bau_process_retry_msg(mdp, bcp); |
1812924b | 337 | |
b8f7fb13 | 338 | /* |
f073cc8f | 339 | * This is a swack message, so we have to reply to it. |
b8f7fb13 CW |
340 | * Count each responding cpu on the socket. This avoids |
341 | * pinging the count's cache line back and forth between | |
342 | * the sockets. | |
343 | */ | |
f073cc8f CW |
344 | sp = &smaster->socket_acknowledge_count[mdp->msg_slot]; |
345 | asp = (struct atomic_short *)sp; | |
346 | socket_ack_count = atom_asr(1, asp); | |
b8f7fb13 | 347 | if (socket_ack_count == bcp->cpus_in_socket) { |
f073cc8f | 348 | int msg_ack_count; |
b8f7fb13 CW |
349 | /* |
350 | * Both sockets dump their completed count total into | |
351 | * the message's count. | |
352 | */ | |
8b6e511e | 353 | *sp = 0; |
f073cc8f CW |
354 | asp = (struct atomic_short *)&msg->acknowledge_count; |
355 | msg_ack_count = atom_asr(socket_ack_count, asp); | |
b8f7fb13 CW |
356 | |
357 | if (msg_ack_count == bcp->cpus_in_uvhub) { | |
358 | /* | |
359 | * All cpus in uvhub saw it; reply | |
c5d35d39 | 360 | * (unless we are in the UV2 workaround) |
b8f7fb13 | 361 | */ |
c5d35d39 | 362 | reply_to_message(mdp, bcp, do_acknowledge); |
b8f7fb13 CW |
363 | } |
364 | } | |
1812924b | 365 | |
b8f7fb13 | 366 | return; |
1812924b CW |
367 | } |
368 | ||
369 | /* | |
485f07d3 | 370 | * Determine the first cpu on a pnode. |
b8f7fb13 | 371 | */ |
485f07d3 | 372 | static int pnode_to_first_cpu(int pnode, struct bau_control *smaster) |
b8f7fb13 CW |
373 | { |
374 | int cpu; | |
485f07d3 | 375 | struct hub_and_pnode *hpp; |
376 | ||
377 | for_each_present_cpu(cpu) { | |
378 | hpp = &smaster->thp[cpu]; | |
379 | if (pnode == hpp->pnode) | |
b8f7fb13 | 380 | return cpu; |
485f07d3 | 381 | } |
b8f7fb13 CW |
382 | return -1; |
383 | } | |
384 | ||
385 | /* | |
386 | * Last resort when we get a large number of destination timeouts is | |
387 | * to clear resources held by a given cpu. | |
388 | * Do this with IPI so that all messages in the BAU message queue | |
f073cc8f | 389 | * can be identified by their nonzero swack_vec field. |
1812924b | 390 | * |
b8f7fb13 CW |
391 | * This is entered for a single cpu on the uvhub. |
392 | * The sender want's this uvhub to free a specific message's | |
f073cc8f | 393 | * swack resources. |
1812924b | 394 | */ |
f073cc8f | 395 | static void do_reset(void *ptr) |
1812924b | 396 | { |
b4c286e6 | 397 | int i; |
f073cc8f CW |
398 | struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id()); |
399 | struct reset_args *rap = (struct reset_args *)ptr; | |
400 | struct bau_pq_entry *msg; | |
401 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 402 | |
b8f7fb13 | 403 | stat->d_resets++; |
b8f7fb13 CW |
404 | /* |
405 | * We're looking for the given sender, and | |
f073cc8f | 406 | * will free its swack resource. |
b8f7fb13 CW |
407 | * If all cpu's finally responded after the timeout, its |
408 | * message 'replied_to' was set. | |
409 | */ | |
f073cc8f CW |
410 | for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { |
411 | unsigned long msg_res; | |
412 | /* do_reset: same conditions for cancellation as | |
413 | bau_process_retry_msg() */ | |
b8f7fb13 CW |
414 | if ((msg->replied_to == 0) && |
415 | (msg->canceled == 0) && | |
416 | (msg->sending_cpu == rap->sender) && | |
f073cc8f | 417 | (msg->swack_vec) && |
b8f7fb13 | 418 | (msg->msg_type != MSG_NOOP)) { |
f073cc8f CW |
419 | unsigned long mmr; |
420 | unsigned long mr; | |
b8f7fb13 CW |
421 | /* |
422 | * make everyone else ignore this message | |
423 | */ | |
424 | msg->canceled = 1; | |
b8f7fb13 CW |
425 | /* |
426 | * only reset the resource if it is still pending | |
427 | */ | |
21e3f12f | 428 | mmr = ops.read_l_sw_ack(); |
f073cc8f CW |
429 | msg_res = msg->swack_vec; |
430 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; | |
b8f7fb13 CW |
431 | if (mmr & msg_res) { |
432 | stat->d_rcanceled++; | |
21e3f12f | 433 | ops.write_l_sw_ack(mr); |
dc163a41 | 434 | } |
dc163a41 IM |
435 | } |
436 | } | |
b8f7fb13 | 437 | return; |
dc163a41 IM |
438 | } |
439 | ||
440 | /* | |
b8f7fb13 CW |
441 | * Use IPI to get all target uvhubs to release resources held by |
442 | * a given sending cpu number. | |
dc163a41 | 443 | */ |
a456eaab | 444 | static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp) |
dc163a41 | 445 | { |
485f07d3 | 446 | int pnode; |
447 | int apnode; | |
f073cc8f | 448 | int maskbits; |
485f07d3 | 449 | int sender = bcp->cpu; |
442d3924 | 450 | cpumask_t *mask = bcp->uvhub_master->cpumask; |
485f07d3 | 451 | struct bau_control *smaster = bcp->socket_master; |
b8f7fb13 | 452 | struct reset_args reset_args; |
dc163a41 | 453 | |
b8f7fb13 | 454 | reset_args.sender = sender; |
020b37ac | 455 | cpumask_clear(mask); |
b8f7fb13 | 456 | /* find a single cpu for each uvhub in this distribution mask */ |
a456eaab | 457 | maskbits = sizeof(struct pnmask) * BITSPERBYTE; |
485f07d3 | 458 | /* each bit is a pnode relative to the partition base pnode */ |
459 | for (pnode = 0; pnode < maskbits; pnode++) { | |
f073cc8f | 460 | int cpu; |
485f07d3 | 461 | if (!bau_uvhub_isset(pnode, distribution)) |
b194b120 | 462 | continue; |
485f07d3 | 463 | apnode = pnode + bcp->partition_base_pnode; |
464 | cpu = pnode_to_first_cpu(apnode, smaster); | |
020b37ac | 465 | cpumask_set_cpu(cpu, mask); |
1812924b | 466 | } |
f073cc8f CW |
467 | |
468 | /* IPI all cpus; preemption is already disabled */ | |
442d3924 | 469 | smp_call_function_many(mask, do_reset, (void *)&reset_args, 1); |
b8f7fb13 CW |
470 | return; |
471 | } | |
472 | ||
20d1c86a PZ |
473 | /* |
474 | * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative | |
475 | * number, not an absolute. It converts a duration in cycles to a duration in | |
476 | * ns. | |
477 | */ | |
478 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) | |
b8f7fb13 | 479 | { |
20d1c86a | 480 | struct cyc2ns_data *data = cyc2ns_read_begin(); |
b8f7fb13 | 481 | unsigned long long ns; |
f073cc8f | 482 | |
20d1c86a PZ |
483 | ns = mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
484 | ||
485 | cyc2ns_read_end(data); | |
486 | return ns; | |
487 | } | |
488 | ||
489 | /* | |
490 | * The reverse of the above; converts a duration in ns to a duration in cycles. | |
a26fd719 | 491 | */ |
20d1c86a PZ |
492 | static inline unsigned long long ns_2_cycles(unsigned long long ns) |
493 | { | |
494 | struct cyc2ns_data *data = cyc2ns_read_begin(); | |
495 | unsigned long long cyc; | |
496 | ||
497 | cyc = (ns << data->cyc2ns_shift) / data->cyc2ns_mul; | |
498 | ||
499 | cyc2ns_read_end(data); | |
500 | return cyc; | |
501 | } | |
502 | ||
503 | static inline unsigned long cycles_2_us(unsigned long long cyc) | |
504 | { | |
505 | return cycles_2_ns(cyc) / NSEC_PER_USEC; | |
506 | } | |
507 | ||
508 | static inline cycles_t sec_2_cycles(unsigned long sec) | |
509 | { | |
510 | return ns_2_cycles(sec * NSEC_PER_SEC); | |
511 | } | |
512 | ||
513 | static inline unsigned long long usec_2_cycles(unsigned long usec) | |
514 | { | |
515 | return ns_2_cycles(usec * NSEC_PER_USEC); | |
1812924b CW |
516 | } |
517 | ||
b194b120 | 518 | /* |
b8f7fb13 CW |
519 | * wait for all cpus on this hub to finish their sends and go quiet |
520 | * leaves uvhub_quiesce set so that no new broadcasts are started by | |
521 | * bau_flush_send_and_wait() | |
522 | */ | |
f073cc8f | 523 | static inline void quiesce_local_uvhub(struct bau_control *hmaster) |
b8f7fb13 | 524 | { |
f073cc8f | 525 | atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
b8f7fb13 CW |
526 | } |
527 | ||
528 | /* | |
529 | * mark this quiet-requestor as done | |
530 | */ | |
f073cc8f | 531 | static inline void end_uvhub_quiesce(struct bau_control *hmaster) |
b8f7fb13 | 532 | { |
f073cc8f CW |
533 | atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
534 | } | |
535 | ||
536 | static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift) | |
537 | { | |
538 | unsigned long descriptor_status; | |
539 | ||
540 | descriptor_status = uv_read_local_mmr(mmr_offset); | |
541 | descriptor_status >>= right_shift; | |
542 | descriptor_status &= UV_ACT_STATUS_MASK; | |
543 | return descriptor_status; | |
b8f7fb13 CW |
544 | } |
545 | ||
546 | /* | |
547 | * Wait for completion of a broadcast software ack message | |
548 | * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP | |
b194b120 | 549 | */ |
2a919596 | 550 | static int uv1_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
551 | unsigned long mmr_offset, int right_shift, |
552 | struct bau_control *bcp, long try) | |
b194b120 | 553 | { |
b194b120 | 554 | unsigned long descriptor_status; |
f073cc8f | 555 | cycles_t ttm; |
712157aa | 556 | struct ptc_stats *stat = bcp->statp; |
b194b120 | 557 | |
f073cc8f | 558 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
b8f7fb13 | 559 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 560 | while ((descriptor_status != DS_IDLE)) { |
b194b120 | 561 | /* |
2a919596 JS |
562 | * Our software ack messages may be blocked because |
563 | * there are no swack resources available. As long | |
564 | * as none of them has timed out hardware will NACK | |
565 | * our message and its state will stay IDLE. | |
b194b120 | 566 | */ |
f073cc8f | 567 | if (descriptor_status == DS_SOURCE_TIMEOUT) { |
b8f7fb13 CW |
568 | stat->s_stimeout++; |
569 | return FLUSH_GIVEUP; | |
f073cc8f | 570 | } else if (descriptor_status == DS_DESTINATION_TIMEOUT) { |
2a919596 | 571 | stat->s_dtimeout++; |
f073cc8f | 572 | ttm = get_cycles(); |
2a919596 JS |
573 | |
574 | /* | |
575 | * Our retries may be blocked by all destination | |
576 | * swack resources being consumed, and a timeout | |
577 | * pending. In that case hardware returns the | |
578 | * ERROR that looks like a destination timeout. | |
579 | */ | |
f073cc8f | 580 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
2a919596 JS |
581 | bcp->conseccompletes = 0; |
582 | return FLUSH_RETRY_PLUGGED; | |
583 | } | |
584 | ||
585 | bcp->conseccompletes = 0; | |
586 | return FLUSH_RETRY_TIMEOUT; | |
587 | } else { | |
588 | /* | |
589 | * descriptor_status is still BUSY | |
590 | */ | |
591 | cpu_relax(); | |
592 | } | |
f073cc8f | 593 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
2a919596 JS |
594 | } |
595 | bcp->conseccompletes++; | |
596 | return FLUSH_COMPLETE; | |
597 | } | |
598 | ||
f073cc8f | 599 | /* |
8b6e511e CW |
600 | * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register. |
601 | * But not currently used. | |
f073cc8f | 602 | */ |
a26fd719 | 603 | static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc) |
2a919596 | 604 | { |
f148b41e | 605 | return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1; |
f073cc8f CW |
606 | } |
607 | ||
c5d35d39 CW |
608 | /* |
609 | * Return whether the status of the descriptor that is normally used for this | |
610 | * cpu (the one indexed by its hub-relative cpu number) is busy. | |
611 | * The status of the original 32 descriptors is always reflected in the 64 | |
612 | * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0. | |
613 | * The bit provided by the activation_status_2 register is irrelevant to | |
614 | * the status if it is only being tested for busy or not busy. | |
615 | */ | |
616 | int normal_busy(struct bau_control *bcp) | |
617 | { | |
618 | int cpu = bcp->uvhub_cpu; | |
619 | int mmr_offset; | |
620 | int right_shift; | |
621 | ||
622 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
623 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
624 | return (((((read_lmmr(mmr_offset) >> right_shift) & | |
625 | UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY); | |
626 | } | |
627 | ||
628 | /* | |
629 | * Entered when a bau descriptor has gone into a permanent busy wait because | |
630 | * of a hardware bug. | |
631 | * Workaround the bug. | |
632 | */ | |
633 | int handle_uv2_busy(struct bau_control *bcp) | |
634 | { | |
c5d35d39 | 635 | struct ptc_stats *stat = bcp->statp; |
c5d35d39 CW |
636 | |
637 | stat->s_uv2_wars++; | |
8b6e511e CW |
638 | bcp->busy = 1; |
639 | return FLUSH_GIVEUP; | |
c5d35d39 CW |
640 | } |
641 | ||
a26fd719 | 642 | static int uv2_3_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
643 | unsigned long mmr_offset, int right_shift, |
644 | struct bau_control *bcp, long try) | |
645 | { | |
646 | unsigned long descriptor_stat; | |
647 | cycles_t ttm; | |
8b6e511e | 648 | int desc = bcp->uvhub_cpu; |
c5d35d39 | 649 | long busy_reps = 0; |
2a919596 JS |
650 | struct ptc_stats *stat = bcp->statp; |
651 | ||
a26fd719 | 652 | descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc); |
f073cc8f | 653 | |
2a919596 | 654 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 655 | while (descriptor_stat != UV2H_DESC_IDLE) { |
8b6e511e CW |
656 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) { |
657 | /* | |
658 | * A h/w bug on the destination side may | |
659 | * have prevented the message being marked | |
660 | * pending, thus it doesn't get replied to | |
661 | * and gets continually nacked until it times | |
662 | * out with a SOURCE_TIMEOUT. | |
663 | */ | |
2a919596 JS |
664 | stat->s_stimeout++; |
665 | return FLUSH_GIVEUP; | |
f073cc8f | 666 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
8b6e511e CW |
667 | ttm = get_cycles(); |
668 | ||
669 | /* | |
670 | * Our retries may be blocked by all destination | |
671 | * swack resources being consumed, and a timeout | |
672 | * pending. In that case hardware returns the | |
673 | * ERROR that looks like a destination timeout. | |
674 | * Without using the extended status we have to | |
675 | * deduce from the short time that this was a | |
676 | * strong nack. | |
677 | */ | |
678 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { | |
679 | bcp->conseccompletes = 0; | |
680 | stat->s_plugged++; | |
681 | /* FLUSH_RETRY_PLUGGED causes hang on boot */ | |
682 | return FLUSH_GIVEUP; | |
683 | } | |
b8f7fb13 | 684 | stat->s_dtimeout++; |
b8f7fb13 | 685 | bcp->conseccompletes = 0; |
8b6e511e CW |
686 | /* FLUSH_RETRY_TIMEOUT causes hang on boot */ |
687 | return FLUSH_GIVEUP; | |
b8f7fb13 | 688 | } else { |
c5d35d39 CW |
689 | busy_reps++; |
690 | if (busy_reps > 1000000) { | |
691 | /* not to hammer on the clock */ | |
692 | busy_reps = 0; | |
693 | ttm = get_cycles(); | |
a26fd719 | 694 | if ((ttm - bcp->send_message) > bcp->timeout_interval) |
c5d35d39 | 695 | return handle_uv2_busy(bcp); |
c5d35d39 | 696 | } |
b8f7fb13 | 697 | /* |
f073cc8f | 698 | * descriptor_stat is still BUSY |
b8f7fb13 CW |
699 | */ |
700 | cpu_relax(); | |
b194b120 | 701 | } |
a26fd719 | 702 | descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc); |
b194b120 | 703 | } |
b8f7fb13 | 704 | bcp->conseccompletes++; |
b194b120 CW |
705 | return FLUSH_COMPLETE; |
706 | } | |
707 | ||
f073cc8f CW |
708 | /* |
709 | * There are 2 status registers; each and array[32] of 2 bits. Set up for | |
710 | * which register to read and position in that register based on cpu in | |
711 | * current hub. | |
712 | */ | |
a26fd719 | 713 | static int wait_completion(struct bau_desc *bau_desc, struct bau_control *bcp, long try) |
2a919596 | 714 | { |
f073cc8f CW |
715 | int right_shift; |
716 | unsigned long mmr_offset; | |
8b6e511e | 717 | int desc = bcp->uvhub_cpu; |
f073cc8f | 718 | |
c5d35d39 | 719 | if (desc < UV_CPUS_PER_AS) { |
f073cc8f | 720 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; |
c5d35d39 | 721 | right_shift = desc * UV_ACT_STATUS_SIZE; |
f073cc8f CW |
722 | } else { |
723 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
c5d35d39 | 724 | right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); |
f073cc8f CW |
725 | } |
726 | ||
da87c937 | 727 | if (bcp->uvhub_version == 1) |
a26fd719 | 728 | return uv1_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try); |
2a919596 | 729 | else |
a26fd719 | 730 | return uv2_3_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try); |
2a919596 JS |
731 | } |
732 | ||
b8f7fb13 | 733 | /* |
f073cc8f | 734 | * Our retries are blocked by all destination sw ack resources being |
f6d8a566 CW |
735 | * in use, and a timeout is pending. In that case hardware immediately |
736 | * returns the ERROR that looks like a destination timeout. | |
737 | */ | |
f073cc8f CW |
738 | static void destination_plugged(struct bau_desc *bau_desc, |
739 | struct bau_control *bcp, | |
f6d8a566 CW |
740 | struct bau_control *hmaster, struct ptc_stats *stat) |
741 | { | |
742 | udelay(bcp->plugged_delay); | |
743 | bcp->plugged_tries++; | |
f073cc8f | 744 | |
f6d8a566 CW |
745 | if (bcp->plugged_tries >= bcp->plugsb4reset) { |
746 | bcp->plugged_tries = 0; | |
f073cc8f | 747 | |
f6d8a566 | 748 | quiesce_local_uvhub(hmaster); |
f073cc8f | 749 | |
f6d8a566 | 750 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 751 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 752 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 753 | |
f6d8a566 | 754 | end_uvhub_quiesce(hmaster); |
f073cc8f | 755 | |
f6d8a566 CW |
756 | bcp->ipi_attempts++; |
757 | stat->s_resets_plug++; | |
758 | } | |
759 | } | |
760 | ||
f073cc8f CW |
761 | static void destination_timeout(struct bau_desc *bau_desc, |
762 | struct bau_control *bcp, struct bau_control *hmaster, | |
763 | struct ptc_stats *stat) | |
f6d8a566 | 764 | { |
f073cc8f | 765 | hmaster->max_concurr = 1; |
f6d8a566 CW |
766 | bcp->timeout_tries++; |
767 | if (bcp->timeout_tries >= bcp->timeoutsb4reset) { | |
768 | bcp->timeout_tries = 0; | |
f073cc8f | 769 | |
f6d8a566 | 770 | quiesce_local_uvhub(hmaster); |
f073cc8f | 771 | |
f6d8a566 | 772 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 773 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 774 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 775 | |
f6d8a566 | 776 | end_uvhub_quiesce(hmaster); |
f073cc8f | 777 | |
f6d8a566 CW |
778 | bcp->ipi_attempts++; |
779 | stat->s_resets_timeout++; | |
780 | } | |
781 | } | |
782 | ||
50fb55ac | 783 | /* |
8b6e511e CW |
784 | * Stop all cpus on a uvhub from using the BAU for a period of time. |
785 | * This is reversed by check_enable. | |
50fb55ac | 786 | */ |
8b6e511e | 787 | static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat) |
50fb55ac | 788 | { |
8b6e511e CW |
789 | int tcpu; |
790 | struct bau_control *tbcp; | |
791 | struct bau_control *hmaster; | |
792 | cycles_t tm1; | |
793 | ||
794 | hmaster = bcp->uvhub_master; | |
795 | spin_lock(&hmaster->disable_lock); | |
796 | if (!bcp->baudisabled) { | |
50fb55ac | 797 | stat->s_bau_disabled++; |
8b6e511e | 798 | tm1 = get_cycles(); |
50fb55ac CW |
799 | for_each_present_cpu(tcpu) { |
800 | tbcp = &per_cpu(bau_control, tcpu); | |
8b6e511e CW |
801 | if (tbcp->uvhub_master == hmaster) { |
802 | tbcp->baudisabled = 1; | |
803 | tbcp->set_bau_on_time = | |
804 | tm1 + bcp->disabled_period; | |
805 | } | |
50fb55ac CW |
806 | } |
807 | } | |
8b6e511e | 808 | spin_unlock(&hmaster->disable_lock); |
50fb55ac CW |
809 | } |
810 | ||
f073cc8f CW |
811 | static void count_max_concurr(int stat, struct bau_control *bcp, |
812 | struct bau_control *hmaster) | |
813 | { | |
814 | bcp->plugged_tries = 0; | |
815 | bcp->timeout_tries = 0; | |
816 | if (stat != FLUSH_COMPLETE) | |
817 | return; | |
818 | if (bcp->conseccompletes <= bcp->complete_threshold) | |
819 | return; | |
820 | if (hmaster->max_concurr >= hmaster->max_concurr_const) | |
821 | return; | |
822 | hmaster->max_concurr++; | |
823 | } | |
824 | ||
825 | static void record_send_stats(cycles_t time1, cycles_t time2, | |
826 | struct bau_control *bcp, struct ptc_stats *stat, | |
827 | int completion_status, int try) | |
828 | { | |
829 | cycles_t elapsed; | |
830 | ||
831 | if (time2 > time1) { | |
832 | elapsed = time2 - time1; | |
833 | stat->s_time += elapsed; | |
834 | ||
835 | if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { | |
836 | bcp->period_requests++; | |
837 | bcp->period_time += elapsed; | |
838 | if ((elapsed > congested_cycles) && | |
8b6e511e CW |
839 | (bcp->period_requests > bcp->cong_reps) && |
840 | ((bcp->period_time / bcp->period_requests) > | |
841 | congested_cycles)) { | |
842 | stat->s_congested++; | |
843 | disable_for_period(bcp, stat); | |
844 | } | |
f073cc8f CW |
845 | } |
846 | } else | |
847 | stat->s_requestor--; | |
848 | ||
849 | if (completion_status == FLUSH_COMPLETE && try > 1) | |
850 | stat->s_retriesok++; | |
8b6e511e | 851 | else if (completion_status == FLUSH_GIVEUP) { |
f073cc8f | 852 | stat->s_giveup++; |
8b6e511e CW |
853 | if (get_cycles() > bcp->period_end) |
854 | bcp->period_giveups = 0; | |
855 | bcp->period_giveups++; | |
856 | if (bcp->period_giveups == 1) | |
857 | bcp->period_end = get_cycles() + bcp->disabled_period; | |
858 | if (bcp->period_giveups > bcp->giveup_limit) { | |
859 | disable_for_period(bcp, stat); | |
860 | stat->s_giveuplimit++; | |
861 | } | |
862 | } | |
f073cc8f CW |
863 | } |
864 | ||
865 | /* | |
866 | * Because of a uv1 hardware bug only a limited number of concurrent | |
867 | * requests can be made. | |
868 | */ | |
869 | static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) | |
870 | { | |
871 | spinlock_t *lock = &hmaster->uvhub_lock; | |
872 | atomic_t *v; | |
873 | ||
874 | v = &hmaster->active_descriptor_count; | |
875 | if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) { | |
876 | stat->s_throttles++; | |
877 | do { | |
878 | cpu_relax(); | |
879 | } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)); | |
880 | } | |
881 | } | |
882 | ||
883 | /* | |
884 | * Handle the completion status of a message send. | |
885 | */ | |
886 | static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, | |
887 | struct bau_control *bcp, struct bau_control *hmaster, | |
888 | struct ptc_stats *stat) | |
889 | { | |
890 | if (completion_status == FLUSH_RETRY_PLUGGED) | |
891 | destination_plugged(bau_desc, bcp, hmaster, stat); | |
892 | else if (completion_status == FLUSH_RETRY_TIMEOUT) | |
893 | destination_timeout(bau_desc, bcp, hmaster, stat); | |
894 | } | |
895 | ||
896 | /* | |
b8f7fb13 | 897 | * Send a broadcast and wait for it to complete. |
b194b120 | 898 | * |
f6d8a566 | 899 | * The flush_mask contains the cpus the broadcast is to be sent to including |
b8f7fb13 | 900 | * cpus that are on the local uvhub. |
b194b120 | 901 | * |
450a007e CW |
902 | * Returns 0 if all flushing represented in the mask was done. |
903 | * Returns 1 if it gives up entirely and the original cpu mask is to be | |
904 | * returned to the kernel. | |
b194b120 | 905 | */ |
8b6e511e CW |
906 | int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp, |
907 | struct bau_desc *bau_desc) | |
b194b120 | 908 | { |
b8f7fb13 | 909 | int seq_number = 0; |
f073cc8f | 910 | int completion_stat = 0; |
da87c937 | 911 | int uv1 = 0; |
b8f7fb13 | 912 | long try = 0; |
b4c286e6 | 913 | unsigned long index; |
b194b120 CW |
914 | cycles_t time1; |
915 | cycles_t time2; | |
712157aa | 916 | struct ptc_stats *stat = bcp->statp; |
b8f7fb13 | 917 | struct bau_control *hmaster = bcp->uvhub_master; |
da87c937 | 918 | struct uv1_bau_msg_header *uv1_hdr = NULL; |
a26fd719 | 919 | struct uv2_3_bau_msg_header *uv2_3_hdr = NULL; |
b8f7fb13 | 920 | |
8b6e511e CW |
921 | if (bcp->uvhub_version == 1) { |
922 | uv1 = 1; | |
f073cc8f | 923 | uv1_throttle(hmaster, stat); |
8b6e511e | 924 | } |
f073cc8f | 925 | |
b8f7fb13 CW |
926 | while (hmaster->uvhub_quiesce) |
927 | cpu_relax(); | |
b194b120 | 928 | |
b194b120 | 929 | time1 = get_cycles(); |
8b6e511e CW |
930 | if (uv1) |
931 | uv1_hdr = &bau_desc->header.uv1_hdr; | |
932 | else | |
a26fd719 CW |
933 | /* uv2 and uv3 */ |
934 | uv2_3_hdr = &bau_desc->header.uv2_3_hdr; | |
8b6e511e | 935 | |
b194b120 | 936 | do { |
8b6e511e | 937 | if (try == 0) { |
da87c937 CW |
938 | if (uv1) |
939 | uv1_hdr->msg_type = MSG_REGULAR; | |
940 | else | |
a26fd719 | 941 | uv2_3_hdr->msg_type = MSG_REGULAR; |
b8f7fb13 CW |
942 | seq_number = bcp->message_number++; |
943 | } else { | |
da87c937 CW |
944 | if (uv1) |
945 | uv1_hdr->msg_type = MSG_RETRY; | |
946 | else | |
a26fd719 | 947 | uv2_3_hdr->msg_type = MSG_RETRY; |
b8f7fb13 CW |
948 | stat->s_retry_messages++; |
949 | } | |
f073cc8f | 950 | |
da87c937 CW |
951 | if (uv1) |
952 | uv1_hdr->sequence = seq_number; | |
953 | else | |
a26fd719 | 954 | uv2_3_hdr->sequence = seq_number; |
8b6e511e | 955 | index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; |
b8f7fb13 | 956 | bcp->send_message = get_cycles(); |
f073cc8f CW |
957 | |
958 | write_mmr_activation(index); | |
959 | ||
b8f7fb13 | 960 | try++; |
f073cc8f CW |
961 | completion_stat = wait_completion(bau_desc, bcp, try); |
962 | ||
963 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); | |
b8f7fb13 | 964 | |
e8e5e8a8 | 965 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { |
b8f7fb13 | 966 | bcp->ipi_attempts = 0; |
8b6e511e | 967 | stat->s_overipilimit++; |
f073cc8f | 968 | completion_stat = FLUSH_GIVEUP; |
b8f7fb13 CW |
969 | break; |
970 | } | |
971 | cpu_relax(); | |
f073cc8f CW |
972 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
973 | (completion_stat == FLUSH_RETRY_TIMEOUT)); | |
974 | ||
b194b120 | 975 | time2 = get_cycles(); |
f073cc8f CW |
976 | |
977 | count_max_concurr(completion_stat, bcp, hmaster); | |
978 | ||
b8f7fb13 CW |
979 | while (hmaster->uvhub_quiesce) |
980 | cpu_relax(); | |
f073cc8f | 981 | |
b8f7fb13 | 982 | atomic_dec(&hmaster->active_descriptor_count); |
f073cc8f CW |
983 | |
984 | record_send_stats(time1, time2, bcp, stat, completion_stat, try); | |
985 | ||
986 | if (completion_stat == FLUSH_GIVEUP) | |
c5d35d39 | 987 | /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */ |
f073cc8f CW |
988 | return 1; |
989 | return 0; | |
990 | } | |
991 | ||
992 | /* | |
8b6e511e CW |
993 | * The BAU is disabled for this uvhub. When the disabled time period has |
994 | * expired re-enable it. | |
995 | * Return 0 if it is re-enabled for all cpus on this uvhub. | |
f073cc8f CW |
996 | */ |
997 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) | |
998 | { | |
999 | int tcpu; | |
1000 | struct bau_control *tbcp; | |
8b6e511e | 1001 | struct bau_control *hmaster; |
f073cc8f | 1002 | |
8b6e511e CW |
1003 | hmaster = bcp->uvhub_master; |
1004 | spin_lock(&hmaster->disable_lock); | |
1005 | if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) { | |
1006 | stat->s_bau_reenabled++; | |
1007 | for_each_present_cpu(tcpu) { | |
1008 | tbcp = &per_cpu(bau_control, tcpu); | |
1009 | if (tbcp->uvhub_master == hmaster) { | |
f073cc8f CW |
1010 | tbcp->baudisabled = 0; |
1011 | tbcp->period_requests = 0; | |
1012 | tbcp->period_time = 0; | |
8b6e511e | 1013 | tbcp->period_giveups = 0; |
50fb55ac CW |
1014 | } |
1015 | } | |
8b6e511e CW |
1016 | spin_unlock(&hmaster->disable_lock); |
1017 | return 0; | |
f073cc8f | 1018 | } |
8b6e511e | 1019 | spin_unlock(&hmaster->disable_lock); |
f073cc8f CW |
1020 | return -1; |
1021 | } | |
1022 | ||
1023 | static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs, | |
1024 | int remotes, struct bau_desc *bau_desc) | |
1025 | { | |
1026 | stat->s_requestor++; | |
1027 | stat->s_ntargcpu += remotes + locals; | |
1028 | stat->s_ntargremotes += remotes; | |
1029 | stat->s_ntarglocals += locals; | |
1030 | ||
1031 | /* uvhub statistics */ | |
1032 | hubs = bau_uvhub_weight(&bau_desc->distribution); | |
1033 | if (locals) { | |
1034 | stat->s_ntarglocaluvhub++; | |
1035 | stat->s_ntargremoteuvhub += (hubs - 1); | |
e8e5e8a8 | 1036 | } else |
f073cc8f CW |
1037 | stat->s_ntargremoteuvhub += hubs; |
1038 | ||
1039 | stat->s_ntarguvhub += hubs; | |
1040 | ||
1041 | if (hubs >= 16) | |
1042 | stat->s_ntarguvhub16++; | |
1043 | else if (hubs >= 8) | |
1044 | stat->s_ntarguvhub8++; | |
1045 | else if (hubs >= 4) | |
1046 | stat->s_ntarguvhub4++; | |
1047 | else if (hubs >= 2) | |
1048 | stat->s_ntarguvhub2++; | |
1049 | else | |
1050 | stat->s_ntarguvhub1++; | |
1051 | } | |
1052 | ||
1053 | /* | |
1054 | * Translate a cpu mask to the uvhub distribution mask in the BAU | |
1055 | * activation descriptor. | |
1056 | */ | |
1057 | static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, | |
1058 | struct bau_desc *bau_desc, int *localsp, int *remotesp) | |
1059 | { | |
1060 | int cpu; | |
1061 | int pnode; | |
1062 | int cnt = 0; | |
1063 | struct hub_and_pnode *hpp; | |
1064 | ||
1065 | for_each_cpu(cpu, flush_mask) { | |
1066 | /* | |
1067 | * The distribution vector is a bit map of pnodes, relative | |
1068 | * to the partition base pnode (and the partition base nasid | |
1069 | * in the header). | |
1070 | * Translate cpu to pnode and hub using a local memory array. | |
1071 | */ | |
1072 | hpp = &bcp->socket_master->thp[cpu]; | |
1073 | pnode = hpp->pnode - bcp->partition_base_pnode; | |
1074 | bau_uvhub_set(pnode, &bau_desc->distribution); | |
1075 | cnt++; | |
1076 | if (hpp->uvhub == bcp->uvhub) | |
1077 | (*localsp)++; | |
1078 | else | |
1079 | (*remotesp)++; | |
b194b120 | 1080 | } |
f073cc8f CW |
1081 | if (!cnt) |
1082 | return 1; | |
450a007e | 1083 | return 0; |
b194b120 CW |
1084 | } |
1085 | ||
f073cc8f CW |
1086 | /* |
1087 | * globally purge translation cache of a virtual address or all TLB's | |
bdbcdd48 | 1088 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b | 1089 | * @mm: mm_struct containing virtual address range |
57c4f430 AS |
1090 | * @start: start virtual address to be removed from TLB |
1091 | * @end: end virtual address to be remove from TLB | |
bdbcdd48 | 1092 | * @cpu: the current cpu |
1812924b CW |
1093 | * |
1094 | * This is the entry point for initiating any UV global TLB shootdown. | |
1095 | * | |
1096 | * Purges the translation caches of all specified processors of the given | |
1097 | * virtual address, or purges all TLB's on specified processors. | |
1098 | * | |
bdbcdd48 TH |
1099 | * The caller has derived the cpumask from the mm_struct. This function |
1100 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 1101 | * |
b8f7fb13 CW |
1102 | * The cpumask is converted into a uvhubmask of the uvhubs containing |
1103 | * those cpus. | |
b194b120 | 1104 | * |
bdbcdd48 TH |
1105 | * Note that this function should be called with preemption disabled. |
1106 | * | |
1107 | * Returns NULL if all remote flushing was done. | |
1108 | * Returns pointer to cpumask if some remote flushing remains to be | |
1109 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 1110 | */ |
bdbcdd48 | 1111 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
a26fd719 CW |
1112 | struct mm_struct *mm, |
1113 | unsigned long start, | |
1114 | unsigned long end, | |
1115 | unsigned int cpu) | |
1812924b | 1116 | { |
b194b120 | 1117 | int locals = 0; |
450a007e CW |
1118 | int remotes = 0; |
1119 | int hubs = 0; | |
dc163a41 | 1120 | struct bau_desc *bau_desc; |
b8f7fb13 CW |
1121 | struct cpumask *flush_mask; |
1122 | struct ptc_stats *stat; | |
1123 | struct bau_control *bcp; | |
8b6e511e CW |
1124 | unsigned long descriptor_status; |
1125 | unsigned long status; | |
bdbcdd48 | 1126 | |
b8f7fb13 | 1127 | bcp = &per_cpu(bau_control, cpu); |
26ef8577 CW |
1128 | |
1129 | if (bcp->nobau) | |
1130 | return cpumask; | |
50fb55ac | 1131 | |
3eae49ca | 1132 | stat = bcp->statp; |
1133 | stat->s_enters++; | |
1134 | ||
8b6e511e CW |
1135 | if (bcp->busy) { |
1136 | descriptor_status = | |
1137 | read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0); | |
1138 | status = ((descriptor_status >> (bcp->uvhub_cpu * | |
1139 | UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1; | |
1140 | if (status == UV2H_DESC_BUSY) | |
1141 | return cpumask; | |
1142 | bcp->busy = 0; | |
1143 | } | |
1144 | ||
50fb55ac CW |
1145 | /* bau was disabled due to slow response */ |
1146 | if (bcp->baudisabled) { | |
8b6e511e CW |
1147 | if (check_enable(bcp, stat)) { |
1148 | stat->s_ipifordisabled++; | |
f073cc8f | 1149 | return cpumask; |
8b6e511e | 1150 | } |
50fb55ac | 1151 | } |
e8e5e8a8 | 1152 | |
b8f7fb13 CW |
1153 | /* |
1154 | * Each sending cpu has a per-cpu mask which it fills from the caller's | |
450a007e CW |
1155 | * cpu mask. All cpus are converted to uvhubs and copied to the |
1156 | * activation descriptor. | |
b8f7fb13 CW |
1157 | */ |
1158 | flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); | |
450a007e | 1159 | /* don't actually do a shootdown of the local cpu */ |
b8f7fb13 | 1160 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); |
f073cc8f | 1161 | |
020b37ac | 1162 | if (cpumask_test_cpu(cpu, cpumask)) |
450a007e | 1163 | stat->s_ntargself++; |
1812924b | 1164 | |
b8f7fb13 | 1165 | bau_desc = bcp->descriptor_base; |
8b6e511e | 1166 | bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu); |
b8f7fb13 | 1167 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
f073cc8f | 1168 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
450a007e | 1169 | return NULL; |
450a007e | 1170 | |
f073cc8f | 1171 | record_send_statistics(stat, locals, hubs, remotes, bau_desc); |
1812924b | 1172 | |
57c4f430 AS |
1173 | if (!end || (end - start) <= PAGE_SIZE) |
1174 | bau_desc->payload.address = start; | |
1175 | else | |
1176 | bau_desc->payload.address = TLB_FLUSH_ALL; | |
bdbcdd48 | 1177 | bau_desc->payload.sending_cpu = cpu; |
b8f7fb13 | 1178 | /* |
450a007e CW |
1179 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
1180 | * or 1 if it gave up and the original cpumask should be returned. | |
b8f7fb13 | 1181 | */ |
8b6e511e | 1182 | if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc)) |
450a007e CW |
1183 | return NULL; |
1184 | else | |
1185 | return cpumask; | |
1812924b CW |
1186 | } |
1187 | ||
c5d35d39 | 1188 | /* |
8b6e511e CW |
1189 | * Search the message queue for any 'other' unprocessed message with the |
1190 | * same software acknowledge resource bit vector as the 'msg' message. | |
c5d35d39 CW |
1191 | */ |
1192 | struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg, | |
8b6e511e | 1193 | struct bau_control *bcp) |
c5d35d39 CW |
1194 | { |
1195 | struct bau_pq_entry *msg_next = msg + 1; | |
8b6e511e | 1196 | unsigned char swack_vec = msg->swack_vec; |
c5d35d39 CW |
1197 | |
1198 | if (msg_next > bcp->queue_last) | |
1199 | msg_next = bcp->queue_first; | |
8b6e511e CW |
1200 | while (msg_next != msg) { |
1201 | if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) && | |
1202 | (msg_next->swack_vec == swack_vec)) | |
c5d35d39 CW |
1203 | return msg_next; |
1204 | msg_next++; | |
1205 | if (msg_next > bcp->queue_last) | |
1206 | msg_next = bcp->queue_first; | |
1207 | } | |
1208 | return NULL; | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * UV2 needs to work around a bug in which an arriving message has not | |
1213 | * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register. | |
1214 | * Such a message must be ignored. | |
1215 | */ | |
1216 | void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp) | |
1217 | { | |
1218 | unsigned long mmr_image; | |
1219 | unsigned char swack_vec; | |
1220 | struct bau_pq_entry *msg = mdp->msg; | |
1221 | struct bau_pq_entry *other_msg; | |
1222 | ||
21e3f12f | 1223 | mmr_image = ops.read_l_sw_ack(); |
c5d35d39 CW |
1224 | swack_vec = msg->swack_vec; |
1225 | ||
1226 | if ((swack_vec & mmr_image) == 0) { | |
1227 | /* | |
1228 | * This message was assigned a swack resource, but no | |
1229 | * reserved acknowlegment is pending. | |
1230 | * The bug has prevented this message from setting the MMR. | |
c5d35d39 | 1231 | */ |
c5d35d39 | 1232 | /* |
8b6e511e CW |
1233 | * Some message has set the MMR 'pending' bit; it might have |
1234 | * been another message. Look for that message. | |
c5d35d39 | 1235 | */ |
8b6e511e CW |
1236 | other_msg = find_another_by_swack(msg, bcp); |
1237 | if (other_msg) { | |
1238 | /* | |
1239 | * There is another. Process this one but do not | |
1240 | * ack it. | |
1241 | */ | |
1242 | bau_process_message(mdp, bcp, 0); | |
1243 | /* | |
1244 | * Let the natural processing of that other message | |
1245 | * acknowledge it. Don't get the processing of sw_ack's | |
1246 | * out of order. | |
1247 | */ | |
1248 | return; | |
1249 | } | |
c5d35d39 CW |
1250 | } |
1251 | ||
1252 | /* | |
8b6e511e CW |
1253 | * Either the MMR shows this one pending a reply or there is no |
1254 | * other message using this sw_ack, so it is safe to acknowledge it. | |
c5d35d39 CW |
1255 | */ |
1256 | bau_process_message(mdp, bcp, 1); | |
1257 | ||
1258 | return; | |
1259 | } | |
1260 | ||
1812924b CW |
1261 | /* |
1262 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
1263 | * See entry_64.S | |
1264 | * | |
1265 | * We received a broadcast assist message. | |
1266 | * | |
b8f7fb13 | 1267 | * Interrupts are disabled; this interrupt could represent |
1812924b CW |
1268 | * the receipt of several messages. |
1269 | * | |
b8f7fb13 CW |
1270 | * All cores/threads on this hub get this interrupt. |
1271 | * The last one to see it does the software ack. | |
1812924b | 1272 | * (the resource will not be freed until noninterruptable cpus see this |
b8f7fb13 | 1273 | * interrupt; hardware may timeout the s/w ack and reply ERROR) |
1812924b | 1274 | */ |
b194b120 | 1275 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 1276 | { |
1812924b | 1277 | int count = 0; |
b8f7fb13 | 1278 | cycles_t time_start; |
f073cc8f | 1279 | struct bau_pq_entry *msg; |
b8f7fb13 CW |
1280 | struct bau_control *bcp; |
1281 | struct ptc_stats *stat; | |
1282 | struct msg_desc msgdesc; | |
1283 | ||
88ed9dd7 | 1284 | ack_APIC_irq(); |
b8f7fb13 | 1285 | time_start = get_cycles(); |
f073cc8f | 1286 | |
b8f7fb13 | 1287 | bcp = &per_cpu(bau_control, smp_processor_id()); |
712157aa | 1288 | stat = bcp->statp; |
f073cc8f CW |
1289 | |
1290 | msgdesc.queue_first = bcp->queue_first; | |
1291 | msgdesc.queue_last = bcp->queue_last; | |
1292 | ||
b8f7fb13 | 1293 | msg = bcp->bau_msg_head; |
f073cc8f | 1294 | while (msg->swack_vec) { |
1812924b | 1295 | count++; |
f073cc8f CW |
1296 | |
1297 | msgdesc.msg_slot = msg - msgdesc.queue_first; | |
b8f7fb13 | 1298 | msgdesc.msg = msg; |
c5d35d39 CW |
1299 | if (bcp->uvhub_version == 2) |
1300 | process_uv2_message(&msgdesc, bcp); | |
1301 | else | |
a26fd719 | 1302 | /* no error workaround for uv1 or uv3 */ |
c5d35d39 | 1303 | bau_process_message(&msgdesc, bcp, 1); |
f073cc8f | 1304 | |
1812924b | 1305 | msg++; |
f073cc8f CW |
1306 | if (msg > msgdesc.queue_last) |
1307 | msg = msgdesc.queue_first; | |
b8f7fb13 | 1308 | bcp->bau_msg_head = msg; |
1812924b | 1309 | } |
b8f7fb13 | 1310 | stat->d_time += (get_cycles() - time_start); |
1812924b | 1311 | if (!count) |
b8f7fb13 | 1312 | stat->d_nomsg++; |
1812924b | 1313 | else if (count > 1) |
b8f7fb13 | 1314 | stat->d_multmsg++; |
1812924b CW |
1315 | } |
1316 | ||
c4c4688f | 1317 | /* |
f073cc8f | 1318 | * Each target uvhub (i.e. a uvhub that has cpu's) needs to have |
c4c4688f CW |
1319 | * shootdown message timeouts enabled. The timeout does not cause |
1320 | * an interrupt, but causes an error message to be returned to | |
1321 | * the sender. | |
1322 | */ | |
f073cc8f | 1323 | static void __init enable_timeouts(void) |
1812924b | 1324 | { |
b8f7fb13 CW |
1325 | int uvhub; |
1326 | int nuvhubs; | |
1812924b | 1327 | int pnode; |
c4c4688f | 1328 | unsigned long mmr_image; |
1812924b | 1329 | |
b8f7fb13 | 1330 | nuvhubs = uv_num_possible_blades(); |
1812924b | 1331 | |
b8f7fb13 CW |
1332 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
1333 | if (!uv_blade_nr_possible_cpus(uvhub)) | |
1812924b | 1334 | continue; |
c4c4688f | 1335 | |
b8f7fb13 | 1336 | pnode = uv_blade_to_pnode(uvhub); |
f073cc8f | 1337 | mmr_image = read_mmr_misc_control(pnode); |
c4c4688f CW |
1338 | /* |
1339 | * Set the timeout period and then lock it in, in three | |
1340 | * steps; captures and locks in the period. | |
1341 | * | |
1342 | * To program the period, the SOFT_ACK_MODE must be off. | |
1343 | */ | |
f073cc8f CW |
1344 | mmr_image &= ~(1L << SOFTACK_MSHIFT); |
1345 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f CW |
1346 | /* |
1347 | * Set the 4-bit period. | |
1348 | */ | |
f073cc8f CW |
1349 | mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT); |
1350 | mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT); | |
1351 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f | 1352 | /* |
2a919596 | 1353 | * UV1: |
c4c4688f CW |
1354 | * Subsequent reversals of the timebase bit (3) cause an |
1355 | * immediate timeout of one or all INTD resources as | |
1356 | * indicated in bits 2:0 (7 causes all of them to timeout). | |
1357 | */ | |
f073cc8f | 1358 | mmr_image |= (1L << SOFTACK_MSHIFT); |
2a919596 | 1359 | if (is_uv2_hub()) { |
a26fd719 | 1360 | /* do not touch the legacy mode bit */ |
8b6e511e CW |
1361 | /* hw bug workaround; do not use extended status */ |
1362 | mmr_image &= ~(1L << UV2_EXT_SHFT); | |
a26fd719 CW |
1363 | } else if (is_uv3_hub()) { |
1364 | mmr_image &= ~(1L << PREFETCH_HINT_SHFT); | |
1365 | mmr_image |= (1L << SB_STATUS_SHFT); | |
2a919596 | 1366 | } |
f073cc8f | 1367 | write_mmr_misc_control(pnode, mmr_image); |
1812924b | 1368 | } |
1812924b CW |
1369 | } |
1370 | ||
f073cc8f | 1371 | static void *ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
1372 | { |
1373 | if (*offset < num_possible_cpus()) | |
1374 | return offset; | |
1375 | return NULL; | |
1376 | } | |
1377 | ||
f073cc8f | 1378 | static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
1379 | { |
1380 | (*offset)++; | |
1381 | if (*offset < num_possible_cpus()) | |
1382 | return offset; | |
1383 | return NULL; | |
1384 | } | |
1385 | ||
f073cc8f | 1386 | static void ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
1387 | { |
1388 | } | |
1389 | ||
1390 | /* | |
f073cc8f | 1391 | * Display the statistics thru /proc/sgi_uv/ptc_statistics |
b8f7fb13 | 1392 | * 'data' points to the cpu number |
f073cc8f | 1393 | * Note: see the descriptions in stat_description[]. |
1812924b | 1394 | */ |
f073cc8f | 1395 | static int ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
1396 | { |
1397 | struct ptc_stats *stat; | |
26ef8577 | 1398 | struct bau_control *bcp; |
1812924b CW |
1399 | int cpu; |
1400 | ||
1401 | cpu = *(loff_t *)data; | |
1812924b | 1402 | if (!cpu) { |
3736708f RV |
1403 | seq_puts(file, |
1404 | "# cpu bauoff sent stime self locals remotes ncpus localhub "); | |
1405 | seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 "); | |
1406 | seq_puts(file, | |
1407 | "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries "); | |
1408 | seq_puts(file, | |
1409 | "rok resetp resett giveup sto bz throt disable "); | |
1410 | seq_puts(file, | |
1411 | "enable wars warshw warwaits enters ipidis plugged "); | |
1412 | seq_puts(file, | |
1413 | "ipiover glim cong swack recv rtime all one mult "); | |
1414 | seq_puts(file, "none retry canc nocan reset rcan\n"); | |
1812924b CW |
1415 | } |
1416 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
26ef8577 | 1417 | bcp = &per_cpu(bau_control, cpu); |
fa2a79ce JC |
1418 | if (bcp->nobau) { |
1419 | seq_printf(file, "cpu %d bau disabled\n", cpu); | |
1420 | return 0; | |
1421 | } | |
26ef8577 | 1422 | stat = bcp->statp; |
b8f7fb13 CW |
1423 | /* source side statistics */ |
1424 | seq_printf(file, | |
8b6e511e | 1425 | "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", |
26ef8577 CW |
1426 | cpu, bcp->nobau, stat->s_requestor, |
1427 | cycles_2_us(stat->s_time), | |
450a007e CW |
1428 | stat->s_ntargself, stat->s_ntarglocals, |
1429 | stat->s_ntargremotes, stat->s_ntargcpu, | |
1430 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, | |
1431 | stat->s_ntarguvhub, stat->s_ntarguvhub16); | |
b54bd9be | 1432 | seq_printf(file, "%ld %ld %ld %ld %ld %ld ", |
b8f7fb13 CW |
1433 | stat->s_ntarguvhub8, stat->s_ntarguvhub4, |
1434 | stat->s_ntarguvhub2, stat->s_ntarguvhub1, | |
b54bd9be | 1435 | stat->s_dtimeout, stat->s_strongnacks); |
8b6e511e | 1436 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ", |
b8f7fb13 CW |
1437 | stat->s_retry_messages, stat->s_retriesok, |
1438 | stat->s_resets_plug, stat->s_resets_timeout, | |
1439 | stat->s_giveup, stat->s_stimeout, | |
8b6e511e CW |
1440 | stat->s_busy, stat->s_throttles); |
1441 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | |
1442 | stat->s_bau_disabled, stat->s_bau_reenabled, | |
1443 | stat->s_uv2_wars, stat->s_uv2_wars_hw, | |
1444 | stat->s_uv2_war_waits, stat->s_enters, | |
1445 | stat->s_ipifordisabled, stat->s_plugged, | |
1446 | stat->s_overipilimit, stat->s_giveuplimit, | |
1447 | stat->s_congested); | |
e8e5e8a8 | 1448 | |
b8f7fb13 CW |
1449 | /* destination side statistics */ |
1450 | seq_printf(file, | |
8b6e511e | 1451 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", |
21e3f12f | 1452 | ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)), |
b8f7fb13 CW |
1453 | stat->d_requestee, cycles_2_us(stat->d_time), |
1454 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, | |
1455 | stat->d_nomsg, stat->d_retries, stat->d_canceled, | |
1456 | stat->d_nocanceled, stat->d_resets, | |
1457 | stat->d_rcanceled); | |
1812924b | 1458 | } |
1812924b CW |
1459 | return 0; |
1460 | } | |
1461 | ||
e8e5e8a8 CW |
1462 | /* |
1463 | * Display the tunables thru debugfs | |
1464 | */ | |
1465 | static ssize_t tunables_read(struct file *file, char __user *userbuf, | |
f073cc8f | 1466 | size_t count, loff_t *ppos) |
e8e5e8a8 | 1467 | { |
b365a85c | 1468 | char *buf; |
e8e5e8a8 CW |
1469 | int ret; |
1470 | ||
8b6e511e CW |
1471 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n", |
1472 | "max_concur plugged_delay plugsb4reset timeoutsb4reset", | |
1473 | "ipi_reset_limit complete_threshold congested_response_us", | |
1474 | "congested_reps disabled_period giveup_limit", | |
f073cc8f | 1475 | max_concurr, plugged_delay, plugsb4reset, |
e8e5e8a8 | 1476 | timeoutsb4reset, ipi_reset_limit, complete_threshold, |
8b6e511e CW |
1477 | congested_respns_us, congested_reps, disabled_period, |
1478 | giveup_limit); | |
e8e5e8a8 | 1479 | |
b365a85c DC |
1480 | if (!buf) |
1481 | return -ENOMEM; | |
1482 | ||
1483 | ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); | |
1484 | kfree(buf); | |
1485 | return ret; | |
e8e5e8a8 CW |
1486 | } |
1487 | ||
1812924b | 1488 | /* |
f073cc8f CW |
1489 | * handle a write to /proc/sgi_uv/ptc_statistics |
1490 | * -1: reset the statistics | |
1812924b | 1491 | * 0: display meaning of the statistics |
1812924b | 1492 | */ |
f073cc8f CW |
1493 | static ssize_t ptc_proc_write(struct file *file, const char __user *user, |
1494 | size_t count, loff_t *data) | |
1812924b | 1495 | { |
b8f7fb13 | 1496 | int cpu; |
f073cc8f CW |
1497 | int i; |
1498 | int elements; | |
b8f7fb13 | 1499 | long input_arg; |
1812924b | 1500 | char optstr[64]; |
b8f7fb13 | 1501 | struct ptc_stats *stat; |
1812924b | 1502 | |
e7eb8726 | 1503 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 1504 | return -EINVAL; |
1812924b CW |
1505 | if (copy_from_user(optstr, user, count)) |
1506 | return -EFAULT; | |
1507 | optstr[count - 1] = '\0'; | |
f073cc8f | 1508 | |
26ef8577 CW |
1509 | if (!strcmp(optstr, "on")) { |
1510 | set_bau_on(); | |
1511 | return count; | |
1512 | } else if (!strcmp(optstr, "off")) { | |
1513 | set_bau_off(); | |
1514 | return count; | |
1515 | } | |
1516 | ||
164109e3 | 1517 | if (kstrtol(optstr, 10, &input_arg) < 0) { |
efa59ab3 | 1518 | pr_debug("%s is invalid\n", optstr); |
1812924b CW |
1519 | return -EINVAL; |
1520 | } | |
1521 | ||
b8f7fb13 | 1522 | if (input_arg == 0) { |
64441745 | 1523 | elements = ARRAY_SIZE(stat_description); |
efa59ab3 AB |
1524 | pr_debug("# cpu: cpu number\n"); |
1525 | pr_debug("Sender statistics:\n"); | |
f073cc8f | 1526 | for (i = 0; i < elements; i++) |
efa59ab3 | 1527 | pr_debug("%s\n", stat_description[i]); |
b8f7fb13 CW |
1528 | } else if (input_arg == -1) { |
1529 | for_each_present_cpu(cpu) { | |
1530 | stat = &per_cpu(ptcstats, cpu); | |
1531 | memset(stat, 0, sizeof(struct ptc_stats)); | |
1532 | } | |
e8e5e8a8 CW |
1533 | } |
1534 | ||
1535 | return count; | |
1536 | } | |
1537 | ||
1538 | static int local_atoi(const char *name) | |
1539 | { | |
1540 | int val = 0; | |
1541 | ||
1542 | for (;; name++) { | |
1543 | switch (*name) { | |
1544 | case '0' ... '9': | |
1545 | val = 10*val+(*name-'0'); | |
1546 | break; | |
1547 | default: | |
1548 | return val; | |
b8f7fb13 | 1549 | } |
1812924b | 1550 | } |
e8e5e8a8 CW |
1551 | } |
1552 | ||
1553 | /* | |
f073cc8f CW |
1554 | * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables. |
1555 | * Zero values reset them to defaults. | |
e8e5e8a8 | 1556 | */ |
f073cc8f CW |
1557 | static int parse_tunables_write(struct bau_control *bcp, char *instr, |
1558 | int count) | |
e8e5e8a8 | 1559 | { |
e8e5e8a8 CW |
1560 | char *p; |
1561 | char *q; | |
f073cc8f CW |
1562 | int cnt = 0; |
1563 | int val; | |
64441745 | 1564 | int e = ARRAY_SIZE(tunables); |
e8e5e8a8 | 1565 | |
e8e5e8a8 CW |
1566 | p = instr + strspn(instr, WHITESPACE); |
1567 | q = p; | |
1568 | for (; *p; p = q + strspn(q, WHITESPACE)) { | |
1569 | q = p + strcspn(p, WHITESPACE); | |
1570 | cnt++; | |
1571 | if (q == p) | |
1572 | break; | |
1573 | } | |
f073cc8f | 1574 | if (cnt != e) { |
efa59ab3 | 1575 | pr_info("bau tunable error: should be %d values\n", e); |
e8e5e8a8 CW |
1576 | return -EINVAL; |
1577 | } | |
1578 | ||
1579 | p = instr + strspn(instr, WHITESPACE); | |
1580 | q = p; | |
1581 | for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) { | |
1582 | q = p + strcspn(p, WHITESPACE); | |
1583 | val = local_atoi(p); | |
1584 | switch (cnt) { | |
1585 | case 0: | |
1586 | if (val == 0) { | |
f073cc8f CW |
1587 | max_concurr = MAX_BAU_CONCURRENT; |
1588 | max_concurr_const = MAX_BAU_CONCURRENT; | |
e8e5e8a8 CW |
1589 | continue; |
1590 | } | |
e8e5e8a8 | 1591 | if (val < 1 || val > bcp->cpus_in_uvhub) { |
efa59ab3 | 1592 | pr_debug( |
e8e5e8a8 CW |
1593 | "Error: BAU max concurrent %d is invalid\n", |
1594 | val); | |
1595 | return -EINVAL; | |
1596 | } | |
f073cc8f CW |
1597 | max_concurr = val; |
1598 | max_concurr_const = val; | |
e8e5e8a8 | 1599 | continue; |
f073cc8f | 1600 | default: |
e8e5e8a8 | 1601 | if (val == 0) |
f073cc8f | 1602 | *tunables[cnt].tunp = tunables[cnt].deflt; |
e8e5e8a8 | 1603 | else |
f073cc8f | 1604 | *tunables[cnt].tunp = val; |
e8e5e8a8 CW |
1605 | continue; |
1606 | } | |
1607 | if (q == p) | |
1608 | break; | |
1609 | } | |
f073cc8f CW |
1610 | return 0; |
1611 | } | |
1612 | ||
1613 | /* | |
1614 | * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables) | |
1615 | */ | |
1616 | static ssize_t tunables_write(struct file *file, const char __user *user, | |
1617 | size_t count, loff_t *data) | |
1618 | { | |
1619 | int cpu; | |
1620 | int ret; | |
1621 | char instr[100]; | |
1622 | struct bau_control *bcp; | |
1623 | ||
1624 | if (count == 0 || count > sizeof(instr)-1) | |
1625 | return -EINVAL; | |
1626 | if (copy_from_user(instr, user, count)) | |
1627 | return -EFAULT; | |
1628 | ||
1629 | instr[count] = '\0'; | |
1630 | ||
00b30cf0 | 1631 | cpu = get_cpu(); |
1632 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1633 | ret = parse_tunables_write(bcp, instr, count); |
00b30cf0 | 1634 | put_cpu(); |
f073cc8f CW |
1635 | if (ret) |
1636 | return ret; | |
1637 | ||
e8e5e8a8 CW |
1638 | for_each_present_cpu(cpu) { |
1639 | bcp = &per_cpu(bau_control, cpu); | |
67492c86 AB |
1640 | bcp->max_concurr = max_concurr; |
1641 | bcp->max_concurr_const = max_concurr; | |
1642 | bcp->plugged_delay = plugged_delay; | |
1643 | bcp->plugsb4reset = plugsb4reset; | |
1644 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1645 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1646 | bcp->complete_threshold = complete_threshold; | |
1647 | bcp->cong_response_us = congested_respns_us; | |
1648 | bcp->cong_reps = congested_reps; | |
1649 | bcp->disabled_period = sec_2_cycles(disabled_period); | |
1650 | bcp->giveup_limit = giveup_limit; | |
e8e5e8a8 | 1651 | } |
1812924b CW |
1652 | return count; |
1653 | } | |
1654 | ||
1655 | static const struct seq_operations uv_ptc_seq_ops = { | |
f073cc8f CW |
1656 | .start = ptc_seq_start, |
1657 | .next = ptc_seq_next, | |
1658 | .stop = ptc_seq_stop, | |
1659 | .show = ptc_seq_show | |
1812924b CW |
1660 | }; |
1661 | ||
f073cc8f | 1662 | static int ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
1663 | { |
1664 | return seq_open(file, &uv_ptc_seq_ops); | |
1665 | } | |
1666 | ||
e8e5e8a8 CW |
1667 | static int tunables_open(struct inode *inode, struct file *file) |
1668 | { | |
1669 | return 0; | |
1670 | } | |
1671 | ||
1812924b | 1672 | static const struct file_operations proc_uv_ptc_operations = { |
f073cc8f | 1673 | .open = ptc_proc_open, |
b194b120 | 1674 | .read = seq_read, |
f073cc8f | 1675 | .write = ptc_proc_write, |
b194b120 CW |
1676 | .llseek = seq_lseek, |
1677 | .release = seq_release, | |
1812924b CW |
1678 | }; |
1679 | ||
e8e5e8a8 CW |
1680 | static const struct file_operations tunables_fops = { |
1681 | .open = tunables_open, | |
1682 | .read = tunables_read, | |
1683 | .write = tunables_write, | |
6038f373 | 1684 | .llseek = default_llseek, |
e8e5e8a8 CW |
1685 | }; |
1686 | ||
b194b120 | 1687 | static int __init uv_ptc_init(void) |
1812924b | 1688 | { |
b194b120 | 1689 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
1690 | |
1691 | if (!is_uv_system()) | |
1692 | return 0; | |
1693 | ||
10f02d11 AD |
1694 | proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL, |
1695 | &proc_uv_ptc_operations); | |
1812924b | 1696 | if (!proc_uv_ptc) { |
efa59ab3 | 1697 | pr_err("unable to create %s proc entry\n", |
1812924b CW |
1698 | UV_PTC_BASENAME); |
1699 | return -EINVAL; | |
1700 | } | |
e8e5e8a8 CW |
1701 | |
1702 | tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL); | |
1703 | if (!tunables_dir) { | |
efa59ab3 | 1704 | pr_err("unable to create debugfs directory %s\n", |
e8e5e8a8 CW |
1705 | UV_BAU_TUNABLES_DIR); |
1706 | return -EINVAL; | |
1707 | } | |
1708 | tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, | |
f073cc8f | 1709 | tunables_dir, NULL, &tunables_fops); |
e8e5e8a8 | 1710 | if (!tunables_file) { |
efa59ab3 | 1711 | pr_err("unable to create debugfs file %s\n", |
e8e5e8a8 CW |
1712 | UV_BAU_TUNABLES_FILE); |
1713 | return -EINVAL; | |
1714 | } | |
1812924b CW |
1715 | return 0; |
1716 | } | |
1717 | ||
1812924b | 1718 | /* |
77ed23f8 | 1719 | * Initialize the sending side's sending buffers. |
1812924b | 1720 | */ |
f073cc8f | 1721 | static void activation_descriptor_init(int node, int pnode, int base_pnode) |
1812924b CW |
1722 | { |
1723 | int i; | |
b8f7fb13 | 1724 | int cpu; |
da87c937 | 1725 | int uv1 = 0; |
6a469e46 | 1726 | unsigned long gpa; |
1812924b | 1727 | unsigned long m; |
b194b120 | 1728 | unsigned long n; |
f073cc8f | 1729 | size_t dsize; |
b8f7fb13 CW |
1730 | struct bau_desc *bau_desc; |
1731 | struct bau_desc *bd2; | |
da87c937 | 1732 | struct uv1_bau_msg_header *uv1_hdr; |
a26fd719 | 1733 | struct uv2_3_bau_msg_header *uv2_3_hdr; |
b8f7fb13 | 1734 | struct bau_control *bcp; |
b194b120 | 1735 | |
0e2595cd | 1736 | /* |
f073cc8f CW |
1737 | * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC) |
1738 | * per cpu; and one per cpu on the uvhub (ADP_SZ) | |
0e2595cd | 1739 | */ |
f073cc8f CW |
1740 | dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC; |
1741 | bau_desc = kmalloc_node(dsize, GFP_KERNEL, node); | |
b8f7fb13 | 1742 | BUG_ON(!bau_desc); |
b4c286e6 | 1743 | |
6a469e46 JS |
1744 | gpa = uv_gpa(bau_desc); |
1745 | n = uv_gpa_to_gnode(gpa); | |
21e3f12f | 1746 | m = ops.bau_gpa_to_offset(gpa); |
da87c937 CW |
1747 | if (is_uv1_hub()) |
1748 | uv1 = 1; | |
b4c286e6 | 1749 | |
77ed23f8 | 1750 | /* the 14-bit pnode */ |
f073cc8f | 1751 | write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); |
0e2595cd | 1752 | /* |
f073cc8f | 1753 | * Initializing all 8 (ITEMS_PER_DESC) descriptors for each |
0e2595cd | 1754 | * cpu even though we only use the first one; one descriptor can |
b8f7fb13 | 1755 | * describe a broadcast to 256 uv hubs. |
0e2595cd | 1756 | */ |
f073cc8f | 1757 | for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { |
b8f7fb13 | 1758 | memset(bd2, 0, sizeof(struct bau_desc)); |
da87c937 CW |
1759 | if (uv1) { |
1760 | uv1_hdr = &bd2->header.uv1_hdr; | |
67492c86 | 1761 | uv1_hdr->swack_flag = 1; |
da87c937 CW |
1762 | /* |
1763 | * The base_dest_nasid set in the message header | |
1764 | * is the nasid of the first uvhub in the partition. | |
1765 | * The bit map will indicate destination pnode numbers | |
1766 | * relative to that base. They may not be consecutive | |
1767 | * if nasid striding is being used. | |
1768 | */ | |
1769 | uv1_hdr->base_dest_nasid = | |
67492c86 AB |
1770 | UV_PNODE_TO_NASID(base_pnode); |
1771 | uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1772 | uv1_hdr->command = UV_NET_ENDPOINT_INTD; | |
1773 | uv1_hdr->int_both = 1; | |
da87c937 CW |
1774 | /* |
1775 | * all others need to be set to zero: | |
1776 | * fairness chaining multilevel count replied_to | |
1777 | */ | |
1778 | } else { | |
8b6e511e | 1779 | /* |
a26fd719 | 1780 | * BIOS uses legacy mode, but uv2 and uv3 hardware always |
8b6e511e CW |
1781 | * uses native mode for selective broadcasts. |
1782 | */ | |
a26fd719 | 1783 | uv2_3_hdr = &bd2->header.uv2_3_hdr; |
67492c86 | 1784 | uv2_3_hdr->swack_flag = 1; |
a26fd719 | 1785 | uv2_3_hdr->base_dest_nasid = |
67492c86 AB |
1786 | UV_PNODE_TO_NASID(base_pnode); |
1787 | uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1788 | uv2_3_hdr->command = UV_NET_ENDPOINT_INTD; | |
da87c937 | 1789 | } |
b194b120 | 1790 | } |
b8f7fb13 CW |
1791 | for_each_present_cpu(cpu) { |
1792 | if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu))) | |
1793 | continue; | |
1794 | bcp = &per_cpu(bau_control, cpu); | |
1795 | bcp->descriptor_base = bau_desc; | |
1796 | } | |
b194b120 CW |
1797 | } |
1798 | ||
1799 | /* | |
1800 | * initialize the destination side's receiving buffers | |
b8f7fb13 CW |
1801 | * entered for each uvhub in the partition |
1802 | * - node is first node (kernel memory notion) on the uvhub | |
1803 | * - pnode is the uvhub's physical identifier | |
b194b120 | 1804 | */ |
f073cc8f | 1805 | static void pq_init(int node, int pnode) |
b194b120 | 1806 | { |
b8f7fb13 | 1807 | int cpu; |
f073cc8f | 1808 | size_t plsize; |
b4c286e6 | 1809 | char *cp; |
f073cc8f | 1810 | void *vp; |
d2a57afa | 1811 | unsigned long gnode, first, last, tail; |
f073cc8f | 1812 | struct bau_pq_entry *pqp; |
b8f7fb13 | 1813 | struct bau_control *bcp; |
1812924b | 1814 | |
f073cc8f CW |
1815 | plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry); |
1816 | vp = kmalloc_node(plsize, GFP_KERNEL, node); | |
1817 | pqp = (struct bau_pq_entry *)vp; | |
dc163a41 | 1818 | BUG_ON(!pqp); |
b4c286e6 | 1819 | |
b194b120 | 1820 | cp = (char *)pqp + 31; |
f073cc8f | 1821 | pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5); |
b8f7fb13 CW |
1822 | |
1823 | for_each_present_cpu(cpu) { | |
1824 | if (pnode != uv_cpu_to_pnode(cpu)) | |
1825 | continue; | |
1826 | /* for every cpu on this pnode: */ | |
1827 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1828 | bcp->queue_first = pqp; |
1829 | bcp->bau_msg_head = pqp; | |
1830 | bcp->queue_last = pqp + (DEST_Q_SIZE - 1); | |
b8f7fb13 | 1831 | } |
d2a57afa | 1832 | |
21e3f12f AB |
1833 | first = ops.bau_gpa_to_offset(uv_gpa(pqp)); |
1834 | last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1))); | |
d2a57afa | 1835 | |
4ea3c51d | 1836 | /* |
6d78059b AB |
1837 | * Pre UV4, the gnode is required to locate the payload queue |
1838 | * and the payload queue tail must be maintained by the kernel. | |
4ea3c51d | 1839 | */ |
6d78059b AB |
1840 | bcp = &per_cpu(bau_control, smp_processor_id()); |
1841 | if (bcp->uvhub_version <= 3) { | |
1842 | tail = first; | |
1843 | gnode = uv_gpa_to_gnode(uv_gpa(pqp)); | |
1844 | first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail; | |
1845 | write_mmr_payload_tail(pnode, tail); | |
1846 | } | |
1847 | ||
21e3f12f AB |
1848 | ops.write_payload_first(pnode, first); |
1849 | ops.write_payload_last(pnode, last); | |
f073cc8f | 1850 | |
b8f7fb13 | 1851 | /* in effect, all msg_type's are set to MSG_NOOP */ |
f073cc8f | 1852 | memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); |
b194b120 | 1853 | } |
1812924b | 1854 | |
b194b120 | 1855 | /* |
b8f7fb13 | 1856 | * Initialization of each UV hub's structures |
b194b120 | 1857 | */ |
f073cc8f | 1858 | static void __init init_uvhub(int uvhub, int vector, int base_pnode) |
b194b120 | 1859 | { |
9674f35b | 1860 | int node; |
b194b120 | 1861 | int pnode; |
b194b120 | 1862 | unsigned long apicid; |
b8f7fb13 CW |
1863 | |
1864 | node = uvhub_to_first_node(uvhub); | |
1865 | pnode = uv_blade_to_pnode(uvhub); | |
f073cc8f CW |
1866 | |
1867 | activation_descriptor_init(node, pnode, base_pnode); | |
1868 | ||
1869 | pq_init(node, pnode); | |
b194b120 | 1870 | /* |
77ed23f8 CW |
1871 | * The below initialization can't be in firmware because the |
1872 | * messaging IRQ will be determined by the OS. | |
b194b120 | 1873 | */ |
8191c9f6 | 1874 | apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; |
f073cc8f | 1875 | write_mmr_data_config(pnode, ((apicid << 32) | vector)); |
b8f7fb13 CW |
1876 | } |
1877 | ||
12a6611f CW |
1878 | /* |
1879 | * We will set BAU_MISC_CONTROL with a timeout period. | |
1880 | * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. | |
f073cc8f | 1881 | * So the destination timeout period has to be calculated from them. |
12a6611f | 1882 | */ |
f073cc8f | 1883 | static int calculate_destination_timeout(void) |
12a6611f CW |
1884 | { |
1885 | unsigned long mmr_image; | |
1886 | int mult1; | |
1887 | int mult2; | |
1888 | int index; | |
1889 | int base; | |
1890 | int ret; | |
1891 | unsigned long ts_ns; | |
1892 | ||
2a919596 | 1893 | if (is_uv1_hub()) { |
f073cc8f | 1894 | mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; |
2a919596 JS |
1895 | mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); |
1896 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; | |
1897 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); | |
1898 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; | |
11cab711 CW |
1899 | ts_ns = timeout_base_ns[index]; |
1900 | ts_ns *= (mult1 * mult2); | |
2a919596 JS |
1901 | ret = ts_ns / 1000; |
1902 | } else { | |
a26fd719 | 1903 | /* same destination timeout for uv2 and uv3 */ |
d059f9fa CW |
1904 | /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ |
1905 | mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL); | |
2a919596 | 1906 | mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; |
f073cc8f | 1907 | if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) |
d059f9fa | 1908 | base = 80; |
2a919596 | 1909 | else |
d059f9fa CW |
1910 | base = 10; |
1911 | mult1 = mmr_image & UV2_ACK_MASK; | |
2a919596 JS |
1912 | ret = mult1 * base; |
1913 | } | |
12a6611f CW |
1914 | return ret; |
1915 | } | |
1916 | ||
f073cc8f CW |
1917 | static void __init init_per_cpu_tunables(void) |
1918 | { | |
1919 | int cpu; | |
1920 | struct bau_control *bcp; | |
1921 | ||
1922 | for_each_present_cpu(cpu) { | |
1923 | bcp = &per_cpu(bau_control, cpu); | |
1924 | bcp->baudisabled = 0; | |
26ef8577 | 1925 | if (nobau) |
1c532e00 | 1926 | bcp->nobau = true; |
f073cc8f CW |
1927 | bcp->statp = &per_cpu(ptcstats, cpu); |
1928 | /* time interval to catch a hardware stay-busy bug */ | |
1929 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); | |
1930 | bcp->max_concurr = max_concurr; | |
1931 | bcp->max_concurr_const = max_concurr; | |
1932 | bcp->plugged_delay = plugged_delay; | |
1933 | bcp->plugsb4reset = plugsb4reset; | |
1934 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1935 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1936 | bcp->complete_threshold = complete_threshold; | |
1937 | bcp->cong_response_us = congested_respns_us; | |
1938 | bcp->cong_reps = congested_reps; | |
67492c86 AB |
1939 | bcp->disabled_period = sec_2_cycles(disabled_period); |
1940 | bcp->giveup_limit = giveup_limit; | |
d2ebc71d CW |
1941 | spin_lock_init(&bcp->queue_lock); |
1942 | spin_lock_init(&bcp->uvhub_lock); | |
8b6e511e | 1943 | spin_lock_init(&bcp->disable_lock); |
f073cc8f CW |
1944 | } |
1945 | } | |
1946 | ||
b8f7fb13 | 1947 | /* |
f073cc8f | 1948 | * Scan all cpus to collect blade and socket summaries. |
b8f7fb13 | 1949 | */ |
f073cc8f CW |
1950 | static int __init get_cpu_topology(int base_pnode, |
1951 | struct uvhub_desc *uvhub_descs, | |
1952 | unsigned char *uvhub_mask) | |
b8f7fb13 | 1953 | { |
b8f7fb13 CW |
1954 | int cpu; |
1955 | int pnode; | |
1956 | int uvhub; | |
f073cc8f | 1957 | int socket; |
b8f7fb13 CW |
1958 | struct bau_control *bcp; |
1959 | struct uvhub_desc *bdp; | |
1960 | struct socket_desc *sdp; | |
b8f7fb13 | 1961 | |
b8f7fb13 CW |
1962 | for_each_present_cpu(cpu) { |
1963 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1964 | |
b8f7fb13 | 1965 | memset(bcp, 0, sizeof(struct bau_control)); |
f073cc8f | 1966 | |
b8f7fb13 | 1967 | pnode = uv_cpu_hub_info(cpu)->pnode; |
f073cc8f | 1968 | if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) { |
efa59ab3 | 1969 | pr_emerg( |
77ed23f8 | 1970 | "cpu %d pnode %d-%d beyond %d; BAU disabled\n", |
f073cc8f | 1971 | cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE); |
77ed23f8 CW |
1972 | return 1; |
1973 | } | |
f073cc8f | 1974 | |
77ed23f8 | 1975 | bcp->osnode = cpu_to_node(cpu); |
f073cc8f CW |
1976 | bcp->partition_base_pnode = base_pnode; |
1977 | ||
b8f7fb13 | 1978 | uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; |
c4026cfd | 1979 | *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); |
b8f7fb13 | 1980 | bdp = &uvhub_descs[uvhub]; |
f073cc8f | 1981 | |
b8f7fb13 CW |
1982 | bdp->num_cpus++; |
1983 | bdp->uvhub = uvhub; | |
1984 | bdp->pnode = pnode; | |
f073cc8f | 1985 | |
a8328ee5 CW |
1986 | /* kludge: 'assuming' one node per socket, and assuming that |
1987 | disabling a socket just leaves a gap in node numbers */ | |
77ed23f8 | 1988 | socket = bcp->osnode & 1; |
a8328ee5 | 1989 | bdp->socket_mask |= (1 << socket); |
b8f7fb13 CW |
1990 | sdp = &bdp->socket[socket]; |
1991 | sdp->cpu_number[sdp->num_cpus] = cpu; | |
1992 | sdp->num_cpus++; | |
cfa60917 | 1993 | if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { |
efa59ab3 | 1994 | pr_emerg("%d cpus per socket invalid\n", |
f073cc8f | 1995 | sdp->num_cpus); |
cfa60917 CW |
1996 | return 1; |
1997 | } | |
b8f7fb13 | 1998 | } |
f073cc8f CW |
1999 | return 0; |
2000 | } | |
2001 | ||
2002 | /* | |
2003 | * Each socket is to get a local array of pnodes/hubs. | |
2004 | */ | |
2005 | static void make_per_cpu_thp(struct bau_control *smaster) | |
2006 | { | |
2007 | int cpu; | |
2008 | size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus(); | |
2009 | ||
2010 | smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode); | |
2011 | memset(smaster->thp, 0, hpsz); | |
2012 | for_each_present_cpu(cpu) { | |
2013 | smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode; | |
2014 | smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; | |
2015 | } | |
2016 | } | |
2017 | ||
442d3924 | 2018 | /* |
2019 | * Each uvhub is to get a local cpumask. | |
2020 | */ | |
2021 | static void make_per_hub_cpumask(struct bau_control *hmaster) | |
2022 | { | |
2023 | int sz = sizeof(cpumask_t); | |
2024 | ||
2025 | hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode); | |
2026 | } | |
2027 | ||
f073cc8f CW |
2028 | /* |
2029 | * Initialize all the per_cpu information for the cpu's on a given socket, | |
2030 | * given what has been gathered into the socket_desc struct. | |
2031 | * And reports the chosen hub and socket masters back to the caller. | |
2032 | */ | |
2033 | static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, | |
2034 | struct bau_control **smasterp, | |
2035 | struct bau_control **hmasterp) | |
2036 | { | |
2037 | int i; | |
2038 | int cpu; | |
2039 | struct bau_control *bcp; | |
2040 | ||
2041 | for (i = 0; i < sdp->num_cpus; i++) { | |
2042 | cpu = sdp->cpu_number[i]; | |
2043 | bcp = &per_cpu(bau_control, cpu); | |
2044 | bcp->cpu = cpu; | |
2045 | if (i == 0) { | |
2046 | *smasterp = bcp; | |
2047 | if (!(*hmasterp)) | |
2048 | *hmasterp = bcp; | |
2049 | } | |
2050 | bcp->cpus_in_uvhub = bdp->num_cpus; | |
2051 | bcp->cpus_in_socket = sdp->num_cpus; | |
2052 | bcp->socket_master = *smasterp; | |
2053 | bcp->uvhub = bdp->uvhub; | |
da87c937 CW |
2054 | if (is_uv1_hub()) |
2055 | bcp->uvhub_version = 1; | |
2056 | else if (is_uv2_hub()) | |
2057 | bcp->uvhub_version = 2; | |
a26fd719 CW |
2058 | else if (is_uv3_hub()) |
2059 | bcp->uvhub_version = 3; | |
58d4ab46 AB |
2060 | else if (is_uv4_hub()) |
2061 | bcp->uvhub_version = 4; | |
da87c937 | 2062 | else { |
58d4ab46 | 2063 | pr_emerg("uvhub version not 1, 2, 3, or 4\n"); |
da87c937 CW |
2064 | return 1; |
2065 | } | |
f073cc8f | 2066 | bcp->uvhub_master = *hmasterp; |
5627a825 MT |
2067 | bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu); |
2068 | ||
f073cc8f | 2069 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { |
efa59ab3 | 2070 | pr_emerg("%d cpus per uvhub invalid\n", |
f073cc8f CW |
2071 | bcp->uvhub_cpu); |
2072 | return 1; | |
2073 | } | |
2074 | } | |
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | /* | |
2079 | * Summarize the blade and socket topology into the per_cpu structures. | |
2080 | */ | |
2081 | static int __init summarize_uvhub_sockets(int nuvhubs, | |
2082 | struct uvhub_desc *uvhub_descs, | |
2083 | unsigned char *uvhub_mask) | |
2084 | { | |
2085 | int socket; | |
2086 | int uvhub; | |
2087 | unsigned short socket_mask; | |
2088 | ||
c4026cfd | 2089 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
2090 | struct uvhub_desc *bdp; |
2091 | struct bau_control *smaster = NULL; | |
2092 | struct bau_control *hmaster = NULL; | |
2093 | ||
c4026cfd CW |
2094 | if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) |
2095 | continue; | |
f073cc8f | 2096 | |
b8f7fb13 | 2097 | bdp = &uvhub_descs[uvhub]; |
a8328ee5 CW |
2098 | socket_mask = bdp->socket_mask; |
2099 | socket = 0; | |
2100 | while (socket_mask) { | |
f073cc8f CW |
2101 | struct socket_desc *sdp; |
2102 | if ((socket_mask & 1)) { | |
2103 | sdp = &bdp->socket[socket]; | |
2104 | if (scan_sock(sdp, bdp, &smaster, &hmaster)) | |
cfa60917 | 2105 | return 1; |
9c9153db | 2106 | make_per_cpu_thp(smaster); |
b8f7fb13 CW |
2107 | } |
2108 | socket++; | |
a8328ee5 | 2109 | socket_mask = (socket_mask >> 1); |
b8f7fb13 | 2110 | } |
442d3924 | 2111 | make_per_hub_cpumask(hmaster); |
b8f7fb13 | 2112 | } |
f073cc8f CW |
2113 | return 0; |
2114 | } | |
2115 | ||
2116 | /* | |
2117 | * initialize the bau_control structure for each cpu | |
2118 | */ | |
2119 | static int __init init_per_cpu(int nuvhubs, int base_part_pnode) | |
2120 | { | |
2121 | unsigned char *uvhub_mask; | |
2122 | void *vp; | |
2123 | struct uvhub_desc *uvhub_descs; | |
2124 | ||
e879c112 AB |
2125 | if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub()) |
2126 | timeout_us = calculate_destination_timeout(); | |
f073cc8f CW |
2127 | |
2128 | vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); | |
2129 | uvhub_descs = (struct uvhub_desc *)vp; | |
2130 | memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); | |
2131 | uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); | |
2132 | ||
2133 | if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 2134 | goto fail; |
f073cc8f CW |
2135 | |
2136 | if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 2137 | goto fail; |
f073cc8f | 2138 | |
b8f7fb13 | 2139 | kfree(uvhub_descs); |
c4026cfd | 2140 | kfree(uvhub_mask); |
f073cc8f | 2141 | init_per_cpu_tunables(); |
cfa60917 | 2142 | return 0; |
bbd270e6 | 2143 | |
2144 | fail: | |
2145 | kfree(uvhub_descs); | |
2146 | kfree(uvhub_mask); | |
2147 | return 1; | |
b194b120 CW |
2148 | } |
2149 | ||
2150 | /* | |
2151 | * Initialization of BAU-related structures | |
2152 | */ | |
2153 | static int __init uv_bau_init(void) | |
2154 | { | |
b8f7fb13 CW |
2155 | int uvhub; |
2156 | int pnode; | |
2157 | int nuvhubs; | |
2c74d666 | 2158 | int cur_cpu; |
f073cc8f | 2159 | int cpus; |
b8f7fb13 | 2160 | int vector; |
f073cc8f | 2161 | cpumask_var_t *mask; |
b194b120 CW |
2162 | |
2163 | if (!is_uv_system()) | |
2164 | return 0; | |
1812924b | 2165 | |
4f059d51 AB |
2166 | if (is_uv4_hub()) |
2167 | ops = uv4_bau_ops; | |
2168 | else if (is_uv3_hub()) | |
5e4f96fe AB |
2169 | ops = uv123_bau_ops; |
2170 | else if (is_uv2_hub()) | |
2171 | ops = uv123_bau_ops; | |
2172 | else if (is_uv1_hub()) | |
2173 | ops = uv123_bau_ops; | |
2174 | ||
f073cc8f CW |
2175 | for_each_possible_cpu(cur_cpu) { |
2176 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); | |
2177 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); | |
2178 | } | |
76ba0ecd | 2179 | |
b8f7fb13 | 2180 | nuvhubs = uv_num_possible_blades(); |
f073cc8f | 2181 | congested_cycles = usec_2_cycles(congested_respns_us); |
9674f35b | 2182 | |
f073cc8f | 2183 | uv_base_pnode = 0x7fffffff; |
77ed23f8 | 2184 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
2185 | cpus = uv_blade_nr_possible_cpus(uvhub); |
2186 | if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode)) | |
2187 | uv_base_pnode = uv_blade_to_pnode(uvhub); | |
77ed23f8 CW |
2188 | } |
2189 | ||
e879c112 AB |
2190 | /* software timeouts are not supported on UV4 */ |
2191 | if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub()) | |
2192 | enable_timeouts(); | |
d059f9fa | 2193 | |
f073cc8f | 2194 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
26ef8577 CW |
2195 | set_bau_off(); |
2196 | nobau_perm = 1; | |
77ed23f8 CW |
2197 | return 0; |
2198 | } | |
b8f7fb13 CW |
2199 | |
2200 | vector = UV_BAU_MESSAGE; | |
a26fd719 | 2201 | for_each_possible_blade(uvhub) { |
b8f7fb13 | 2202 | if (uv_blade_nr_possible_cpus(uvhub)) |
f073cc8f | 2203 | init_uvhub(uvhub, vector, uv_base_pnode); |
a26fd719 | 2204 | } |
b8f7fb13 | 2205 | |
b8f7fb13 CW |
2206 | alloc_intr_gate(vector, uv_bau_message_intr1); |
2207 | ||
2208 | for_each_possible_blade(uvhub) { | |
93a7ca0c | 2209 | if (uv_blade_nr_possible_cpus(uvhub)) { |
f073cc8f CW |
2210 | unsigned long val; |
2211 | unsigned long mmr; | |
93a7ca0c CW |
2212 | pnode = uv_blade_to_pnode(uvhub); |
2213 | /* INIT the bau */ | |
f073cc8f CW |
2214 | val = 1L << 63; |
2215 | write_gmmr_activation(pnode, val); | |
93a7ca0c | 2216 | mmr = 1; /* should be 1 to broadcast to both sockets */ |
da87c937 CW |
2217 | if (!is_uv1_hub()) |
2218 | write_mmr_data_broadcast(pnode, mmr); | |
93a7ca0c | 2219 | } |
b8f7fb13 | 2220 | } |
b4c286e6 | 2221 | |
1812924b CW |
2222 | return 0; |
2223 | } | |
b8f7fb13 | 2224 | core_initcall(uv_bau_init); |
e8e5e8a8 | 2225 | fs_initcall(uv_ptc_init); |