[mirror_ubuntu-artful-kernel.git] / arch / x86 / platform / uv / uv_nmi.c

/*
 * SGI NMI support routines
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Copyright (c) 2009-2013 Silicon Graphics, Inc.  All Rights Reserved.
 *  Copyright (c) Mike Travis
 */

#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/kdb.h>
#include <linux/kexec.h>
#include <linux/kgdb.h>
#include <linux/module.h>
#include <linux/nmi.h>
#include <linux/sched.h>
#include <linux/slab.h>

#include <asm/apic.h>
#include <asm/current.h>
#include <asm/kdebug.h>
#include <asm/local64.h>
#include <asm/nmi.h>
#include <asm/traps.h>
#include <asm/uv/uv.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/uv_mmrs.h>

/*
 * UV handler for NMI
 *
 * Handle system-wide NMI events generated by the global 'power nmi' command.
 *
 * Basic operation is to field the NMI interrupt on each cpu and wait
 * until all cpus have arrived into the nmi handler.  If some cpus do not
 * make it into the handler, try and force them in with the IPI(NMI) signal.
 *
 * We also have to lessen UV Hub MMR accesses as much as possible as this
 * disrupts the UV Hub's primary mission of directing NumaLink traffic and
 * can cause system problems to occur.
 *
 * To do this we register our primary NMI notifier on the NMI_UNKNOWN
 * chain.  This reduces the number of false NMI calls when the perf
 * tools are running which generate an enormous number of NMIs per
 * second (~4M/s for 1024 cpu threads).  Our secondary NMI handler is
 * very short as it only checks that if it has been "pinged" with the
 * IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
 *
 */

static struct uv_hub_nmi_s **uv_hub_nmi_list;

DEFINE_PER_CPU(struct uv_cpu_nmi_s, __uv_cpu_nmi);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_nmi);

static unsigned long nmi_mmr;
static unsigned long nmi_mmr_clear;
static unsigned long nmi_mmr_pending;

static atomic_t	uv_in_nmi;
static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
static atomic_t uv_nmi_cpus_in_nmi = ATOMIC_INIT(-1);
static atomic_t uv_nmi_slave_continue;
static cpumask_var_t uv_nmi_cpu_mask;

/* Values for uv_nmi_slave_continue */
#define SLAVE_CLEAR	0
#define SLAVE_CONTINUE	1
#define SLAVE_EXIT	2

/*
 * Default is all stack dumps go to the console and buffer.
 * Lower level to send to log buffer only.
 */
static int uv_nmi_loglevel = 7;
module_param_named(dump_loglevel, uv_nmi_loglevel, int, 0644);

/*
 * The following values show statistics on how perf events are affecting
 * this system.
 */
static int param_get_local64(char *buffer, const struct kernel_param *kp)
{
	return sprintf(buffer, "%lu\n", local64_read((local64_t *)kp->arg));
}

static int param_set_local64(const char *val, const struct kernel_param *kp)
{
	/* clear on any write */
	local64_set((local64_t *)kp->arg, 0);
	return 0;
}

static struct kernel_param_ops param_ops_local64 = {
	.get = param_get_local64,
	.set = param_set_local64,
};
#define param_check_local64(name, p) __param_check(name, p, local64_t)

static local64_t uv_nmi_count;
module_param_named(nmi_count, uv_nmi_count, local64, 0644);

static local64_t uv_nmi_misses;
module_param_named(nmi_misses, uv_nmi_misses, local64, 0644);

static local64_t uv_nmi_ping_count;
module_param_named(ping_count, uv_nmi_ping_count, local64, 0644);

static local64_t uv_nmi_ping_misses;
module_param_named(ping_misses, uv_nmi_ping_misses, local64, 0644);

/*
 * Following values allow tuning for large systems under heavy loading
 */
static int uv_nmi_initial_delay = 100;
module_param_named(initial_delay, uv_nmi_initial_delay, int, 0644);

static int uv_nmi_slave_delay = 100;
module_param_named(slave_delay, uv_nmi_slave_delay, int, 0644);

static int uv_nmi_loop_delay = 100;
module_param_named(loop_delay, uv_nmi_loop_delay, int, 0644);

static int uv_nmi_trigger_delay = 10000;
module_param_named(trigger_delay, uv_nmi_trigger_delay, int, 0644);

static int uv_nmi_wait_count = 100;
module_param_named(wait_count, uv_nmi_wait_count, int, 0644);

static int uv_nmi_retry_count = 500;
module_param_named(retry_count, uv_nmi_retry_count, int, 0644);

/*
 * Valid NMI Actions:
 *  "dump"	- dump process stack for each cpu
 *  "ips"	- dump IP info for each cpu
 *  "kdump"	- do crash dump
 *  "kdb"	- enter KDB/KGDB (default)
 */
static char uv_nmi_action[8] = "kdb";
module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644);

static inline bool uv_nmi_action_is(const char *action)
{
	return (strncmp(uv_nmi_action, action, strlen(action)) == 0);
}

/* Setup which NMI support is present in system */
static void uv_nmi_setup_mmrs(void)
{
	if (uv_read_local_mmr(UVH_NMI_MMRX_SUPPORTED)) {
		uv_write_local_mmr(UVH_NMI_MMRX_REQ,
					1UL << UVH_NMI_MMRX_REQ_SHIFT);
		nmi_mmr = UVH_NMI_MMRX;
		nmi_mmr_clear = UVH_NMI_MMRX_CLEAR;
		nmi_mmr_pending = 1UL << UVH_NMI_MMRX_SHIFT;
		pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMRX_TYPE);
	} else {
		nmi_mmr = UVH_NMI_MMR;
		nmi_mmr_clear = UVH_NMI_MMR_CLEAR;
		nmi_mmr_pending = 1UL << UVH_NMI_MMR_SHIFT;
		pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMR_TYPE);
	}
}

/* Read NMI MMR and check if NMI flag was set by BMC. */
static inline int uv_nmi_test_mmr(struct uv_hub_nmi_s *hub_nmi)
{
	hub_nmi->nmi_value = uv_read_local_mmr(nmi_mmr);
	atomic_inc(&hub_nmi->read_mmr_count);
	return !!(hub_nmi->nmi_value & nmi_mmr_pending);
}

static inline void uv_local_mmr_clear_nmi(void)
{
	uv_write_local_mmr(nmi_mmr_clear, nmi_mmr_pending);
}

/*
 * If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
 * return true.  If first cpu in on the system, set global "in_nmi" flag.
 */
static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi)
{
	int first = atomic_add_unless(&hub_nmi->in_nmi, 1, 1);

	if (first) {
		atomic_set(&hub_nmi->cpu_owner, cpu);
		if (atomic_add_unless(&uv_in_nmi, 1, 1))
			atomic_set(&uv_nmi_cpu, cpu);

		atomic_inc(&hub_nmi->nmi_count);
	}
	return first;
}

/* Check if this is a system NMI event */
static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
{
	int cpu = smp_processor_id();
	int nmi = 0;

	local64_inc(&uv_nmi_count);
	uv_cpu_nmi.queries++;

	do {
		nmi = atomic_read(&hub_nmi->in_nmi);
		if (nmi)
			break;

		if (raw_spin_trylock(&hub_nmi->nmi_lock)) {

			/* check hub MMR NMI flag */
			if (uv_nmi_test_mmr(hub_nmi)) {
				uv_set_in_nmi(cpu, hub_nmi);
				nmi = 1;
				break;
			}

			/* MMR NMI flag is clear */
			raw_spin_unlock(&hub_nmi->nmi_lock);

		} else {
			/* wait a moment for the hub nmi locker to set flag */
			cpu_relax();
			udelay(uv_nmi_slave_delay);

			/* re-check hub in_nmi flag */
			nmi = atomic_read(&hub_nmi->in_nmi);
			if (nmi)
				break;
		}

		/* check if this BMC missed setting the MMR NMI flag */
		if (!nmi) {
			nmi = atomic_read(&uv_in_nmi);
			if (nmi)
				uv_set_in_nmi(cpu, hub_nmi);
		}

	} while (0);

	if (!nmi)
		local64_inc(&uv_nmi_misses);

	return nmi;
}

/* Need to reset the NMI MMR register, but only once per hub. */
static inline void uv_clear_nmi(int cpu)
{
	struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi;

	if (cpu == atomic_read(&hub_nmi->cpu_owner)) {
		atomic_set(&hub_nmi->cpu_owner, -1);
		atomic_set(&hub_nmi->in_nmi, 0);
		uv_local_mmr_clear_nmi();
		raw_spin_unlock(&hub_nmi->nmi_lock);
	}
}

/* Print non-responding cpus */
static void uv_nmi_nr_cpus_pr(char *fmt)
{
	static char cpu_list[1024];
	int len = sizeof(cpu_list);
	int c = cpumask_weight(uv_nmi_cpu_mask);
	int n = cpulist_scnprintf(cpu_list, len, uv_nmi_cpu_mask);

	if (n >= len-1)
		strcpy(&cpu_list[len - 6], "...\n");

	printk(fmt, c, cpu_list);
}

/* Ping non-responding cpus attemping to force them into the NMI handler */
static void uv_nmi_nr_cpus_ping(void)
{
	int cpu;

	for_each_cpu(cpu, uv_nmi_cpu_mask)
		atomic_set(&uv_cpu_nmi_per(cpu).pinging, 1);

	apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI);
}

/* Clean up flags for cpus that ignored both NMI and ping */
static void uv_nmi_cleanup_mask(void)
{
	int cpu;

	for_each_cpu(cpu, uv_nmi_cpu_mask) {
		atomic_set(&uv_cpu_nmi_per(cpu).pinging, 0);
		atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_OUT);
		cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
	}
}

/* Loop waiting as cpus enter nmi handler */
static int uv_nmi_wait_cpus(int first)
{
	int i, j, k, n = num_online_cpus();
	int last_k = 0, waiting = 0;

	if (first) {
		cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask);
		k = 0;
	} else {
		k = n - cpumask_weight(uv_nmi_cpu_mask);
	}

	udelay(uv_nmi_initial_delay);
	for (i = 0; i < uv_nmi_retry_count; i++) {
		int loop_delay = uv_nmi_loop_delay;

		for_each_cpu(j, uv_nmi_cpu_mask) {
			if (atomic_read(&uv_cpu_nmi_per(j).state)) {
				cpumask_clear_cpu(j, uv_nmi_cpu_mask);
				if (++k >= n)
					break;
			}
		}
		if (k >= n) {		/* all in? */
			k = n;
			break;
		}
		if (last_k != k) {	/* abort if no new cpus coming in */
			last_k = k;
			waiting = 0;
		} else if (++waiting > uv_nmi_wait_count)
			break;

		/* extend delay if waiting only for cpu 0 */
		if (waiting && (n - k) == 1 &&
		    cpumask_test_cpu(0, uv_nmi_cpu_mask))
			loop_delay *= 100;

		udelay(loop_delay);
	}
	atomic_set(&uv_nmi_cpus_in_nmi, k);
	return n - k;
}

/* Wait until all slave cpus have entered UV NMI handler */
static void uv_nmi_wait(int master)
{
	/* indicate this cpu is in */
	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_IN);

	/* if not the first cpu in (the master), then we are a slave cpu */
	if (!master)
		return;

	do {
		/* wait for all other cpus to gather here */
		if (!uv_nmi_wait_cpus(1))
			break;

		/* if not all made it in, send IPI NMI to them */
		uv_nmi_nr_cpus_pr(KERN_ALERT
			"UV: Sending NMI IPI to %d non-responding CPUs: %s\n");
		uv_nmi_nr_cpus_ping();

		/* if all cpus are in, then done */
		if (!uv_nmi_wait_cpus(0))
			break;

		uv_nmi_nr_cpus_pr(KERN_ALERT
			"UV: %d CPUs not in NMI loop: %s\n");
	} while (0);

	pr_alert("UV: %d of %d CPUs in NMI\n",
		atomic_read(&uv_nmi_cpus_in_nmi), num_online_cpus());
}

static void uv_nmi_dump_cpu_ip_hdr(void)
{
	printk(KERN_DEFAULT
		"\nUV: %4s %6s %-32s %s   (Note: PID 0 not listed)\n",
		"CPU", "PID", "COMMAND", "IP");
}

static void uv_nmi_dump_cpu_ip(int cpu, struct pt_regs *regs)
{
	printk(KERN_DEFAULT "UV: %4d %6d %-32.32s ",
		cpu, current->pid, current->comm);

	printk_address(regs->ip);
}

/* Dump this cpu's state */
static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs)
{
	const char *dots = " ................................. ";

	if (uv_nmi_action_is("ips")) {
		if (cpu == 0)
			uv_nmi_dump_cpu_ip_hdr();

		if (current->pid != 0)
			uv_nmi_dump_cpu_ip(cpu, regs);

	} else if (uv_nmi_action_is("dump")) {
		printk(KERN_DEFAULT
			"UV:%sNMI process trace for CPU %d\n", dots, cpu);
		show_regs(regs);
	}
	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE);
}

/* Trigger a slave cpu to dump it's state */
static void uv_nmi_trigger_dump(int cpu)
{
	int retry = uv_nmi_trigger_delay;

	if (atomic_read(&uv_cpu_nmi_per(cpu).state) != UV_NMI_STATE_IN)
		return;

	atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP);
	do {
		cpu_relax();
		udelay(10);
		if (atomic_read(&uv_cpu_nmi_per(cpu).state)
				!= UV_NMI_STATE_DUMP)
			return;
	} while (--retry > 0);

	pr_crit("UV: CPU %d stuck in process dump function\n", cpu);
	atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP_DONE);
}

/* Wait until all cpus ready to exit */
static void uv_nmi_sync_exit(int master)
{
	atomic_dec(&uv_nmi_cpus_in_nmi);
	if (master) {
		while (atomic_read(&uv_nmi_cpus_in_nmi) > 0)
			cpu_relax();
		atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR);
	} else {
		while (atomic_read(&uv_nmi_slave_continue))
			cpu_relax();
	}
}

/* Walk through cpu list and dump state of each */
static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master)
{
	if (master) {
		int tcpu;
		int ignored = 0;
		int saved_console_loglevel = console_loglevel;

		pr_alert("UV: tracing %s for %d CPUs from CPU %d\n",
			uv_nmi_action_is("ips") ? "IPs" : "processes",
			atomic_read(&uv_nmi_cpus_in_nmi), cpu);

		console_loglevel = uv_nmi_loglevel;
		atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
		for_each_online_cpu(tcpu) {
			if (cpumask_test_cpu(tcpu, uv_nmi_cpu_mask))
				ignored++;
			else if (tcpu == cpu)
				uv_nmi_dump_state_cpu(tcpu, regs);
			else
				uv_nmi_trigger_dump(tcpu);
		}
		if (ignored)
			printk(KERN_DEFAULT "UV: %d CPUs ignored NMI\n",
				ignored);

		console_loglevel = saved_console_loglevel;
		pr_alert("UV: process trace complete\n");
	} else {
		while (!atomic_read(&uv_nmi_slave_continue))
			cpu_relax();
		while (atomic_read(&uv_cpu_nmi.state) != UV_NMI_STATE_DUMP)
			cpu_relax();
		uv_nmi_dump_state_cpu(cpu, regs);
	}
	uv_nmi_sync_exit(master);
}

static void uv_nmi_touch_watchdogs(void)
{
	touch_softlockup_watchdog_sync();
	clocksource_touch_watchdog();
	rcu_cpu_stall_reset();
	touch_nmi_watchdog();
}

#if defined(CONFIG_KEXEC)
static atomic_t uv_nmi_kexec_failed;
static void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
{
	/* Call crash to dump system state */
	if (master) {
		pr_emerg("UV: NMI executing crash_kexec on CPU%d\n", cpu);
		crash_kexec(regs);

		pr_emerg("UV: crash_kexec unexpectedly returned, ");
		if (!kexec_crash_image) {
			pr_cont("crash kernel not loaded\n");
			atomic_set(&uv_nmi_kexec_failed, 1);
			uv_nmi_sync_exit(1);
			return;
		}
		pr_cont("kexec busy, stalling cpus while waiting\n");
	}

	/* If crash exec fails the slaves should return, otherwise stall */
	while (atomic_read(&uv_nmi_kexec_failed) == 0)
		mdelay(10);

	/* Crash kernel most likely not loaded, return in an orderly fashion */
	uv_nmi_sync_exit(0);
}

#else /* !CONFIG_KEXEC */
static inline void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
{
	if (master)
		pr_err("UV: NMI kdump: KEXEC not supported in this kernel\n");
}
#endif /* !CONFIG_KEXEC */

#ifdef CONFIG_KGDB_KDB
/* Call KDB from NMI handler */
static void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
{
	int ret;

	if (master) {
		/* call KGDB NMI handler as MASTER */
		ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs,
			KDB_REASON_SYSTEM_NMI, &uv_nmi_slave_continue);
		if (ret) {
			pr_alert("KDB returned error, is kgdboc set?\n");
			atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
		}
	} else {
		/* wait for KGDB signal that it's ready for slaves to enter */
		int sig;

		do {
			cpu_relax();
			sig = atomic_read(&uv_nmi_slave_continue);
		} while (!sig);

		/* call KGDB as slave */
		if (sig == SLAVE_CONTINUE)
			kgdb_nmicallback(cpu, regs);
	}
	uv_nmi_sync_exit(master);
}

#else /* !CONFIG_KGDB_KDB */
static inline void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
{
	pr_err("UV: NMI error: KGDB/KDB is not enabled in this kernel\n");
}
#endif /* !CONFIG_KGDB_KDB */

/*
 * UV NMI handler
 */
int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
{
	struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi;
	int cpu = smp_processor_id();
	int master = 0;
	unsigned long flags;

	local_irq_save(flags);

	/* If not a UV System NMI, ignore */
	if (!atomic_read(&uv_cpu_nmi.pinging) && !uv_check_nmi(hub_nmi)) {
		local_irq_restore(flags);
		return NMI_DONE;
	}

	/* Indicate we are the first CPU into the NMI handler */
	master = (atomic_read(&uv_nmi_cpu) == cpu);

	/* If NMI action is "kdump", then attempt to do it */
	if (uv_nmi_action_is("kdump"))
		uv_nmi_kdump(cpu, master, regs);

	/* Pause as all cpus enter the NMI handler */
	uv_nmi_wait(master);

	/* Dump state of each cpu */
	if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump"))
		uv_nmi_dump_state(cpu, regs, master);

	/* Call KDB if enabled */
	else if (uv_nmi_action_is("kdb"))
		uv_call_kdb(cpu, regs, master);

	/* Clear per_cpu "in nmi" flag */
	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_OUT);

	/* Clear MMR NMI flag on each hub */
	uv_clear_nmi(cpu);

	/* Clear global flags */
	if (master) {
		if (cpumask_weight(uv_nmi_cpu_mask))
			uv_nmi_cleanup_mask();
		atomic_set(&uv_nmi_cpus_in_nmi, -1);
		atomic_set(&uv_nmi_cpu, -1);
		atomic_set(&uv_in_nmi, 0);
	}

	uv_nmi_touch_watchdogs();
	local_irq_restore(flags);

	return NMI_HANDLED;
}

/*
 * NMI handler for pulling in CPUs when perf events are grabbing our NMI
 */
static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
{
	int ret;

	uv_cpu_nmi.queries++;
	if (!atomic_read(&uv_cpu_nmi.pinging)) {
		local64_inc(&uv_nmi_ping_misses);
		return NMI_DONE;
	}

	uv_cpu_nmi.pings++;
	local64_inc(&uv_nmi_ping_count);
	ret = uv_handle_nmi(reason, regs);
	atomic_set(&uv_cpu_nmi.pinging, 0);
	return ret;
}

static void uv_register_nmi_notifier(void)
{
	if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
		pr_warn("UV: NMI handler failed to register\n");

	if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping"))
		pr_warn("UV: PING NMI handler failed to register\n");
}

void uv_nmi_init(void)
{
	unsigned int value;

	/*
	 * Unmask NMI on all cpus
	 */
	value = apic_read(APIC_LVT1) | APIC_DM_NMI;
	value &= ~APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);
}

void uv_nmi_setup(void)
{
	int size = sizeof(void *) * (1 << NODES_SHIFT);
	int cpu, nid;

	/* Setup hub nmi info */
	uv_nmi_setup_mmrs();
	uv_hub_nmi_list = kzalloc(size, GFP_KERNEL);
	pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
	BUG_ON(!uv_hub_nmi_list);
	size = sizeof(struct uv_hub_nmi_s);
	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		if (uv_hub_nmi_list[nid] == NULL) {
			uv_hub_nmi_list[nid] = kzalloc_node(size,
							    GFP_KERNEL, nid);
			BUG_ON(!uv_hub_nmi_list[nid]);
			raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock));
			atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1);
		}
		uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
	}
	BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
	uv_register_nmi_notifier();
}
Commit	Line	Data
1e019421	1	/*
b5dfcb09	2	* SGI NMI support routines
1e019421 MT	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	* Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
	19	* Copyright (c) Mike Travis
	20	*/
	21
	22	#include <linux/cpu.h>
0d12ef0c	23	#include <linux/delay.h>
e379ea82	24	#include <linux/kdb.h>
12ba6c99	25	#include <linux/kexec.h>
e379ea82	26	#include <linux/kgdb.h>
0d12ef0c	27	#include <linux/module.h>
1e019421	28	#include <linux/nmi.h>
0d12ef0c MT	29	#include <linux/sched.h>
0d12ef0c MT	30	#include <linux/slab.h>
1e019421 MT	31
1e019421 MT	32	#include <asm/apic.h>
0d12ef0c MT	33	#include <asm/current.h>
	34	#include <asm/kdebug.h>
	35	#include <asm/local64.h>
1e019421	36	#include <asm/nmi.h>
e379ea82	37	#include <asm/traps.h>
1e019421 MT	38	#include <asm/uv/uv.h>
	39	#include <asm/uv/uv_hub.h>
	40	#include <asm/uv/uv_mmrs.h>
	41
0d12ef0c MT	42	/*
	43	* UV handler for NMI
	44	*
	45	* Handle system-wide NMI events generated by the global 'power nmi' command.
	46	*
	47	* Basic operation is to field the NMI interrupt on each cpu and wait
	48	* until all cpus have arrived into the nmi handler. If some cpus do not
	49	* make it into the handler, try and force them in with the IPI(NMI) signal.
	50	*
	51	* We also have to lessen UV Hub MMR accesses as much as possible as this
	52	* disrupts the UV Hub's primary mission of directing NumaLink traffic and
	53	* can cause system problems to occur.
	54	*
	55	* To do this we register our primary NMI notifier on the NMI_UNKNOWN
	56	* chain. This reduces the number of false NMI calls when the perf
	57	* tools are running which generate an enormous number of NMIs per
	58	* second (~4M/s for 1024 cpu threads). Our secondary NMI handler is
	59	* very short as it only checks that if it has been "pinged" with the
	60	* IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
	61	*
	62	*/
	63
	64	static struct uv_hub_nmi_s **uv_hub_nmi_list;
	65
	66	DEFINE_PER_CPU(struct uv_cpu_nmi_s, __uv_cpu_nmi);
	67	EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_nmi);
	68
	69	static unsigned long nmi_mmr;
	70	static unsigned long nmi_mmr_clear;
	71	static unsigned long nmi_mmr_pending;
	72
	73	static atomic_t uv_in_nmi;
	74	static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
	75	static atomic_t uv_nmi_cpus_in_nmi = ATOMIC_INIT(-1);
	76	static atomic_t uv_nmi_slave_continue;
	77	static cpumask_var_t uv_nmi_cpu_mask;
	78
	79	/* Values for uv_nmi_slave_continue */
	80	#define SLAVE_CLEAR 0
	81	#define SLAVE_CONTINUE 1
	82	#define SLAVE_EXIT 2
1e019421 MT	83
1e019421 MT	84	/*
0d12ef0c MT	85	* Default is all stack dumps go to the console and buffer.
0d12ef0c MT	86	* Lower level to send to log buffer only.
1e019421	87	*/
0d12ef0c MT	88	static int uv_nmi_loglevel = 7;
	89	module_param_named(dump_loglevel, uv_nmi_loglevel, int, 0644);
	90
	91	/*
	92	* The following values show statistics on how perf events are affecting
	93	* this system.
	94	*/
	95	static int param_get_local64(char buffer, const struct kernel_param kp)
1e019421	96	{
0d12ef0c MT	97	return sprintf(buffer, "%lu\n", local64_read((local64_t *)kp->arg));
0d12ef0c MT	98	}
1e019421	99
0d12ef0c MT	100	static int param_set_local64(const char val, const struct kernel_param kp)
	101	{
	102	/* clear on any write */
	103	local64_set((local64_t *)kp->arg, 0);
	104	return 0;
	105	}
	106
	107	static struct kernel_param_ops param_ops_local64 = {
	108	.get = param_get_local64,
	109	.set = param_set_local64,
	110	};
	111	#define param_check_local64(name, p) __param_check(name, p, local64_t)
	112
	113	static local64_t uv_nmi_count;
	114	module_param_named(nmi_count, uv_nmi_count, local64, 0644);
	115
	116	static local64_t uv_nmi_misses;
	117	module_param_named(nmi_misses, uv_nmi_misses, local64, 0644);
	118
	119	static local64_t uv_nmi_ping_count;
	120	module_param_named(ping_count, uv_nmi_ping_count, local64, 0644);
	121
	122	static local64_t uv_nmi_ping_misses;
	123	module_param_named(ping_misses, uv_nmi_ping_misses, local64, 0644);
	124
	125	/*
	126	* Following values allow tuning for large systems under heavy loading
	127	*/
	128	static int uv_nmi_initial_delay = 100;
	129	module_param_named(initial_delay, uv_nmi_initial_delay, int, 0644);
	130
	131	static int uv_nmi_slave_delay = 100;
	132	module_param_named(slave_delay, uv_nmi_slave_delay, int, 0644);
	133
	134	static int uv_nmi_loop_delay = 100;
	135	module_param_named(loop_delay, uv_nmi_loop_delay, int, 0644);
	136
	137	static int uv_nmi_trigger_delay = 10000;
	138	module_param_named(trigger_delay, uv_nmi_trigger_delay, int, 0644);
	139
	140	static int uv_nmi_wait_count = 100;
	141	module_param_named(wait_count, uv_nmi_wait_count, int, 0644);
	142
	143	static int uv_nmi_retry_count = 500;
	144	module_param_named(retry_count, uv_nmi_retry_count, int, 0644);
	145
3c121d9a MT	146	/*
	147	* Valid NMI Actions:
	148	* "dump" - dump process stack for each cpu
	149	* "ips" - dump IP info for each cpu
12ba6c99	150	* "kdump" - do crash dump
e379ea82	151	* "kdb" - enter KDB/KGDB (default)
3c121d9a	152	*/
e379ea82	153	static char uv_nmi_action[8] = "kdb";
3c121d9a MT	154	module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644);
	155
	156	static inline bool uv_nmi_action_is(const char *action)
	157	{
	158	return (strncmp(uv_nmi_action, action, strlen(action)) == 0);
	159	}
	160
0d12ef0c MT	161	/* Setup which NMI support is present in system */
	162	static void uv_nmi_setup_mmrs(void)
	163	{
	164	if (uv_read_local_mmr(UVH_NMI_MMRX_SUPPORTED)) {
	165	uv_write_local_mmr(UVH_NMI_MMRX_REQ,
	166	1UL << UVH_NMI_MMRX_REQ_SHIFT);
	167	nmi_mmr = UVH_NMI_MMRX;
	168	nmi_mmr_clear = UVH_NMI_MMRX_CLEAR;
	169	nmi_mmr_pending = 1UL << UVH_NMI_MMRX_SHIFT;
	170	pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMRX_TYPE);
	171	} else {
	172	nmi_mmr = UVH_NMI_MMR;
	173	nmi_mmr_clear = UVH_NMI_MMR_CLEAR;
	174	nmi_mmr_pending = 1UL << UVH_NMI_MMR_SHIFT;
	175	pr_info("UV: SMI NMI support: %s\n", UVH_NMI_MMR_TYPE);
	176	}
	177	}
	178
	179	/* Read NMI MMR and check if NMI flag was set by BMC. */
	180	static inline int uv_nmi_test_mmr(struct uv_hub_nmi_s *hub_nmi)
	181	{
	182	hub_nmi->nmi_value = uv_read_local_mmr(nmi_mmr);
	183	atomic_inc(&hub_nmi->read_mmr_count);
	184	return !!(hub_nmi->nmi_value & nmi_mmr_pending);
	185	}
	186
	187	static inline void uv_local_mmr_clear_nmi(void)
	188	{
	189	uv_write_local_mmr(nmi_mmr_clear, nmi_mmr_pending);
	190	}
	191
	192	/*
	193	* If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
	194	* return true. If first cpu in on the system, set global "in_nmi" flag.
	195	*/
	196	static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi)
	197	{
	198	int first = atomic_add_unless(&hub_nmi->in_nmi, 1, 1);
	199
	200	if (first) {
	201	atomic_set(&hub_nmi->cpu_owner, cpu);
	202	if (atomic_add_unless(&uv_in_nmi, 1, 1))
	203	atomic_set(&uv_nmi_cpu, cpu);
	204
	205	atomic_inc(&hub_nmi->nmi_count);
	206	}
	207	return first;
	208	}
	209
	210	/* Check if this is a system NMI event */
	211	static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
	212	{
	213	int cpu = smp_processor_id();
	214	int nmi = 0;
	215
	216	local64_inc(&uv_nmi_count);
	217	uv_cpu_nmi.queries++;
	218
	219	do {
	220	nmi = atomic_read(&hub_nmi->in_nmi);
	221	if (nmi)
	222	break;
	223
	224	if (raw_spin_trylock(&hub_nmi->nmi_lock)) {
225
226	/* check hub MMR NMI flag */
227	if (uv_nmi_test_mmr(hub_nmi)) {
228	uv_set_in_nmi(cpu, hub_nmi);
229	nmi = 1;
230	break;
231	}
232
233	/* MMR NMI flag is clear */
234	raw_spin_unlock(&hub_nmi->nmi_lock);
235
236	} else {
237	/* wait a moment for the hub nmi locker to set flag */
238	cpu_relax();
239	udelay(uv_nmi_slave_delay);
240
241	/* re-check hub in_nmi flag */
242	nmi = atomic_read(&hub_nmi->in_nmi);
243	if (nmi)
244	break;
245	}
246
247	/* check if this BMC missed setting the MMR NMI flag */
248	if (!nmi) {
249	nmi = atomic_read(&uv_in_nmi);
250	if (nmi)
251	uv_set_in_nmi(cpu, hub_nmi);
252	}
253
254	} while (0);
255
256	if (!nmi)
257	local64_inc(&uv_nmi_misses);
258
259	return nmi;
260	}
261
262	/* Need to reset the NMI MMR register, but only once per hub. */
263	static inline void uv_clear_nmi(int cpu)
264	{
265	struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi;
266
267	if (cpu == atomic_read(&hub_nmi->cpu_owner)) {
268	atomic_set(&hub_nmi->cpu_owner, -1);
269	atomic_set(&hub_nmi->in_nmi, 0);
270	uv_local_mmr_clear_nmi();
271	raw_spin_unlock(&hub_nmi->nmi_lock);
272	}
273	}
274
275	/* Print non-responding cpus */
276	static void uv_nmi_nr_cpus_pr(char *fmt)
277	{
278	static char cpu_list[1024];
279	int len = sizeof(cpu_list);
280	int c = cpumask_weight(uv_nmi_cpu_mask);
281	int n = cpulist_scnprintf(cpu_list, len, uv_nmi_cpu_mask);
282
283	if (n >= len-1)
284	strcpy(&cpu_list[len - 6], "...\n");
285
286	printk(fmt, c, cpu_list);
287	}
288
289	/* Ping non-responding cpus attemping to force them into the NMI handler */
290	static void uv_nmi_nr_cpus_ping(void)
291	{
292	int cpu;
293
294	for_each_cpu(cpu, uv_nmi_cpu_mask)
295	atomic_set(&uv_cpu_nmi_per(cpu).pinging, 1);
296
297	apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI);
298	}
299
300	/* Clean up flags for cpus that ignored both NMI and ping */
301	static void uv_nmi_cleanup_mask(void)
302	{
303	int cpu;
304
305	for_each_cpu(cpu, uv_nmi_cpu_mask) {
306	atomic_set(&uv_cpu_nmi_per(cpu).pinging, 0);
307	atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_OUT);
308	cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
309	}
310	}
311
312	/* Loop waiting as cpus enter nmi handler */
313	static int uv_nmi_wait_cpus(int first)
314	{
315	int i, j, k, n = num_online_cpus();
316	int last_k = 0, waiting = 0;
317
318	if (first) {
319	cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask);
320	k = 0;
321	} else {
322	k = n - cpumask_weight(uv_nmi_cpu_mask);
323	}
324
325	udelay(uv_nmi_initial_delay);
326	for (i = 0; i < uv_nmi_retry_count; i++) {
327	int loop_delay = uv_nmi_loop_delay;
328
329	for_each_cpu(j, uv_nmi_cpu_mask) {
330	if (atomic_read(&uv_cpu_nmi_per(j).state)) {
331	cpumask_clear_cpu(j, uv_nmi_cpu_mask);
332	if (++k >= n)
333	break;
334	}
335	}
336	if (k >= n) { /* all in? */
337	k = n;
338	break;
339	}
340	if (last_k != k) { /* abort if no new cpus coming in */
341	last_k = k;
342	waiting = 0;
343	} else if (++waiting > uv_nmi_wait_count)
344	break;
345
346	/* extend delay if waiting only for cpu 0 */
347	if (waiting && (n - k) == 1 &&
348	cpumask_test_cpu(0, uv_nmi_cpu_mask))
349	loop_delay *= 100;
350
351	udelay(loop_delay);
352	}
353	atomic_set(&uv_nmi_cpus_in_nmi, k);
354	return n - k;
355	}
356
357	/* Wait until all slave cpus have entered UV NMI handler */
358	static void uv_nmi_wait(int master)
359	{
360	/* indicate this cpu is in */
361	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_IN);
362
363	/* if not the first cpu in (the master), then we are a slave cpu */
364	if (!master)
365	return;
366
367	do {
368	/* wait for all other cpus to gather here */
369	if (!uv_nmi_wait_cpus(1))
370	break;
371
372	/* if not all made it in, send IPI NMI to them */
373	uv_nmi_nr_cpus_pr(KERN_ALERT
374	"UV: Sending NMI IPI to %d non-responding CPUs: %s\n");
375	uv_nmi_nr_cpus_ping();
376
377	/* if all cpus are in, then done */
378	if (!uv_nmi_wait_cpus(0))
379	break;
380
381	uv_nmi_nr_cpus_pr(KERN_ALERT
382	"UV: %d CPUs not in NMI loop: %s\n");
383	} while (0);
384
385	pr_alert("UV: %d of %d CPUs in NMI\n",
386	atomic_read(&uv_nmi_cpus_in_nmi), num_online_cpus());
387	}
388
3c121d9a MT	389	static void uv_nmi_dump_cpu_ip_hdr(void)
	390	{
	391	printk(KERN_DEFAULT
	392	"\nUV: %4s %6s %-32s %s (Note: PID 0 not listed)\n",
	393	"CPU", "PID", "COMMAND", "IP");
	394	}
	395
	396	static void uv_nmi_dump_cpu_ip(int cpu, struct pt_regs *regs)
	397	{
	398	printk(KERN_DEFAULT "UV: %4d %6d %-32.32s ",
	399	cpu, current->pid, current->comm);
	400
5f01c988	401	printk_address(regs->ip);
3c121d9a MT	402	}
3c121d9a MT	403
0d12ef0c MT	404	/* Dump this cpu's state */
	405	static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs)
	406	{
	407	const char *dots = " ................................. ";
	408
3c121d9a MT	409	if (uv_nmi_action_is("ips")) {
	410	if (cpu == 0)
	411	uv_nmi_dump_cpu_ip_hdr();
	412
	413	if (current->pid != 0)
	414	uv_nmi_dump_cpu_ip(cpu, regs);
	415
	416	} else if (uv_nmi_action_is("dump")) {
	417	printk(KERN_DEFAULT
	418	"UV:%sNMI process trace for CPU %d\n", dots, cpu);
	419	show_regs(regs);
	420	}
0d12ef0c MT	421	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE);
	422	}
	423
	424	/* Trigger a slave cpu to dump it's state */
	425	static void uv_nmi_trigger_dump(int cpu)
	426	{
	427	int retry = uv_nmi_trigger_delay;
	428
	429	if (atomic_read(&uv_cpu_nmi_per(cpu).state) != UV_NMI_STATE_IN)
	430	return;
	431
	432	atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP);
	433	do {
	434	cpu_relax();
	435	udelay(10);
	436	if (atomic_read(&uv_cpu_nmi_per(cpu).state)
	437	!= UV_NMI_STATE_DUMP)
	438	return;
	439	} while (--retry > 0);
	440
	441	pr_crit("UV: CPU %d stuck in process dump function\n", cpu);
	442	atomic_set(&uv_cpu_nmi_per(cpu).state, UV_NMI_STATE_DUMP_DONE);
	443	}
	444
	445	/* Wait until all cpus ready to exit */
	446	static void uv_nmi_sync_exit(int master)
	447	{
	448	atomic_dec(&uv_nmi_cpus_in_nmi);
	449	if (master) {
	450	while (atomic_read(&uv_nmi_cpus_in_nmi) > 0)
	451	cpu_relax();
	452	atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR);
	453	} else {
	454	while (atomic_read(&uv_nmi_slave_continue))
	455	cpu_relax();
	456	}
	457	}
	458
	459	/* Walk through cpu list and dump state of each */
	460	static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master)
	461	{
	462	if (master) {
	463	int tcpu;
	464	int ignored = 0;
	465	int saved_console_loglevel = console_loglevel;
	466
3c121d9a MT	467	pr_alert("UV: tracing %s for %d CPUs from CPU %d\n",
3c121d9a MT	468	uv_nmi_action_is("ips") ? "IPs" : "processes",
0d12ef0c MT	469	atomic_read(&uv_nmi_cpus_in_nmi), cpu);
	470
	471	console_loglevel = uv_nmi_loglevel;
	472	atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
	473	for_each_online_cpu(tcpu) {
	474	if (cpumask_test_cpu(tcpu, uv_nmi_cpu_mask))
	475	ignored++;
	476	else if (tcpu == cpu)
	477	uv_nmi_dump_state_cpu(tcpu, regs);
	478	else
	479	uv_nmi_trigger_dump(tcpu);
1e019421	480	}
0d12ef0c MT	481	if (ignored)
	482	printk(KERN_DEFAULT "UV: %d CPUs ignored NMI\n",
	483	ignored);
	484
	485	console_loglevel = saved_console_loglevel;
	486	pr_alert("UV: process trace complete\n");
	487	} else {
	488	while (!atomic_read(&uv_nmi_slave_continue))
	489	cpu_relax();
	490	while (atomic_read(&uv_cpu_nmi.state) != UV_NMI_STATE_DUMP)
	491	cpu_relax();
	492	uv_nmi_dump_state_cpu(cpu, regs);
1e019421	493	}
0d12ef0c MT	494	uv_nmi_sync_exit(master);
0d12ef0c MT	495	}
1e019421	496
0d12ef0c MT	497	static void uv_nmi_touch_watchdogs(void)
	498	{
	499	touch_softlockup_watchdog_sync();
	500	clocksource_touch_watchdog();
	501	rcu_cpu_stall_reset();
	502	touch_nmi_watchdog();
	503	}
	504
12ba6c99	505	#if defined(CONFIG_KEXEC)
74c93f9d	506	static atomic_t uv_nmi_kexec_failed;
12ba6c99 MT	507	static void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
	508	{
	509	/* Call crash to dump system state */
	510	if (master) {
	511	pr_emerg("UV: NMI executing crash_kexec on CPU%d\n", cpu);
	512	crash_kexec(regs);
	513
	514	pr_emerg("UV: crash_kexec unexpectedly returned, ");
	515	if (!kexec_crash_image) {
	516	pr_cont("crash kernel not loaded\n");
	517	atomic_set(&uv_nmi_kexec_failed, 1);
	518	uv_nmi_sync_exit(1);
	519	return;
	520	}
	521	pr_cont("kexec busy, stalling cpus while waiting\n");
	522	}
	523
	524	/* If crash exec fails the slaves should return, otherwise stall */
	525	while (atomic_read(&uv_nmi_kexec_failed) == 0)
	526	mdelay(10);
	527
	528	/* Crash kernel most likely not loaded, return in an orderly fashion */
	529	uv_nmi_sync_exit(0);
	530	}
	531
	532	#else /* !CONFIG_KEXEC */
	533	static inline void uv_nmi_kdump(int cpu, int master, struct pt_regs *regs)
	534	{
	535	if (master)
	536	pr_err("UV: NMI kdump: KEXEC not supported in this kernel\n");
	537	}
	538	#endif /* !CONFIG_KEXEC */
	539
e379ea82 MT	540	#ifdef CONFIG_KGDB_KDB
	541	/* Call KDB from NMI handler */
	542	static void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
	543	{
	544	int ret;
	545
	546	if (master) {
	547	/* call KGDB NMI handler as MASTER */
	548	ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs,
fc8b1374	549	KDB_REASON_SYSTEM_NMI, &uv_nmi_slave_continue);
e379ea82 MT	550	if (ret) {
	551	pr_alert("KDB returned error, is kgdboc set?\n");
	552	atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
	553	}
	554	} else {
	555	/* wait for KGDB signal that it's ready for slaves to enter */
	556	int sig;
	557
	558	do {
	559	cpu_relax();
	560	sig = atomic_read(&uv_nmi_slave_continue);
	561	} while (!sig);
	562
	563	/* call KGDB as slave */
	564	if (sig == SLAVE_CONTINUE)
	565	kgdb_nmicallback(cpu, regs);
	566	}
	567	uv_nmi_sync_exit(master);
	568	}
	569
	570	#else /* !CONFIG_KGDB_KDB */
	571	static inline void uv_call_kdb(int cpu, struct pt_regs *regs, int master)
	572	{
	573	pr_err("UV: NMI error: KGDB/KDB is not enabled in this kernel\n");
	574	}
	575	#endif /* !CONFIG_KGDB_KDB */
	576
0d12ef0c MT	577	/*
	578	* UV NMI handler
	579	*/
	580	int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
	581	{
	582	struct uv_hub_nmi_s *hub_nmi = uv_hub_nmi;
	583	int cpu = smp_processor_id();
	584	int master = 0;
	585	unsigned long flags;
	586
	587	local_irq_save(flags);
	588
	589	/* If not a UV System NMI, ignore */
	590	if (!atomic_read(&uv_cpu_nmi.pinging) && !uv_check_nmi(hub_nmi)) {
	591	local_irq_restore(flags);
1e019421	592	return NMI_DONE;
0d12ef0c	593	}
1e019421	594
0d12ef0c MT	595	/* Indicate we are the first CPU into the NMI handler */
0d12ef0c MT	596	master = (atomic_read(&uv_nmi_cpu) == cpu);
1e019421	597
12ba6c99 MT	598	/* If NMI action is "kdump", then attempt to do it */
	599	if (uv_nmi_action_is("kdump"))
	600	uv_nmi_kdump(cpu, master, regs);
	601
0d12ef0c MT	602	/* Pause as all cpus enter the NMI handler */
	603	uv_nmi_wait(master);
	604
	605	/* Dump state of each cpu */
3c121d9a MT	606	if (uv_nmi_action_is("ips") \|\| uv_nmi_action_is("dump"))
3c121d9a MT	607	uv_nmi_dump_state(cpu, regs, master);
0d12ef0c	608
e379ea82 MT	609	/* Call KDB if enabled */
	610	else if (uv_nmi_action_is("kdb"))
	611	uv_call_kdb(cpu, regs, master);
	612
0d12ef0c MT	613	/* Clear per_cpu "in nmi" flag */
	614	atomic_set(&uv_cpu_nmi.state, UV_NMI_STATE_OUT);
	615
	616	/* Clear MMR NMI flag on each hub */
	617	uv_clear_nmi(cpu);
	618
	619	/* Clear global flags */
	620	if (master) {
	621	if (cpumask_weight(uv_nmi_cpu_mask))
	622	uv_nmi_cleanup_mask();
	623	atomic_set(&uv_nmi_cpus_in_nmi, -1);
	624	atomic_set(&uv_nmi_cpu, -1);
	625	atomic_set(&uv_in_nmi, 0);
	626	}
	627
	628	uv_nmi_touch_watchdogs();
	629	local_irq_restore(flags);
1e019421 MT	630
	631	return NMI_HANDLED;
	632	}
	633
0d12ef0c MT	634	/*
	635	* NMI handler for pulling in CPUs when perf events are grabbing our NMI
	636	*/
74c93f9d	637	static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
0d12ef0c MT	638	{
	639	int ret;
	640
	641	uv_cpu_nmi.queries++;
	642	if (!atomic_read(&uv_cpu_nmi.pinging)) {
	643	local64_inc(&uv_nmi_ping_misses);
	644	return NMI_DONE;
	645	}
	646
	647	uv_cpu_nmi.pings++;
	648	local64_inc(&uv_nmi_ping_count);
	649	ret = uv_handle_nmi(reason, regs);
	650	atomic_set(&uv_cpu_nmi.pinging, 0);
	651	return ret;
	652	}
	653
74c93f9d	654	static void uv_register_nmi_notifier(void)
1e019421 MT	655	{
1e019421 MT	656	if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
0d12ef0c MT	657	pr_warn("UV: NMI handler failed to register\n");
	658
	659	if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping"))
	660	pr_warn("UV: PING NMI handler failed to register\n");
1e019421 MT	661	}
	662
	663	void uv_nmi_init(void)
	664	{
	665	unsigned int value;
	666
	667	/*
	668	* Unmask NMI on all cpus
	669	*/
	670	value = apic_read(APIC_LVT1) \| APIC_DM_NMI;
	671	value &= ~APIC_LVT_MASKED;
	672	apic_write(APIC_LVT1, value);
	673	}
	674
0d12ef0c MT	675	void uv_nmi_setup(void)
	676	{
	677	int size = sizeof(void ) (1 << NODES_SHIFT);
	678	int cpu, nid;
	679
	680	/* Setup hub nmi info */
	681	uv_nmi_setup_mmrs();
	682	uv_hub_nmi_list = kzalloc(size, GFP_KERNEL);
	683	pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
	684	BUG_ON(!uv_hub_nmi_list);
	685	size = sizeof(struct uv_hub_nmi_s);
	686	for_each_present_cpu(cpu) {
	687	nid = cpu_to_node(cpu);
	688	if (uv_hub_nmi_list[nid] == NULL) {
	689	uv_hub_nmi_list[nid] = kzalloc_node(size,
	690	GFP_KERNEL, nid);
	691	BUG_ON(!uv_hub_nmi_list[nid]);
	692	raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock));
	693	atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1);
	694	}
	695	uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
	696	}
8a1f4653	697	BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
74c93f9d	698	uv_register_nmi_notifier();
0d12ef0c	699	}