[mirror_ubuntu-artful-kernel.git] / arch / x86 / platform / uv / uv_time.c

/*
 * SGI RTC clock/timer routines.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 *  Copyright (c) 2009-2013 Silicon Graphics, Inc.  All Rights Reserved.
 *  Copyright (c) Dimitri Sivanich
 */
#include <linux/clockchips.h>
#include <linux/slab.h>

#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>
#include <asm/uv/bios.h>
#include <asm/uv/uv.h>
#include <asm/apic.h>
#include <asm/cpu.h>

#define RTC_NAME		"sgi_rtc"

static cycle_t uv_read_rtc(struct clocksource *cs);
static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
static void uv_rtc_timer_setup(enum clock_event_mode,
				struct clock_event_device *);

static struct clocksource clocksource_uv = {
	.name		= RTC_NAME,
	.rating		= 299,
	.read		= uv_read_rtc,
	.mask		= (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct clock_event_device clock_event_device_uv = {
	.name		= RTC_NAME,
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 20,
	.rating		= 400,
	.irq		= -1,
	.set_next_event	= uv_rtc_next_event,
	.set_mode	= uv_rtc_timer_setup,
	.event_handler	= NULL,
};

static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);

/* There is one of these allocated per node */
struct uv_rtc_timer_head {
	spinlock_t	lock;
	/* next cpu waiting for timer, local node relative: */
	int		next_cpu;
	/* number of cpus on this node: */
	int		ncpus;
	struct {
		int	lcpu;		/* systemwide logical cpu number */
		u64	expires;	/* next timer expiration for this cpu */
	} cpu[1];
};

/*
 * Access to uv_rtc_timer_head via blade id.
 */
static struct uv_rtc_timer_head		**blade_info __read_mostly;

static int				uv_rtc_evt_enable;

/*
 * Hardware interface routines
 */

/* Send IPIs to another node */
static void uv_rtc_send_IPI(int cpu)
{
	unsigned long apicid, val;
	int pnode;

	apicid = cpu_physical_id(cpu);
	pnode = uv_apicid_to_pnode(apicid);
	apicid |= uv_apicid_hibits;
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	      (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	      (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);

	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

/* Check for an RTC interrupt pending */
static int uv_intr_pending(int pnode)
{
	if (is_uv1_hub())
		return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
			UV1H_EVENT_OCCURRED0_RTC1_MASK;
	else if (is_uvx_hub())
		return uv_read_global_mmr64(pnode, UVXH_EVENT_OCCURRED2) &
			UVXH_EVENT_OCCURRED2_RTC_1_MASK;
	return 0;
}

/* Setup interrupt and return non-zero if early expiration occurred. */
static int uv_setup_intr(int cpu, u64 expires)
{
	u64 val;
	unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits;
	int pnode = uv_cpu_to_pnode(cpu);

	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
		UVH_RTC1_INT_CONFIG_M_MASK);
	uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);

	if (is_uv1_hub())
		uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
				UV1H_EVENT_OCCURRED0_RTC1_MASK);
	else
		uv_write_global_mmr64(pnode, UVXH_EVENT_OCCURRED2_ALIAS,
				UVXH_EVENT_OCCURRED2_RTC_1_MASK);

	val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
		((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);

	/* Set configuration */
	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
	/* Initialize comparator value */
	uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);

	if (uv_read_rtc(NULL) <= expires)
		return 0;

	return !uv_intr_pending(pnode);
}

/*
 * Per-cpu timer tracking routines
 */

static __init void uv_rtc_deallocate_timers(void)
{
	int bid;

	for_each_possible_blade(bid) {
		kfree(blade_info[bid]);
	}
	kfree(blade_info);
}

/* Allocate per-node list of cpu timer expiration times. */
static __init int uv_rtc_allocate_timers(void)
{
	int cpu;

	blade_info = kzalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
	if (!blade_info)
		return -ENOMEM;

	for_each_present_cpu(cpu) {
		int nid = cpu_to_node(cpu);
		int bid = uv_cpu_to_blade_id(cpu);
		int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
		struct uv_rtc_timer_head *head = blade_info[bid];

		if (!head) {
			head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
				(uv_blade_nr_possible_cpus(bid) *
					2 * sizeof(u64)),
				GFP_KERNEL, nid);
			if (!head) {
				uv_rtc_deallocate_timers();
				return -ENOMEM;
			}
			spin_lock_init(&head->lock);
			head->ncpus = uv_blade_nr_possible_cpus(bid);
			head->next_cpu = -1;
			blade_info[bid] = head;
		}

		head->cpu[bcpu].lcpu = cpu;
		head->cpu[bcpu].expires = ULLONG_MAX;
	}

	return 0;
}

/* Find and set the next expiring timer.  */
static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
{
	u64 lowest = ULLONG_MAX;
	int c, bcpu = -1;

	head->next_cpu = -1;
	for (c = 0; c < head->ncpus; c++) {
		u64 exp = head->cpu[c].expires;
		if (exp < lowest) {
			bcpu = c;
			lowest = exp;
		}
	}
	if (bcpu >= 0) {
		head->next_cpu = bcpu;
		c = head->cpu[bcpu].lcpu;
		if (uv_setup_intr(c, lowest))
			/* If we didn't set it up in time, trigger */
			uv_rtc_send_IPI(c);
	} else {
		uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
			UVH_RTC1_INT_CONFIG_M_MASK);
	}
}

/*
 * Set expiration time for current cpu.
 *
 * Returns 1 if we missed the expiration time.
 */
static int uv_rtc_set_timer(int cpu, u64 expires)
{
	int pnode = uv_cpu_to_pnode(cpu);
	int bid = uv_cpu_to_blade_id(cpu);
	struct uv_rtc_timer_head *head = blade_info[bid];
	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	u64 *t = &head->cpu[bcpu].expires;
	unsigned long flags;
	int next_cpu;

	spin_lock_irqsave(&head->lock, flags);

	next_cpu = head->next_cpu;
	*t = expires;

	/* Will this one be next to go off? */
	if (next_cpu < 0 || bcpu == next_cpu ||
			expires < head->cpu[next_cpu].expires) {
		head->next_cpu = bcpu;
		if (uv_setup_intr(cpu, expires)) {
			*t = ULLONG_MAX;
			uv_rtc_find_next_timer(head, pnode);
			spin_unlock_irqrestore(&head->lock, flags);
			return -ETIME;
		}
	}

	spin_unlock_irqrestore(&head->lock, flags);
	return 0;
}

/*
 * Unset expiration time for current cpu.
 *
 * Returns 1 if this timer was pending.
 */
static int uv_rtc_unset_timer(int cpu, int force)
{
	int pnode = uv_cpu_to_pnode(cpu);
	int bid = uv_cpu_to_blade_id(cpu);
	struct uv_rtc_timer_head *head = blade_info[bid];
	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	u64 *t = &head->cpu[bcpu].expires;
	unsigned long flags;
	int rc = 0;

	spin_lock_irqsave(&head->lock, flags);

	if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
		rc = 1;

	if (rc) {
		*t = ULLONG_MAX;
		/* Was the hardware setup for this timer? */
		if (head->next_cpu == bcpu)
			uv_rtc_find_next_timer(head, pnode);
	}

	spin_unlock_irqrestore(&head->lock, flags);

	return rc;
}


/*
 * Kernel interface routines.
 */

/*
 * Read the RTC.
 *
 * Starting with HUB rev 2.0, the UV RTC register is replicated across all
 * cachelines of it's own page.  This allows faster simultaneous reads
 * from a given socket.
 */
static cycle_t uv_read_rtc(struct clocksource *cs)
{
	unsigned long offset;

	if (uv_get_min_hub_revision_id() == 1)
		offset = 0;
	else
		offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;

	return (cycle_t)uv_read_local_mmr(UVH_RTC | offset);
}

/*
 * Program the next event, relative to now
 */
static int uv_rtc_next_event(unsigned long delta,
			     struct clock_event_device *ced)
{
	int ced_cpu = cpumask_first(ced->cpumask);

	return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
}

/*
 * Setup the RTC timer in oneshot mode
 */
static void uv_rtc_timer_setup(enum clock_event_mode mode,
			       struct clock_event_device *evt)
{
	int ced_cpu = cpumask_first(evt->cpumask);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here yet */
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		uv_rtc_unset_timer(ced_cpu, 1);
		break;
	}
}

static void uv_rtc_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);

	if (!ced || !ced->event_handler)
		return;

	if (uv_rtc_unset_timer(cpu, 0) != 1)
		return;

	ced->event_handler(ced);
}

static int __init uv_enable_evt_rtc(char *str)
{
	uv_rtc_evt_enable = 1;

	return 1;
}
__setup("uvrtcevt", uv_enable_evt_rtc);

static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
{
	struct clock_event_device *ced = this_cpu_ptr(&cpu_ced);

	*ced = clock_event_device_uv;
	ced->cpumask = cpumask_of(smp_processor_id());
	clockevents_register_device(ced);
}

static __init int uv_rtc_setup_clock(void)
{
	int rc;

	if (!is_uv_system())
		return -ENODEV;

	rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
	if (rc)
		printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
	else
		printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
			sn_rtc_cycles_per_second/(unsigned long)1E6);

	if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
		return rc;

	/* Setup and register clockevents */
	rc = uv_rtc_allocate_timers();
	if (rc)
		goto error;

	x86_platform_ipi_callback = uv_rtc_interrupt;

	clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
				NSEC_PER_SEC, clock_event_device_uv.shift);

	clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
						sn_rtc_cycles_per_second;

	clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
				(NSEC_PER_SEC / sn_rtc_cycles_per_second);

	rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
	if (rc) {
		x86_platform_ipi_callback = NULL;
		uv_rtc_deallocate_timers();
		goto error;
	}

	printk(KERN_INFO "UV RTC clockevents registered\n");

	return 0;

error:
	clocksource_unregister(&clocksource_uv);
	printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);

	return rc;
}
arch_initcall(uv_rtc_setup_clock);
Commit	Line	Data
5ab5ab34 DS	1	/*
	2	* SGI RTC clock/timer routines.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
0af63520	18	* Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
5ab5ab34 DS	19	* Copyright (c) Dimitri Sivanich
	20	*/
	21	#include <linux/clockchips.h>
5a0e3ad6	22	#include <linux/slab.h>
5ab5ab34 DS	23
	24	#include <asm/uv/uv_mmrs.h>
	25	#include <asm/uv/uv_hub.h>
	26	#include <asm/uv/bios.h>
	27	#include <asm/uv/uv.h>
1400b3fa DS	28	#include <asm/apic.h>
1400b3fa DS	29	#include <asm/cpu.h>
5ab5ab34 DS	30
	31	#define RTC_NAME "sgi_rtc"
	32
c5428e95	33	static cycle_t uv_read_rtc(struct clocksource *cs);
5ab5ab34 DS	34	static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
	35	static void uv_rtc_timer_setup(enum clock_event_mode,
	36	struct clock_event_device *);
	37
	38	static struct clocksource clocksource_uv = {
	39	.name = RTC_NAME,
b0deca2e	40	.rating = 299,
5ab5ab34 DS	41	.read = uv_read_rtc,
5ab5ab34 DS	42	.mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
5ab5ab34 DS	43	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	44	};
	45
	46	static struct clock_event_device clock_event_device_uv = {
	47	.name = RTC_NAME,
	48	.features = CLOCK_EVT_FEAT_ONESHOT,
	49	.shift = 20,
	50	.rating = 400,
	51	.irq = -1,
	52	.set_next_event = uv_rtc_next_event,
	53	.set_mode = uv_rtc_timer_setup,
	54	.event_handler = NULL,
	55	};
	56
	57	static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
	58
	59	/* There is one of these allocated per node */
	60	struct uv_rtc_timer_head {
	61	spinlock_t lock;
	62	/* next cpu waiting for timer, local node relative: */
	63	int next_cpu;
	64	/* number of cpus on this node: */
	65	int ncpus;
	66	struct {
	67	int lcpu; /* systemwide logical cpu number */
	68	u64 expires; /* next timer expiration for this cpu */
	69	} cpu[1];
	70	};
	71
	72	/*
	73	* Access to uv_rtc_timer_head via blade id.
	74	*/
	75	static struct uv_rtc_timer_head **blade_info __read_mostly;
	76
8c28de4d	77	static int uv_rtc_evt_enable;
5ab5ab34 DS	78
	79	/*
	80	* Hardware interface routines
	81	*/
	82
	83	/* Send IPIs to another node */
	84	static void uv_rtc_send_IPI(int cpu)
	85	{
	86	unsigned long apicid, val;
	87	int pnode;
	88
1400b3fa	89	apicid = cpu_physical_id(cpu);
5ab5ab34	90	pnode = uv_apicid_to_pnode(apicid);
8191c9f6	91	apicid \|= uv_apicid_hibits;
5ab5ab34 DS	92	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
5ab5ab34 DS	93	(apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
4a4de9c7	94	(X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
5ab5ab34 DS	95
	96	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	97	}
	98
	99	/* Check for an RTC interrupt pending */
	100	static int uv_intr_pending(int pnode)
	101	{
2a919596 JS	102	if (is_uv1_hub())
	103	return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
	104	UV1H_EVENT_OCCURRED0_RTC1_MASK;
0af63520 MT	105	else if (is_uvx_hub())
	106	return uv_read_global_mmr64(pnode, UVXH_EVENT_OCCURRED2) &
	107	UVXH_EVENT_OCCURRED2_RTC_1_MASK;
	108	return 0;
5ab5ab34 DS	109	}
	110
	111	/* Setup interrupt and return non-zero if early expiration occurred. */
	112	static int uv_setup_intr(int cpu, u64 expires)
	113	{
	114	u64 val;
8191c9f6	115	unsigned long apicid = cpu_physical_id(cpu) \| uv_apicid_hibits;
5ab5ab34 DS	116	int pnode = uv_cpu_to_pnode(cpu);
	117
	118	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
	119	UVH_RTC1_INT_CONFIG_M_MASK);
	120	uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
	121
2a919596 JS	122	if (is_uv1_hub())
	123	uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
	124	UV1H_EVENT_OCCURRED0_RTC1_MASK);
	125	else
0af63520 MT	126	uv_write_global_mmr64(pnode, UVXH_EVENT_OCCURRED2_ALIAS,
0af63520 MT	127	UVXH_EVENT_OCCURRED2_RTC_1_MASK);
5ab5ab34	128
4a4de9c7	129	val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) \|
8191c9f6	130	((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
5ab5ab34 DS	131
	132	/* Set configuration */
	133	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
	134	/* Initialize comparator value */
	135	uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
	136
e47938b1 DS	137	if (uv_read_rtc(NULL) <= expires)
	138	return 0;
	139
	140	return !uv_intr_pending(pnode);
5ab5ab34 DS	141	}
	142
	143	/*
	144	* Per-cpu timer tracking routines
	145	*/
	146
	147	static __init void uv_rtc_deallocate_timers(void)
	148	{
	149	int bid;
	150
	151	for_each_possible_blade(bid) {
	152	kfree(blade_info[bid]);
	153	}
	154	kfree(blade_info);
	155	}
	156
	157	/* Allocate per-node list of cpu timer expiration times. */
	158	static __init int uv_rtc_allocate_timers(void)
	159	{
	160	int cpu;
	161
e87b686b	162	blade_info = kzalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
5ab5ab34 DS	163	if (!blade_info)
5ab5ab34 DS	164	return -ENOMEM;
5ab5ab34 DS	165
	166	for_each_present_cpu(cpu) {
	167	int nid = cpu_to_node(cpu);
	168	int bid = uv_cpu_to_blade_id(cpu);
	169	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	170	struct uv_rtc_timer_head *head = blade_info[bid];
	171
	172	if (!head) {
	173	head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
	174	(uv_blade_nr_possible_cpus(bid) *
	175	2 * sizeof(u64)),
	176	GFP_KERNEL, nid);
	177	if (!head) {
	178	uv_rtc_deallocate_timers();
	179	return -ENOMEM;
	180	}
	181	spin_lock_init(&head->lock);
	182	head->ncpus = uv_blade_nr_possible_cpus(bid);
	183	head->next_cpu = -1;
	184	blade_info[bid] = head;
	185	}
	186
	187	head->cpu[bcpu].lcpu = cpu;
	188	head->cpu[bcpu].expires = ULLONG_MAX;
	189	}
	190
	191	return 0;
	192	}
	193
	194	/* Find and set the next expiring timer. */
	195	static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
	196	{
	197	u64 lowest = ULLONG_MAX;
	198	int c, bcpu = -1;
	199
	200	head->next_cpu = -1;
	201	for (c = 0; c < head->ncpus; c++) {
	202	u64 exp = head->cpu[c].expires;
	203	if (exp < lowest) {
	204	bcpu = c;
	205	lowest = exp;
	206	}
	207	}
	208	if (bcpu >= 0) {
	209	head->next_cpu = bcpu;
	210	c = head->cpu[bcpu].lcpu;
	211	if (uv_setup_intr(c, lowest))
	212	/* If we didn't set it up in time, trigger */
	213	uv_rtc_send_IPI(c);
	214	} else {
	215	uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
	216	UVH_RTC1_INT_CONFIG_M_MASK);
	217	}
	218	}
	219
	220	/*
	221	* Set expiration time for current cpu.
	222	*
	223	* Returns 1 if we missed the expiration time.
	224	*/
	225	static int uv_rtc_set_timer(int cpu, u64 expires)
	226	{
	227	int pnode = uv_cpu_to_pnode(cpu);
	228	int bid = uv_cpu_to_blade_id(cpu);
229	struct uv_rtc_timer_head *head = blade_info[bid];
230	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
231	u64 *t = &head->cpu[bcpu].expires;
232	unsigned long flags;
233	int next_cpu;
234
235	spin_lock_irqsave(&head->lock, flags);
236
237	next_cpu = head->next_cpu;
238	*t = expires;
e47938b1	239
5ab5ab34 DS	240	/* Will this one be next to go off? */
	241	if (next_cpu < 0 \|\| bcpu == next_cpu \|\|
	242	expires < head->cpu[next_cpu].expires) {
	243	head->next_cpu = bcpu;
	244	if (uv_setup_intr(cpu, expires)) {
	245	*t = ULLONG_MAX;
	246	uv_rtc_find_next_timer(head, pnode);
	247	spin_unlock_irqrestore(&head->lock, flags);
e47938b1	248	return -ETIME;
5ab5ab34 DS	249	}
	250	}
	251
	252	spin_unlock_irqrestore(&head->lock, flags);
	253	return 0;
	254	}
	255
	256	/*
	257	* Unset expiration time for current cpu.
	258	*
	259	* Returns 1 if this timer was pending.
	260	*/
e47938b1	261	static int uv_rtc_unset_timer(int cpu, int force)
5ab5ab34 DS	262	{
	263	int pnode = uv_cpu_to_pnode(cpu);
	264	int bid = uv_cpu_to_blade_id(cpu);
	265	struct uv_rtc_timer_head *head = blade_info[bid];
	266	int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
	267	u64 *t = &head->cpu[bcpu].expires;
	268	unsigned long flags;
	269	int rc = 0;
	270
	271	spin_lock_irqsave(&head->lock, flags);
	272
e47938b1	273	if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) \|\| force)
5ab5ab34 DS	274	rc = 1;
5ab5ab34 DS	275
e47938b1 DS	276	if (rc) {
	277	*t = ULLONG_MAX;
	278	/* Was the hardware setup for this timer? */
	279	if (head->next_cpu == bcpu)
	280	uv_rtc_find_next_timer(head, pnode);
	281	}
5ab5ab34 DS	282
	283	spin_unlock_irqrestore(&head->lock, flags);
	284
	285	return rc;
	286	}
	287
	288
	289	/*
	290	* Kernel interface routines.
	291	*/
	292
	293	/*
	294	* Read the RTC.
aca3bb59 DS	295	*
	296	* Starting with HUB rev 2.0, the UV RTC register is replicated across all
	297	* cachelines of it's own page. This allows faster simultaneous reads
	298	* from a given socket.
5ab5ab34	299	*/
c5428e95	300	static cycle_t uv_read_rtc(struct clocksource *cs)
5ab5ab34	301	{
aca3bb59 DS	302	unsigned long offset;
	303
	304	if (uv_get_min_hub_revision_id() == 1)
	305	offset = 0;
	306	else
	307	offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
	308
	309	return (cycle_t)uv_read_local_mmr(UVH_RTC \| offset);
5ab5ab34 DS	310	}
	311
	312	/*
	313	* Program the next event, relative to now
	314	*/
	315	static int uv_rtc_next_event(unsigned long delta,
	316	struct clock_event_device *ced)
	317	{
	318	int ced_cpu = cpumask_first(ced->cpumask);
	319
c5428e95	320	return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
5ab5ab34 DS	321	}
	322
	323	/*
	324	* Setup the RTC timer in oneshot mode
	325	*/
	326	static void uv_rtc_timer_setup(enum clock_event_mode mode,
	327	struct clock_event_device *evt)
	328	{
	329	int ced_cpu = cpumask_first(evt->cpumask);
	330
	331	switch (mode) {
	332	case CLOCK_EVT_MODE_PERIODIC:
	333	case CLOCK_EVT_MODE_ONESHOT:
	334	case CLOCK_EVT_MODE_RESUME:
	335	/* Nothing to do here yet */
	336	break;
	337	case CLOCK_EVT_MODE_UNUSED:
	338	case CLOCK_EVT_MODE_SHUTDOWN:
e47938b1	339	uv_rtc_unset_timer(ced_cpu, 1);
5ab5ab34 DS	340	break;
	341	}
	342	}
	343
	344	static void uv_rtc_interrupt(void)
	345	{
5ab5ab34	346	int cpu = smp_processor_id();
e47938b1	347	struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
5ab5ab34 DS	348
	349	if (!ced \|\| !ced->event_handler)
	350	return;
	351
e47938b1	352	if (uv_rtc_unset_timer(cpu, 0) != 1)
5ab5ab34 DS	353	return;
	354
	355	ced->event_handler(ced);
	356	}
	357
8c28de4d DS	358	static int __init uv_enable_evt_rtc(char *str)
	359	{
	360	uv_rtc_evt_enable = 1;
	361
	362	return 1;
	363	}
	364	__setup("uvrtcevt", uv_enable_evt_rtc);
	365
5ab5ab34 DS	366	static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
5ab5ab34 DS	367	{
89cbc767	368	struct clock_event_device *ced = this_cpu_ptr(&cpu_ced);
5ab5ab34 DS	369
	370	*ced = clock_event_device_uv;
	371	ced->cpumask = cpumask_of(smp_processor_id());
	372	clockevents_register_device(ced);
	373	}
	374
	375	static __init int uv_rtc_setup_clock(void)
	376	{
	377	int rc;
	378
581f202b	379	if (!is_uv_system())
5ab5ab34 DS	380	return -ENODEV;
5ab5ab34 DS	381
b01cc1b0	382	rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
8c28de4d DS	383	if (rc)
	384	printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
	385	else
	386	printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
	387	sn_rtc_cycles_per_second/(unsigned long)1E6);
	388
581f202b	389	if (rc \|\| !uv_rtc_evt_enable \|\| x86_platform_ipi_callback)
5ab5ab34	390	return rc;
8c28de4d	391
5ab5ab34 DS	392	/* Setup and register clockevents */
5ab5ab34 DS	393	rc = uv_rtc_allocate_timers();
d5991ff2 DS	394	if (rc)
	395	goto error;
	396
4a4de9c7	397	x86_platform_ipi_callback = uv_rtc_interrupt;
5ab5ab34 DS	398
	399	clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
	400	NSEC_PER_SEC, clock_event_device_uv.shift);
	401
	402	clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
	403	sn_rtc_cycles_per_second;
	404
	405	clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
	406	(NSEC_PER_SEC / sn_rtc_cycles_per_second);
	407
	408	rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
	409	if (rc) {
4a4de9c7	410	x86_platform_ipi_callback = NULL;
5ab5ab34	411	uv_rtc_deallocate_timers();
d5991ff2	412	goto error;
5ab5ab34 DS	413	}
5ab5ab34 DS	414
d5991ff2 DS	415	printk(KERN_INFO "UV RTC clockevents registered\n");
	416
	417	return 0;
	418
	419	error:
	420	clocksource_unregister(&clocksource_uv);
	421	printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
	422
5ab5ab34 DS	423	return rc;
	424	}
	425	arch_initcall(uv_rtc_setup_clock);