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1da177e4 | 1 | /* |
6d48becd | 2 | * Suspend support specific for i386/x86-64. |
1da177e4 LT |
3 | * |
4 | * Distribute under GPLv2 | |
5 | * | |
cf7700fe | 6 | * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl> |
a2531293 | 7 | * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz> |
1da177e4 LT |
8 | * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> |
9 | */ | |
10 | ||
1da177e4 | 11 | #include <linux/suspend.h> |
69c60c88 | 12 | #include <linux/export.h> |
f6783d20 | 13 | #include <linux/smp.h> |
1d9d8639 | 14 | #include <linux/perf_event.h> |
f6783d20 | 15 | |
3dd08325 | 16 | #include <asm/pgtable.h> |
f6783d20 | 17 | #include <asm/proto.h> |
3ebad590 | 18 | #include <asm/mtrr.h> |
f6783d20 SL |
19 | #include <asm/page.h> |
20 | #include <asm/mce.h> | |
a8af7898 | 21 | #include <asm/suspend.h> |
1e350066 | 22 | #include <asm/debugreg.h> |
a71c8bc5 | 23 | #include <asm/cpu.h> |
1da177e4 | 24 | |
833b2ca0 | 25 | #ifdef CONFIG_X86_32 |
d6efc2f7 AK |
26 | __visible unsigned long saved_context_ebx; |
27 | __visible unsigned long saved_context_esp, saved_context_ebp; | |
28 | __visible unsigned long saved_context_esi, saved_context_edi; | |
29 | __visible unsigned long saved_context_eflags; | |
833b2ca0 | 30 | #endif |
cc456c4e | 31 | struct saved_context saved_context; |
1da177e4 | 32 | |
5c9c9bec RW |
33 | /** |
34 | * __save_processor_state - save CPU registers before creating a | |
35 | * hibernation image and before restoring the memory state from it | |
36 | * @ctxt - structure to store the registers contents in | |
37 | * | |
38 | * NOTE: If there is a CPU register the modification of which by the | |
39 | * boot kernel (ie. the kernel used for loading the hibernation image) | |
40 | * might affect the operations of the restored target kernel (ie. the one | |
41 | * saved in the hibernation image), then its contents must be saved by this | |
42 | * function. In other words, if kernel A is hibernated and different | |
43 | * kernel B is used for loading the hibernation image into memory, the | |
44 | * kernel A's __save_processor_state() function must save all registers | |
45 | * needed by kernel A, so that it can operate correctly after the resume | |
46 | * regardless of what kernel B does in the meantime. | |
47 | */ | |
cae45957 | 48 | static void __save_processor_state(struct saved_context *ctxt) |
1da177e4 | 49 | { |
f9ebbe53 SL |
50 | #ifdef CONFIG_X86_32 |
51 | mtrr_save_fixed_ranges(NULL); | |
52 | #endif | |
1da177e4 LT |
53 | kernel_fpu_begin(); |
54 | ||
55 | /* | |
56 | * descriptor tables | |
57 | */ | |
f9ebbe53 | 58 | #ifdef CONFIG_X86_32 |
f9ebbe53 SL |
59 | store_idt(&ctxt->idt); |
60 | #else | |
61 | /* CONFIG_X86_64 */ | |
9d1c6e7c | 62 | store_idt((struct desc_ptr *)&ctxt->idt_limit); |
f9ebbe53 | 63 | #endif |
cc456c4e KRW |
64 | /* |
65 | * We save it here, but restore it only in the hibernate case. | |
66 | * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit | |
67 | * mode in "secondary_startup_64". In 32-bit mode it is done via | |
68 | * 'pmode_gdt' in wakeup_start. | |
69 | */ | |
70 | ctxt->gdt_desc.size = GDT_SIZE - 1; | |
71 | ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id()); | |
72 | ||
9d1c6e7c | 73 | store_tr(ctxt->tr); |
1da177e4 LT |
74 | |
75 | /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ | |
1da177e4 LT |
76 | /* |
77 | * segment registers | |
78 | */ | |
f9ebbe53 SL |
79 | #ifdef CONFIG_X86_32 |
80 | savesegment(es, ctxt->es); | |
81 | savesegment(fs, ctxt->fs); | |
82 | savesegment(gs, ctxt->gs); | |
83 | savesegment(ss, ctxt->ss); | |
84 | #else | |
85 | /* CONFIG_X86_64 */ | |
1da177e4 LT |
86 | asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); |
87 | asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); | |
88 | asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); | |
89 | asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); | |
90 | asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); | |
91 | ||
92 | rdmsrl(MSR_FS_BASE, ctxt->fs_base); | |
93 | rdmsrl(MSR_GS_BASE, ctxt->gs_base); | |
94 | rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); | |
3ebad590 | 95 | mtrr_save_fixed_ranges(NULL); |
1da177e4 | 96 | |
f9ebbe53 SL |
97 | rdmsrl(MSR_EFER, ctxt->efer); |
98 | #endif | |
99 | ||
1da177e4 | 100 | /* |
cf7700fe | 101 | * control registers |
1da177e4 | 102 | */ |
f51c9452 GOC |
103 | ctxt->cr0 = read_cr0(); |
104 | ctxt->cr2 = read_cr2(); | |
105 | ctxt->cr3 = read_cr3(); | |
1e02ce4c AL |
106 | ctxt->cr4 = __read_cr4_safe(); |
107 | #ifdef CONFIG_X86_64 | |
f51c9452 | 108 | ctxt->cr8 = read_cr8(); |
f9ebbe53 | 109 | #endif |
85a0e753 OZ |
110 | ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, |
111 | &ctxt->misc_enable); | |
1da177e4 LT |
112 | } |
113 | ||
f9ebbe53 | 114 | /* Needed by apm.c */ |
1da177e4 LT |
115 | void save_processor_state(void) |
116 | { | |
117 | __save_processor_state(&saved_context); | |
b74f05d6 | 118 | x86_platform.save_sched_clock_state(); |
1da177e4 | 119 | } |
f9ebbe53 SL |
120 | #ifdef CONFIG_X86_32 |
121 | EXPORT_SYMBOL(save_processor_state); | |
122 | #endif | |
1da177e4 | 123 | |
08967f94 | 124 | static void do_fpu_end(void) |
1da177e4 | 125 | { |
08967f94 | 126 | /* |
3134d04b | 127 | * Restore FPU regs if necessary. |
08967f94 SL |
128 | */ |
129 | kernel_fpu_end(); | |
1da177e4 LT |
130 | } |
131 | ||
3134d04b SL |
132 | static void fix_processor_context(void) |
133 | { | |
134 | int cpu = smp_processor_id(); | |
24933b82 | 135 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
4d681be3 | 136 | #ifdef CONFIG_X86_64 |
137 | struct desc_struct *desc = get_cpu_gdt_table(cpu); | |
138 | tss_desc tss; | |
139 | #endif | |
3134d04b SL |
140 | set_tss_desc(cpu, t); /* |
141 | * This just modifies memory; should not be | |
142 | * necessary. But... This is necessary, because | |
143 | * 386 hardware has concept of busy TSS or some | |
144 | * similar stupidity. | |
145 | */ | |
146 | ||
147 | #ifdef CONFIG_X86_64 | |
4d681be3 | 148 | memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc)); |
149 | tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */ | |
150 | write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS); | |
3134d04b SL |
151 | |
152 | syscall_init(); /* This sets MSR_*STAR and related */ | |
153 | #endif | |
154 | load_TR_desc(); /* This does ltr */ | |
155 | load_LDT(¤t->active_mm->context); /* This does lldt */ | |
9254aaa0 IM |
156 | |
157 | fpu__resume_cpu(); | |
3134d04b SL |
158 | } |
159 | ||
5c9c9bec RW |
160 | /** |
161 | * __restore_processor_state - restore the contents of CPU registers saved | |
162 | * by __save_processor_state() | |
163 | * @ctxt - structure to load the registers contents from | |
164 | */ | |
b8f99b3e | 165 | static void notrace __restore_processor_state(struct saved_context *ctxt) |
1da177e4 | 166 | { |
85a0e753 OZ |
167 | if (ctxt->misc_enable_saved) |
168 | wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); | |
1da177e4 LT |
169 | /* |
170 | * control registers | |
171 | */ | |
3134d04b SL |
172 | /* cr4 was introduced in the Pentium CPU */ |
173 | #ifdef CONFIG_X86_32 | |
174 | if (ctxt->cr4) | |
1e02ce4c | 175 | __write_cr4(ctxt->cr4); |
3134d04b SL |
176 | #else |
177 | /* CONFIG X86_64 */ | |
3c321bce | 178 | wrmsrl(MSR_EFER, ctxt->efer); |
f51c9452 | 179 | write_cr8(ctxt->cr8); |
1e02ce4c | 180 | __write_cr4(ctxt->cr4); |
3134d04b | 181 | #endif |
f51c9452 GOC |
182 | write_cr3(ctxt->cr3); |
183 | write_cr2(ctxt->cr2); | |
184 | write_cr0(ctxt->cr0); | |
1da177e4 | 185 | |
8d783b3e PM |
186 | /* |
187 | * now restore the descriptor tables to their proper values | |
188 | * ltr is done i fix_processor_context(). | |
189 | */ | |
3134d04b | 190 | #ifdef CONFIG_X86_32 |
3134d04b SL |
191 | load_idt(&ctxt->idt); |
192 | #else | |
193 | /* CONFIG_X86_64 */ | |
9d1c6e7c | 194 | load_idt((const struct desc_ptr *)&ctxt->idt_limit); |
3134d04b | 195 | #endif |
8d783b3e | 196 | |
1da177e4 LT |
197 | /* |
198 | * segment registers | |
199 | */ | |
3134d04b SL |
200 | #ifdef CONFIG_X86_32 |
201 | loadsegment(es, ctxt->es); | |
202 | loadsegment(fs, ctxt->fs); | |
203 | loadsegment(gs, ctxt->gs); | |
204 | loadsegment(ss, ctxt->ss); | |
205 | ||
206 | /* | |
207 | * sysenter MSRs | |
208 | */ | |
209 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
210 | enable_sep_cpu(); | |
211 | #else | |
212 | /* CONFIG_X86_64 */ | |
1da177e4 LT |
213 | asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); |
214 | asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); | |
215 | asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); | |
216 | load_gs_index(ctxt->gs); | |
217 | asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); | |
218 | ||
219 | wrmsrl(MSR_FS_BASE, ctxt->fs_base); | |
220 | wrmsrl(MSR_GS_BASE, ctxt->gs_base); | |
221 | wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); | |
3134d04b | 222 | #endif |
1da177e4 | 223 | |
1da177e4 LT |
224 | fix_processor_context(); |
225 | ||
226 | do_fpu_end(); | |
dba69d10 | 227 | x86_platform.restore_sched_clock_state(); |
d0af9eed | 228 | mtrr_bp_restore(); |
1d9d8639 | 229 | perf_restore_debug_store(); |
1da177e4 LT |
230 | } |
231 | ||
3134d04b | 232 | /* Needed by apm.c */ |
b8f99b3e | 233 | void notrace restore_processor_state(void) |
1da177e4 LT |
234 | { |
235 | __restore_processor_state(&saved_context); | |
236 | } | |
3134d04b SL |
237 | #ifdef CONFIG_X86_32 |
238 | EXPORT_SYMBOL(restore_processor_state); | |
239 | #endif | |
209efae1 FY |
240 | |
241 | /* | |
242 | * When bsp_check() is called in hibernate and suspend, cpu hotplug | |
243 | * is disabled already. So it's unnessary to handle race condition between | |
244 | * cpumask query and cpu hotplug. | |
245 | */ | |
246 | static int bsp_check(void) | |
247 | { | |
248 | if (cpumask_first(cpu_online_mask) != 0) { | |
249 | pr_warn("CPU0 is offline.\n"); | |
250 | return -ENODEV; | |
251 | } | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | static int bsp_pm_callback(struct notifier_block *nb, unsigned long action, | |
257 | void *ptr) | |
258 | { | |
259 | int ret = 0; | |
260 | ||
261 | switch (action) { | |
262 | case PM_SUSPEND_PREPARE: | |
263 | case PM_HIBERNATION_PREPARE: | |
264 | ret = bsp_check(); | |
265 | break; | |
a71c8bc5 FY |
266 | #ifdef CONFIG_DEBUG_HOTPLUG_CPU0 |
267 | case PM_RESTORE_PREPARE: | |
268 | /* | |
269 | * When system resumes from hibernation, online CPU0 because | |
270 | * 1. it's required for resume and | |
271 | * 2. the CPU was online before hibernation | |
272 | */ | |
273 | if (!cpu_online(0)) | |
274 | _debug_hotplug_cpu(0, 1); | |
275 | break; | |
276 | case PM_POST_RESTORE: | |
277 | /* | |
278 | * When a resume really happens, this code won't be called. | |
279 | * | |
280 | * This code is called only when user space hibernation software | |
281 | * prepares for snapshot device during boot time. So we just | |
282 | * call _debug_hotplug_cpu() to restore to CPU0's state prior to | |
283 | * preparing the snapshot device. | |
284 | * | |
285 | * This works for normal boot case in our CPU0 hotplug debug | |
286 | * mode, i.e. CPU0 is offline and user mode hibernation | |
287 | * software initializes during boot time. | |
288 | * | |
289 | * If CPU0 is online and user application accesses snapshot | |
290 | * device after boot time, this will offline CPU0 and user may | |
291 | * see different CPU0 state before and after accessing | |
292 | * the snapshot device. But hopefully this is not a case when | |
293 | * user debugging CPU0 hotplug. Even if users hit this case, | |
294 | * they can easily online CPU0 back. | |
295 | * | |
296 | * To simplify this debug code, we only consider normal boot | |
297 | * case. Otherwise we need to remember CPU0's state and restore | |
298 | * to that state and resolve racy conditions etc. | |
299 | */ | |
300 | _debug_hotplug_cpu(0, 0); | |
301 | break; | |
302 | #endif | |
209efae1 FY |
303 | default: |
304 | break; | |
305 | } | |
306 | return notifier_from_errno(ret); | |
307 | } | |
308 | ||
309 | static int __init bsp_pm_check_init(void) | |
310 | { | |
311 | /* | |
312 | * Set this bsp_pm_callback as lower priority than | |
313 | * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called | |
314 | * earlier to disable cpu hotplug before bsp online check. | |
315 | */ | |
316 | pm_notifier(bsp_pm_callback, -INT_MAX); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | core_initcall(bsp_pm_check_init); |