[mirror_ubuntu-bionic-kernel.git] / arch / x86_64 / kernel / head.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *
 *  $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/desc.h>
#include <asm/segment.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>
	
/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
 * because we need identity-mapped pages on setup so define __START_KERNEL to
 * 0x100000 for this stage
 * 
 */

	.text
	.section .bootstrap.text
	.code32
	.globl startup_32
/* %bx:	 1 if coming from smp trampoline on secondary cpu */ 
startup_32:
	
	/*
	 * At this point the CPU runs in 32bit protected mode (CS.D = 1) with
	 * paging disabled and the point of this file is to switch to 64bit
	 * long mode with a kernel mapping for kerneland to jump into the
	 * kernel virtual addresses.
 	 * There is no stack until we set one up.
	 */

	/* Initialize the %ds segment register */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds

	/* Load new GDT with the 64bit segments using 32bit descriptor */
	lgdt	pGDT32 - __START_KERNEL_map

	/* If the CPU doesn't support CPUID this will double fault.
	 * Unfortunately it is hard to check for CPUID without a stack. 
	 */
	
	/* Check if extended functions are implemented */		
	movl	$0x80000000, %eax
	cpuid
	cmpl	$0x80000000, %eax
	jbe	no_long_mode
	/* Check if long mode is implemented */
	mov	$0x80000001, %eax
	cpuid
	btl	$29, %edx
	jnc	no_long_mode

	/*
	 * Prepare for entering 64bits mode
	 */

	/* Enable PAE mode */
	xorl	%eax, %eax
	btsl	$5, %eax
	movl	%eax, %cr4

	/* Setup early boot stage 4 level pagetables */
	movl	$(boot_level4_pgt - __START_KERNEL_map), %eax
	movl	%eax, %cr3

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr

	/* Enable Long Mode */
	btsl	$_EFER_LME, %eax
				
	/* Make changes effective */
	wrmsr

	xorl	%eax, %eax
	btsl	$31, %eax			/* Enable paging and in turn activate Long Mode */
	btsl	$0, %eax			/* Enable protected mode */
	/* Make changes effective */
	movl	%eax, %cr0
	/*
	 * At this point we're in long mode but in 32bit compatibility mode
	 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
	 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
	 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
	 */
	ljmp	$__KERNEL_CS, $(startup_64 - __START_KERNEL_map)

	.code64
	.org 0x100	
	.globl startup_64
startup_64:
	/* We come here either from startup_32
	 * or directly from a 64bit bootloader.
	 * Since we may have come directly from a bootloader we
	 * reload the page tables here.
	 */

	/* Enable PAE mode and PGE */
	xorq	%rax, %rax
	btsq	$5, %rax
	btsq	$7, %rax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(boot_level4_pgt - __START_KERNEL_map), %rax
	movq	%rax, %cr3

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr

	/* Enable System Call */
	btsl	$_EFER_SCE, %eax

	/* No Execute supported? */
	btl	$20,%edi
	jnc     1f
	btsl	$_EFER_NX, %eax
1:
	/* Make changes effective */
	wrmsr

	/* Setup cr0 */
#define CR0_PM				1		/* protected mode */
#define CR0_MP				(1<<1)
#define CR0_ET				(1<<4)
#define CR0_NE				(1<<5)
#define CR0_WP				(1<<16)
#define CR0_AM				(1<<18)
#define CR0_PAGING 			(1<<31)
	movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq init_rsp(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	cpu_gdt_descr

	/* 
	 * Setup up a dummy PDA. this is just for some early bootup code
	 * that does in_interrupt() 
	 */ 
	movl	$MSR_GS_BASE,%ecx
	movq	$empty_zero_page,%rax
	movq    %rax,%rdx
	shrq	$32,%rdx
	wrmsr	

	/* set up data segments. actually 0 would do too */
	movl $__KERNEL_DS,%eax
	movl %eax,%ds	
	movl %eax,%ss
	movl %eax,%es
			
	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address , this is only possible as indirect
	 * jump
	 */
	movq	initial_code(%rip),%rax
	jmp	*%rax

	/* SMP bootup changes these two */
	.align	8
	.globl	initial_code
initial_code:
	.quad	x86_64_start_kernel
	.globl init_rsp
init_rsp:
	.quad  init_thread_union+THREAD_SIZE-8

ENTRY(early_idt_handler)
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)
	xorl %eax,%eax
	movq 8(%rsp),%rsi	# get rip
	movq (%rsp),%rdx
	movq %cr2,%rcx
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
#ifdef CONFIG_KALLSYMS	
	leaq early_idt_ripmsg(%rip),%rdi
	movq 8(%rsp),%rsi	# get rip again
	call __print_symbol
#endif
1:	hlt
	jmp 1b
early_recursion_flag:
	.long 0

early_idt_msg:
	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
early_idt_ripmsg:
	.asciz "RIP %s\n"

.code32
ENTRY(no_long_mode)
	/* This isn't an x86-64 CPU so hang */
1:
	jmp	1b

.org 0xf00
	.globl pGDT32
pGDT32:
	.word	gdt_end-cpu_gdt_table-1
	.long	cpu_gdt_table-__START_KERNEL_map

.org 0xf10	
ljumpvector:
	.long	startup_64-__START_KERNEL_map
	.word	__KERNEL_CS

ENTRY(stext)
ENTRY(_stext)

	$page = 0
#define NEXT_PAGE(name) \
	$page = $page + 1; \
	.org $page * 0x1000; \
	phys_/**/name = $page * 0x1000 + __PHYSICAL_START; \
ENTRY(name)

NEXT_PAGE(init_level4_pgt)
	/* This gets initialized in x86_64_start_kernel */
	.fill	512,8,0

NEXT_PAGE(level3_ident_pgt)
	.quad	phys_level2_ident_pgt | 0x007
	.fill	511,8,0

NEXT_PAGE(level3_kernel_pgt)
	.fill	510,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	phys_level2_kernel_pgt | 0x007
	.fill	1,8,0

NEXT_PAGE(level2_ident_pgt)
	/* 40MB for bootup. 	*/
	i = 0
	.rept 20
	.quad	i << 21 | 0x083
	i = i + 1
	.endr
	/* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
	.globl temp_boot_pmds
temp_boot_pmds:
	.fill	492,8,0
	
NEXT_PAGE(level2_kernel_pgt)
	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	   When you change this change KERNEL_TEXT_SIZE in page.h too. */
	/* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
	i = 0
	.rept 20
	.quad	i << 21 | 0x183
	i = i + 1
	.endr
	/* Module mapping starts here */
	.fill	492,8,0

NEXT_PAGE(level3_physmem_pgt)
	.quad	phys_level2_kernel_pgt | 0x007	/* so that __va works even before pagetable_init */
	.fill	511,8,0

#undef NEXT_PAGE

	.data

#ifdef CONFIG_ACPI_SLEEP
	.align PAGE_SIZE
ENTRY(wakeup_level4_pgt)
	.quad	phys_level3_ident_pgt | 0x007
	.fill	255,8,0
	.quad	phys_level3_physmem_pgt | 0x007
	.fill	254,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	phys_level3_kernel_pgt | 0x007
#endif

#ifndef CONFIG_HOTPLUG_CPU
	__INITDATA
#endif
	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
	.align PAGE_SIZE
ENTRY(boot_level4_pgt)
	.quad	phys_level3_ident_pgt | 0x007
	.fill	255,8,0
	.quad	phys_level3_physmem_pgt | 0x007
	.fill	254,8,0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	phys_level3_kernel_pgt | 0x007

	.data

	.align 16
	.globl cpu_gdt_descr
cpu_gdt_descr:
	.word	gdt_end-cpu_gdt_table-1
gdt:
	.quad	cpu_gdt_table
#ifdef CONFIG_SMP
	.rept	NR_CPUS-1
	.word	0
	.quad	0
	.endr
#endif

/* We need valid kernel segments for data and code in long mode too
 * IRET will check the segment types  kkeil 2000/10/28
 * Also sysret mandates a special GDT layout 
 */
		 		
	.section .data.page_aligned, "aw"
	.align PAGE_SIZE

/* The TLS descriptors are currently at a different place compared to i386.
   Hopefully nobody expects them at a fixed place (Wine?) */
	
ENTRY(cpu_gdt_table)
	.quad	0x0000000000000000	/* NULL descriptor */
	.quad	0x0			/* unused */
	.quad	0x00af9a000000ffff	/* __KERNEL_CS */
	.quad	0x00cf92000000ffff	/* __KERNEL_DS */
	.quad	0x00cffa000000ffff	/* __USER32_CS */
	.quad	0x00cff2000000ffff	/* __USER_DS, __USER32_DS  */		
	.quad	0x00affa000000ffff	/* __USER_CS */
	.quad	0x00cf9a000000ffff	/* __KERNEL32_CS */
	.quad	0,0			/* TSS */
	.quad	0,0			/* LDT */
	.quad   0,0,0			/* three TLS descriptors */ 
	.quad	0			/* unused */
gdt_end:	
	/* asm/segment.h:GDT_ENTRIES must match this */	
	/* This should be a multiple of the cache line size */
	/* GDTs of other CPUs are now dynamically allocated */

	/* zero the remaining page */
	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0

	.section .bss, "aw", @nobits
	.align L1_CACHE_BYTES
ENTRY(idt_table)
	.skip 256 * 16

	.section .bss.page_aligned, "aw", @nobits
	.align PAGE_SIZE
ENTRY(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
	8	*
	9	* $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
	10	*/
	11
	12
	13	#include <linux/linkage.h>
	14	#include <linux/threads.h>
f6c2e333	15	#include <linux/init.h>
1da177e4 LT	16	#include <asm/desc.h>
	17	#include <asm/segment.h>
	18	#include <asm/page.h>
	19	#include <asm/msr.h>
	20	#include <asm/cache.h>
	21
	22	/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
	23	* because we need identity-mapped pages on setup so define __START_KERNEL to
	24	* 0x100000 for this stage
	25	*
	26	*/
	27
	28	.text
eaeae0cc	29	.section .bootstrap.text
1da177e4 LT	30	.code32
	31	.globl startup_32
	32	/* %bx: 1 if coming from smp trampoline on secondary cpu */
	33	startup_32:
	34
	35	/*
	36	* At this point the CPU runs in 32bit protected mode (CS.D = 1) with
	37	* paging disabled and the point of this file is to switch to 64bit
	38	* long mode with a kernel mapping for kerneland to jump into the
	39	* kernel virtual addresses.
	40	* There is no stack until we set one up.
	41	*/
	42
	43	/* Initialize the %ds segment register */
	44	movl $__KERNEL_DS,%eax
	45	movl %eax,%ds
	46
	47	/* Load new GDT with the 64bit segments using 32bit descriptor */
	48	lgdt pGDT32 - __START_KERNEL_map
	49
	50	/* If the CPU doesn't support CPUID this will double fault.
	51	* Unfortunately it is hard to check for CPUID without a stack.
	52	*/
	53
	54	/* Check if extended functions are implemented */
	55	movl $0x80000000, %eax
	56	cpuid
	57	cmpl $0x80000000, %eax
	58	jbe no_long_mode
	59	/* Check if long mode is implemented */
	60	mov $0x80000001, %eax
	61	cpuid
	62	btl $29, %edx
	63	jnc no_long_mode
	64
	65	/*
	66	* Prepare for entering 64bits mode
	67	*/
	68
	69	/* Enable PAE mode */
	70	xorl %eax, %eax
	71	btsl $5, %eax
	72	movl %eax, %cr4
	73
	74	/* Setup early boot stage 4 level pagetables */
f6c2e333	75	movl $(boot_level4_pgt - __START_KERNEL_map), %eax
1da177e4 LT	76	movl %eax, %cr3
	77
	78	/* Setup EFER (Extended Feature Enable Register) */
	79	movl $MSR_EFER, %ecx
	80	rdmsr
	81
	82	/* Enable Long Mode */
	83	btsl $_EFER_LME, %eax
	84
	85	/* Make changes effective */
	86	wrmsr
	87
	88	xorl %eax, %eax
	89	btsl $31, %eax /* Enable paging and in turn activate Long Mode */
	90	btsl $0, %eax /* Enable protected mode */
	91	/* Make changes effective */
	92	movl %eax, %cr0
	93	/*
	94	* At this point we're in long mode but in 32bit compatibility mode
	95	* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
	96	* EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
	97	* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
	98	*/
	99	ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map)
	100
	101	.code64
	102	.org 0x100
	103	.globl startup_64
	104	startup_64:
	105	/* We come here either from startup_32
	106	* or directly from a 64bit bootloader.
	107	* Since we may have come directly from a bootloader we
	108	* reload the page tables here.
	109	*/
	110
	111	/* Enable PAE mode and PGE */
	112	xorq %rax, %rax
	113	btsq $5, %rax
	114	btsq $7, %rax
	115	movq %rax, %cr4
	116
	117	/* Setup early boot stage 4 level pagetables. */
f6c2e333	118	movq $(boot_level4_pgt - __START_KERNEL_map), %rax
1da177e4 LT	119	movq %rax, %cr3
	120
	121	/* Check if nx is implemented */
	122	movl $0x80000001, %eax
	123	cpuid
	124	movl %edx,%edi
	125
	126	/* Setup EFER (Extended Feature Enable Register) */
	127	movl $MSR_EFER, %ecx
	128	rdmsr
	129
	130	/* Enable System Call */
	131	btsl $_EFER_SCE, %eax
	132
	133	/* No Execute supported? */
	134	btl $20,%edi
	135	jnc 1f
	136	btsl $_EFER_NX, %eax
	137	1:
	138	/* Make changes effective */
	139	wrmsr
	140
	141	/* Setup cr0 */
3829ee6b AK	142	#define CR0_PM 1 /* protected mode */
	143	#define CR0_MP (1<<1)
	144	#define CR0_ET (1<<4)
	145	#define CR0_NE (1<<5)
	146	#define CR0_WP (1<<16)
	147	#define CR0_AM (1<<18)
	148	#define CR0_PAGING (1<<31)
	149	movl $CR0_PM\|CR0_MP\|CR0_ET\|CR0_NE\|CR0_WP\|CR0_AM\|CR0_PAGING,%eax
1da177e4 LT	150	/* Make changes effective */
	151	movq %rax, %cr0
	152
	153	/* Setup a boot time stack */
	154	movq init_rsp(%rip),%rsp
	155
	156	/* zero EFLAGS after setting rsp */
	157	pushq $0
	158	popfq
	159
	160	/*
	161	* We must switch to a new descriptor in kernel space for the GDT
	162	* because soon the kernel won't have access anymore to the userspace
	163	* addresses where we're currently running on. We have to do that here
	164	* because in 32bit we couldn't load a 64bit linear address.
	165	*/
	166	lgdt cpu_gdt_descr
	167
	168	/*
	169	* Setup up a dummy PDA. this is just for some early bootup code
	170	* that does in_interrupt()
	171	*/
	172	movl $MSR_GS_BASE,%ecx
	173	movq $empty_zero_page,%rax
	174	movq %rax,%rdx
	175	shrq $32,%rdx
	176	wrmsr
	177
	178	/* set up data segments. actually 0 would do too */
	179	movl $__KERNEL_DS,%eax
	180	movl %eax,%ds
	181	movl %eax,%ss
	182	movl %eax,%es
	183
	184	/* esi is pointer to real mode structure with interesting info.
	185	pass it to C */
	186	movl %esi, %edi
	187
	188	/* Finally jump to run C code and to be on real kernel address
	189	* Since we are running on identity-mapped space we have to jump
	190	* to the full 64bit address , this is only possible as indirect
	191	* jump
	192	*/
	193	movq initial_code(%rip),%rax
	194	jmp *%rax
	195
e57113bc JB	196	/* SMP bootup changes these two */
e57113bc JB	197	.align 8
1da177e4 LT	198	.globl initial_code
	199	initial_code:
	200	.quad x86_64_start_kernel
	201	.globl init_rsp
	202	init_rsp:
	203	.quad init_thread_union+THREAD_SIZE-8
	204
	205	ENTRY(early_idt_handler)
b957591f AK	206	cmpl $2,early_recursion_flag(%rip)
	207	jz 1f
	208	incl early_recursion_flag(%rip)
1da177e4 LT	209	xorl %eax,%eax
	210	movq 8(%rsp),%rsi # get rip
	211	movq (%rsp),%rdx
	212	movq %cr2,%rcx
	213	leaq early_idt_msg(%rip),%rdi
	214	call early_printk
b957591f AK	215	cmpl $2,early_recursion_flag(%rip)
	216	jz 1f
	217	call dump_stack
6574ffd7 AK	218	#ifdef CONFIG_KALLSYMS
	219	leaq early_idt_ripmsg(%rip),%rdi
	220	movq 8(%rsp),%rsi # get rip again
	221	call __print_symbol
	222	#endif
1da177e4 LT	223	1: hlt
1da177e4 LT	224	jmp 1b
b957591f AK	225	early_recursion_flag:
b957591f AK	226	.long 0
1da177e4 LT	227
	228	early_idt_msg:
	229	.asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
6574ffd7 AK	230	early_idt_ripmsg:
6574ffd7 AK	231	.asciz "RIP %s\n"
1da177e4 LT	232
	233	.code32
	234	ENTRY(no_long_mode)
	235	/* This isn't an x86-64 CPU so hang */
	236	1:
	237	jmp 1b
	238
	239	.org 0xf00
	240	.globl pGDT32
	241	pGDT32:
e57113bc	242	.word gdt_end-cpu_gdt_table-1
1da177e4 LT	243	.long cpu_gdt_table-__START_KERNEL_map
	244
	245	.org 0xf10
	246	ljumpvector:
	247	.long startup_64-__START_KERNEL_map
	248	.word __KERNEL_CS
	249
	250	ENTRY(stext)
	251	ENTRY(_stext)
	252
f0cf5d1a JB	253	$page = 0
	254	#define NEXT_PAGE(name) \
	255	$page = $page + 1; \
	256	.org $page * 0x1000; \
	257	phys_/*/name = $page 0x1000 + __PHYSICAL_START; \
	258	ENTRY(name)
	259
	260	NEXT_PAGE(init_level4_pgt)
f6c2e333 SS	261	/* This gets initialized in x86_64_start_kernel */
f6c2e333 SS	262	.fill 512,8,0
1da177e4	263
f0cf5d1a JB	264	NEXT_PAGE(level3_ident_pgt)
f0cf5d1a JB	265	.quad phys_level2_ident_pgt \| 0x007
1da177e4 LT	266	.fill 511,8,0
1da177e4 LT	267
f0cf5d1a	268	NEXT_PAGE(level3_kernel_pgt)
1da177e4 LT	269	.fill 510,8,0
1da177e4 LT	270	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
f0cf5d1a	271	.quad phys_level2_kernel_pgt \| 0x007
1da177e4 LT	272	.fill 1,8,0
1da177e4 LT	273
f0cf5d1a	274	NEXT_PAGE(level2_ident_pgt)
1da177e4	275	/* 40MB for bootup. */
f0cf5d1a JB	276	i = 0
	277	.rept 20
	278	.quad i << 21 \| 0x083
	279	i = i + 1
	280	.endr
1da177e4 LT	281	/* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */
	282	.globl temp_boot_pmds
	283	temp_boot_pmds:
	284	.fill 492,8,0
	285
f0cf5d1a	286	NEXT_PAGE(level2_kernel_pgt)
1da177e4 LT	287	/* 40MB kernel mapping. The kernel code cannot be bigger than that.
	288	When you change this change KERNEL_TEXT_SIZE in page.h too. */
	289	/* (2^48-(2102410241024)-((2^39)511)-((2^30)510)) = 0 /
f0cf5d1a JB	290	i = 0
	291	.rept 20
	292	.quad i << 21 \| 0x183
	293	i = i + 1
	294	.endr
1da177e4 LT	295	/* Module mapping starts here */
	296	.fill 492,8,0
	297
f0cf5d1a JB	298	NEXT_PAGE(level3_physmem_pgt)
	299	.quad phys_level2_kernel_pgt \| 0x007 /* so that __va works even before pagetable_init */
	300	.fill 511,8,0
1da177e4	301
f0cf5d1a	302	#undef NEXT_PAGE
1da177e4	303
f0cf5d1a	304	.data
1da177e4	305
1da177e4	306	#ifdef CONFIG_ACPI_SLEEP
f0cf5d1a	307	.align PAGE_SIZE
1da177e4	308	ENTRY(wakeup_level4_pgt)
f0cf5d1a	309	.quad phys_level3_ident_pgt \| 0x007
1da177e4	310	.fill 255,8,0
f0cf5d1a	311	.quad phys_level3_physmem_pgt \| 0x007
1da177e4 LT	312	.fill 254,8,0
1da177e4 LT	313	/* (2^48-(2102410241024))/(2^39) = 511 /
f0cf5d1a	314	.quad phys_level3_kernel_pgt \| 0x007
1da177e4 LT	315	#endif
1da177e4 LT	316
f6c2e333 SS	317	#ifndef CONFIG_HOTPLUG_CPU
	318	__INITDATA
	319	#endif
	320	/*
	321	* This default setting generates an ident mapping at address 0x100000
	322	* and a mapping for the kernel that precisely maps virtual address
	323	* 0xffffffff80000000 to physical address 0x000000. (always using
	324	* 2Mbyte large pages provided by PAE mode)
	325	*/
	326	.align PAGE_SIZE
	327	ENTRY(boot_level4_pgt)
f0cf5d1a	328	.quad phys_level3_ident_pgt \| 0x007
f6c2e333	329	.fill 255,8,0
f0cf5d1a	330	.quad phys_level3_physmem_pgt \| 0x007
f6c2e333 SS	331	.fill 254,8,0
f6c2e333 SS	332	/* (2^48-(2102410241024))/(2^39) = 511 /
f0cf5d1a	333	.quad phys_level3_kernel_pgt \| 0x007
f6c2e333	334
1da177e4 LT	335	.data
	336
	337	.align 16
	338	.globl cpu_gdt_descr
	339	cpu_gdt_descr:
e57113bc	340	.word gdt_end-cpu_gdt_table-1
1da177e4 LT	341	gdt:
	342	.quad cpu_gdt_table
	343	#ifdef CONFIG_SMP
	344	.rept NR_CPUS-1
	345	.word 0
	346	.quad 0
	347	.endr
	348	#endif
	349
	350	/* We need valid kernel segments for data and code in long mode too
	351	* IRET will check the segment types kkeil 2000/10/28
	352	* Also sysret mandates a special GDT layout
	353	*/
	354
e57113bc JB	355	.section .data.page_aligned, "aw"
e57113bc JB	356	.align PAGE_SIZE
1da177e4 LT	357
	358	/* The TLS descriptors are currently at a different place compared to i386.
	359	Hopefully nobody expects them at a fixed place (Wine?) */
	360
	361	ENTRY(cpu_gdt_table)
	362	.quad 0x0000000000000000 /* NULL descriptor */
cdc4b9c0	363	.quad 0x0 /* unused */
1da177e4 LT	364	.quad 0x00af9a000000ffff /* __KERNEL_CS */
	365	.quad 0x00cf92000000ffff /* __KERNEL_DS */
	366	.quad 0x00cffa000000ffff /* __USER32_CS */
	367	.quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
	368	.quad 0x00affa000000ffff /* __USER_CS */
	369	.quad 0x00cf9a000000ffff /* __KERNEL32_CS */
	370	.quad 0,0 /* TSS */
	371	.quad 0,0 /* LDT */
	372	.quad 0,0,0 /* three TLS descriptors */
cdc4b9c0	373	.quad 0 /* unused */
1da177e4 LT	374	gdt_end:
	375	/* asm/segment.h:GDT_ENTRIES must match this */
	376	/* This should be a multiple of the cache line size */
c11efdf9 RT	377	/* GDTs of other CPUs are now dynamically allocated */
	378
	379	/* zero the remaining page */
	380	.fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
1da177e4	381
e57113bc JB	382	.section .bss, "aw", @nobits
	383	.align L1_CACHE_BYTES
	384	ENTRY(idt_table)
	385	.skip 256 * 16
1da177e4	386
e57113bc JB	387	.section .bss.page_aligned, "aw", @nobits
	388	.align PAGE_SIZE
	389	ENTRY(empty_zero_page)
	390	.skip PAGE_SIZE