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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit | |
3 | * | |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1da177e4 LT |
8 | */ |
9 | ||
10 | ||
11 | #include <linux/linkage.h> | |
12 | #include <linux/threads.h> | |
f6c2e333 | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <asm/desc.h> |
15 | #include <asm/segment.h> | |
16 | #include <asm/page.h> | |
17 | #include <asm/msr.h> | |
18 | #include <asm/cache.h> | |
19 | ||
20 | /* we are not able to switch in one step to the final KERNEL ADRESS SPACE | |
21 | * because we need identity-mapped pages on setup so define __START_KERNEL to | |
22 | * 0x100000 for this stage | |
23 | * | |
24 | */ | |
25 | ||
26 | .text | |
eaeae0cc | 27 | .section .bootstrap.text |
1da177e4 LT |
28 | .code32 |
29 | .globl startup_32 | |
30 | /* %bx: 1 if coming from smp trampoline on secondary cpu */ | |
31 | startup_32: | |
32 | ||
33 | /* | |
34 | * At this point the CPU runs in 32bit protected mode (CS.D = 1) with | |
35 | * paging disabled and the point of this file is to switch to 64bit | |
36 | * long mode with a kernel mapping for kerneland to jump into the | |
37 | * kernel virtual addresses. | |
38 | * There is no stack until we set one up. | |
39 | */ | |
40 | ||
41 | /* Initialize the %ds segment register */ | |
42 | movl $__KERNEL_DS,%eax | |
43 | movl %eax,%ds | |
44 | ||
45 | /* Load new GDT with the 64bit segments using 32bit descriptor */ | |
46 | lgdt pGDT32 - __START_KERNEL_map | |
47 | ||
48 | /* If the CPU doesn't support CPUID this will double fault. | |
49 | * Unfortunately it is hard to check for CPUID without a stack. | |
50 | */ | |
51 | ||
52 | /* Check if extended functions are implemented */ | |
53 | movl $0x80000000, %eax | |
54 | cpuid | |
55 | cmpl $0x80000000, %eax | |
56 | jbe no_long_mode | |
57 | /* Check if long mode is implemented */ | |
58 | mov $0x80000001, %eax | |
59 | cpuid | |
60 | btl $29, %edx | |
61 | jnc no_long_mode | |
62 | ||
63 | /* | |
64 | * Prepare for entering 64bits mode | |
65 | */ | |
66 | ||
67 | /* Enable PAE mode */ | |
68 | xorl %eax, %eax | |
69 | btsl $5, %eax | |
70 | movl %eax, %cr4 | |
71 | ||
72 | /* Setup early boot stage 4 level pagetables */ | |
f6c2e333 | 73 | movl $(boot_level4_pgt - __START_KERNEL_map), %eax |
1da177e4 LT |
74 | movl %eax, %cr3 |
75 | ||
76 | /* Setup EFER (Extended Feature Enable Register) */ | |
77 | movl $MSR_EFER, %ecx | |
78 | rdmsr | |
79 | ||
80 | /* Enable Long Mode */ | |
81 | btsl $_EFER_LME, %eax | |
82 | ||
83 | /* Make changes effective */ | |
84 | wrmsr | |
85 | ||
86 | xorl %eax, %eax | |
87 | btsl $31, %eax /* Enable paging and in turn activate Long Mode */ | |
88 | btsl $0, %eax /* Enable protected mode */ | |
89 | /* Make changes effective */ | |
90 | movl %eax, %cr0 | |
91 | /* | |
92 | * At this point we're in long mode but in 32bit compatibility mode | |
93 | * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn | |
94 | * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use | |
95 | * the new gdt/idt that has __KERNEL_CS with CS.L = 1. | |
96 | */ | |
97 | ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map) | |
98 | ||
99 | .code64 | |
100 | .org 0x100 | |
101 | .globl startup_64 | |
102 | startup_64: | |
103 | /* We come here either from startup_32 | |
104 | * or directly from a 64bit bootloader. | |
105 | * Since we may have come directly from a bootloader we | |
106 | * reload the page tables here. | |
107 | */ | |
108 | ||
109 | /* Enable PAE mode and PGE */ | |
110 | xorq %rax, %rax | |
111 | btsq $5, %rax | |
112 | btsq $7, %rax | |
113 | movq %rax, %cr4 | |
114 | ||
115 | /* Setup early boot stage 4 level pagetables. */ | |
f6c2e333 | 116 | movq $(boot_level4_pgt - __START_KERNEL_map), %rax |
1da177e4 LT |
117 | movq %rax, %cr3 |
118 | ||
119 | /* Check if nx is implemented */ | |
120 | movl $0x80000001, %eax | |
121 | cpuid | |
122 | movl %edx,%edi | |
123 | ||
124 | /* Setup EFER (Extended Feature Enable Register) */ | |
125 | movl $MSR_EFER, %ecx | |
126 | rdmsr | |
127 | ||
128 | /* Enable System Call */ | |
129 | btsl $_EFER_SCE, %eax | |
130 | ||
131 | /* No Execute supported? */ | |
132 | btl $20,%edi | |
133 | jnc 1f | |
134 | btsl $_EFER_NX, %eax | |
135 | 1: | |
136 | /* Make changes effective */ | |
137 | wrmsr | |
138 | ||
139 | /* Setup cr0 */ | |
3829ee6b AK |
140 | #define CR0_PM 1 /* protected mode */ |
141 | #define CR0_MP (1<<1) | |
142 | #define CR0_ET (1<<4) | |
143 | #define CR0_NE (1<<5) | |
144 | #define CR0_WP (1<<16) | |
145 | #define CR0_AM (1<<18) | |
146 | #define CR0_PAGING (1<<31) | |
147 | movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax | |
1da177e4 LT |
148 | /* Make changes effective */ |
149 | movq %rax, %cr0 | |
150 | ||
151 | /* Setup a boot time stack */ | |
152 | movq init_rsp(%rip),%rsp | |
153 | ||
154 | /* zero EFLAGS after setting rsp */ | |
155 | pushq $0 | |
156 | popfq | |
157 | ||
158 | /* | |
159 | * We must switch to a new descriptor in kernel space for the GDT | |
160 | * because soon the kernel won't have access anymore to the userspace | |
161 | * addresses where we're currently running on. We have to do that here | |
162 | * because in 32bit we couldn't load a 64bit linear address. | |
163 | */ | |
164 | lgdt cpu_gdt_descr | |
165 | ||
166 | /* | |
167 | * Setup up a dummy PDA. this is just for some early bootup code | |
168 | * that does in_interrupt() | |
169 | */ | |
170 | movl $MSR_GS_BASE,%ecx | |
171 | movq $empty_zero_page,%rax | |
172 | movq %rax,%rdx | |
173 | shrq $32,%rdx | |
174 | wrmsr | |
175 | ||
176 | /* set up data segments. actually 0 would do too */ | |
177 | movl $__KERNEL_DS,%eax | |
178 | movl %eax,%ds | |
179 | movl %eax,%ss | |
180 | movl %eax,%es | |
181 | ||
182 | /* esi is pointer to real mode structure with interesting info. | |
183 | pass it to C */ | |
184 | movl %esi, %edi | |
185 | ||
186 | /* Finally jump to run C code and to be on real kernel address | |
187 | * Since we are running on identity-mapped space we have to jump | |
188 | * to the full 64bit address , this is only possible as indirect | |
189 | * jump | |
190 | */ | |
191 | movq initial_code(%rip),%rax | |
c05991ed | 192 | pushq $0 # fake return address |
1da177e4 LT |
193 | jmp *%rax |
194 | ||
e57113bc JB |
195 | /* SMP bootup changes these two */ |
196 | .align 8 | |
1da177e4 LT |
197 | .globl initial_code |
198 | initial_code: | |
199 | .quad x86_64_start_kernel | |
200 | .globl init_rsp | |
201 | init_rsp: | |
202 | .quad init_thread_union+THREAD_SIZE-8 | |
203 | ||
204 | ENTRY(early_idt_handler) | |
b957591f AK |
205 | cmpl $2,early_recursion_flag(%rip) |
206 | jz 1f | |
207 | incl early_recursion_flag(%rip) | |
1da177e4 LT |
208 | xorl %eax,%eax |
209 | movq 8(%rsp),%rsi # get rip | |
210 | movq (%rsp),%rdx | |
211 | movq %cr2,%rcx | |
212 | leaq early_idt_msg(%rip),%rdi | |
213 | call early_printk | |
b957591f AK |
214 | cmpl $2,early_recursion_flag(%rip) |
215 | jz 1f | |
216 | call dump_stack | |
6574ffd7 AK |
217 | #ifdef CONFIG_KALLSYMS |
218 | leaq early_idt_ripmsg(%rip),%rdi | |
219 | movq 8(%rsp),%rsi # get rip again | |
220 | call __print_symbol | |
221 | #endif | |
1da177e4 LT |
222 | 1: hlt |
223 | jmp 1b | |
b957591f AK |
224 | early_recursion_flag: |
225 | .long 0 | |
1da177e4 LT |
226 | |
227 | early_idt_msg: | |
228 | .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n" | |
6574ffd7 AK |
229 | early_idt_ripmsg: |
230 | .asciz "RIP %s\n" | |
1da177e4 LT |
231 | |
232 | .code32 | |
233 | ENTRY(no_long_mode) | |
234 | /* This isn't an x86-64 CPU so hang */ | |
235 | 1: | |
236 | jmp 1b | |
237 | ||
238 | .org 0xf00 | |
239 | .globl pGDT32 | |
240 | pGDT32: | |
e57113bc | 241 | .word gdt_end-cpu_gdt_table-1 |
1da177e4 LT |
242 | .long cpu_gdt_table-__START_KERNEL_map |
243 | ||
244 | .org 0xf10 | |
245 | ljumpvector: | |
246 | .long startup_64-__START_KERNEL_map | |
247 | .word __KERNEL_CS | |
248 | ||
249 | ENTRY(stext) | |
250 | ENTRY(_stext) | |
251 | ||
f0cf5d1a JB |
252 | $page = 0 |
253 | #define NEXT_PAGE(name) \ | |
254 | $page = $page + 1; \ | |
255 | .org $page * 0x1000; \ | |
256 | phys_/**/name = $page * 0x1000 + __PHYSICAL_START; \ | |
257 | ENTRY(name) | |
258 | ||
259 | NEXT_PAGE(init_level4_pgt) | |
f6c2e333 SS |
260 | /* This gets initialized in x86_64_start_kernel */ |
261 | .fill 512,8,0 | |
1da177e4 | 262 | |
f0cf5d1a JB |
263 | NEXT_PAGE(level3_ident_pgt) |
264 | .quad phys_level2_ident_pgt | 0x007 | |
1da177e4 LT |
265 | .fill 511,8,0 |
266 | ||
f0cf5d1a | 267 | NEXT_PAGE(level3_kernel_pgt) |
1da177e4 LT |
268 | .fill 510,8,0 |
269 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ | |
f0cf5d1a | 270 | .quad phys_level2_kernel_pgt | 0x007 |
1da177e4 LT |
271 | .fill 1,8,0 |
272 | ||
f0cf5d1a | 273 | NEXT_PAGE(level2_ident_pgt) |
1da177e4 | 274 | /* 40MB for bootup. */ |
f0cf5d1a JB |
275 | i = 0 |
276 | .rept 20 | |
277 | .quad i << 21 | 0x083 | |
278 | i = i + 1 | |
279 | .endr | |
1da177e4 LT |
280 | /* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */ |
281 | .globl temp_boot_pmds | |
282 | temp_boot_pmds: | |
283 | .fill 492,8,0 | |
284 | ||
f0cf5d1a | 285 | NEXT_PAGE(level2_kernel_pgt) |
1da177e4 LT |
286 | /* 40MB kernel mapping. The kernel code cannot be bigger than that. |
287 | When you change this change KERNEL_TEXT_SIZE in page.h too. */ | |
288 | /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ | |
f0cf5d1a JB |
289 | i = 0 |
290 | .rept 20 | |
291 | .quad i << 21 | 0x183 | |
292 | i = i + 1 | |
293 | .endr | |
1da177e4 LT |
294 | /* Module mapping starts here */ |
295 | .fill 492,8,0 | |
296 | ||
f0cf5d1a JB |
297 | NEXT_PAGE(level3_physmem_pgt) |
298 | .quad phys_level2_kernel_pgt | 0x007 /* so that __va works even before pagetable_init */ | |
299 | .fill 511,8,0 | |
1da177e4 | 300 | |
f0cf5d1a | 301 | #undef NEXT_PAGE |
1da177e4 | 302 | |
f0cf5d1a | 303 | .data |
1da177e4 | 304 | |
1da177e4 | 305 | #ifdef CONFIG_ACPI_SLEEP |
f0cf5d1a | 306 | .align PAGE_SIZE |
1da177e4 | 307 | ENTRY(wakeup_level4_pgt) |
f0cf5d1a | 308 | .quad phys_level3_ident_pgt | 0x007 |
1da177e4 | 309 | .fill 255,8,0 |
f0cf5d1a | 310 | .quad phys_level3_physmem_pgt | 0x007 |
1da177e4 LT |
311 | .fill 254,8,0 |
312 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
f0cf5d1a | 313 | .quad phys_level3_kernel_pgt | 0x007 |
1da177e4 LT |
314 | #endif |
315 | ||
f6c2e333 SS |
316 | #ifndef CONFIG_HOTPLUG_CPU |
317 | __INITDATA | |
318 | #endif | |
319 | /* | |
320 | * This default setting generates an ident mapping at address 0x100000 | |
321 | * and a mapping for the kernel that precisely maps virtual address | |
322 | * 0xffffffff80000000 to physical address 0x000000. (always using | |
323 | * 2Mbyte large pages provided by PAE mode) | |
324 | */ | |
325 | .align PAGE_SIZE | |
326 | ENTRY(boot_level4_pgt) | |
f0cf5d1a | 327 | .quad phys_level3_ident_pgt | 0x007 |
f6c2e333 | 328 | .fill 255,8,0 |
f0cf5d1a | 329 | .quad phys_level3_physmem_pgt | 0x007 |
f6c2e333 SS |
330 | .fill 254,8,0 |
331 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
f0cf5d1a | 332 | .quad phys_level3_kernel_pgt | 0x007 |
f6c2e333 | 333 | |
1da177e4 LT |
334 | .data |
335 | ||
336 | .align 16 | |
337 | .globl cpu_gdt_descr | |
338 | cpu_gdt_descr: | |
e57113bc | 339 | .word gdt_end-cpu_gdt_table-1 |
1da177e4 LT |
340 | gdt: |
341 | .quad cpu_gdt_table | |
342 | #ifdef CONFIG_SMP | |
343 | .rept NR_CPUS-1 | |
344 | .word 0 | |
345 | .quad 0 | |
346 | .endr | |
347 | #endif | |
348 | ||
349 | /* We need valid kernel segments for data and code in long mode too | |
350 | * IRET will check the segment types kkeil 2000/10/28 | |
351 | * Also sysret mandates a special GDT layout | |
352 | */ | |
353 | ||
e57113bc JB |
354 | .section .data.page_aligned, "aw" |
355 | .align PAGE_SIZE | |
1da177e4 LT |
356 | |
357 | /* The TLS descriptors are currently at a different place compared to i386. | |
358 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
359 | ||
360 | ENTRY(cpu_gdt_table) | |
361 | .quad 0x0000000000000000 /* NULL descriptor */ | |
cdc4b9c0 | 362 | .quad 0x0 /* unused */ |
1da177e4 LT |
363 | .quad 0x00af9a000000ffff /* __KERNEL_CS */ |
364 | .quad 0x00cf92000000ffff /* __KERNEL_DS */ | |
365 | .quad 0x00cffa000000ffff /* __USER32_CS */ | |
366 | .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */ | |
367 | .quad 0x00affa000000ffff /* __USER_CS */ | |
368 | .quad 0x00cf9a000000ffff /* __KERNEL32_CS */ | |
369 | .quad 0,0 /* TSS */ | |
370 | .quad 0,0 /* LDT */ | |
371 | .quad 0,0,0 /* three TLS descriptors */ | |
c08c8205 | 372 | .quad 0x0000f40000000000 /* node/CPU stored in limit */ |
1da177e4 LT |
373 | gdt_end: |
374 | /* asm/segment.h:GDT_ENTRIES must match this */ | |
375 | /* This should be a multiple of the cache line size */ | |
c11efdf9 RT |
376 | /* GDTs of other CPUs are now dynamically allocated */ |
377 | ||
378 | /* zero the remaining page */ | |
379 | .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 | |
1da177e4 | 380 | |
e57113bc JB |
381 | .section .bss, "aw", @nobits |
382 | .align L1_CACHE_BYTES | |
383 | ENTRY(idt_table) | |
384 | .skip 256 * 16 | |
1da177e4 | 385 | |
e57113bc JB |
386 | .section .bss.page_aligned, "aw", @nobits |
387 | .align PAGE_SIZE | |
388 | ENTRY(empty_zero_page) | |
389 | .skip PAGE_SIZE |