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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit | |
3 | * | |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
8 | * | |
9 | * $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $ | |
10 | */ | |
11 | ||
12 | ||
13 | #include <linux/linkage.h> | |
14 | #include <linux/threads.h> | |
f6c2e333 | 15 | #include <linux/init.h> |
1da177e4 LT |
16 | #include <asm/desc.h> |
17 | #include <asm/segment.h> | |
18 | #include <asm/page.h> | |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
21 | ||
22 | /* we are not able to switch in one step to the final KERNEL ADRESS SPACE | |
23 | * because we need identity-mapped pages on setup so define __START_KERNEL to | |
24 | * 0x100000 for this stage | |
25 | * | |
26 | */ | |
27 | ||
28 | .text | |
29 | .code32 | |
30 | .globl startup_32 | |
31 | /* %bx: 1 if coming from smp trampoline on secondary cpu */ | |
32 | startup_32: | |
33 | ||
34 | /* | |
35 | * At this point the CPU runs in 32bit protected mode (CS.D = 1) with | |
36 | * paging disabled and the point of this file is to switch to 64bit | |
37 | * long mode with a kernel mapping for kerneland to jump into the | |
38 | * kernel virtual addresses. | |
39 | * There is no stack until we set one up. | |
40 | */ | |
41 | ||
42 | /* Initialize the %ds segment register */ | |
43 | movl $__KERNEL_DS,%eax | |
44 | movl %eax,%ds | |
45 | ||
46 | /* Load new GDT with the 64bit segments using 32bit descriptor */ | |
47 | lgdt pGDT32 - __START_KERNEL_map | |
48 | ||
49 | /* If the CPU doesn't support CPUID this will double fault. | |
50 | * Unfortunately it is hard to check for CPUID without a stack. | |
51 | */ | |
52 | ||
53 | /* Check if extended functions are implemented */ | |
54 | movl $0x80000000, %eax | |
55 | cpuid | |
56 | cmpl $0x80000000, %eax | |
57 | jbe no_long_mode | |
58 | /* Check if long mode is implemented */ | |
59 | mov $0x80000001, %eax | |
60 | cpuid | |
61 | btl $29, %edx | |
62 | jnc no_long_mode | |
63 | ||
64 | /* | |
65 | * Prepare for entering 64bits mode | |
66 | */ | |
67 | ||
68 | /* Enable PAE mode */ | |
69 | xorl %eax, %eax | |
70 | btsl $5, %eax | |
71 | movl %eax, %cr4 | |
72 | ||
73 | /* Setup early boot stage 4 level pagetables */ | |
f6c2e333 | 74 | movl $(boot_level4_pgt - __START_KERNEL_map), %eax |
1da177e4 LT |
75 | movl %eax, %cr3 |
76 | ||
77 | /* Setup EFER (Extended Feature Enable Register) */ | |
78 | movl $MSR_EFER, %ecx | |
79 | rdmsr | |
80 | ||
81 | /* Enable Long Mode */ | |
82 | btsl $_EFER_LME, %eax | |
83 | ||
84 | /* Make changes effective */ | |
85 | wrmsr | |
86 | ||
87 | xorl %eax, %eax | |
88 | btsl $31, %eax /* Enable paging and in turn activate Long Mode */ | |
89 | btsl $0, %eax /* Enable protected mode */ | |
90 | /* Make changes effective */ | |
91 | movl %eax, %cr0 | |
92 | /* | |
93 | * At this point we're in long mode but in 32bit compatibility mode | |
94 | * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn | |
95 | * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use | |
96 | * the new gdt/idt that has __KERNEL_CS with CS.L = 1. | |
97 | */ | |
98 | ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map) | |
99 | ||
100 | .code64 | |
101 | .org 0x100 | |
102 | .globl startup_64 | |
103 | startup_64: | |
104 | /* We come here either from startup_32 | |
105 | * or directly from a 64bit bootloader. | |
106 | * Since we may have come directly from a bootloader we | |
107 | * reload the page tables here. | |
108 | */ | |
109 | ||
110 | /* Enable PAE mode and PGE */ | |
111 | xorq %rax, %rax | |
112 | btsq $5, %rax | |
113 | btsq $7, %rax | |
114 | movq %rax, %cr4 | |
115 | ||
116 | /* Setup early boot stage 4 level pagetables. */ | |
f6c2e333 | 117 | movq $(boot_level4_pgt - __START_KERNEL_map), %rax |
1da177e4 LT |
118 | movq %rax, %cr3 |
119 | ||
120 | /* Check if nx is implemented */ | |
121 | movl $0x80000001, %eax | |
122 | cpuid | |
123 | movl %edx,%edi | |
124 | ||
125 | /* Setup EFER (Extended Feature Enable Register) */ | |
126 | movl $MSR_EFER, %ecx | |
127 | rdmsr | |
128 | ||
129 | /* Enable System Call */ | |
130 | btsl $_EFER_SCE, %eax | |
131 | ||
132 | /* No Execute supported? */ | |
133 | btl $20,%edi | |
134 | jnc 1f | |
135 | btsl $_EFER_NX, %eax | |
136 | 1: | |
137 | /* Make changes effective */ | |
138 | wrmsr | |
139 | ||
140 | /* Setup cr0 */ | |
3829ee6b AK |
141 | #define CR0_PM 1 /* protected mode */ |
142 | #define CR0_MP (1<<1) | |
143 | #define CR0_ET (1<<4) | |
144 | #define CR0_NE (1<<5) | |
145 | #define CR0_WP (1<<16) | |
146 | #define CR0_AM (1<<18) | |
147 | #define CR0_PAGING (1<<31) | |
148 | movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax | |
1da177e4 LT |
149 | /* Make changes effective */ |
150 | movq %rax, %cr0 | |
151 | ||
152 | /* Setup a boot time stack */ | |
153 | movq init_rsp(%rip),%rsp | |
154 | ||
155 | /* zero EFLAGS after setting rsp */ | |
156 | pushq $0 | |
157 | popfq | |
158 | ||
159 | /* | |
160 | * We must switch to a new descriptor in kernel space for the GDT | |
161 | * because soon the kernel won't have access anymore to the userspace | |
162 | * addresses where we're currently running on. We have to do that here | |
163 | * because in 32bit we couldn't load a 64bit linear address. | |
164 | */ | |
165 | lgdt cpu_gdt_descr | |
166 | ||
167 | /* | |
168 | * Setup up a dummy PDA. this is just for some early bootup code | |
169 | * that does in_interrupt() | |
170 | */ | |
171 | movl $MSR_GS_BASE,%ecx | |
172 | movq $empty_zero_page,%rax | |
173 | movq %rax,%rdx | |
174 | shrq $32,%rdx | |
175 | wrmsr | |
176 | ||
177 | /* set up data segments. actually 0 would do too */ | |
178 | movl $__KERNEL_DS,%eax | |
179 | movl %eax,%ds | |
180 | movl %eax,%ss | |
181 | movl %eax,%es | |
182 | ||
183 | /* esi is pointer to real mode structure with interesting info. | |
184 | pass it to C */ | |
185 | movl %esi, %edi | |
186 | ||
187 | /* Finally jump to run C code and to be on real kernel address | |
188 | * Since we are running on identity-mapped space we have to jump | |
189 | * to the full 64bit address , this is only possible as indirect | |
190 | * jump | |
191 | */ | |
192 | movq initial_code(%rip),%rax | |
193 | jmp *%rax | |
194 | ||
195 | /* SMP bootup changes these two */ | |
196 | .globl initial_code | |
197 | initial_code: | |
198 | .quad x86_64_start_kernel | |
199 | .globl init_rsp | |
200 | init_rsp: | |
201 | .quad init_thread_union+THREAD_SIZE-8 | |
202 | ||
203 | ENTRY(early_idt_handler) | |
b957591f AK |
204 | cmpl $2,early_recursion_flag(%rip) |
205 | jz 1f | |
206 | incl early_recursion_flag(%rip) | |
1da177e4 LT |
207 | xorl %eax,%eax |
208 | movq 8(%rsp),%rsi # get rip | |
209 | movq (%rsp),%rdx | |
210 | movq %cr2,%rcx | |
211 | leaq early_idt_msg(%rip),%rdi | |
212 | call early_printk | |
b957591f AK |
213 | cmpl $2,early_recursion_flag(%rip) |
214 | jz 1f | |
215 | call dump_stack | |
6574ffd7 AK |
216 | #ifdef CONFIG_KALLSYMS |
217 | leaq early_idt_ripmsg(%rip),%rdi | |
218 | movq 8(%rsp),%rsi # get rip again | |
219 | call __print_symbol | |
220 | #endif | |
1da177e4 LT |
221 | 1: hlt |
222 | jmp 1b | |
b957591f AK |
223 | early_recursion_flag: |
224 | .long 0 | |
1da177e4 LT |
225 | |
226 | early_idt_msg: | |
227 | .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n" | |
6574ffd7 AK |
228 | early_idt_ripmsg: |
229 | .asciz "RIP %s\n" | |
1da177e4 LT |
230 | |
231 | .code32 | |
232 | ENTRY(no_long_mode) | |
233 | /* This isn't an x86-64 CPU so hang */ | |
234 | 1: | |
235 | jmp 1b | |
236 | ||
237 | .org 0xf00 | |
238 | .globl pGDT32 | |
239 | pGDT32: | |
240 | .word gdt_end-cpu_gdt_table | |
241 | .long cpu_gdt_table-__START_KERNEL_map | |
242 | ||
243 | .org 0xf10 | |
244 | ljumpvector: | |
245 | .long startup_64-__START_KERNEL_map | |
246 | .word __KERNEL_CS | |
247 | ||
248 | ENTRY(stext) | |
249 | ENTRY(_stext) | |
250 | ||
f0cf5d1a JB |
251 | $page = 0 |
252 | #define NEXT_PAGE(name) \ | |
253 | $page = $page + 1; \ | |
254 | .org $page * 0x1000; \ | |
255 | phys_/**/name = $page * 0x1000 + __PHYSICAL_START; \ | |
256 | ENTRY(name) | |
257 | ||
258 | NEXT_PAGE(init_level4_pgt) | |
f6c2e333 SS |
259 | /* This gets initialized in x86_64_start_kernel */ |
260 | .fill 512,8,0 | |
1da177e4 | 261 | |
f0cf5d1a JB |
262 | NEXT_PAGE(level3_ident_pgt) |
263 | .quad phys_level2_ident_pgt | 0x007 | |
1da177e4 LT |
264 | .fill 511,8,0 |
265 | ||
f0cf5d1a | 266 | NEXT_PAGE(level3_kernel_pgt) |
1da177e4 LT |
267 | .fill 510,8,0 |
268 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ | |
f0cf5d1a | 269 | .quad phys_level2_kernel_pgt | 0x007 |
1da177e4 LT |
270 | .fill 1,8,0 |
271 | ||
f0cf5d1a | 272 | NEXT_PAGE(level2_ident_pgt) |
1da177e4 | 273 | /* 40MB for bootup. */ |
f0cf5d1a JB |
274 | i = 0 |
275 | .rept 20 | |
276 | .quad i << 21 | 0x083 | |
277 | i = i + 1 | |
278 | .endr | |
1da177e4 LT |
279 | /* Temporary mappings for the super early allocator in arch/x86_64/mm/init.c */ |
280 | .globl temp_boot_pmds | |
281 | temp_boot_pmds: | |
282 | .fill 492,8,0 | |
283 | ||
f0cf5d1a | 284 | NEXT_PAGE(level2_kernel_pgt) |
1da177e4 LT |
285 | /* 40MB kernel mapping. The kernel code cannot be bigger than that. |
286 | When you change this change KERNEL_TEXT_SIZE in page.h too. */ | |
287 | /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ | |
f0cf5d1a JB |
288 | i = 0 |
289 | .rept 20 | |
290 | .quad i << 21 | 0x183 | |
291 | i = i + 1 | |
292 | .endr | |
1da177e4 LT |
293 | /* Module mapping starts here */ |
294 | .fill 492,8,0 | |
295 | ||
f0cf5d1a | 296 | NEXT_PAGE(empty_zero_page) |
1da177e4 | 297 | |
f0cf5d1a JB |
298 | NEXT_PAGE(level3_physmem_pgt) |
299 | .quad phys_level2_kernel_pgt | 0x007 /* so that __va works even before pagetable_init */ | |
300 | .fill 511,8,0 | |
1da177e4 | 301 | |
f0cf5d1a | 302 | #undef NEXT_PAGE |
1da177e4 | 303 | |
f0cf5d1a | 304 | .data |
1da177e4 | 305 | |
1da177e4 | 306 | #ifdef CONFIG_ACPI_SLEEP |
f0cf5d1a | 307 | .align PAGE_SIZE |
1da177e4 | 308 | ENTRY(wakeup_level4_pgt) |
f0cf5d1a | 309 | .quad phys_level3_ident_pgt | 0x007 |
1da177e4 | 310 | .fill 255,8,0 |
f0cf5d1a | 311 | .quad phys_level3_physmem_pgt | 0x007 |
1da177e4 LT |
312 | .fill 254,8,0 |
313 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
f0cf5d1a | 314 | .quad phys_level3_kernel_pgt | 0x007 |
1da177e4 LT |
315 | #endif |
316 | ||
f6c2e333 SS |
317 | #ifndef CONFIG_HOTPLUG_CPU |
318 | __INITDATA | |
319 | #endif | |
320 | /* | |
321 | * This default setting generates an ident mapping at address 0x100000 | |
322 | * and a mapping for the kernel that precisely maps virtual address | |
323 | * 0xffffffff80000000 to physical address 0x000000. (always using | |
324 | * 2Mbyte large pages provided by PAE mode) | |
325 | */ | |
326 | .align PAGE_SIZE | |
327 | ENTRY(boot_level4_pgt) | |
f0cf5d1a | 328 | .quad phys_level3_ident_pgt | 0x007 |
f6c2e333 | 329 | .fill 255,8,0 |
f0cf5d1a | 330 | .quad phys_level3_physmem_pgt | 0x007 |
f6c2e333 SS |
331 | .fill 254,8,0 |
332 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
f0cf5d1a | 333 | .quad phys_level3_kernel_pgt | 0x007 |
f6c2e333 | 334 | |
1da177e4 LT |
335 | .data |
336 | ||
337 | .align 16 | |
338 | .globl cpu_gdt_descr | |
339 | cpu_gdt_descr: | |
340 | .word gdt_end-cpu_gdt_table | |
341 | gdt: | |
342 | .quad cpu_gdt_table | |
343 | #ifdef CONFIG_SMP | |
344 | .rept NR_CPUS-1 | |
345 | .word 0 | |
346 | .quad 0 | |
347 | .endr | |
348 | #endif | |
349 | ||
350 | /* We need valid kernel segments for data and code in long mode too | |
351 | * IRET will check the segment types kkeil 2000/10/28 | |
352 | * Also sysret mandates a special GDT layout | |
353 | */ | |
354 | ||
c11efdf9 | 355 | .align PAGE_SIZE |
1da177e4 LT |
356 | |
357 | /* The TLS descriptors are currently at a different place compared to i386. | |
358 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
359 | ||
360 | ENTRY(cpu_gdt_table) | |
361 | .quad 0x0000000000000000 /* NULL descriptor */ | |
cdc4b9c0 | 362 | .quad 0x0 /* unused */ |
1da177e4 LT |
363 | .quad 0x00af9a000000ffff /* __KERNEL_CS */ |
364 | .quad 0x00cf92000000ffff /* __KERNEL_DS */ | |
365 | .quad 0x00cffa000000ffff /* __USER32_CS */ | |
366 | .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */ | |
367 | .quad 0x00affa000000ffff /* __USER_CS */ | |
368 | .quad 0x00cf9a000000ffff /* __KERNEL32_CS */ | |
369 | .quad 0,0 /* TSS */ | |
370 | .quad 0,0 /* LDT */ | |
371 | .quad 0,0,0 /* three TLS descriptors */ | |
cdc4b9c0 | 372 | .quad 0 /* unused */ |
1da177e4 LT |
373 | gdt_end: |
374 | /* asm/segment.h:GDT_ENTRIES must match this */ | |
375 | /* This should be a multiple of the cache line size */ | |
c11efdf9 RT |
376 | /* GDTs of other CPUs are now dynamically allocated */ |
377 | ||
378 | /* zero the remaining page */ | |
379 | .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 | |
1da177e4 | 380 | |
1da177e4 LT |
381 | ENTRY(idt_table) |
382 | .rept 256 | |
383 | .quad 0 | |
384 | .quad 0 | |
385 | .endr | |
386 |