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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
1da177e4 LT |
32 | |
33 | /* Have we found an MP table */ | |
34 | int smp_found_config; | |
35 | unsigned int __initdata maxcpus = NR_CPUS; | |
36 | ||
1da177e4 LT |
37 | /* |
38 | * Various Linux-internal data structures created from the | |
39 | * MP-table. | |
40 | */ | |
55f05ffa | 41 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 | 42 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
1da177e4 LT |
43 | |
44 | static int mp_current_pci_id = 0; | |
45 | /* I/O APIC entries */ | |
46 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
47 | ||
48 | /* # of MP IRQ source entries */ | |
49 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
50 | ||
51 | /* MP IRQ source entries */ | |
52 | int mp_irq_entries; | |
53 | ||
54 | int nr_ioapics; | |
1da177e4 LT |
55 | unsigned long mp_lapic_addr = 0; |
56 | ||
57 | ||
58 | ||
59 | /* Processor that is doing the boot up */ | |
60 | unsigned int boot_cpu_id = -1U; | |
61 | /* Internal processor count */ | |
43999d9e | 62 | unsigned int num_processors __cpuinitdata = 0; |
420f8f68 | 63 | |
43999d9e | 64 | unsigned disabled_cpus __cpuinitdata; |
1da177e4 LT |
65 | |
66 | /* Bitmask of physically existing CPUs */ | |
67 | physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE; | |
68 | ||
1da177e4 LT |
69 | u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; |
70 | ||
71 | ||
72 | /* | |
73 | * Intel MP BIOS table parsing routines: | |
74 | */ | |
75 | ||
76 | /* | |
77 | * Checksum an MP configuration block. | |
78 | */ | |
79 | ||
80 | static int __init mpf_checksum(unsigned char *mp, int len) | |
81 | { | |
82 | int sum = 0; | |
83 | ||
84 | while (len--) | |
85 | sum += *mp++; | |
86 | ||
87 | return sum & 0xFF; | |
88 | } | |
89 | ||
51f62e18 | 90 | static void __cpuinit MP_processor_info (struct mpc_config_processor *m) |
1da177e4 | 91 | { |
8893166f | 92 | int cpu; |
51f62e18 | 93 | cpumask_t tmp_map; |
f2c2cca3 | 94 | char *bootup_cpu = ""; |
1da177e4 | 95 | |
420f8f68 AK |
96 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
97 | disabled_cpus++; | |
1da177e4 | 98 | return; |
420f8f68 | 99 | } |
1da177e4 | 100 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
f2c2cca3 | 101 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 LT |
102 | boot_cpu_id = m->mpc_apicid; |
103 | } | |
f2c2cca3 AK |
104 | |
105 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
106 | ||
1da177e4 LT |
107 | if (num_processors >= NR_CPUS) { |
108 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
109 | " Processor ignored.\n", NR_CPUS); | |
110 | return; | |
111 | } | |
1da177e4 | 112 | |
51f62e18 AR |
113 | num_processors++; |
114 | cpus_complement(tmp_map, cpu_present_map); | |
115 | cpu = first_cpu(tmp_map); | |
116 | ||
1da177e4 | 117 | physid_set(m->mpc_apicid, phys_cpu_present_map); |
18a2b647 AK |
118 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
119 | /* | |
120 | * bios_cpu_apicid is required to have processors listed | |
121 | * in same order as logical cpu numbers. Hence the first | |
122 | * entry is BSP, and so on. | |
123 | */ | |
61b1b2d0 | 124 | cpu = 0; |
51f62e18 | 125 | } |
61b1b2d0 AK |
126 | bios_cpu_apicid[cpu] = m->mpc_apicid; |
127 | x86_cpu_to_apicid[cpu] = m->mpc_apicid; | |
128 | ||
129 | cpu_set(cpu, cpu_possible_map); | |
130 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
131 | } |
132 | ||
133 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
134 | { | |
135 | char str[7]; | |
136 | ||
137 | memcpy(str, m->mpc_bustype, 6); | |
138 | str[6] = 0; | |
139 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
140 | ||
141 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 142 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 143 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 144 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
145 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
146 | mp_current_pci_id++; | |
1da177e4 LT |
147 | } else { |
148 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
149 | } | |
150 | } | |
151 | ||
013bf2c5 AK |
152 | static int bad_ioapic(unsigned long address) |
153 | { | |
154 | if (nr_ioapics >= MAX_IO_APICS) { | |
155 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
156 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
157 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
158 | } | |
159 | if (!address) { | |
160 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
161 | " found in table, skipping!\n"); | |
162 | return 1; | |
163 | } | |
164 | return 0; | |
165 | } | |
166 | ||
1da177e4 LT |
167 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
168 | { | |
169 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
170 | return; | |
171 | ||
f2c2cca3 AK |
172 | printk("I/O APIC #%d at 0x%X.\n", |
173 | m->mpc_apicid, m->mpc_apicaddr); | |
013bf2c5 AK |
174 | |
175 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 176 | return; |
013bf2c5 | 177 | |
1da177e4 LT |
178 | mp_ioapics[nr_ioapics] = *m; |
179 | nr_ioapics++; | |
180 | } | |
181 | ||
182 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
183 | { | |
184 | mp_irqs [mp_irq_entries] = *m; | |
185 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
186 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
187 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
188 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
189 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 190 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
191 | panic("Max # of irq sources exceeded!!\n"); |
192 | } | |
193 | ||
194 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
195 | { | |
196 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
197 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
198 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
199 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
200 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
201 | } |
202 | ||
203 | /* | |
204 | * Read/parse the MPC | |
205 | */ | |
206 | ||
207 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
208 | { | |
209 | char str[16]; | |
210 | int count=sizeof(*mpc); | |
211 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
212 | ||
213 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
aecc6361 | 214 | printk("MPTABLE: bad signature [%c%c%c%c]!\n", |
1da177e4 LT |
215 | mpc->mpc_signature[0], |
216 | mpc->mpc_signature[1], | |
217 | mpc->mpc_signature[2], | |
218 | mpc->mpc_signature[3]); | |
219 | return 0; | |
220 | } | |
221 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
aecc6361 | 222 | printk("MPTABLE: checksum error!\n"); |
1da177e4 LT |
223 | return 0; |
224 | } | |
225 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
aecc6361 | 226 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
1da177e4 LT |
227 | mpc->mpc_spec); |
228 | return 0; | |
229 | } | |
230 | if (!mpc->mpc_lapic) { | |
aecc6361 | 231 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
232 | return 0; |
233 | } | |
234 | memcpy(str,mpc->mpc_oem,8); | |
aecc6361 AK |
235 | str[8] = 0; |
236 | printk(KERN_INFO "MPTABLE: OEM ID: %s ",str); | |
1da177e4 LT |
237 | |
238 | memcpy(str,mpc->mpc_productid,12); | |
aecc6361 AK |
239 | str[12] = 0; |
240 | printk("MPTABLE: Product ID: %s ",str); | |
1da177e4 | 241 | |
aecc6361 | 242 | printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic); |
1da177e4 LT |
243 | |
244 | /* save the local APIC address, it might be non-default */ | |
245 | if (!acpi_lapic) | |
aecc6361 | 246 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 LT |
247 | |
248 | /* | |
249 | * Now process the configuration blocks. | |
250 | */ | |
251 | while (count < mpc->mpc_length) { | |
252 | switch(*mpt) { | |
253 | case MP_PROCESSOR: | |
254 | { | |
255 | struct mpc_config_processor *m= | |
256 | (struct mpc_config_processor *)mpt; | |
257 | if (!acpi_lapic) | |
aecc6361 | 258 | MP_processor_info(m); |
1da177e4 LT |
259 | mpt += sizeof(*m); |
260 | count += sizeof(*m); | |
261 | break; | |
262 | } | |
263 | case MP_BUS: | |
264 | { | |
265 | struct mpc_config_bus *m= | |
266 | (struct mpc_config_bus *)mpt; | |
267 | MP_bus_info(m); | |
268 | mpt += sizeof(*m); | |
269 | count += sizeof(*m); | |
270 | break; | |
271 | } | |
272 | case MP_IOAPIC: | |
273 | { | |
274 | struct mpc_config_ioapic *m= | |
275 | (struct mpc_config_ioapic *)mpt; | |
276 | MP_ioapic_info(m); | |
aecc6361 AK |
277 | mpt += sizeof(*m); |
278 | count += sizeof(*m); | |
1da177e4 LT |
279 | break; |
280 | } | |
281 | case MP_INTSRC: | |
282 | { | |
283 | struct mpc_config_intsrc *m= | |
284 | (struct mpc_config_intsrc *)mpt; | |
285 | ||
286 | MP_intsrc_info(m); | |
aecc6361 AK |
287 | mpt += sizeof(*m); |
288 | count += sizeof(*m); | |
1da177e4 LT |
289 | break; |
290 | } | |
291 | case MP_LINTSRC: | |
292 | { | |
293 | struct mpc_config_lintsrc *m= | |
294 | (struct mpc_config_lintsrc *)mpt; | |
295 | MP_lintsrc_info(m); | |
aecc6361 AK |
296 | mpt += sizeof(*m); |
297 | count += sizeof(*m); | |
1da177e4 LT |
298 | break; |
299 | } | |
300 | } | |
301 | } | |
3c43f039 | 302 | setup_apic_routing(); |
1da177e4 | 303 | if (!num_processors) |
aecc6361 | 304 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
305 | return num_processors; |
306 | } | |
307 | ||
308 | static int __init ELCR_trigger(unsigned int irq) | |
309 | { | |
310 | unsigned int port; | |
311 | ||
312 | port = 0x4d0 + (irq >> 3); | |
313 | return (inb(port) >> (irq & 7)) & 1; | |
314 | } | |
315 | ||
316 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
317 | { | |
318 | struct mpc_config_intsrc intsrc; | |
319 | int i; | |
320 | int ELCR_fallback = 0; | |
321 | ||
322 | intsrc.mpc_type = MP_INTSRC; | |
323 | intsrc.mpc_irqflag = 0; /* conforming */ | |
324 | intsrc.mpc_srcbus = 0; | |
325 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
326 | ||
327 | intsrc.mpc_irqtype = mp_INT; | |
328 | ||
329 | /* | |
330 | * If true, we have an ISA/PCI system with no IRQ entries | |
331 | * in the MP table. To prevent the PCI interrupts from being set up | |
332 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
333 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
334 | * never be level sensitive, so we simply see if the ELCR agrees. | |
335 | * If it does, we assume it's valid. | |
336 | */ | |
337 | if (mpc_default_type == 5) { | |
338 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
339 | ||
340 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
341 | printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n"); | |
342 | else { | |
343 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
344 | ELCR_fallback = 1; | |
345 | } | |
346 | } | |
347 | ||
348 | for (i = 0; i < 16; i++) { | |
349 | switch (mpc_default_type) { | |
350 | case 2: | |
351 | if (i == 0 || i == 13) | |
352 | continue; /* IRQ0 & IRQ13 not connected */ | |
353 | /* fall through */ | |
354 | default: | |
355 | if (i == 2) | |
356 | continue; /* IRQ2 is never connected */ | |
357 | } | |
358 | ||
359 | if (ELCR_fallback) { | |
360 | /* | |
361 | * If the ELCR indicates a level-sensitive interrupt, we | |
362 | * copy that information over to the MP table in the | |
363 | * irqflag field (level sensitive, active high polarity). | |
364 | */ | |
365 | if (ELCR_trigger(i)) | |
366 | intsrc.mpc_irqflag = 13; | |
367 | else | |
368 | intsrc.mpc_irqflag = 0; | |
369 | } | |
370 | ||
371 | intsrc.mpc_srcbusirq = i; | |
372 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
373 | MP_intsrc_info(&intsrc); | |
374 | } | |
375 | ||
376 | intsrc.mpc_irqtype = mp_ExtINT; | |
377 | intsrc.mpc_srcbusirq = 0; | |
378 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
379 | MP_intsrc_info(&intsrc); | |
380 | } | |
381 | ||
382 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
383 | { | |
384 | struct mpc_config_processor processor; | |
385 | struct mpc_config_bus bus; | |
386 | struct mpc_config_ioapic ioapic; | |
387 | struct mpc_config_lintsrc lintsrc; | |
388 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
389 | int i; | |
390 | ||
391 | /* | |
392 | * local APIC has default address | |
393 | */ | |
394 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
395 | ||
396 | /* | |
397 | * 2 CPUs, numbered 0 & 1. | |
398 | */ | |
399 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 400 | processor.mpc_apicver = 0; |
1da177e4 | 401 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
402 | processor.mpc_cpufeature = 0; |
403 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
404 | processor.mpc_reserved[0] = 0; |
405 | processor.mpc_reserved[1] = 0; | |
406 | for (i = 0; i < 2; i++) { | |
407 | processor.mpc_apicid = i; | |
408 | MP_processor_info(&processor); | |
409 | } | |
410 | ||
411 | bus.mpc_type = MP_BUS; | |
412 | bus.mpc_busid = 0; | |
413 | switch (mpc_default_type) { | |
414 | default: | |
415 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
416 | mpc_default_type); | |
417 | /* fall through */ | |
418 | case 1: | |
419 | case 5: | |
420 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
421 | break; | |
1da177e4 LT |
422 | } |
423 | MP_bus_info(&bus); | |
424 | if (mpc_default_type > 4) { | |
425 | bus.mpc_busid = 1; | |
426 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
427 | MP_bus_info(&bus); | |
428 | } | |
429 | ||
430 | ioapic.mpc_type = MP_IOAPIC; | |
431 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 432 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
433 | ioapic.mpc_flags = MPC_APIC_USABLE; |
434 | ioapic.mpc_apicaddr = 0xFEC00000; | |
435 | MP_ioapic_info(&ioapic); | |
436 | ||
437 | /* | |
438 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
439 | */ | |
440 | construct_default_ioirq_mptable(mpc_default_type); | |
441 | ||
442 | lintsrc.mpc_type = MP_LINTSRC; | |
443 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
444 | lintsrc.mpc_srcbusid = 0; | |
445 | lintsrc.mpc_srcbusirq = 0; | |
446 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
447 | for (i = 0; i < 2; i++) { | |
448 | lintsrc.mpc_irqtype = linttypes[i]; | |
449 | lintsrc.mpc_destapiclint = i; | |
450 | MP_lintsrc_info(&lintsrc); | |
451 | } | |
452 | } | |
453 | ||
454 | static struct intel_mp_floating *mpf_found; | |
455 | ||
456 | /* | |
457 | * Scan the memory blocks for an SMP configuration block. | |
458 | */ | |
459 | void __init get_smp_config (void) | |
460 | { | |
461 | struct intel_mp_floating *mpf = mpf_found; | |
462 | ||
463 | /* | |
1da177e4 LT |
464 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
465 | * processors, where MPS only supports physical. | |
466 | */ | |
467 | if (acpi_lapic && acpi_ioapic) { | |
468 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
469 | return; | |
470 | } | |
471 | else if (acpi_lapic) | |
472 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
473 | ||
474 | printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
1da177e4 LT |
475 | |
476 | /* | |
477 | * Now see if we need to read further. | |
478 | */ | |
479 | if (mpf->mpf_feature1 != 0) { | |
480 | ||
481 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
482 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
483 | ||
484 | } else if (mpf->mpf_physptr) { | |
485 | ||
486 | /* | |
487 | * Read the physical hardware table. Anything here will | |
488 | * override the defaults. | |
489 | */ | |
f6c2e333 | 490 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
491 | smp_found_config = 0; |
492 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
493 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
494 | return; | |
495 | } | |
496 | /* | |
497 | * If there are no explicit MP IRQ entries, then we are | |
498 | * broken. We set up most of the low 16 IO-APIC pins to | |
499 | * ISA defaults and hope it will work. | |
500 | */ | |
501 | if (!mp_irq_entries) { | |
502 | struct mpc_config_bus bus; | |
503 | ||
504 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
505 | ||
506 | bus.mpc_type = MP_BUS; | |
507 | bus.mpc_busid = 0; | |
508 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
509 | MP_bus_info(&bus); | |
510 | ||
511 | construct_default_ioirq_mptable(0); | |
512 | } | |
513 | ||
514 | } else | |
515 | BUG(); | |
516 | ||
517 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
518 | /* | |
519 | * Only use the first configuration found. | |
520 | */ | |
521 | } | |
522 | ||
523 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
524 | { | |
525 | extern void __bad_mpf_size(void); | |
526 | unsigned int *bp = phys_to_virt(base); | |
527 | struct intel_mp_floating *mpf; | |
528 | ||
529 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); | |
530 | if (sizeof(*mpf) != 16) | |
531 | __bad_mpf_size(); | |
532 | ||
533 | while (length > 0) { | |
534 | mpf = (struct intel_mp_floating *)bp; | |
535 | if ((*bp == SMP_MAGIC_IDENT) && | |
536 | (mpf->mpf_length == 1) && | |
537 | !mpf_checksum((unsigned char *)bp, 16) && | |
538 | ((mpf->mpf_specification == 1) | |
539 | || (mpf->mpf_specification == 4)) ) { | |
540 | ||
541 | smp_found_config = 1; | |
542 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); | |
543 | if (mpf->mpf_physptr) | |
544 | reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE); | |
545 | mpf_found = mpf; | |
546 | return 1; | |
547 | } | |
548 | bp += 4; | |
549 | length -= 16; | |
550 | } | |
551 | return 0; | |
552 | } | |
553 | ||
a01fd3ba | 554 | void __init find_smp_config(void) |
1da177e4 LT |
555 | { |
556 | unsigned int address; | |
557 | ||
558 | /* | |
559 | * FIXME: Linux assumes you have 640K of base ram.. | |
560 | * this continues the error... | |
561 | * | |
562 | * 1) Scan the bottom 1K for a signature | |
563 | * 2) Scan the top 1K of base RAM | |
564 | * 3) Scan the 64K of bios | |
565 | */ | |
566 | if (smp_scan_config(0x0,0x400) || | |
567 | smp_scan_config(639*0x400,0x400) || | |
568 | smp_scan_config(0xF0000,0x10000)) | |
569 | return; | |
570 | /* | |
e5099134 | 571 | * If it is an SMP machine we should know now. |
1da177e4 LT |
572 | * |
573 | * there is a real-mode segmented pointer pointing to the | |
574 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
575 | * | |
576 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
577 | * area, and as such this kind of SMP config may be less | |
578 | * trustworthy, simply because the SMP table may have been | |
579 | * stomped on during early boot. These loaders are buggy and | |
580 | * should be fixed. | |
581 | */ | |
582 | ||
583 | address = *(unsigned short *)phys_to_virt(0x40E); | |
584 | address <<= 4; | |
585 | if (smp_scan_config(address, 0x1000)) | |
586 | return; | |
587 | ||
588 | /* If we have come this far, we did not find an MP table */ | |
589 | printk(KERN_INFO "No mptable found.\n"); | |
590 | } | |
591 | ||
1da177e4 LT |
592 | /* -------------------------------------------------------------------------- |
593 | ACPI-based MP Configuration | |
594 | -------------------------------------------------------------------------- */ | |
595 | ||
888ba6c6 | 596 | #ifdef CONFIG_ACPI |
1da177e4 | 597 | |
efec3b9a | 598 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
599 | { |
600 | mp_lapic_addr = (unsigned long) address; | |
1da177e4 | 601 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
1da177e4 LT |
602 | if (boot_cpu_id == -1U) |
603 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
604 | } |
605 | ||
efec3b9a | 606 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
607 | { |
608 | struct mpc_config_processor processor; | |
609 | int boot_cpu = 0; | |
610 | ||
e4251e13 | 611 | if (id == boot_cpu_id) |
1da177e4 LT |
612 | boot_cpu = 1; |
613 | ||
614 | processor.mpc_type = MP_PROCESSOR; | |
615 | processor.mpc_apicid = id; | |
f2c2cca3 | 616 | processor.mpc_apicver = 0; |
1da177e4 LT |
617 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
618 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
f2c2cca3 AK |
619 | processor.mpc_cpufeature = 0; |
620 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
621 | processor.mpc_reserved[0] = 0; |
622 | processor.mpc_reserved[1] = 0; | |
623 | ||
624 | MP_processor_info(&processor); | |
625 | } | |
626 | ||
1da177e4 LT |
627 | #define MP_ISA_BUS 0 |
628 | #define MP_MAX_IOAPIC_PIN 127 | |
629 | ||
630 | static struct mp_ioapic_routing { | |
631 | int apic_id; | |
632 | int gsi_start; | |
633 | int gsi_end; | |
634 | u32 pin_programmed[4]; | |
635 | } mp_ioapic_routing[MAX_IO_APICS]; | |
636 | ||
efec3b9a | 637 | static int mp_find_ioapic(int gsi) |
1da177e4 | 638 | { |
efec3b9a | 639 | int i = 0; |
1da177e4 LT |
640 | |
641 | /* Find the IOAPIC that manages this GSI. */ | |
642 | for (i = 0; i < nr_ioapics; i++) { | |
643 | if ((gsi >= mp_ioapic_routing[i].gsi_start) | |
644 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
645 | return i; | |
646 | } | |
647 | ||
648 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
649 | return -1; |
650 | } | |
1da177e4 | 651 | |
efec3b9a | 652 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 653 | { |
efec3b9a | 654 | int idx = 0; |
1da177e4 | 655 | |
013bf2c5 | 656 | if (bad_ioapic(address)) |
1da177e4 | 657 | return; |
1da177e4 LT |
658 | |
659 | idx = nr_ioapics++; | |
660 | ||
661 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
662 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
663 | mp_ioapics[idx].mpc_apicaddr = address; | |
664 | ||
665 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
0af2be0b | 666 | mp_ioapics[idx].mpc_apicid = id; |
f2c2cca3 | 667 | mp_ioapics[idx].mpc_apicver = 0; |
1da177e4 LT |
668 | |
669 | /* | |
670 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
671 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
672 | */ | |
673 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
674 | mp_ioapic_routing[idx].gsi_start = gsi_base; | |
675 | mp_ioapic_routing[idx].gsi_end = gsi_base + | |
676 | io_apic_get_redir_entries(idx); | |
677 | ||
f2c2cca3 | 678 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
1da177e4 | 679 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
f2c2cca3 | 680 | mp_ioapics[idx].mpc_apicaddr, |
1da177e4 LT |
681 | mp_ioapic_routing[idx].gsi_start, |
682 | mp_ioapic_routing[idx].gsi_end); | |
1da177e4 LT |
683 | } |
684 | ||
efec3b9a AK |
685 | void __init |
686 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
687 | { |
688 | struct mpc_config_intsrc intsrc; | |
689 | int ioapic = -1; | |
690 | int pin = -1; | |
691 | ||
692 | /* | |
693 | * Convert 'gsi' to 'ioapic.pin'. | |
694 | */ | |
695 | ioapic = mp_find_ioapic(gsi); | |
696 | if (ioapic < 0) | |
697 | return; | |
698 | pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
699 | ||
700 | /* | |
701 | * TBD: This check is for faulty timer entries, where the override | |
702 | * erroneously sets the trigger to level, resulting in a HUGE | |
703 | * increase of timer interrupts! | |
704 | */ | |
705 | if ((bus_irq == 0) && (trigger == 3)) | |
706 | trigger = 1; | |
707 | ||
708 | intsrc.mpc_type = MP_INTSRC; | |
709 | intsrc.mpc_irqtype = mp_INT; | |
710 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
711 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
712 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
713 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
714 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
715 | ||
716 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
717 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
718 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
719 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
720 | ||
721 | mp_irqs[mp_irq_entries] = intsrc; | |
722 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
723 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
724 | } |
725 | ||
efec3b9a | 726 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
727 | { |
728 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
729 | int i = 0; |
730 | int ioapic = -1; | |
1da177e4 LT |
731 | |
732 | /* | |
733 | * Fabricate the legacy ISA bus (bus #31). | |
734 | */ | |
55f05ffa | 735 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
736 | |
737 | /* | |
738 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
739 | */ | |
740 | ioapic = mp_find_ioapic(0); | |
741 | if (ioapic < 0) | |
742 | return; | |
743 | ||
744 | intsrc.mpc_type = MP_INTSRC; | |
745 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
746 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
747 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
748 | ||
749 | /* | |
750 | * Use the default configuration for the IRQs 0-15. Unless | |
751 | * overridden by (MADT) interrupt source override entries. | |
752 | */ | |
753 | for (i = 0; i < 16; i++) { | |
754 | int idx; | |
755 | ||
756 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
757 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
758 | ||
759 | /* Do we already have a mapping for this ISA IRQ? */ | |
760 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
761 | break; | |
762 | ||
763 | /* Do we already have a mapping for this IOAPIC pin */ | |
764 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
765 | (irq->mpc_dstirq == i)) | |
766 | break; | |
767 | } | |
768 | ||
769 | if (idx != mp_irq_entries) { | |
770 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
771 | continue; /* IRQ already used */ | |
772 | } | |
773 | ||
774 | intsrc.mpc_irqtype = mp_INT; | |
775 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
776 | intsrc.mpc_dstirq = i; | |
777 | ||
778 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
779 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
780 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
781 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
782 | intsrc.mpc_dstirq); | |
783 | ||
784 | mp_irqs[mp_irq_entries] = intsrc; | |
785 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
786 | panic("Max # of irq sources exceeded!\n"); | |
787 | } | |
1da177e4 LT |
788 | } |
789 | ||
50eca3eb | 790 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 791 | { |
efec3b9a AK |
792 | int ioapic = -1; |
793 | int ioapic_pin = 0; | |
794 | int idx, bit = 0; | |
1da177e4 LT |
795 | |
796 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
797 | return gsi; | |
798 | ||
1da177e4 | 799 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 800 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 801 | return gsi; |
1da177e4 LT |
802 | |
803 | ioapic = mp_find_ioapic(gsi); | |
804 | if (ioapic < 0) { | |
805 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
806 | return gsi; | |
807 | } | |
808 | ||
809 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
810 | ||
811 | /* | |
812 | * Avoid pin reprogramming. PRTs typically include entries | |
813 | * with redundant pin->gsi mappings (but unique PCI devices); | |
814 | * we only program the IOAPIC on the first. | |
815 | */ | |
816 | bit = ioapic_pin % 32; | |
817 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
818 | if (idx > 3) { | |
819 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
820 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
821 | ioapic_pin); | |
822 | return gsi; | |
823 | } | |
824 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
825 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
826 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 827 | return gsi; |
1da177e4 LT |
828 | } |
829 | ||
830 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
831 | ||
832 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
50eca3eb BM |
833 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
834 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
835 | return gsi; |
836 | } | |
888ba6c6 | 837 | #endif /*CONFIG_ACPI*/ |