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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/calgary.h> | |
40 | #include <asm/tce.h> | |
41 | #include <asm/pci-direct.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/dma.h> | |
b34e90b8 | 44 | #include <asm/rio.h> |
e465058d | 45 | |
bff6547b MBY |
46 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
47 | int use_calgary __read_mostly = 1; | |
48 | #else | |
49 | int use_calgary __read_mostly = 0; | |
50 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
51 | ||
e465058d | 52 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 53 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d | 54 | |
e465058d | 55 | /* register offsets inside the host bridge space */ |
cb01fc72 MBY |
56 | #define CALGARY_CONFIG_REG 0x0108 |
57 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
58 | #define PHB_PLSSR_OFFSET 0x0120 |
59 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
60 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
61 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
62 | #define PHB_MEM_1_LOW 0x0190 | |
63 | #define PHB_MEM_1_HIGH 0x01A0 | |
64 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
65 | #define PHB_MEM_1_SIZE 0x01C0 | |
66 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
67 | #define PHB_AER_OFFSET 0x0200 | |
68 | #define PHB_CONFIG_0_HIGH 0x0220 | |
69 | #define PHB_CONFIG_0_LOW 0x0230 | |
70 | #define PHB_CONFIG_0_END 0x0240 | |
71 | #define PHB_MEM_2_LOW 0x02B0 | |
72 | #define PHB_MEM_2_HIGH 0x02C0 | |
73 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
74 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
75 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
76 | ||
c3860108 | 77 | /* CalIOC2 specific */ |
8bcf7705 MBY |
78 | #define PHB_SAVIOR_L2 0x0DB0 |
79 | #define PHB_PAGE_MIG_CTRL 0x0DA8 | |
80 | #define PHB_PAGE_MIG_DEBUG 0x0DA0 | |
8cb32dc7 | 81 | #define PHB_ROOT_COMPLEX_STATUS 0x0CB0 |
c3860108 | 82 | |
e465058d JM |
83 | /* PHB_CONFIG_RW */ |
84 | #define PHB_TCE_ENABLE 0x20000000 | |
85 | #define PHB_SLOT_DISABLE 0x1C000000 | |
86 | #define PHB_DAC_DISABLE 0x01000000 | |
87 | #define PHB_MEM2_ENABLE 0x00400000 | |
88 | #define PHB_MCSR_ENABLE 0x00100000 | |
89 | /* TAR (Table Address Register) */ | |
90 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
91 | #define TAR_VALID 0x0000000000000008UL | |
92 | /* CSR (Channel/DMA Status Register) */ | |
93 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 | 94 | /* CCR (Calgary Configuration Register) */ |
8bcf7705 | 95 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL |
00be3fa4 | 96 | /* PMCR/PMDR (Page Migration Control/Debug Registers */ |
8bcf7705 MBY |
97 | #define PMR_SOFTSTOP 0x80000000 |
98 | #define PMR_SOFTSTOPFAULT 0x40000000 | |
99 | #define PMR_HARDSTOP 0x20000000 | |
e465058d JM |
100 | |
101 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 102 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
103 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
104 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
105 | #define PHBS_PER_CALGARY 4 |
106 | ||
107 | /* register offsets in Calgary's internal register space */ | |
108 | static const unsigned long tar_offsets[] = { | |
109 | 0x0580 /* TAR0 */, | |
110 | 0x0588 /* TAR1 */, | |
111 | 0x0590 /* TAR2 */, | |
112 | 0x0598 /* TAR3 */ | |
113 | }; | |
114 | ||
115 | static const unsigned long split_queue_offsets[] = { | |
116 | 0x4870 /* SPLIT QUEUE 0 */, | |
117 | 0x5870 /* SPLIT QUEUE 1 */, | |
118 | 0x6870 /* SPLIT QUEUE 2 */, | |
119 | 0x7870 /* SPLIT QUEUE 3 */ | |
120 | }; | |
121 | ||
122 | static const unsigned long phb_offsets[] = { | |
123 | 0x8000 /* PHB0 */, | |
124 | 0x9000 /* PHB1 */, | |
125 | 0xA000 /* PHB2 */, | |
126 | 0xB000 /* PHB3 */ | |
127 | }; | |
128 | ||
b34e90b8 LV |
129 | /* PHB debug registers */ |
130 | ||
131 | static const unsigned long phb_debug_offsets[] = { | |
132 | 0x4000 /* PHB 0 DEBUG */, | |
133 | 0x5000 /* PHB 1 DEBUG */, | |
134 | 0x6000 /* PHB 2 DEBUG */, | |
135 | 0x7000 /* PHB 3 DEBUG */ | |
136 | }; | |
137 | ||
138 | /* | |
139 | * STUFF register for each debug PHB, | |
140 | * byte 1 = start bus number, byte 2 = end bus number | |
141 | */ | |
142 | ||
143 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
144 | ||
310adfdd MBY |
145 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
146 | ||
e465058d JM |
147 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
148 | static int translate_empty_slots __read_mostly = 0; | |
149 | static int calgary_detected __read_mostly = 0; | |
150 | ||
b34e90b8 LV |
151 | static struct rio_table_hdr *rio_table_hdr __initdata; |
152 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 153 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 154 | |
f38db651 MBY |
155 | struct calgary_bus_info { |
156 | void *tce_space; | |
0577f148 | 157 | unsigned char translation_disabled; |
f38db651 | 158 | signed char phbid; |
b34e90b8 | 159 | void __iomem *bbar; |
f38db651 MBY |
160 | }; |
161 | ||
ff297b8c MBY |
162 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
163 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
8cb32dc7 | 164 | static void calgary_dump_error_regs(struct iommu_table *tbl); |
c3860108 | 165 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
00be3fa4 | 166 | static void calioc2_tce_cache_blast(struct iommu_table *tbl); |
8cb32dc7 | 167 | static void calioc2_dump_error_regs(struct iommu_table *tbl); |
ff297b8c MBY |
168 | |
169 | static struct cal_chipset_ops calgary_chip_ops = { | |
170 | .handle_quirks = calgary_handle_quirks, | |
8cb32dc7 MBY |
171 | .tce_cache_blast = calgary_tce_cache_blast, |
172 | .dump_error_regs = calgary_dump_error_regs | |
ff297b8c | 173 | }; |
e465058d | 174 | |
c3860108 MBY |
175 | static struct cal_chipset_ops calioc2_chip_ops = { |
176 | .handle_quirks = calioc2_handle_quirks, | |
8cb32dc7 MBY |
177 | .tce_cache_blast = calioc2_tce_cache_blast, |
178 | .dump_error_regs = calioc2_dump_error_regs | |
c3860108 MBY |
179 | }; |
180 | ||
ff297b8c | 181 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
182 | |
183 | /* enable this to stress test the chip's TCE cache */ | |
184 | #ifdef CONFIG_IOMMU_DEBUG | |
de684652 MBY |
185 | int debugging __read_mostly = 1; |
186 | ||
796e4390 MBY |
187 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
188 | int expected, unsigned long start, unsigned long end) | |
189 | { | |
190 | unsigned long idx = start; | |
191 | ||
192 | BUG_ON(start >= end); | |
193 | ||
194 | while (idx < end) { | |
195 | if (!!test_bit(idx, bitmap) != expected) | |
196 | return idx; | |
197 | ++idx; | |
198 | } | |
199 | ||
200 | /* all bits have the expected value */ | |
201 | return ~0UL; | |
202 | } | |
de684652 MBY |
203 | #else /* debugging is disabled */ |
204 | int debugging __read_mostly = 0; | |
205 | ||
796e4390 MBY |
206 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
207 | int expected, unsigned long start, unsigned long end) | |
208 | { | |
209 | return ~0UL; | |
210 | } | |
8a244590 | 211 | |
de684652 | 212 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
213 | |
214 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
215 | { | |
216 | unsigned int npages; | |
217 | ||
218 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
219 | npages >>= PAGE_SHIFT; | |
220 | ||
221 | return npages; | |
222 | } | |
223 | ||
224 | static inline int translate_phb(struct pci_dev* dev) | |
225 | { | |
f38db651 | 226 | int disabled = bus_info[dev->bus->number].translation_disabled; |
e465058d JM |
227 | return !disabled; |
228 | } | |
229 | ||
230 | static void iommu_range_reserve(struct iommu_table *tbl, | |
8bcf7705 | 231 | unsigned long start_addr, unsigned int npages) |
e465058d JM |
232 | { |
233 | unsigned long index; | |
234 | unsigned long end; | |
796e4390 | 235 | unsigned long badbit; |
e465058d JM |
236 | |
237 | index = start_addr >> PAGE_SHIFT; | |
238 | ||
239 | /* bail out if we're asked to reserve a region we don't cover */ | |
240 | if (index >= tbl->it_size) | |
241 | return; | |
242 | ||
243 | end = index + npages; | |
244 | if (end > tbl->it_size) /* don't go off the table */ | |
245 | end = tbl->it_size; | |
246 | ||
796e4390 MBY |
247 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
248 | if (badbit != ~0UL) { | |
249 | if (printk_ratelimit()) | |
e465058d JM |
250 | printk(KERN_ERR "Calgary: entry already allocated at " |
251 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 252 | badbit, tbl, start_addr, npages); |
e465058d | 253 | } |
796e4390 MBY |
254 | |
255 | set_bit_string(tbl->it_map, index, npages); | |
e465058d JM |
256 | } |
257 | ||
258 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
259 | unsigned int npages) | |
260 | { | |
261 | unsigned long offset; | |
262 | ||
263 | BUG_ON(npages == 0); | |
264 | ||
265 | offset = find_next_zero_string(tbl->it_map, tbl->it_hint, | |
266 | tbl->it_size, npages); | |
267 | if (offset == ~0UL) { | |
ff297b8c | 268 | tbl->chip_ops->tce_cache_blast(tbl); |
e465058d JM |
269 | offset = find_next_zero_string(tbl->it_map, 0, |
270 | tbl->it_size, npages); | |
271 | if (offset == ~0UL) { | |
272 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
273 | if (panic_on_overflow) | |
274 | panic("Calgary: fix the allocator.\n"); | |
275 | else | |
276 | return bad_dma_address; | |
277 | } | |
278 | } | |
279 | ||
280 | set_bit_string(tbl->it_map, offset, npages); | |
281 | tbl->it_hint = offset + npages; | |
282 | BUG_ON(tbl->it_hint > tbl->it_size); | |
283 | ||
284 | return offset; | |
285 | } | |
286 | ||
287 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr, | |
288 | unsigned int npages, int direction) | |
289 | { | |
290 | unsigned long entry, flags; | |
291 | dma_addr_t ret = bad_dma_address; | |
292 | ||
293 | spin_lock_irqsave(&tbl->it_lock, flags); | |
294 | ||
295 | entry = iommu_range_alloc(tbl, npages); | |
296 | ||
297 | if (unlikely(entry == bad_dma_address)) | |
298 | goto error; | |
299 | ||
300 | /* set the return dma address */ | |
301 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
302 | ||
303 | /* put the TCEs in the HW table */ | |
304 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
305 | direction); | |
306 | ||
307 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
308 | ||
309 | return ret; | |
310 | ||
311 | error: | |
312 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
313 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | |
314 | "iommu %p\n", npages, tbl); | |
315 | return bad_dma_address; | |
316 | } | |
317 | ||
318 | static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
319 | unsigned int npages) | |
320 | { | |
321 | unsigned long entry; | |
796e4390 | 322 | unsigned long badbit; |
310adfdd MBY |
323 | unsigned long badend; |
324 | ||
325 | /* were we called with bad_dma_address? */ | |
326 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
327 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
328 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
329 | "address 0x%Lx\n", dma_addr); | |
330 | WARN_ON(1); | |
331 | return; | |
332 | } | |
e465058d JM |
333 | |
334 | entry = dma_addr >> PAGE_SHIFT; | |
335 | ||
336 | BUG_ON(entry + npages > tbl->it_size); | |
337 | ||
338 | tce_free(tbl, entry, npages); | |
339 | ||
796e4390 MBY |
340 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
341 | if (badbit != ~0UL) { | |
342 | if (printk_ratelimit()) | |
e465058d JM |
343 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
344 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 345 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
346 | } |
347 | ||
348 | __clear_bit_string(tbl->it_map, entry, npages); | |
e465058d JM |
349 | } |
350 | ||
351 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
352 | unsigned int npages) | |
353 | { | |
354 | unsigned long flags; | |
355 | ||
356 | spin_lock_irqsave(&tbl->it_lock, flags); | |
357 | ||
358 | __iommu_free(tbl, dma_addr, npages); | |
359 | ||
360 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
361 | } | |
362 | ||
35b6dfa0 MBY |
363 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
364 | { | |
8a244590 MBY |
365 | struct pci_dev *pdev; |
366 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
367 | struct iommu_table *tbl; |
368 | ||
8a244590 MBY |
369 | pdev = to_pci_dev(dev); |
370 | ||
371 | /* is the device behind a bridge? */ | |
372 | if (unlikely(pdev->bus->parent)) | |
373 | pbus = pdev->bus->parent; | |
374 | else | |
375 | pbus = pdev->bus; | |
376 | ||
377 | tbl = pbus->self->sysdata; | |
7354b075 MBY |
378 | |
379 | BUG_ON(pdev->bus->parent && | |
380 | (tbl->it_busno != pdev->bus->parent->number)); | |
35b6dfa0 MBY |
381 | |
382 | return tbl; | |
383 | } | |
384 | ||
e465058d JM |
385 | static void __calgary_unmap_sg(struct iommu_table *tbl, |
386 | struct scatterlist *sglist, int nelems, int direction) | |
387 | { | |
388 | while (nelems--) { | |
389 | unsigned int npages; | |
390 | dma_addr_t dma = sglist->dma_address; | |
391 | unsigned int dmalen = sglist->dma_length; | |
392 | ||
393 | if (dmalen == 0) | |
394 | break; | |
395 | ||
396 | npages = num_dma_pages(dma, dmalen); | |
397 | __iommu_free(tbl, dma, npages); | |
398 | sglist++; | |
399 | } | |
400 | } | |
401 | ||
402 | void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, | |
403 | int nelems, int direction) | |
404 | { | |
405 | unsigned long flags; | |
35b6dfa0 | 406 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
407 | |
408 | if (!translate_phb(to_pci_dev(dev))) | |
409 | return; | |
410 | ||
411 | spin_lock_irqsave(&tbl->it_lock, flags); | |
412 | ||
413 | __calgary_unmap_sg(tbl, sglist, nelems, direction); | |
414 | ||
415 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
416 | } | |
417 | ||
418 | static int calgary_nontranslate_map_sg(struct device* dev, | |
419 | struct scatterlist *sg, int nelems, int direction) | |
420 | { | |
421 | int i; | |
422 | ||
8bcf7705 | 423 | for (i = 0; i < nelems; i++ ) { |
e465058d JM |
424 | struct scatterlist *s = &sg[i]; |
425 | BUG_ON(!s->page); | |
426 | s->dma_address = virt_to_bus(page_address(s->page) +s->offset); | |
427 | s->dma_length = s->length; | |
428 | } | |
429 | return nelems; | |
430 | } | |
431 | ||
432 | int calgary_map_sg(struct device *dev, struct scatterlist *sg, | |
433 | int nelems, int direction) | |
434 | { | |
35b6dfa0 | 435 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
436 | unsigned long flags; |
437 | unsigned long vaddr; | |
438 | unsigned int npages; | |
439 | unsigned long entry; | |
440 | int i; | |
441 | ||
442 | if (!translate_phb(to_pci_dev(dev))) | |
443 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); | |
444 | ||
445 | spin_lock_irqsave(&tbl->it_lock, flags); | |
446 | ||
447 | for (i = 0; i < nelems; i++ ) { | |
448 | struct scatterlist *s = &sg[i]; | |
449 | BUG_ON(!s->page); | |
450 | ||
451 | vaddr = (unsigned long)page_address(s->page) + s->offset; | |
452 | npages = num_dma_pages(vaddr, s->length); | |
453 | ||
454 | entry = iommu_range_alloc(tbl, npages); | |
455 | if (entry == bad_dma_address) { | |
456 | /* makes sure unmap knows to stop */ | |
457 | s->dma_length = 0; | |
458 | goto error; | |
459 | } | |
460 | ||
461 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
462 | ||
463 | /* insert into HW table */ | |
464 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
465 | direction); | |
466 | ||
467 | s->dma_length = s->length; | |
468 | } | |
469 | ||
470 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
471 | ||
472 | return nelems; | |
473 | error: | |
474 | __calgary_unmap_sg(tbl, sg, nelems, direction); | |
475 | for (i = 0; i < nelems; i++) { | |
476 | sg[i].dma_address = bad_dma_address; | |
477 | sg[i].dma_length = 0; | |
478 | } | |
479 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
480 | return 0; | |
481 | } | |
482 | ||
483 | dma_addr_t calgary_map_single(struct device *dev, void *vaddr, | |
484 | size_t size, int direction) | |
485 | { | |
486 | dma_addr_t dma_handle = bad_dma_address; | |
487 | unsigned long uaddr; | |
488 | unsigned int npages; | |
35b6dfa0 | 489 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
490 | |
491 | uaddr = (unsigned long)vaddr; | |
492 | npages = num_dma_pages(uaddr, size); | |
493 | ||
494 | if (translate_phb(to_pci_dev(dev))) | |
495 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction); | |
496 | else | |
497 | dma_handle = virt_to_bus(vaddr); | |
498 | ||
499 | return dma_handle; | |
500 | } | |
501 | ||
502 | void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, | |
503 | size_t size, int direction) | |
504 | { | |
35b6dfa0 | 505 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
506 | unsigned int npages; |
507 | ||
508 | if (!translate_phb(to_pci_dev(dev))) | |
509 | return; | |
510 | ||
511 | npages = num_dma_pages(dma_handle, size); | |
512 | iommu_free(tbl, dma_handle, npages); | |
513 | } | |
514 | ||
515 | void* calgary_alloc_coherent(struct device *dev, size_t size, | |
516 | dma_addr_t *dma_handle, gfp_t flag) | |
517 | { | |
518 | void *ret = NULL; | |
519 | dma_addr_t mapping; | |
520 | unsigned int npages, order; | |
35b6dfa0 | 521 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
522 | |
523 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
524 | npages = size >> PAGE_SHIFT; | |
525 | order = get_order(size); | |
526 | ||
527 | /* alloc enough pages (and possibly more) */ | |
528 | ret = (void *)__get_free_pages(flag, order); | |
529 | if (!ret) | |
530 | goto error; | |
531 | memset(ret, 0, size); | |
532 | ||
533 | if (translate_phb(to_pci_dev(dev))) { | |
534 | /* set up tces to cover the allocated range */ | |
535 | mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL); | |
536 | if (mapping == bad_dma_address) | |
537 | goto free; | |
538 | ||
539 | *dma_handle = mapping; | |
540 | } else /* non translated slot */ | |
541 | *dma_handle = virt_to_bus(ret); | |
542 | ||
543 | return ret; | |
544 | ||
545 | free: | |
546 | free_pages((unsigned long)ret, get_order(size)); | |
547 | ret = NULL; | |
548 | error: | |
549 | return ret; | |
550 | } | |
551 | ||
e6584504 | 552 | static const struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
553 | .alloc_coherent = calgary_alloc_coherent, |
554 | .map_single = calgary_map_single, | |
555 | .unmap_single = calgary_unmap_single, | |
556 | .map_sg = calgary_map_sg, | |
557 | .unmap_sg = calgary_unmap_sg, | |
558 | }; | |
559 | ||
b34e90b8 LV |
560 | static inline void __iomem * busno_to_bbar(unsigned char num) |
561 | { | |
562 | return bus_info[num].bbar; | |
563 | } | |
564 | ||
e465058d JM |
565 | static inline int busno_to_phbid(unsigned char num) |
566 | { | |
f38db651 | 567 | return bus_info[num].phbid; |
e465058d JM |
568 | } |
569 | ||
570 | static inline unsigned long split_queue_offset(unsigned char num) | |
571 | { | |
572 | size_t idx = busno_to_phbid(num); | |
573 | ||
574 | return split_queue_offsets[idx]; | |
575 | } | |
576 | ||
577 | static inline unsigned long tar_offset(unsigned char num) | |
578 | { | |
579 | size_t idx = busno_to_phbid(num); | |
580 | ||
581 | return tar_offsets[idx]; | |
582 | } | |
583 | ||
584 | static inline unsigned long phb_offset(unsigned char num) | |
585 | { | |
586 | size_t idx = busno_to_phbid(num); | |
587 | ||
588 | return phb_offsets[idx]; | |
589 | } | |
590 | ||
591 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
592 | { | |
593 | unsigned long target = ((unsigned long)bar) | offset; | |
594 | return (void __iomem*)target; | |
595 | } | |
596 | ||
8a244590 MBY |
597 | static inline int is_calioc2(unsigned short device) |
598 | { | |
599 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
600 | } | |
601 | ||
602 | static inline int is_calgary(unsigned short device) | |
603 | { | |
604 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
605 | } | |
606 | ||
607 | static inline int is_cal_pci_dev(unsigned short device) | |
608 | { | |
609 | return (is_calgary(device) || is_calioc2(device)); | |
610 | } | |
611 | ||
ff297b8c | 612 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
613 | { |
614 | u64 val; | |
615 | u32 aer; | |
616 | int i = 0; | |
617 | void __iomem *bbar = tbl->bbar; | |
618 | void __iomem *target; | |
619 | ||
620 | /* disable arbitration on the bus */ | |
621 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
622 | aer = readl(target); | |
623 | writel(0, target); | |
624 | ||
625 | /* read plssr to ensure it got there */ | |
626 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
627 | val = readl(target); | |
628 | ||
629 | /* poll split queues until all DMA activity is done */ | |
630 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
631 | do { | |
632 | val = readq(target); | |
633 | i++; | |
634 | } while ((val & 0xff) != 0xff && i < 100); | |
635 | if (i == 100) | |
636 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
637 | "continuing anyway\n"); | |
638 | ||
639 | /* invalidate TCE cache */ | |
640 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
641 | writeq(tbl->tar_val, target); | |
642 | ||
643 | /* enable arbitration */ | |
644 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
645 | writel(aer, target); | |
646 | (void)readl(target); /* flush */ | |
647 | } | |
648 | ||
00be3fa4 MBY |
649 | static void calioc2_tce_cache_blast(struct iommu_table *tbl) |
650 | { | |
651 | void __iomem *bbar = tbl->bbar; | |
652 | void __iomem *target; | |
653 | u64 val64; | |
654 | u32 val; | |
655 | int i = 0; | |
656 | int count = 1; | |
657 | unsigned char bus = tbl->it_busno; | |
658 | ||
659 | begin: | |
660 | printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast " | |
661 | "sequence - count %d\n", bus, count); | |
662 | ||
663 | /* 1. using the Page Migration Control reg set SoftStop */ | |
664 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
665 | val = be32_to_cpu(readl(target)); | |
666 | printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target); | |
667 | val |= PMR_SOFTSTOP; | |
668 | printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target); | |
669 | writel(cpu_to_be32(val), target); | |
670 | ||
671 | /* 2. poll split queues until all DMA activity is done */ | |
672 | printk(KERN_DEBUG "2a. starting to poll split queues\n"); | |
673 | target = calgary_reg(bbar, split_queue_offset(bus)); | |
674 | do { | |
675 | val64 = readq(target); | |
676 | i++; | |
677 | } while ((val64 & 0xff) != 0xff && i < 100); | |
678 | if (i == 100) | |
679 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | |
680 | "continuing anyway\n"); | |
681 | ||
682 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | |
683 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
684 | val = be32_to_cpu(readl(target)); | |
685 | printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target); | |
686 | ||
687 | /* 4. if SoftStopFault - goto (1) */ | |
688 | if (val & PMR_SOFTSTOPFAULT) { | |
689 | if (++count < 100) | |
690 | goto begin; | |
691 | else { | |
692 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | |
693 | "aborting TCE cache flush sequence!\n"); | |
694 | return; /* pray for the best */ | |
695 | } | |
696 | } | |
697 | ||
698 | /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */ | |
699 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
700 | printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target); | |
701 | val = be32_to_cpu(readl(target)); | |
702 | printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target); | |
703 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | |
704 | val = be32_to_cpu(readl(target)); | |
705 | printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target); | |
706 | ||
707 | /* 6. invalidate TCE cache */ | |
708 | printk(KERN_DEBUG "6. invalidating TCE cache\n"); | |
709 | target = calgary_reg(bbar, tar_offset(bus)); | |
710 | writeq(tbl->tar_val, target); | |
711 | ||
712 | /* 7. Re-read PMCR */ | |
713 | printk(KERN_DEBUG "7a. Re-reading PMCR\n"); | |
714 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
715 | val = be32_to_cpu(readl(target)); | |
716 | printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target); | |
717 | ||
718 | /* 8. Remove HardStop */ | |
719 | printk(KERN_DEBUG "8a. removing HardStop from PMCR\n"); | |
720 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL); | |
721 | val = 0; | |
722 | printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target); | |
723 | writel(cpu_to_be32(val), target); | |
724 | val = be32_to_cpu(readl(target)); | |
725 | printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target); | |
726 | } | |
727 | ||
e465058d JM |
728 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, |
729 | u64 limit) | |
730 | { | |
731 | unsigned int numpages; | |
732 | ||
733 | limit = limit | 0xfffff; | |
734 | limit++; | |
735 | ||
736 | numpages = ((limit - start) >> PAGE_SHIFT); | |
737 | iommu_range_reserve(dev->sysdata, start, numpages); | |
738 | } | |
739 | ||
740 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
741 | { | |
742 | void __iomem *target; | |
743 | u64 low, high, sizelow; | |
744 | u64 start, limit; | |
745 | struct iommu_table *tbl = dev->sysdata; | |
746 | unsigned char busnum = dev->bus->number; | |
747 | void __iomem *bbar = tbl->bbar; | |
748 | ||
749 | /* peripheral MEM_1 region */ | |
750 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
751 | low = be32_to_cpu(readl(target)); | |
752 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
753 | high = be32_to_cpu(readl(target)); | |
754 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
755 | sizelow = be32_to_cpu(readl(target)); | |
756 | ||
757 | start = (high << 32) | low; | |
758 | limit = sizelow; | |
759 | ||
760 | calgary_reserve_mem_region(dev, start, limit); | |
761 | } | |
762 | ||
763 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
764 | { | |
765 | void __iomem *target; | |
766 | u32 val32; | |
767 | u64 low, high, sizelow, sizehigh; | |
768 | u64 start, limit; | |
769 | struct iommu_table *tbl = dev->sysdata; | |
770 | unsigned char busnum = dev->bus->number; | |
771 | void __iomem *bbar = tbl->bbar; | |
772 | ||
773 | /* is it enabled? */ | |
774 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
775 | val32 = be32_to_cpu(readl(target)); | |
776 | if (!(val32 & PHB_MEM2_ENABLE)) | |
777 | return; | |
778 | ||
779 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
780 | low = be32_to_cpu(readl(target)); | |
781 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
782 | high = be32_to_cpu(readl(target)); | |
783 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
784 | sizelow = be32_to_cpu(readl(target)); | |
785 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
786 | sizehigh = be32_to_cpu(readl(target)); | |
787 | ||
788 | start = (high << 32) | low; | |
789 | limit = (sizehigh << 32) | sizelow; | |
790 | ||
791 | calgary_reserve_mem_region(dev, start, limit); | |
792 | } | |
793 | ||
794 | /* | |
795 | * some regions of the IO address space do not get translated, so we | |
796 | * must not give devices IO addresses in those regions. The regions | |
797 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
798 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
799 | * later. | |
800 | */ | |
801 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
802 | { | |
803 | unsigned int npages; | |
e465058d JM |
804 | u64 start; |
805 | struct iommu_table *tbl = dev->sysdata; | |
806 | ||
310adfdd MBY |
807 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
808 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
809 | |
810 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
e8f20414 | 811 | /* for CalIOC2 - avoid the entire first MB */ |
8a244590 MBY |
812 | if (is_calgary(dev->device)) { |
813 | start = (640 * 1024); | |
814 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
815 | } else { /* calioc2 */ | |
816 | start = 0; | |
e8f20414 | 817 | npages = (1 * 1024 * 1024) >> PAGE_SHIFT; |
8a244590 | 818 | } |
e465058d JM |
819 | iommu_range_reserve(tbl, start, npages); |
820 | ||
821 | /* reserve the two PCI peripheral memory regions in IO space */ | |
822 | calgary_reserve_peripheral_mem_1(dev); | |
823 | calgary_reserve_peripheral_mem_2(dev); | |
824 | } | |
825 | ||
826 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
827 | { | |
828 | u64 val64; | |
829 | u64 table_phys; | |
830 | void __iomem *target; | |
831 | int ret; | |
832 | struct iommu_table *tbl; | |
833 | ||
834 | /* build TCE tables for each PHB */ | |
835 | ret = build_tce_table(dev, bbar); | |
836 | if (ret) | |
837 | return ret; | |
838 | ||
f38db651 MBY |
839 | tbl = dev->sysdata; |
840 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; | |
841 | tce_free(tbl, 0, tbl->it_size); | |
842 | ||
8bcf7705 MBY |
843 | if (is_calgary(dev->device)) |
844 | tbl->chip_ops = &calgary_chip_ops; | |
c3860108 MBY |
845 | else if (is_calioc2(dev->device)) |
846 | tbl->chip_ops = &calioc2_chip_ops; | |
8bcf7705 MBY |
847 | else |
848 | BUG(); | |
ff297b8c | 849 | |
e465058d JM |
850 | calgary_reserve_regions(dev); |
851 | ||
852 | /* set TARs for each PHB */ | |
853 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
854 | val64 = be64_to_cpu(readq(target)); | |
855 | ||
856 | /* zero out all TAR bits under sw control */ | |
857 | val64 &= ~TAR_SW_BITS; | |
e465058d | 858 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 859 | |
e465058d JM |
860 | val64 |= table_phys; |
861 | ||
862 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
863 | val64 |= (u64) specified_table_size; | |
864 | ||
865 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 866 | |
e465058d JM |
867 | writeq(tbl->tar_val, target); |
868 | readq(target); /* flush */ | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
b8f4fe66 | 873 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
874 | { |
875 | u64 val64; | |
876 | struct iommu_table *tbl = dev->sysdata; | |
877 | void __iomem *target; | |
b8f4fe66 | 878 | unsigned int bitmapsz; |
e465058d JM |
879 | |
880 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
881 | val64 = be64_to_cpu(readq(target)); | |
882 | val64 &= ~TAR_SW_BITS; | |
883 | writeq(cpu_to_be64(val64), target); | |
884 | readq(target); /* flush */ | |
885 | ||
b8f4fe66 MBY |
886 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
887 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
888 | tbl->it_map = NULL; | |
889 | ||
e465058d JM |
890 | kfree(tbl); |
891 | dev->sysdata = NULL; | |
b8f4fe66 MBY |
892 | |
893 | /* Can't free bootmem allocated memory after system is up :-( */ | |
894 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
895 | } |
896 | ||
8a244590 MBY |
897 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
898 | { | |
899 | void __iomem *bbar = tbl->bbar; | |
8cb32dc7 | 900 | void __iomem *target; |
ddbd41b4 | 901 | u32 csr, plssr; |
8cb32dc7 MBY |
902 | |
903 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
ddbd41b4 MBY |
904 | csr = be32_to_cpu(readl(target)); |
905 | ||
906 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
907 | plssr = be32_to_cpu(readl(target)); | |
8cb32dc7 MBY |
908 | |
909 | /* If no error, the agent ID in the CSR is not valid */ | |
910 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | |
ddbd41b4 | 911 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); |
8cb32dc7 MBY |
912 | } |
913 | ||
914 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | |
915 | { | |
916 | void __iomem *bbar = tbl->bbar; | |
917 | u32 csr, csmr, plssr, mck, rcstat; | |
8a244590 MBY |
918 | void __iomem *target; |
919 | unsigned long phboff = phb_offset(tbl->it_busno); | |
920 | unsigned long erroff; | |
921 | u32 errregs[7]; | |
922 | int i; | |
923 | ||
924 | /* dump CSR */ | |
925 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
926 | csr = be32_to_cpu(readl(target)); | |
927 | /* dump PLSSR */ | |
928 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
929 | plssr = be32_to_cpu(readl(target)); | |
930 | /* dump CSMR */ | |
931 | target = calgary_reg(bbar, phboff | 0x290); | |
932 | csmr = be32_to_cpu(readl(target)); | |
933 | /* dump mck */ | |
934 | target = calgary_reg(bbar, phboff | 0x800); | |
935 | mck = be32_to_cpu(readl(target)); | |
936 | ||
8cb32dc7 MBY |
937 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", |
938 | tbl->it_busno); | |
939 | ||
940 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | |
941 | csr, plssr, csmr, mck); | |
8a244590 MBY |
942 | |
943 | /* dump rest of error regs */ | |
944 | printk(KERN_EMERG "Calgary: "); | |
945 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
7354b075 MBY |
946 | /* err regs are at 0x810 - 0x870 */ |
947 | erroff = (0x810 + (i * 0x10)); | |
8a244590 MBY |
948 | target = calgary_reg(bbar, phboff | erroff); |
949 | errregs[i] = be32_to_cpu(readl(target)); | |
950 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
951 | } | |
952 | printk("\n"); | |
8cb32dc7 MBY |
953 | |
954 | /* root complex status */ | |
955 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | |
956 | rcstat = be32_to_cpu(readl(target)); | |
957 | printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat, | |
958 | PHB_ROOT_COMPLEX_STATUS); | |
8a244590 MBY |
959 | } |
960 | ||
e465058d JM |
961 | static void calgary_watchdog(unsigned long data) |
962 | { | |
963 | struct pci_dev *dev = (struct pci_dev *)data; | |
964 | struct iommu_table *tbl = dev->sysdata; | |
965 | void __iomem *bbar = tbl->bbar; | |
966 | u32 val32; | |
967 | void __iomem *target; | |
968 | ||
969 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
970 | val32 = be32_to_cpu(readl(target)); | |
971 | ||
972 | /* If no error, the agent ID in the CSR is not valid */ | |
973 | if (val32 & CSR_AGENT_MASK) { | |
8cb32dc7 | 974 | tbl->chip_ops->dump_error_regs(tbl); |
8a244590 MBY |
975 | |
976 | /* reset error */ | |
e465058d JM |
977 | writel(0, target); |
978 | ||
979 | /* Disable bus that caused the error */ | |
980 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 981 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
982 | val32 = be32_to_cpu(readl(target)); |
983 | val32 |= PHB_SLOT_DISABLE; | |
984 | writel(cpu_to_be32(val32), target); | |
985 | readl(target); /* flush */ | |
986 | } else { | |
987 | /* Reset the timer */ | |
988 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
989 | } | |
990 | } | |
991 | ||
a2b663f6 MBY |
992 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
993 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
994 | { |
995 | u64 val64; | |
996 | void __iomem *target; | |
58db8548 | 997 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
998 | u64 mask; |
999 | ||
1000 | switch (busno_to_phbid(busnum)) { | |
1001 | case 0: phb_shift = (63 - 19); | |
1002 | break; | |
1003 | case 1: phb_shift = (63 - 23); | |
1004 | break; | |
1005 | case 2: phb_shift = (63 - 27); | |
1006 | break; | |
1007 | case 3: phb_shift = (63 - 35); | |
1008 | break; | |
1009 | default: | |
1010 | BUG_ON(busno_to_phbid(busnum)); | |
1011 | } | |
1012 | ||
1013 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
1014 | val64 = be64_to_cpu(readq(target)); | |
1015 | ||
1016 | /* zero out this PHB's timer bits */ | |
1017 | mask = ~(0xFUL << phb_shift); | |
1018 | val64 &= mask; | |
a2b663f6 | 1019 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
1020 | writeq(cpu_to_be64(val64), target); |
1021 | readq(target); /* flush */ | |
1022 | } | |
1023 | ||
c3860108 MBY |
1024 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
1025 | { | |
1026 | unsigned char busnum = dev->bus->number; | |
1027 | void __iomem *bbar = tbl->bbar; | |
1028 | void __iomem *target; | |
1029 | u32 val; | |
1030 | ||
8bcf7705 MBY |
1031 | /* |
1032 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
1033 | */ | |
1034 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
1035 | val = cpu_to_be32(readl(target)); | |
1036 | val |= 0x00800000; | |
1037 | writel(cpu_to_be32(val), target); | |
c3860108 MBY |
1038 | } |
1039 | ||
1040 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) | |
b8d2ea1b MBY |
1041 | { |
1042 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
1043 | |
1044 | /* | |
1045 | * Give split completion a longer timeout on bus 1 for aic94xx | |
1046 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
1047 | */ | |
c3860108 | 1048 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
1049 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
1050 | CCR_2SEC_TIMEOUT); | |
1051 | } | |
1052 | ||
e465058d JM |
1053 | static void __init calgary_enable_translation(struct pci_dev *dev) |
1054 | { | |
1055 | u32 val32; | |
1056 | unsigned char busnum; | |
1057 | void __iomem *target; | |
1058 | void __iomem *bbar; | |
1059 | struct iommu_table *tbl; | |
1060 | ||
1061 | busnum = dev->bus->number; | |
1062 | tbl = dev->sysdata; | |
1063 | bbar = tbl->bbar; | |
1064 | ||
1065 | /* enable TCE in PHB Config Register */ | |
1066 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1067 | val32 = be32_to_cpu(readl(target)); | |
1068 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
1069 | ||
8a244590 MBY |
1070 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
1071 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
1072 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
1073 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
1074 | "bus.\n"); | |
1075 | ||
1076 | writel(cpu_to_be32(val32), target); | |
1077 | readl(target); /* flush */ | |
1078 | ||
1079 | init_timer(&tbl->watchdog_timer); | |
1080 | tbl->watchdog_timer.function = &calgary_watchdog; | |
1081 | tbl->watchdog_timer.data = (unsigned long)dev; | |
1082 | mod_timer(&tbl->watchdog_timer, jiffies); | |
1083 | } | |
1084 | ||
1085 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
1086 | { | |
1087 | u32 val32; | |
1088 | unsigned char busnum; | |
1089 | void __iomem *target; | |
1090 | void __iomem *bbar; | |
1091 | struct iommu_table *tbl; | |
1092 | ||
1093 | busnum = dev->bus->number; | |
1094 | tbl = dev->sysdata; | |
1095 | bbar = tbl->bbar; | |
1096 | ||
1097 | /* disable TCE in PHB Config Register */ | |
1098 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
1099 | val32 = be32_to_cpu(readl(target)); | |
1100 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
1101 | ||
70d666d6 | 1102 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
1103 | writel(cpu_to_be32(val32), target); |
1104 | readl(target); /* flush */ | |
1105 | ||
1106 | del_timer_sync(&tbl->watchdog_timer); | |
1107 | } | |
1108 | ||
a4fc520a | 1109 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 1110 | { |
871b1700 | 1111 | pci_dev_get(dev); |
e465058d | 1112 | dev->sysdata = NULL; |
8a244590 MBY |
1113 | |
1114 | /* is the device behind a bridge? */ | |
1115 | if (dev->bus->parent) | |
1116 | dev->bus->parent->self = dev; | |
1117 | else | |
1118 | dev->bus->self = dev; | |
e465058d JM |
1119 | } |
1120 | ||
1121 | static int __init calgary_init_one(struct pci_dev *dev) | |
1122 | { | |
e465058d | 1123 | void __iomem *bbar; |
ff297b8c | 1124 | struct iommu_table *tbl; |
e465058d JM |
1125 | int ret; |
1126 | ||
dedc9937 JM |
1127 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1128 | ||
eae93755 | 1129 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1130 | ret = calgary_setup_tar(dev, bbar); |
1131 | if (ret) | |
eae93755 | 1132 | goto done; |
e465058d | 1133 | |
871b1700 | 1134 | pci_dev_get(dev); |
8a244590 MBY |
1135 | |
1136 | if (dev->bus->parent) { | |
1137 | if (dev->bus->parent->self) | |
1138 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1139 | "bus->parent->self!\n", dev); | |
1140 | dev->bus->parent->self = dev; | |
1141 | } else | |
1142 | dev->bus->self = dev; | |
b8d2ea1b | 1143 | |
ff297b8c MBY |
1144 | tbl = dev->sysdata; |
1145 | tbl->chip_ops->handle_quirks(tbl, dev); | |
b8d2ea1b | 1146 | |
e465058d JM |
1147 | calgary_enable_translation(dev); |
1148 | ||
1149 | return 0; | |
1150 | ||
e465058d JM |
1151 | done: |
1152 | return ret; | |
1153 | } | |
1154 | ||
eae93755 | 1155 | static int __init calgary_locate_bbars(void) |
e465058d | 1156 | { |
eae93755 MBY |
1157 | int ret; |
1158 | int rioidx, phb, bus; | |
b34e90b8 LV |
1159 | void __iomem *bbar; |
1160 | void __iomem *target; | |
eae93755 | 1161 | unsigned long offset; |
b34e90b8 LV |
1162 | u8 start_bus, end_bus; |
1163 | u32 val; | |
1164 | ||
eae93755 MBY |
1165 | ret = -ENODATA; |
1166 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1167 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1168 | |
eae93755 | 1169 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1170 | continue; |
1171 | ||
1172 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1173 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1174 | if (!bbar) | |
1175 | goto error; | |
b34e90b8 LV |
1176 | |
1177 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1178 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1179 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1180 | |
b34e90b8 | 1181 | val = be32_to_cpu(readl(target)); |
8a244590 | 1182 | |
b34e90b8 | 1183 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1184 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1185 | |
1186 | if (end_bus) { | |
1187 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1188 | bus_info[bus].bbar = bbar; | |
1189 | bus_info[bus].phbid = phb; | |
1190 | } | |
1191 | } else { | |
1192 | bus_info[start_bus].bbar = bbar; | |
1193 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1194 | } |
1195 | } | |
1196 | } | |
1197 | ||
eae93755 MBY |
1198 | return 0; |
1199 | ||
1200 | error: | |
1201 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1202 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1203 | if (bus_info[bus].bbar) | |
1204 | iounmap(bus_info[bus].bbar); | |
1205 | ||
1206 | return ret; | |
1207 | } | |
1208 | ||
1209 | static int __init calgary_init(void) | |
1210 | { | |
1211 | int ret; | |
1212 | struct pci_dev *dev = NULL; | |
7354b075 | 1213 | void *tce_space; |
eae93755 MBY |
1214 | |
1215 | ret = calgary_locate_bbars(); | |
1216 | if (ret) | |
1217 | return ret; | |
e465058d | 1218 | |
dedc9937 | 1219 | do { |
8a244590 | 1220 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1221 | if (!dev) |
1222 | break; | |
8a244590 MBY |
1223 | if (!is_cal_pci_dev(dev->device)) |
1224 | continue; | |
e465058d JM |
1225 | if (!translate_phb(dev)) { |
1226 | calgary_init_one_nontraslated(dev); | |
1227 | continue; | |
1228 | } | |
8a244590 | 1229 | tce_space = bus_info[dev->bus->number].tce_space; |
12de257b | 1230 | if (!tce_space && !translate_empty_slots) |
e465058d | 1231 | continue; |
12de257b | 1232 | |
e465058d JM |
1233 | ret = calgary_init_one(dev); |
1234 | if (ret) | |
1235 | goto error; | |
dedc9937 | 1236 | } while (1); |
e465058d JM |
1237 | |
1238 | return ret; | |
1239 | ||
1240 | error: | |
dedc9937 | 1241 | do { |
7cd8b686 | 1242 | dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM, |
8a244590 | 1243 | PCI_ANY_ID, dev); |
9f2dc46d MBY |
1244 | if (!dev) |
1245 | break; | |
8a244590 MBY |
1246 | if (!is_cal_pci_dev(dev->device)) |
1247 | continue; | |
e465058d JM |
1248 | if (!translate_phb(dev)) { |
1249 | pci_dev_put(dev); | |
1250 | continue; | |
1251 | } | |
f38db651 | 1252 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 1253 | continue; |
871b1700 | 1254 | |
e465058d | 1255 | calgary_disable_translation(dev); |
b8f4fe66 | 1256 | calgary_free_bus(dev); |
871b1700 | 1257 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 1258 | } while (1); |
e465058d JM |
1259 | |
1260 | return ret; | |
1261 | } | |
1262 | ||
1263 | static inline int __init determine_tce_table_size(u64 ram) | |
1264 | { | |
1265 | int ret; | |
1266 | ||
1267 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1268 | return specified_table_size; | |
1269 | ||
1270 | /* | |
1271 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1272 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1273 | * larger table size has twice as many entries, so shift the | |
1274 | * max ram address by 13 to divide by 8K and then look at the | |
1275 | * order of the result to choose between 0-7. | |
1276 | */ | |
1277 | ret = get_order(ram >> 13); | |
1278 | if (ret > TCE_TABLE_SIZE_8M) | |
1279 | ret = TCE_TABLE_SIZE_8M; | |
1280 | ||
1281 | return ret; | |
1282 | } | |
1283 | ||
b34e90b8 LV |
1284 | static int __init build_detail_arrays(void) |
1285 | { | |
1286 | unsigned long ptr; | |
1287 | int i, scal_detail_size, rio_detail_size; | |
1288 | ||
1289 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1290 | printk(KERN_WARNING | |
eae93755 | 1291 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1292 | "but system has %d nodes.\n", |
1293 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1294 | return -ENODEV; | |
1295 | } | |
1296 | ||
1297 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1298 | case 2: |
1299 | scal_detail_size = 11; | |
1300 | rio_detail_size = 13; | |
1301 | break; | |
1302 | case 3: | |
1303 | scal_detail_size = 12; | |
1304 | rio_detail_size = 15; | |
1305 | break; | |
eae93755 MBY |
1306 | default: |
1307 | printk(KERN_WARNING | |
1308 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1309 | rio_table_hdr->version); | |
1310 | return -EPROTO; | |
b34e90b8 LV |
1311 | } |
1312 | ||
1313 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1314 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1315 | i++, ptr += scal_detail_size) | |
1316 | scal_devs[i] = (struct scal_detail *)ptr; | |
1317 | ||
1318 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1319 | i++, ptr += rio_detail_size) | |
1320 | rio_devs[i] = (struct rio_detail *)ptr; | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
8a244590 | 1325 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1326 | { |
8a244590 | 1327 | int dev; |
e465058d | 1328 | u32 val; |
8a244590 MBY |
1329 | |
1330 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1331 | /* | |
1332 | * FIXME: properly scan for devices accross the | |
1333 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1334 | */ | |
1335 | return 1; | |
1336 | } | |
1337 | ||
1338 | for (dev = 1; dev < 8; dev++) { | |
1339 | val = read_pci_config(bus, dev, 0, 0); | |
1340 | if (val != 0xffffffff) | |
1341 | break; | |
1342 | } | |
1343 | return (val != 0xffffffff); | |
1344 | } | |
1345 | ||
1346 | void __init detect_calgary(void) | |
1347 | { | |
d2105b10 | 1348 | int bus; |
e465058d | 1349 | void *tbl; |
d2105b10 | 1350 | int calgary_found = 0; |
b34e90b8 | 1351 | unsigned long ptr; |
136f1e7a | 1352 | unsigned int offset, prev_offset; |
eae93755 | 1353 | int ret; |
e465058d JM |
1354 | |
1355 | /* | |
1356 | * if the user specified iommu=off or iommu=soft or we found | |
1357 | * another HW IOMMU already, bail out. | |
1358 | */ | |
1359 | if (swiotlb || no_iommu || iommu_detected) | |
1360 | return; | |
1361 | ||
bff6547b MBY |
1362 | if (!use_calgary) |
1363 | return; | |
1364 | ||
0637a70a AK |
1365 | if (!early_pci_allowed()) |
1366 | return; | |
1367 | ||
b92cc559 MBY |
1368 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1369 | ||
b34e90b8 LV |
1370 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1371 | ||
1372 | rio_table_hdr = NULL; | |
136f1e7a | 1373 | prev_offset = 0; |
b34e90b8 | 1374 | offset = 0x180; |
136f1e7a IM |
1375 | /* |
1376 | * The next offset is stored in the 1st word. | |
1377 | * Only parse up until the offset increases: | |
1378 | */ | |
1379 | while (offset > prev_offset) { | |
b34e90b8 LV |
1380 | /* The block id is stored in the 2nd word */ |
1381 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1382 | /* set the pointer past the offset & block id */ | |
eae93755 | 1383 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1384 | break; |
1385 | } | |
136f1e7a | 1386 | prev_offset = offset; |
b34e90b8 LV |
1387 | offset = *((unsigned short *)(ptr + offset)); |
1388 | } | |
eae93755 | 1389 | if (!rio_table_hdr) { |
b92cc559 MBY |
1390 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1391 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1392 | return; |
1393 | } | |
1394 | ||
eae93755 MBY |
1395 | ret = build_detail_arrays(); |
1396 | if (ret) { | |
b92cc559 | 1397 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1398 | return; |
eae93755 | 1399 | } |
b34e90b8 | 1400 | |
e465058d JM |
1401 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
1402 | ||
d2105b10 | 1403 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1404 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1405 | unsigned short pci_device; |
1406 | u32 val; | |
1407 | ||
1408 | val = read_pci_config(bus, 0, 0, 0); | |
1409 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1410 | |
8a244590 | 1411 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1412 | continue; |
d2105b10 | 1413 | |
f38db651 | 1414 | if (info->translation_disabled) |
e465058d | 1415 | continue; |
f38db651 | 1416 | |
8a244590 MBY |
1417 | if (calgary_bus_has_devices(bus, pci_device) || |
1418 | translate_empty_slots) { | |
1419 | tbl = alloc_tce_table(); | |
1420 | if (!tbl) | |
1421 | goto cleanup; | |
1422 | info->tce_space = tbl; | |
1423 | calgary_found = 1; | |
d2105b10 | 1424 | } |
e465058d JM |
1425 | } |
1426 | ||
b92cc559 MBY |
1427 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1428 | calgary_found ? "found" : "not found"); | |
1429 | ||
d2105b10 | 1430 | if (calgary_found) { |
e465058d JM |
1431 | iommu_detected = 1; |
1432 | calgary_detected = 1; | |
de684652 MBY |
1433 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1434 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1435 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1436 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1437 | } |
1438 | return; | |
1439 | ||
1440 | cleanup: | |
f38db651 MBY |
1441 | for (--bus; bus >= 0; --bus) { |
1442 | struct calgary_bus_info *info = &bus_info[bus]; | |
1443 | ||
1444 | if (info->tce_space) | |
1445 | free_tce_table(info->tce_space); | |
1446 | } | |
e465058d JM |
1447 | } |
1448 | ||
1449 | int __init calgary_iommu_init(void) | |
1450 | { | |
1451 | int ret; | |
1452 | ||
1453 | if (no_iommu || swiotlb) | |
1454 | return -ENODEV; | |
1455 | ||
1456 | if (!calgary_detected) | |
1457 | return -ENODEV; | |
1458 | ||
1459 | /* ok, we're trying to use Calgary - let's roll */ | |
1460 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1461 | ||
1462 | ret = calgary_init(); | |
1463 | if (ret) { | |
1464 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1465 | "falling back to no_iommu\n", ret); | |
1466 | if (end_pfn > MAX_DMA32_PFN) | |
1467 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1468 | "32bit PCI may malfunction.\n"); | |
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | force_iommu = 1; | |
310adfdd | 1473 | bad_dma_address = 0x0; |
e465058d JM |
1474 | dma_ops = &calgary_dma_ops; |
1475 | ||
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | static int __init calgary_parse_options(char *p) | |
1480 | { | |
1481 | unsigned int bridge; | |
1482 | size_t len; | |
1483 | char* endp; | |
1484 | ||
1485 | while (*p) { | |
1486 | if (!strncmp(p, "64k", 3)) | |
1487 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1488 | else if (!strncmp(p, "128k", 4)) | |
1489 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1490 | else if (!strncmp(p, "256k", 4)) | |
1491 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1492 | else if (!strncmp(p, "512k", 4)) | |
1493 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1494 | else if (!strncmp(p, "1M", 2)) | |
1495 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1496 | else if (!strncmp(p, "2M", 2)) | |
1497 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1498 | else if (!strncmp(p, "4M", 2)) | |
1499 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1500 | else if (!strncmp(p, "8M", 2)) | |
1501 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1502 | ||
1503 | len = strlen("translate_empty_slots"); | |
1504 | if (!strncmp(p, "translate_empty_slots", len)) | |
1505 | translate_empty_slots = 1; | |
1506 | ||
1507 | len = strlen("disable"); | |
1508 | if (!strncmp(p, "disable", len)) { | |
1509 | p += len; | |
1510 | if (*p == '=') | |
1511 | ++p; | |
1512 | if (*p == '\0') | |
1513 | break; | |
1514 | bridge = simple_strtol(p, &endp, 0); | |
1515 | if (p == endp) | |
1516 | break; | |
1517 | ||
d2105b10 | 1518 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1519 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1520 | "translation for PHB %#x\n", bridge); |
f38db651 | 1521 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1522 | } |
1523 | } | |
1524 | ||
1525 | p = strpbrk(p, ","); | |
1526 | if (!p) | |
1527 | break; | |
1528 | ||
1529 | p++; /* skip ',' */ | |
1530 | } | |
1531 | return 1; | |
1532 | } | |
1533 | __setup("calgary=", calgary_parse_options); | |
07877cf6 MBY |
1534 | |
1535 | static void __init calgary_fixup_one_tce_space(struct pci_dev *dev) | |
1536 | { | |
1537 | struct iommu_table *tbl; | |
1538 | unsigned int npages; | |
1539 | int i; | |
1540 | ||
1541 | tbl = dev->sysdata; | |
1542 | ||
1543 | for (i = 0; i < 4; i++) { | |
1544 | struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i]; | |
1545 | ||
1546 | /* Don't give out TCEs that map MEM resources */ | |
1547 | if (!(r->flags & IORESOURCE_MEM)) | |
1548 | continue; | |
1549 | ||
1550 | /* 0-based? we reserve the whole 1st MB anyway */ | |
1551 | if (!r->start) | |
1552 | continue; | |
1553 | ||
1554 | /* cover the whole region */ | |
1555 | npages = (r->end - r->start) >> PAGE_SHIFT; | |
1556 | npages++; | |
1557 | ||
07877cf6 MBY |
1558 | iommu_range_reserve(tbl, r->start, npages); |
1559 | } | |
1560 | } | |
1561 | ||
1562 | static int __init calgary_fixup_tce_spaces(void) | |
1563 | { | |
1564 | struct pci_dev *dev = NULL; | |
1565 | void *tce_space; | |
1566 | ||
1567 | if (no_iommu || swiotlb || !calgary_detected) | |
1568 | return -ENODEV; | |
1569 | ||
12de257b | 1570 | printk(KERN_DEBUG "Calgary: fixing up tce spaces\n"); |
07877cf6 MBY |
1571 | |
1572 | do { | |
1573 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); | |
1574 | if (!dev) | |
1575 | break; | |
1576 | if (!is_cal_pci_dev(dev->device)) | |
1577 | continue; | |
1578 | if (!translate_phb(dev)) | |
1579 | continue; | |
1580 | ||
1581 | tce_space = bus_info[dev->bus->number].tce_space; | |
1582 | if (!tce_space) | |
1583 | continue; | |
1584 | ||
1585 | calgary_fixup_one_tce_space(dev); | |
1586 | ||
1587 | } while (1); | |
1588 | ||
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | /* | |
1593 | * We need to be call after pcibios_assign_resources (fs_initcall level) | |
1594 | * and before device_initcall. | |
1595 | */ | |
1596 | rootfs_initcall(calgary_fixup_tce_spaces); |