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Commit | Line | Data |
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e465058d JM |
1 | /* |
2 | * Derived from arch/powerpc/kernel/iommu.c | |
3 | * | |
9882234b | 4 | * Copyright IBM Corporation, 2006-2007 |
d8d2bedf | 5 | * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us> |
e465058d | 6 | * |
d8d2bedf | 7 | * Author: Jon Mason <jdmason@kudzu.us> |
aa0a9f37 MBY |
8 | * Author: Muli Ben-Yehuda <muli@il.ibm.com> |
9 | ||
e465058d JM |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
e465058d JM |
25 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/pci_ids.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/delay.h> | |
38 | #include <asm/proto.h> | |
39 | #include <asm/calgary.h> | |
40 | #include <asm/tce.h> | |
41 | #include <asm/pci-direct.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/dma.h> | |
b34e90b8 | 44 | #include <asm/rio.h> |
e465058d | 45 | |
bff6547b MBY |
46 | #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT |
47 | int use_calgary __read_mostly = 1; | |
48 | #else | |
49 | int use_calgary __read_mostly = 0; | |
50 | #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */ | |
51 | ||
e465058d | 52 | #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1 |
8a244590 | 53 | #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308 |
e465058d JM |
54 | |
55 | /* we need these for register space address calculation */ | |
56 | #define START_ADDRESS 0xfe000000 | |
57 | #define CHASSIS_BASE 0 | |
58 | #define ONE_BASED_CHASSIS_NUM 1 | |
59 | ||
60 | /* register offsets inside the host bridge space */ | |
cb01fc72 MBY |
61 | #define CALGARY_CONFIG_REG 0x0108 |
62 | #define PHB_CSR_OFFSET 0x0110 /* Channel Status */ | |
e465058d JM |
63 | #define PHB_PLSSR_OFFSET 0x0120 |
64 | #define PHB_CONFIG_RW_OFFSET 0x0160 | |
65 | #define PHB_IOBASE_BAR_LOW 0x0170 | |
66 | #define PHB_IOBASE_BAR_HIGH 0x0180 | |
67 | #define PHB_MEM_1_LOW 0x0190 | |
68 | #define PHB_MEM_1_HIGH 0x01A0 | |
69 | #define PHB_IO_ADDR_SIZE 0x01B0 | |
70 | #define PHB_MEM_1_SIZE 0x01C0 | |
71 | #define PHB_MEM_ST_OFFSET 0x01D0 | |
72 | #define PHB_AER_OFFSET 0x0200 | |
73 | #define PHB_CONFIG_0_HIGH 0x0220 | |
74 | #define PHB_CONFIG_0_LOW 0x0230 | |
75 | #define PHB_CONFIG_0_END 0x0240 | |
76 | #define PHB_MEM_2_LOW 0x02B0 | |
77 | #define PHB_MEM_2_HIGH 0x02C0 | |
78 | #define PHB_MEM_2_SIZE_HIGH 0x02D0 | |
79 | #define PHB_MEM_2_SIZE_LOW 0x02E0 | |
80 | #define PHB_DOSHOLE_OFFSET 0x08E0 | |
81 | ||
c3860108 MBY |
82 | /* CalIOC2 specific */ |
83 | #define PHB_SAVIOR_L2 0x0DB0 | |
84 | ||
e465058d JM |
85 | /* PHB_CONFIG_RW */ |
86 | #define PHB_TCE_ENABLE 0x20000000 | |
87 | #define PHB_SLOT_DISABLE 0x1C000000 | |
88 | #define PHB_DAC_DISABLE 0x01000000 | |
89 | #define PHB_MEM2_ENABLE 0x00400000 | |
90 | #define PHB_MCSR_ENABLE 0x00100000 | |
91 | /* TAR (Table Address Register) */ | |
92 | #define TAR_SW_BITS 0x0000ffffffff800fUL | |
93 | #define TAR_VALID 0x0000000000000008UL | |
94 | /* CSR (Channel/DMA Status Register) */ | |
95 | #define CSR_AGENT_MASK 0xffe0ffff | |
cb01fc72 MBY |
96 | /* CCR (Calgary Configuration Register) */ |
97 | #define CCR_2SEC_TIMEOUT 0x000000000000000EUL | |
e465058d JM |
98 | |
99 | #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */ | |
d2105b10 | 100 | #define MAX_NUM_CHASSIS 8 /* max number of chassis */ |
4ea8a5d8 MBY |
101 | /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */ |
102 | #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2) | |
e465058d JM |
103 | #define PHBS_PER_CALGARY 4 |
104 | ||
105 | /* register offsets in Calgary's internal register space */ | |
106 | static const unsigned long tar_offsets[] = { | |
107 | 0x0580 /* TAR0 */, | |
108 | 0x0588 /* TAR1 */, | |
109 | 0x0590 /* TAR2 */, | |
110 | 0x0598 /* TAR3 */ | |
111 | }; | |
112 | ||
113 | static const unsigned long split_queue_offsets[] = { | |
114 | 0x4870 /* SPLIT QUEUE 0 */, | |
115 | 0x5870 /* SPLIT QUEUE 1 */, | |
116 | 0x6870 /* SPLIT QUEUE 2 */, | |
117 | 0x7870 /* SPLIT QUEUE 3 */ | |
118 | }; | |
119 | ||
120 | static const unsigned long phb_offsets[] = { | |
121 | 0x8000 /* PHB0 */, | |
122 | 0x9000 /* PHB1 */, | |
123 | 0xA000 /* PHB2 */, | |
124 | 0xB000 /* PHB3 */ | |
125 | }; | |
126 | ||
b34e90b8 LV |
127 | /* PHB debug registers */ |
128 | ||
129 | static const unsigned long phb_debug_offsets[] = { | |
130 | 0x4000 /* PHB 0 DEBUG */, | |
131 | 0x5000 /* PHB 1 DEBUG */, | |
132 | 0x6000 /* PHB 2 DEBUG */, | |
133 | 0x7000 /* PHB 3 DEBUG */ | |
134 | }; | |
135 | ||
136 | /* | |
137 | * STUFF register for each debug PHB, | |
138 | * byte 1 = start bus number, byte 2 = end bus number | |
139 | */ | |
140 | ||
141 | #define PHB_DEBUG_STUFF_OFFSET 0x0020 | |
142 | ||
310adfdd MBY |
143 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
144 | ||
e465058d JM |
145 | unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED; |
146 | static int translate_empty_slots __read_mostly = 0; | |
147 | static int calgary_detected __read_mostly = 0; | |
148 | ||
b34e90b8 LV |
149 | static struct rio_table_hdr *rio_table_hdr __initdata; |
150 | static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata; | |
eae93755 | 151 | static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata; |
b34e90b8 | 152 | |
f38db651 MBY |
153 | struct calgary_bus_info { |
154 | void *tce_space; | |
0577f148 | 155 | unsigned char translation_disabled; |
f38db651 | 156 | signed char phbid; |
b34e90b8 | 157 | void __iomem *bbar; |
f38db651 MBY |
158 | }; |
159 | ||
ff297b8c MBY |
160 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
161 | static void calgary_tce_cache_blast(struct iommu_table *tbl); | |
c3860108 | 162 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev); |
ff297b8c MBY |
163 | |
164 | static struct cal_chipset_ops calgary_chip_ops = { | |
165 | .handle_quirks = calgary_handle_quirks, | |
166 | .tce_cache_blast = calgary_tce_cache_blast | |
167 | }; | |
e465058d | 168 | |
c3860108 MBY |
169 | static struct cal_chipset_ops calioc2_chip_ops = { |
170 | .handle_quirks = calioc2_handle_quirks, | |
171 | .tce_cache_blast = NULL | |
172 | }; | |
173 | ||
ff297b8c | 174 | static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, }; |
e465058d JM |
175 | |
176 | /* enable this to stress test the chip's TCE cache */ | |
177 | #ifdef CONFIG_IOMMU_DEBUG | |
de684652 MBY |
178 | int debugging __read_mostly = 1; |
179 | ||
796e4390 MBY |
180 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
181 | int expected, unsigned long start, unsigned long end) | |
182 | { | |
183 | unsigned long idx = start; | |
184 | ||
185 | BUG_ON(start >= end); | |
186 | ||
187 | while (idx < end) { | |
188 | if (!!test_bit(idx, bitmap) != expected) | |
189 | return idx; | |
190 | ++idx; | |
191 | } | |
192 | ||
193 | /* all bits have the expected value */ | |
194 | return ~0UL; | |
195 | } | |
de684652 MBY |
196 | #else /* debugging is disabled */ |
197 | int debugging __read_mostly = 0; | |
198 | ||
796e4390 MBY |
199 | static inline unsigned long verify_bit_range(unsigned long* bitmap, |
200 | int expected, unsigned long start, unsigned long end) | |
201 | { | |
202 | return ~0UL; | |
203 | } | |
8a244590 | 204 | |
de684652 | 205 | #endif /* CONFIG_IOMMU_DEBUG */ |
e465058d JM |
206 | |
207 | static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen) | |
208 | { | |
209 | unsigned int npages; | |
210 | ||
211 | npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK); | |
212 | npages >>= PAGE_SHIFT; | |
213 | ||
214 | return npages; | |
215 | } | |
216 | ||
217 | static inline int translate_phb(struct pci_dev* dev) | |
218 | { | |
f38db651 | 219 | int disabled = bus_info[dev->bus->number].translation_disabled; |
e465058d JM |
220 | return !disabled; |
221 | } | |
222 | ||
223 | static void iommu_range_reserve(struct iommu_table *tbl, | |
224 | unsigned long start_addr, unsigned int npages) | |
225 | { | |
226 | unsigned long index; | |
227 | unsigned long end; | |
796e4390 | 228 | unsigned long badbit; |
e465058d JM |
229 | |
230 | index = start_addr >> PAGE_SHIFT; | |
231 | ||
232 | /* bail out if we're asked to reserve a region we don't cover */ | |
233 | if (index >= tbl->it_size) | |
234 | return; | |
235 | ||
236 | end = index + npages; | |
237 | if (end > tbl->it_size) /* don't go off the table */ | |
238 | end = tbl->it_size; | |
239 | ||
796e4390 MBY |
240 | badbit = verify_bit_range(tbl->it_map, 0, index, end); |
241 | if (badbit != ~0UL) { | |
242 | if (printk_ratelimit()) | |
e465058d JM |
243 | printk(KERN_ERR "Calgary: entry already allocated at " |
244 | "0x%lx tbl %p dma 0x%lx npages %u\n", | |
796e4390 | 245 | badbit, tbl, start_addr, npages); |
e465058d | 246 | } |
796e4390 MBY |
247 | |
248 | set_bit_string(tbl->it_map, index, npages); | |
e465058d JM |
249 | } |
250 | ||
251 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
252 | unsigned int npages) | |
253 | { | |
254 | unsigned long offset; | |
255 | ||
256 | BUG_ON(npages == 0); | |
257 | ||
258 | offset = find_next_zero_string(tbl->it_map, tbl->it_hint, | |
259 | tbl->it_size, npages); | |
260 | if (offset == ~0UL) { | |
ff297b8c | 261 | tbl->chip_ops->tce_cache_blast(tbl); |
e465058d JM |
262 | offset = find_next_zero_string(tbl->it_map, 0, |
263 | tbl->it_size, npages); | |
264 | if (offset == ~0UL) { | |
265 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | |
266 | if (panic_on_overflow) | |
267 | panic("Calgary: fix the allocator.\n"); | |
268 | else | |
269 | return bad_dma_address; | |
270 | } | |
271 | } | |
272 | ||
273 | set_bit_string(tbl->it_map, offset, npages); | |
274 | tbl->it_hint = offset + npages; | |
275 | BUG_ON(tbl->it_hint > tbl->it_size); | |
276 | ||
277 | return offset; | |
278 | } | |
279 | ||
280 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr, | |
281 | unsigned int npages, int direction) | |
282 | { | |
283 | unsigned long entry, flags; | |
284 | dma_addr_t ret = bad_dma_address; | |
285 | ||
286 | spin_lock_irqsave(&tbl->it_lock, flags); | |
287 | ||
288 | entry = iommu_range_alloc(tbl, npages); | |
289 | ||
290 | if (unlikely(entry == bad_dma_address)) | |
291 | goto error; | |
292 | ||
293 | /* set the return dma address */ | |
294 | ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK); | |
295 | ||
296 | /* put the TCEs in the HW table */ | |
297 | tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK, | |
298 | direction); | |
299 | ||
300 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
301 | ||
302 | return ret; | |
303 | ||
304 | error: | |
305 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
306 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | |
307 | "iommu %p\n", npages, tbl); | |
308 | return bad_dma_address; | |
309 | } | |
310 | ||
311 | static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
312 | unsigned int npages) | |
313 | { | |
314 | unsigned long entry; | |
796e4390 | 315 | unsigned long badbit; |
310adfdd MBY |
316 | unsigned long badend; |
317 | ||
318 | /* were we called with bad_dma_address? */ | |
319 | badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE); | |
320 | if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) { | |
321 | printk(KERN_ERR "Calgary: driver tried unmapping bad DMA " | |
322 | "address 0x%Lx\n", dma_addr); | |
323 | WARN_ON(1); | |
324 | return; | |
325 | } | |
e465058d JM |
326 | |
327 | entry = dma_addr >> PAGE_SHIFT; | |
328 | ||
329 | BUG_ON(entry + npages > tbl->it_size); | |
330 | ||
331 | tce_free(tbl, entry, npages); | |
332 | ||
796e4390 MBY |
333 | badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages); |
334 | if (badbit != ~0UL) { | |
335 | if (printk_ratelimit()) | |
e465058d JM |
336 | printk(KERN_ERR "Calgary: bit is off at 0x%lx " |
337 | "tbl %p dma 0x%Lx entry 0x%lx npages %u\n", | |
796e4390 | 338 | badbit, tbl, dma_addr, entry, npages); |
e465058d JM |
339 | } |
340 | ||
341 | __clear_bit_string(tbl->it_map, entry, npages); | |
e465058d JM |
342 | } |
343 | ||
344 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
345 | unsigned int npages) | |
346 | { | |
347 | unsigned long flags; | |
348 | ||
349 | spin_lock_irqsave(&tbl->it_lock, flags); | |
350 | ||
351 | __iommu_free(tbl, dma_addr, npages); | |
352 | ||
353 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
354 | } | |
355 | ||
35b6dfa0 MBY |
356 | static inline struct iommu_table *find_iommu_table(struct device *dev) |
357 | { | |
8a244590 MBY |
358 | struct pci_dev *pdev; |
359 | struct pci_bus *pbus; | |
35b6dfa0 MBY |
360 | struct iommu_table *tbl; |
361 | ||
8a244590 MBY |
362 | pdev = to_pci_dev(dev); |
363 | ||
364 | /* is the device behind a bridge? */ | |
365 | if (unlikely(pdev->bus->parent)) | |
366 | pbus = pdev->bus->parent; | |
367 | else | |
368 | pbus = pdev->bus; | |
369 | ||
370 | tbl = pbus->self->sysdata; | |
371 | BUG_ON(pdev->bus->parent && (tbl->it_busno != pdev->bus->parent->number)); | |
35b6dfa0 MBY |
372 | |
373 | return tbl; | |
374 | } | |
375 | ||
e465058d JM |
376 | static void __calgary_unmap_sg(struct iommu_table *tbl, |
377 | struct scatterlist *sglist, int nelems, int direction) | |
378 | { | |
379 | while (nelems--) { | |
380 | unsigned int npages; | |
381 | dma_addr_t dma = sglist->dma_address; | |
382 | unsigned int dmalen = sglist->dma_length; | |
383 | ||
384 | if (dmalen == 0) | |
385 | break; | |
386 | ||
387 | npages = num_dma_pages(dma, dmalen); | |
388 | __iommu_free(tbl, dma, npages); | |
389 | sglist++; | |
390 | } | |
391 | } | |
392 | ||
393 | void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist, | |
394 | int nelems, int direction) | |
395 | { | |
396 | unsigned long flags; | |
35b6dfa0 | 397 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
398 | |
399 | if (!translate_phb(to_pci_dev(dev))) | |
400 | return; | |
401 | ||
402 | spin_lock_irqsave(&tbl->it_lock, flags); | |
403 | ||
404 | __calgary_unmap_sg(tbl, sglist, nelems, direction); | |
405 | ||
406 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
407 | } | |
408 | ||
409 | static int calgary_nontranslate_map_sg(struct device* dev, | |
410 | struct scatterlist *sg, int nelems, int direction) | |
411 | { | |
412 | int i; | |
413 | ||
414 | for (i = 0; i < nelems; i++ ) { | |
415 | struct scatterlist *s = &sg[i]; | |
416 | BUG_ON(!s->page); | |
417 | s->dma_address = virt_to_bus(page_address(s->page) +s->offset); | |
418 | s->dma_length = s->length; | |
419 | } | |
420 | return nelems; | |
421 | } | |
422 | ||
423 | int calgary_map_sg(struct device *dev, struct scatterlist *sg, | |
424 | int nelems, int direction) | |
425 | { | |
35b6dfa0 | 426 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
427 | unsigned long flags; |
428 | unsigned long vaddr; | |
429 | unsigned int npages; | |
430 | unsigned long entry; | |
431 | int i; | |
432 | ||
433 | if (!translate_phb(to_pci_dev(dev))) | |
434 | return calgary_nontranslate_map_sg(dev, sg, nelems, direction); | |
435 | ||
436 | spin_lock_irqsave(&tbl->it_lock, flags); | |
437 | ||
438 | for (i = 0; i < nelems; i++ ) { | |
439 | struct scatterlist *s = &sg[i]; | |
440 | BUG_ON(!s->page); | |
441 | ||
442 | vaddr = (unsigned long)page_address(s->page) + s->offset; | |
443 | npages = num_dma_pages(vaddr, s->length); | |
444 | ||
445 | entry = iommu_range_alloc(tbl, npages); | |
446 | if (entry == bad_dma_address) { | |
447 | /* makes sure unmap knows to stop */ | |
448 | s->dma_length = 0; | |
449 | goto error; | |
450 | } | |
451 | ||
452 | s->dma_address = (entry << PAGE_SHIFT) | s->offset; | |
453 | ||
454 | /* insert into HW table */ | |
455 | tce_build(tbl, entry, npages, vaddr & PAGE_MASK, | |
456 | direction); | |
457 | ||
458 | s->dma_length = s->length; | |
459 | } | |
460 | ||
461 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
462 | ||
463 | return nelems; | |
464 | error: | |
465 | __calgary_unmap_sg(tbl, sg, nelems, direction); | |
466 | for (i = 0; i < nelems; i++) { | |
467 | sg[i].dma_address = bad_dma_address; | |
468 | sg[i].dma_length = 0; | |
469 | } | |
470 | spin_unlock_irqrestore(&tbl->it_lock, flags); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | dma_addr_t calgary_map_single(struct device *dev, void *vaddr, | |
475 | size_t size, int direction) | |
476 | { | |
477 | dma_addr_t dma_handle = bad_dma_address; | |
478 | unsigned long uaddr; | |
479 | unsigned int npages; | |
35b6dfa0 | 480 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
481 | |
482 | uaddr = (unsigned long)vaddr; | |
483 | npages = num_dma_pages(uaddr, size); | |
484 | ||
485 | if (translate_phb(to_pci_dev(dev))) | |
486 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction); | |
487 | else | |
488 | dma_handle = virt_to_bus(vaddr); | |
489 | ||
490 | return dma_handle; | |
491 | } | |
492 | ||
493 | void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle, | |
494 | size_t size, int direction) | |
495 | { | |
35b6dfa0 | 496 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
497 | unsigned int npages; |
498 | ||
499 | if (!translate_phb(to_pci_dev(dev))) | |
500 | return; | |
501 | ||
502 | npages = num_dma_pages(dma_handle, size); | |
503 | iommu_free(tbl, dma_handle, npages); | |
504 | } | |
505 | ||
506 | void* calgary_alloc_coherent(struct device *dev, size_t size, | |
507 | dma_addr_t *dma_handle, gfp_t flag) | |
508 | { | |
509 | void *ret = NULL; | |
510 | dma_addr_t mapping; | |
511 | unsigned int npages, order; | |
35b6dfa0 | 512 | struct iommu_table *tbl = find_iommu_table(dev); |
e465058d JM |
513 | |
514 | size = PAGE_ALIGN(size); /* size rounded up to full pages */ | |
515 | npages = size >> PAGE_SHIFT; | |
516 | order = get_order(size); | |
517 | ||
518 | /* alloc enough pages (and possibly more) */ | |
519 | ret = (void *)__get_free_pages(flag, order); | |
520 | if (!ret) | |
521 | goto error; | |
522 | memset(ret, 0, size); | |
523 | ||
524 | if (translate_phb(to_pci_dev(dev))) { | |
525 | /* set up tces to cover the allocated range */ | |
526 | mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL); | |
527 | if (mapping == bad_dma_address) | |
528 | goto free; | |
529 | ||
530 | *dma_handle = mapping; | |
531 | } else /* non translated slot */ | |
532 | *dma_handle = virt_to_bus(ret); | |
533 | ||
534 | return ret; | |
535 | ||
536 | free: | |
537 | free_pages((unsigned long)ret, get_order(size)); | |
538 | ret = NULL; | |
539 | error: | |
540 | return ret; | |
541 | } | |
542 | ||
e6584504 | 543 | static const struct dma_mapping_ops calgary_dma_ops = { |
e465058d JM |
544 | .alloc_coherent = calgary_alloc_coherent, |
545 | .map_single = calgary_map_single, | |
546 | .unmap_single = calgary_unmap_single, | |
547 | .map_sg = calgary_map_sg, | |
548 | .unmap_sg = calgary_unmap_sg, | |
549 | }; | |
550 | ||
b34e90b8 LV |
551 | static inline void __iomem * busno_to_bbar(unsigned char num) |
552 | { | |
553 | return bus_info[num].bbar; | |
554 | } | |
555 | ||
e465058d JM |
556 | static inline int busno_to_phbid(unsigned char num) |
557 | { | |
f38db651 | 558 | return bus_info[num].phbid; |
e465058d JM |
559 | } |
560 | ||
561 | static inline unsigned long split_queue_offset(unsigned char num) | |
562 | { | |
563 | size_t idx = busno_to_phbid(num); | |
564 | ||
565 | return split_queue_offsets[idx]; | |
566 | } | |
567 | ||
568 | static inline unsigned long tar_offset(unsigned char num) | |
569 | { | |
570 | size_t idx = busno_to_phbid(num); | |
571 | ||
572 | return tar_offsets[idx]; | |
573 | } | |
574 | ||
575 | static inline unsigned long phb_offset(unsigned char num) | |
576 | { | |
577 | size_t idx = busno_to_phbid(num); | |
578 | ||
579 | return phb_offsets[idx]; | |
580 | } | |
581 | ||
582 | static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset) | |
583 | { | |
584 | unsigned long target = ((unsigned long)bar) | offset; | |
585 | return (void __iomem*)target; | |
586 | } | |
587 | ||
8a244590 MBY |
588 | static inline int is_calioc2(unsigned short device) |
589 | { | |
590 | return (device == PCI_DEVICE_ID_IBM_CALIOC2); | |
591 | } | |
592 | ||
593 | static inline int is_calgary(unsigned short device) | |
594 | { | |
595 | return (device == PCI_DEVICE_ID_IBM_CALGARY); | |
596 | } | |
597 | ||
598 | static inline int is_cal_pci_dev(unsigned short device) | |
599 | { | |
600 | return (is_calgary(device) || is_calioc2(device)); | |
601 | } | |
602 | ||
ff297b8c | 603 | static void calgary_tce_cache_blast(struct iommu_table *tbl) |
e465058d JM |
604 | { |
605 | u64 val; | |
606 | u32 aer; | |
607 | int i = 0; | |
608 | void __iomem *bbar = tbl->bbar; | |
609 | void __iomem *target; | |
610 | ||
611 | /* disable arbitration on the bus */ | |
612 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
613 | aer = readl(target); | |
614 | writel(0, target); | |
615 | ||
616 | /* read plssr to ensure it got there */ | |
617 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET); | |
618 | val = readl(target); | |
619 | ||
620 | /* poll split queues until all DMA activity is done */ | |
621 | target = calgary_reg(bbar, split_queue_offset(tbl->it_busno)); | |
622 | do { | |
623 | val = readq(target); | |
624 | i++; | |
625 | } while ((val & 0xff) != 0xff && i < 100); | |
626 | if (i == 100) | |
627 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | |
628 | "continuing anyway\n"); | |
629 | ||
630 | /* invalidate TCE cache */ | |
631 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | |
632 | writeq(tbl->tar_val, target); | |
633 | ||
634 | /* enable arbitration */ | |
635 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET); | |
636 | writel(aer, target); | |
637 | (void)readl(target); /* flush */ | |
638 | } | |
639 | ||
640 | static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start, | |
641 | u64 limit) | |
642 | { | |
643 | unsigned int numpages; | |
644 | ||
645 | limit = limit | 0xfffff; | |
646 | limit++; | |
647 | ||
648 | numpages = ((limit - start) >> PAGE_SHIFT); | |
649 | iommu_range_reserve(dev->sysdata, start, numpages); | |
650 | } | |
651 | ||
652 | static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev) | |
653 | { | |
654 | void __iomem *target; | |
655 | u64 low, high, sizelow; | |
656 | u64 start, limit; | |
657 | struct iommu_table *tbl = dev->sysdata; | |
658 | unsigned char busnum = dev->bus->number; | |
659 | void __iomem *bbar = tbl->bbar; | |
660 | ||
661 | /* peripheral MEM_1 region */ | |
662 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW); | |
663 | low = be32_to_cpu(readl(target)); | |
664 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH); | |
665 | high = be32_to_cpu(readl(target)); | |
666 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE); | |
667 | sizelow = be32_to_cpu(readl(target)); | |
668 | ||
669 | start = (high << 32) | low; | |
670 | limit = sizelow; | |
671 | ||
672 | calgary_reserve_mem_region(dev, start, limit); | |
673 | } | |
674 | ||
675 | static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev) | |
676 | { | |
677 | void __iomem *target; | |
678 | u32 val32; | |
679 | u64 low, high, sizelow, sizehigh; | |
680 | u64 start, limit; | |
681 | struct iommu_table *tbl = dev->sysdata; | |
682 | unsigned char busnum = dev->bus->number; | |
683 | void __iomem *bbar = tbl->bbar; | |
684 | ||
685 | /* is it enabled? */ | |
686 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
687 | val32 = be32_to_cpu(readl(target)); | |
688 | if (!(val32 & PHB_MEM2_ENABLE)) | |
689 | return; | |
690 | ||
691 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW); | |
692 | low = be32_to_cpu(readl(target)); | |
693 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH); | |
694 | high = be32_to_cpu(readl(target)); | |
695 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW); | |
696 | sizelow = be32_to_cpu(readl(target)); | |
697 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH); | |
698 | sizehigh = be32_to_cpu(readl(target)); | |
699 | ||
700 | start = (high << 32) | low; | |
701 | limit = (sizehigh << 32) | sizelow; | |
702 | ||
703 | calgary_reserve_mem_region(dev, start, limit); | |
704 | } | |
705 | ||
706 | /* | |
707 | * some regions of the IO address space do not get translated, so we | |
708 | * must not give devices IO addresses in those regions. The regions | |
709 | * are the 640KB-1MB region and the two PCI peripheral memory holes. | |
710 | * Reserve all of them in the IOMMU bitmap to avoid giving them out | |
711 | * later. | |
712 | */ | |
713 | static void __init calgary_reserve_regions(struct pci_dev *dev) | |
714 | { | |
715 | unsigned int npages; | |
e465058d JM |
716 | u64 start; |
717 | struct iommu_table *tbl = dev->sysdata; | |
718 | ||
310adfdd MBY |
719 | /* reserve EMERGENCY_PAGES from bad_dma_address and up */ |
720 | iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES); | |
e465058d JM |
721 | |
722 | /* avoid the BIOS/VGA first 640KB-1MB region */ | |
8a244590 MBY |
723 | /* for CalIOC2 - avoid the entire first 2MB */ |
724 | if (is_calgary(dev->device)) { | |
725 | start = (640 * 1024); | |
726 | npages = ((1024 - 640) * 1024) >> PAGE_SHIFT; | |
727 | } else { /* calioc2 */ | |
728 | start = 0; | |
729 | npages = (2 * 1024 * 1024) >> PAGE_SHIFT; | |
730 | } | |
e465058d JM |
731 | iommu_range_reserve(tbl, start, npages); |
732 | ||
733 | /* reserve the two PCI peripheral memory regions in IO space */ | |
734 | calgary_reserve_peripheral_mem_1(dev); | |
735 | calgary_reserve_peripheral_mem_2(dev); | |
736 | } | |
737 | ||
738 | static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar) | |
739 | { | |
740 | u64 val64; | |
741 | u64 table_phys; | |
742 | void __iomem *target; | |
743 | int ret; | |
744 | struct iommu_table *tbl; | |
745 | ||
746 | /* build TCE tables for each PHB */ | |
747 | ret = build_tce_table(dev, bbar); | |
748 | if (ret) | |
749 | return ret; | |
750 | ||
f38db651 MBY |
751 | tbl = dev->sysdata; |
752 | tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space; | |
753 | tce_free(tbl, 0, tbl->it_size); | |
754 | ||
c3860108 MBY |
755 | if (is_calgary(dev->device)) |
756 | tbl->chip_ops = &calgary_chip_ops; | |
757 | else if (is_calioc2(dev->device)) | |
758 | tbl->chip_ops = &calioc2_chip_ops; | |
759 | else | |
760 | BUG(); | |
ff297b8c | 761 | |
e465058d JM |
762 | calgary_reserve_regions(dev); |
763 | ||
764 | /* set TARs for each PHB */ | |
765 | target = calgary_reg(bbar, tar_offset(dev->bus->number)); | |
766 | val64 = be64_to_cpu(readq(target)); | |
767 | ||
768 | /* zero out all TAR bits under sw control */ | |
769 | val64 &= ~TAR_SW_BITS; | |
e465058d | 770 | table_phys = (u64)__pa(tbl->it_base); |
8a244590 | 771 | |
e465058d JM |
772 | val64 |= table_phys; |
773 | ||
774 | BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M); | |
775 | val64 |= (u64) specified_table_size; | |
776 | ||
777 | tbl->tar_val = cpu_to_be64(val64); | |
8a244590 | 778 | |
e465058d JM |
779 | writeq(tbl->tar_val, target); |
780 | readq(target); /* flush */ | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
b8f4fe66 | 785 | static void __init calgary_free_bus(struct pci_dev *dev) |
e465058d JM |
786 | { |
787 | u64 val64; | |
788 | struct iommu_table *tbl = dev->sysdata; | |
789 | void __iomem *target; | |
b8f4fe66 | 790 | unsigned int bitmapsz; |
e465058d JM |
791 | |
792 | target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number)); | |
793 | val64 = be64_to_cpu(readq(target)); | |
794 | val64 &= ~TAR_SW_BITS; | |
795 | writeq(cpu_to_be64(val64), target); | |
796 | readq(target); /* flush */ | |
797 | ||
b8f4fe66 MBY |
798 | bitmapsz = tbl->it_size / BITS_PER_BYTE; |
799 | free_pages((unsigned long)tbl->it_map, get_order(bitmapsz)); | |
800 | tbl->it_map = NULL; | |
801 | ||
e465058d JM |
802 | kfree(tbl); |
803 | dev->sysdata = NULL; | |
b8f4fe66 MBY |
804 | |
805 | /* Can't free bootmem allocated memory after system is up :-( */ | |
806 | bus_info[dev->bus->number].tce_space = NULL; | |
e465058d JM |
807 | } |
808 | ||
8a244590 MBY |
809 | static void calgary_dump_error_regs(struct iommu_table *tbl) |
810 | { | |
811 | void __iomem *bbar = tbl->bbar; | |
812 | u32 csr, csmr, plssr, mck; | |
813 | void __iomem *target; | |
814 | unsigned long phboff = phb_offset(tbl->it_busno); | |
815 | unsigned long erroff; | |
816 | u32 errregs[7]; | |
817 | int i; | |
818 | ||
819 | /* dump CSR */ | |
820 | target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET); | |
821 | csr = be32_to_cpu(readl(target)); | |
822 | /* dump PLSSR */ | |
823 | target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET); | |
824 | plssr = be32_to_cpu(readl(target)); | |
825 | /* dump CSMR */ | |
826 | target = calgary_reg(bbar, phboff | 0x290); | |
827 | csmr = be32_to_cpu(readl(target)); | |
828 | /* dump mck */ | |
829 | target = calgary_reg(bbar, phboff | 0x800); | |
830 | mck = be32_to_cpu(readl(target)); | |
831 | ||
832 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR " | |
833 | "0x%08x@MCK\n", csr, plssr, csmr, mck); | |
834 | ||
835 | /* dump rest of error regs */ | |
836 | printk(KERN_EMERG "Calgary: "); | |
837 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | |
838 | erroff = (0x810 + (i * 0x10)); /* err regs are at 0x810 - 0x870 */ | |
839 | target = calgary_reg(bbar, phboff | erroff); | |
840 | errregs[i] = be32_to_cpu(readl(target)); | |
841 | printk("0x%08x@0x%lx ", errregs[i], erroff); | |
842 | } | |
843 | printk("\n"); | |
844 | } | |
845 | ||
e465058d JM |
846 | static void calgary_watchdog(unsigned long data) |
847 | { | |
848 | struct pci_dev *dev = (struct pci_dev *)data; | |
849 | struct iommu_table *tbl = dev->sysdata; | |
850 | void __iomem *bbar = tbl->bbar; | |
851 | u32 val32; | |
852 | void __iomem *target; | |
853 | ||
854 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET); | |
855 | val32 = be32_to_cpu(readl(target)); | |
856 | ||
857 | /* If no error, the agent ID in the CSR is not valid */ | |
858 | if (val32 & CSR_AGENT_MASK) { | |
8a244590 MBY |
859 | printk(KERN_EMERG "Calgary: DMA error on PHB %#x\n", |
860 | dev->bus->number); | |
861 | calgary_dump_error_regs(tbl); | |
862 | ||
863 | /* reset error */ | |
e465058d JM |
864 | writel(0, target); |
865 | ||
866 | /* Disable bus that caused the error */ | |
867 | target = calgary_reg(bbar, phb_offset(tbl->it_busno) | | |
8a244590 | 868 | PHB_CONFIG_RW_OFFSET); |
e465058d JM |
869 | val32 = be32_to_cpu(readl(target)); |
870 | val32 |= PHB_SLOT_DISABLE; | |
871 | writel(cpu_to_be32(val32), target); | |
872 | readl(target); /* flush */ | |
873 | } else { | |
874 | /* Reset the timer */ | |
875 | mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ); | |
876 | } | |
877 | } | |
878 | ||
a2b663f6 MBY |
879 | static void __init calgary_set_split_completion_timeout(void __iomem *bbar, |
880 | unsigned char busnum, unsigned long timeout) | |
cb01fc72 MBY |
881 | { |
882 | u64 val64; | |
883 | void __iomem *target; | |
58db8548 | 884 | unsigned int phb_shift = ~0; /* silence gcc */ |
cb01fc72 MBY |
885 | u64 mask; |
886 | ||
887 | switch (busno_to_phbid(busnum)) { | |
888 | case 0: phb_shift = (63 - 19); | |
889 | break; | |
890 | case 1: phb_shift = (63 - 23); | |
891 | break; | |
892 | case 2: phb_shift = (63 - 27); | |
893 | break; | |
894 | case 3: phb_shift = (63 - 35); | |
895 | break; | |
896 | default: | |
897 | BUG_ON(busno_to_phbid(busnum)); | |
898 | } | |
899 | ||
900 | target = calgary_reg(bbar, CALGARY_CONFIG_REG); | |
901 | val64 = be64_to_cpu(readq(target)); | |
902 | ||
903 | /* zero out this PHB's timer bits */ | |
904 | mask = ~(0xFUL << phb_shift); | |
905 | val64 &= mask; | |
a2b663f6 | 906 | val64 |= (timeout << phb_shift); |
cb01fc72 MBY |
907 | writeq(cpu_to_be64(val64), target); |
908 | readq(target); /* flush */ | |
909 | } | |
910 | ||
c3860108 MBY |
911 | static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) |
912 | { | |
913 | unsigned char busnum = dev->bus->number; | |
914 | void __iomem *bbar = tbl->bbar; | |
915 | void __iomem *target; | |
916 | u32 val; | |
917 | ||
918 | /* | |
919 | * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1 | |
920 | */ | |
921 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2); | |
922 | val = cpu_to_be32(readl(target)); | |
923 | val |= 0x00800000; | |
924 | writel(cpu_to_be32(val), target); | |
925 | } | |
926 | ||
927 | static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev) | |
b8d2ea1b MBY |
928 | { |
929 | unsigned char busnum = dev->bus->number; | |
b8d2ea1b MBY |
930 | |
931 | /* | |
932 | * Give split completion a longer timeout on bus 1 for aic94xx | |
933 | * http://bugzilla.kernel.org/show_bug.cgi?id=7180 | |
934 | */ | |
c3860108 | 935 | if (is_calgary(dev->device) && (busnum == 1)) |
b8d2ea1b MBY |
936 | calgary_set_split_completion_timeout(tbl->bbar, busnum, |
937 | CCR_2SEC_TIMEOUT); | |
938 | } | |
939 | ||
e465058d JM |
940 | static void __init calgary_enable_translation(struct pci_dev *dev) |
941 | { | |
942 | u32 val32; | |
943 | unsigned char busnum; | |
944 | void __iomem *target; | |
945 | void __iomem *bbar; | |
946 | struct iommu_table *tbl; | |
947 | ||
948 | busnum = dev->bus->number; | |
949 | tbl = dev->sysdata; | |
950 | bbar = tbl->bbar; | |
951 | ||
952 | /* enable TCE in PHB Config Register */ | |
953 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
954 | val32 = be32_to_cpu(readl(target)); | |
955 | val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE; | |
956 | ||
8a244590 MBY |
957 | printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n", |
958 | (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ? | |
959 | "Calgary" : "CalIOC2", busnum); | |
e465058d JM |
960 | printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this " |
961 | "bus.\n"); | |
962 | ||
963 | writel(cpu_to_be32(val32), target); | |
964 | readl(target); /* flush */ | |
965 | ||
966 | init_timer(&tbl->watchdog_timer); | |
967 | tbl->watchdog_timer.function = &calgary_watchdog; | |
968 | tbl->watchdog_timer.data = (unsigned long)dev; | |
969 | mod_timer(&tbl->watchdog_timer, jiffies); | |
970 | } | |
971 | ||
972 | static void __init calgary_disable_translation(struct pci_dev *dev) | |
973 | { | |
974 | u32 val32; | |
975 | unsigned char busnum; | |
976 | void __iomem *target; | |
977 | void __iomem *bbar; | |
978 | struct iommu_table *tbl; | |
979 | ||
980 | busnum = dev->bus->number; | |
981 | tbl = dev->sysdata; | |
982 | bbar = tbl->bbar; | |
983 | ||
984 | /* disable TCE in PHB Config Register */ | |
985 | target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET); | |
986 | val32 = be32_to_cpu(readl(target)); | |
987 | val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE); | |
988 | ||
70d666d6 | 989 | printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum); |
e465058d JM |
990 | writel(cpu_to_be32(val32), target); |
991 | readl(target); /* flush */ | |
992 | ||
993 | del_timer_sync(&tbl->watchdog_timer); | |
994 | } | |
995 | ||
a4fc520a | 996 | static void __init calgary_init_one_nontraslated(struct pci_dev *dev) |
e465058d | 997 | { |
871b1700 | 998 | pci_dev_get(dev); |
e465058d | 999 | dev->sysdata = NULL; |
8a244590 MBY |
1000 | |
1001 | /* is the device behind a bridge? */ | |
1002 | if (dev->bus->parent) | |
1003 | dev->bus->parent->self = dev; | |
1004 | else | |
1005 | dev->bus->self = dev; | |
e465058d JM |
1006 | } |
1007 | ||
1008 | static int __init calgary_init_one(struct pci_dev *dev) | |
1009 | { | |
e465058d | 1010 | void __iomem *bbar; |
ff297b8c | 1011 | struct iommu_table *tbl; |
e465058d JM |
1012 | int ret; |
1013 | ||
dedc9937 JM |
1014 | BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM); |
1015 | ||
eae93755 | 1016 | bbar = busno_to_bbar(dev->bus->number); |
e465058d JM |
1017 | ret = calgary_setup_tar(dev, bbar); |
1018 | if (ret) | |
eae93755 | 1019 | goto done; |
e465058d | 1020 | |
871b1700 | 1021 | pci_dev_get(dev); |
8a244590 MBY |
1022 | |
1023 | if (dev->bus->parent) { | |
1024 | if (dev->bus->parent->self) | |
1025 | printk(KERN_WARNING "Calgary: IEEEE, dev %p has " | |
1026 | "bus->parent->self!\n", dev); | |
1027 | dev->bus->parent->self = dev; | |
1028 | } else | |
1029 | dev->bus->self = dev; | |
b8d2ea1b | 1030 | |
ff297b8c MBY |
1031 | tbl = dev->sysdata; |
1032 | tbl->chip_ops->handle_quirks(tbl, dev); | |
b8d2ea1b | 1033 | |
e465058d JM |
1034 | calgary_enable_translation(dev); |
1035 | ||
1036 | return 0; | |
1037 | ||
e465058d JM |
1038 | done: |
1039 | return ret; | |
1040 | } | |
1041 | ||
eae93755 | 1042 | static int __init calgary_locate_bbars(void) |
e465058d | 1043 | { |
eae93755 MBY |
1044 | int ret; |
1045 | int rioidx, phb, bus; | |
b34e90b8 LV |
1046 | void __iomem *bbar; |
1047 | void __iomem *target; | |
eae93755 | 1048 | unsigned long offset; |
b34e90b8 LV |
1049 | u8 start_bus, end_bus; |
1050 | u32 val; | |
1051 | ||
eae93755 MBY |
1052 | ret = -ENODATA; |
1053 | for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) { | |
1054 | struct rio_detail *rio = rio_devs[rioidx]; | |
b34e90b8 | 1055 | |
eae93755 | 1056 | if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY)) |
b34e90b8 LV |
1057 | continue; |
1058 | ||
1059 | /* map entire 1MB of Calgary config space */ | |
eae93755 MBY |
1060 | bbar = ioremap_nocache(rio->BBAR, 1024 * 1024); |
1061 | if (!bbar) | |
1062 | goto error; | |
b34e90b8 LV |
1063 | |
1064 | for (phb = 0; phb < PHBS_PER_CALGARY; phb++) { | |
eae93755 MBY |
1065 | offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET; |
1066 | target = calgary_reg(bbar, offset); | |
b34e90b8 | 1067 | |
b34e90b8 | 1068 | val = be32_to_cpu(readl(target)); |
8a244590 | 1069 | |
b34e90b8 | 1070 | start_bus = (u8)((val & 0x00FF0000) >> 16); |
eae93755 | 1071 | end_bus = (u8)((val & 0x0000FF00) >> 8); |
8a244590 MBY |
1072 | |
1073 | if (end_bus) { | |
1074 | for (bus = start_bus; bus <= end_bus; bus++) { | |
1075 | bus_info[bus].bbar = bbar; | |
1076 | bus_info[bus].phbid = phb; | |
1077 | } | |
1078 | } else { | |
1079 | bus_info[start_bus].bbar = bbar; | |
1080 | bus_info[start_bus].phbid = phb; | |
b34e90b8 LV |
1081 | } |
1082 | } | |
1083 | } | |
1084 | ||
eae93755 MBY |
1085 | return 0; |
1086 | ||
1087 | error: | |
1088 | /* scan bus_info and iounmap any bbars we previously ioremap'd */ | |
1089 | for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++) | |
1090 | if (bus_info[bus].bbar) | |
1091 | iounmap(bus_info[bus].bbar); | |
1092 | ||
1093 | return ret; | |
1094 | } | |
1095 | ||
1096 | static int __init calgary_init(void) | |
1097 | { | |
1098 | int ret; | |
1099 | struct pci_dev *dev = NULL; | |
8a244590 | 1100 | void* tce_space; |
eae93755 MBY |
1101 | |
1102 | ret = calgary_locate_bbars(); | |
1103 | if (ret) | |
1104 | return ret; | |
e465058d | 1105 | |
dedc9937 | 1106 | do { |
8a244590 | 1107 | dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev); |
e465058d JM |
1108 | if (!dev) |
1109 | break; | |
8a244590 MBY |
1110 | if (!is_cal_pci_dev(dev->device)) |
1111 | continue; | |
e465058d JM |
1112 | if (!translate_phb(dev)) { |
1113 | calgary_init_one_nontraslated(dev); | |
1114 | continue; | |
1115 | } | |
8a244590 MBY |
1116 | tce_space = bus_info[dev->bus->number].tce_space; |
1117 | if (!tce_space && !translate_empty_slots) { | |
1118 | printk("Calg: %p failed tce_space check\n", dev); | |
e465058d | 1119 | continue; |
8a244590 | 1120 | } |
e465058d JM |
1121 | ret = calgary_init_one(dev); |
1122 | if (ret) | |
1123 | goto error; | |
dedc9937 | 1124 | } while (1); |
e465058d JM |
1125 | |
1126 | return ret; | |
1127 | ||
1128 | error: | |
dedc9937 | 1129 | do { |
7cd8b686 | 1130 | dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM, |
8a244590 | 1131 | PCI_ANY_ID, dev); |
9f2dc46d MBY |
1132 | if (!dev) |
1133 | break; | |
8a244590 MBY |
1134 | if (!is_cal_pci_dev(dev->device)) |
1135 | continue; | |
e465058d JM |
1136 | if (!translate_phb(dev)) { |
1137 | pci_dev_put(dev); | |
1138 | continue; | |
1139 | } | |
f38db651 | 1140 | if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots) |
e465058d | 1141 | continue; |
871b1700 | 1142 | |
e465058d | 1143 | calgary_disable_translation(dev); |
b8f4fe66 | 1144 | calgary_free_bus(dev); |
871b1700 | 1145 | pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */ |
dedc9937 | 1146 | } while (1); |
e465058d JM |
1147 | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | static inline int __init determine_tce_table_size(u64 ram) | |
1152 | { | |
1153 | int ret; | |
1154 | ||
1155 | if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED) | |
1156 | return specified_table_size; | |
1157 | ||
1158 | /* | |
1159 | * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to | |
1160 | * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each | |
1161 | * larger table size has twice as many entries, so shift the | |
1162 | * max ram address by 13 to divide by 8K and then look at the | |
1163 | * order of the result to choose between 0-7. | |
1164 | */ | |
1165 | ret = get_order(ram >> 13); | |
1166 | if (ret > TCE_TABLE_SIZE_8M) | |
1167 | ret = TCE_TABLE_SIZE_8M; | |
1168 | ||
1169 | return ret; | |
1170 | } | |
1171 | ||
b34e90b8 LV |
1172 | static int __init build_detail_arrays(void) |
1173 | { | |
1174 | unsigned long ptr; | |
1175 | int i, scal_detail_size, rio_detail_size; | |
1176 | ||
1177 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){ | |
1178 | printk(KERN_WARNING | |
eae93755 | 1179 | "Calgary: MAX_NUMNODES too low! Defined as %d, " |
b34e90b8 LV |
1180 | "but system has %d nodes.\n", |
1181 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | |
1182 | return -ENODEV; | |
1183 | } | |
1184 | ||
1185 | switch (rio_table_hdr->version){ | |
b34e90b8 LV |
1186 | case 2: |
1187 | scal_detail_size = 11; | |
1188 | rio_detail_size = 13; | |
1189 | break; | |
1190 | case 3: | |
1191 | scal_detail_size = 12; | |
1192 | rio_detail_size = 15; | |
1193 | break; | |
eae93755 MBY |
1194 | default: |
1195 | printk(KERN_WARNING | |
1196 | "Calgary: Invalid Rio Grande Table Version: %d\n", | |
1197 | rio_table_hdr->version); | |
1198 | return -EPROTO; | |
b34e90b8 LV |
1199 | } |
1200 | ||
1201 | ptr = ((unsigned long)rio_table_hdr) + 3; | |
1202 | for (i = 0; i < rio_table_hdr->num_scal_dev; | |
1203 | i++, ptr += scal_detail_size) | |
1204 | scal_devs[i] = (struct scal_detail *)ptr; | |
1205 | ||
1206 | for (i = 0; i < rio_table_hdr->num_rio_dev; | |
1207 | i++, ptr += rio_detail_size) | |
1208 | rio_devs[i] = (struct rio_detail *)ptr; | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
8a244590 | 1213 | static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev) |
e465058d | 1214 | { |
8a244590 | 1215 | int dev; |
e465058d | 1216 | u32 val; |
8a244590 MBY |
1217 | |
1218 | if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) { | |
1219 | /* | |
1220 | * FIXME: properly scan for devices accross the | |
1221 | * PCI-to-PCI bridge on every CalIOC2 port. | |
1222 | */ | |
1223 | return 1; | |
1224 | } | |
1225 | ||
1226 | for (dev = 1; dev < 8; dev++) { | |
1227 | val = read_pci_config(bus, dev, 0, 0); | |
1228 | if (val != 0xffffffff) | |
1229 | break; | |
1230 | } | |
1231 | return (val != 0xffffffff); | |
1232 | } | |
1233 | ||
1234 | void __init detect_calgary(void) | |
1235 | { | |
d2105b10 | 1236 | int bus; |
e465058d | 1237 | void *tbl; |
d2105b10 | 1238 | int calgary_found = 0; |
b34e90b8 | 1239 | unsigned long ptr; |
136f1e7a | 1240 | unsigned int offset, prev_offset; |
eae93755 | 1241 | int ret; |
e465058d JM |
1242 | |
1243 | /* | |
1244 | * if the user specified iommu=off or iommu=soft or we found | |
1245 | * another HW IOMMU already, bail out. | |
1246 | */ | |
1247 | if (swiotlb || no_iommu || iommu_detected) | |
1248 | return; | |
1249 | ||
bff6547b MBY |
1250 | if (!use_calgary) |
1251 | return; | |
1252 | ||
0637a70a AK |
1253 | if (!early_pci_allowed()) |
1254 | return; | |
1255 | ||
b92cc559 MBY |
1256 | printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n"); |
1257 | ||
b34e90b8 LV |
1258 | ptr = (unsigned long)phys_to_virt(get_bios_ebda()); |
1259 | ||
1260 | rio_table_hdr = NULL; | |
136f1e7a | 1261 | prev_offset = 0; |
b34e90b8 | 1262 | offset = 0x180; |
136f1e7a IM |
1263 | /* |
1264 | * The next offset is stored in the 1st word. | |
1265 | * Only parse up until the offset increases: | |
1266 | */ | |
1267 | while (offset > prev_offset) { | |
b34e90b8 LV |
1268 | /* The block id is stored in the 2nd word */ |
1269 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){ | |
1270 | /* set the pointer past the offset & block id */ | |
eae93755 | 1271 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); |
b34e90b8 LV |
1272 | break; |
1273 | } | |
136f1e7a | 1274 | prev_offset = offset; |
b34e90b8 LV |
1275 | offset = *((unsigned short *)(ptr + offset)); |
1276 | } | |
eae93755 | 1277 | if (!rio_table_hdr) { |
b92cc559 MBY |
1278 | printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table " |
1279 | "in EBDA - bailing!\n"); | |
b34e90b8 LV |
1280 | return; |
1281 | } | |
1282 | ||
eae93755 MBY |
1283 | ret = build_detail_arrays(); |
1284 | if (ret) { | |
b92cc559 | 1285 | printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret); |
b34e90b8 | 1286 | return; |
eae93755 | 1287 | } |
b34e90b8 | 1288 | |
e465058d JM |
1289 | specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE); |
1290 | ||
d2105b10 | 1291 | for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) { |
f38db651 | 1292 | struct calgary_bus_info *info = &bus_info[bus]; |
8a244590 MBY |
1293 | unsigned short pci_device; |
1294 | u32 val; | |
1295 | ||
1296 | val = read_pci_config(bus, 0, 0, 0); | |
1297 | pci_device = (val & 0xFFFF0000) >> 16; | |
d2105b10 | 1298 | |
8a244590 | 1299 | if (!is_cal_pci_dev(pci_device)) |
e465058d | 1300 | continue; |
d2105b10 | 1301 | |
f38db651 | 1302 | if (info->translation_disabled) |
e465058d | 1303 | continue; |
f38db651 | 1304 | |
8a244590 MBY |
1305 | if (calgary_bus_has_devices(bus, pci_device) || |
1306 | translate_empty_slots) { | |
1307 | tbl = alloc_tce_table(); | |
1308 | if (!tbl) | |
1309 | goto cleanup; | |
1310 | info->tce_space = tbl; | |
1311 | calgary_found = 1; | |
1312 | printk("Calg: allocated tce_table %p for bus 0x%x\n", | |
1313 | info->tce_space, bus); | |
d2105b10 | 1314 | } |
e465058d JM |
1315 | } |
1316 | ||
b92cc559 MBY |
1317 | printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n", |
1318 | calgary_found ? "found" : "not found"); | |
1319 | ||
d2105b10 | 1320 | if (calgary_found) { |
e465058d JM |
1321 | iommu_detected = 1; |
1322 | calgary_detected = 1; | |
de684652 MBY |
1323 | printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n"); |
1324 | printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, " | |
1325 | "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size, | |
1326 | debugging ? "enabled" : "disabled"); | |
e465058d JM |
1327 | } |
1328 | return; | |
1329 | ||
1330 | cleanup: | |
f38db651 MBY |
1331 | for (--bus; bus >= 0; --bus) { |
1332 | struct calgary_bus_info *info = &bus_info[bus]; | |
1333 | ||
1334 | if (info->tce_space) | |
1335 | free_tce_table(info->tce_space); | |
1336 | } | |
e465058d JM |
1337 | } |
1338 | ||
1339 | int __init calgary_iommu_init(void) | |
1340 | { | |
1341 | int ret; | |
1342 | ||
1343 | if (no_iommu || swiotlb) | |
1344 | return -ENODEV; | |
1345 | ||
1346 | if (!calgary_detected) | |
1347 | return -ENODEV; | |
1348 | ||
1349 | /* ok, we're trying to use Calgary - let's roll */ | |
1350 | printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n"); | |
1351 | ||
1352 | ret = calgary_init(); | |
1353 | if (ret) { | |
1354 | printk(KERN_ERR "PCI-DMA: Calgary init failed %d, " | |
1355 | "falling back to no_iommu\n", ret); | |
1356 | if (end_pfn > MAX_DMA32_PFN) | |
1357 | printk(KERN_ERR "WARNING more than 4GB of memory, " | |
1358 | "32bit PCI may malfunction.\n"); | |
1359 | return ret; | |
1360 | } | |
1361 | ||
1362 | force_iommu = 1; | |
310adfdd | 1363 | bad_dma_address = 0x0; |
e465058d JM |
1364 | dma_ops = &calgary_dma_ops; |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static int __init calgary_parse_options(char *p) | |
1370 | { | |
1371 | unsigned int bridge; | |
1372 | size_t len; | |
1373 | char* endp; | |
1374 | ||
1375 | while (*p) { | |
1376 | if (!strncmp(p, "64k", 3)) | |
1377 | specified_table_size = TCE_TABLE_SIZE_64K; | |
1378 | else if (!strncmp(p, "128k", 4)) | |
1379 | specified_table_size = TCE_TABLE_SIZE_128K; | |
1380 | else if (!strncmp(p, "256k", 4)) | |
1381 | specified_table_size = TCE_TABLE_SIZE_256K; | |
1382 | else if (!strncmp(p, "512k", 4)) | |
1383 | specified_table_size = TCE_TABLE_SIZE_512K; | |
1384 | else if (!strncmp(p, "1M", 2)) | |
1385 | specified_table_size = TCE_TABLE_SIZE_1M; | |
1386 | else if (!strncmp(p, "2M", 2)) | |
1387 | specified_table_size = TCE_TABLE_SIZE_2M; | |
1388 | else if (!strncmp(p, "4M", 2)) | |
1389 | specified_table_size = TCE_TABLE_SIZE_4M; | |
1390 | else if (!strncmp(p, "8M", 2)) | |
1391 | specified_table_size = TCE_TABLE_SIZE_8M; | |
1392 | ||
1393 | len = strlen("translate_empty_slots"); | |
1394 | if (!strncmp(p, "translate_empty_slots", len)) | |
1395 | translate_empty_slots = 1; | |
1396 | ||
1397 | len = strlen("disable"); | |
1398 | if (!strncmp(p, "disable", len)) { | |
1399 | p += len; | |
1400 | if (*p == '=') | |
1401 | ++p; | |
1402 | if (*p == '\0') | |
1403 | break; | |
1404 | bridge = simple_strtol(p, &endp, 0); | |
1405 | if (p == endp) | |
1406 | break; | |
1407 | ||
d2105b10 | 1408 | if (bridge < MAX_PHB_BUS_NUM) { |
e465058d | 1409 | printk(KERN_INFO "Calgary: disabling " |
70d666d6 | 1410 | "translation for PHB %#x\n", bridge); |
f38db651 | 1411 | bus_info[bridge].translation_disabled = 1; |
e465058d JM |
1412 | } |
1413 | } | |
1414 | ||
1415 | p = strpbrk(p, ","); | |
1416 | if (!p) | |
1417 | break; | |
1418 | ||
1419 | p++; /* skip ',' */ | |
1420 | } | |
1421 | return 1; | |
1422 | } | |
1423 | __setup("calgary=", calgary_parse_options); |