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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86-64/kernel/time.c | |
3 | * | |
4 | * "High Precision Event Timer" based timekeeping. | |
5 | * | |
6 | * Copyright (c) 1991,1992,1995 Linus Torvalds | |
7 | * Copyright (c) 1994 Alan Modra | |
8 | * Copyright (c) 1995 Markus Kuhn | |
9 | * Copyright (c) 1996 Ingo Molnar | |
10 | * Copyright (c) 1998 Andrea Arcangeli | |
11 | * Copyright (c) 2002 Vojtech Pavlik | |
12 | * Copyright (c) 2003 Andi Kleen | |
13 | * RTC support code taken from arch/i386/kernel/timers/time_hpet.c | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/mc146818rtc.h> | |
1da177e4 LT |
21 | #include <linux/time.h> |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/sysdev.h> | |
26 | #include <linux/bcd.h> | |
27 | #include <linux/kallsyms.h> | |
312df5f1 | 28 | #include <linux/acpi.h> |
8d916406 | 29 | #ifdef CONFIG_ACPI |
312df5f1 | 30 | #include <acpi/achware.h> /* for PM timer frequency */ |
8d916406 | 31 | #endif |
1da177e4 LT |
32 | #include <asm/8253pit.h> |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/vsyscall.h> | |
35 | #include <asm/timex.h> | |
36 | #include <asm/proto.h> | |
37 | #include <asm/hpet.h> | |
38 | #include <asm/sections.h> | |
39 | #include <linux/cpufreq.h> | |
40 | #include <linux/hpet.h> | |
41 | #ifdef CONFIG_X86_LOCAL_APIC | |
42 | #include <asm/apic.h> | |
43 | #endif | |
44 | ||
1da177e4 LT |
45 | #ifdef CONFIG_CPU_FREQ |
46 | static void cpufreq_delayed_get(void); | |
47 | #endif | |
48 | extern void i8254_timer_resume(void); | |
49 | extern int using_apic_timer; | |
50 | ||
51 | DEFINE_SPINLOCK(rtc_lock); | |
52 | DEFINE_SPINLOCK(i8253_lock); | |
53 | ||
73dea47f | 54 | int nohpet __initdata = 0; |
1da177e4 LT |
55 | static int notsc __initdata = 0; |
56 | ||
57 | #undef HPET_HACK_ENABLE_DANGEROUS | |
58 | ||
59 | unsigned int cpu_khz; /* TSC clocks / usec, not used here */ | |
60 | static unsigned long hpet_period; /* fsecs / HPET clock */ | |
61 | unsigned long hpet_tick; /* HPET clocks / interrupt */ | |
33042a9f | 62 | int hpet_use_timer; /* Use counter of hpet for time keeping, otherwise PIT */ |
1da177e4 LT |
63 | unsigned long vxtime_hz = PIT_TICK_RATE; |
64 | int report_lost_ticks; /* command line option */ | |
65 | unsigned long long monotonic_base; | |
66 | ||
67 | struct vxtime_data __vxtime __section_vxtime; /* for vsyscalls */ | |
68 | ||
69 | volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES; | |
70 | unsigned long __wall_jiffies __section_wall_jiffies = INITIAL_JIFFIES; | |
71 | struct timespec __xtime __section_xtime; | |
72 | struct timezone __sys_tz __section_sys_tz; | |
73 | ||
1da177e4 LT |
74 | /* |
75 | * do_gettimeoffset() returns microseconds since last timer interrupt was | |
76 | * triggered by hardware. A memory read of HPET is slower than a register read | |
77 | * of TSC, but much more reliable. It's also synchronized to the timer | |
78 | * interrupt. Note that do_gettimeoffset() may return more than hpet_tick, if a | |
79 | * timer interrupt has happened already, but vxtime.trigger wasn't updated yet. | |
80 | * This is not a problem, because jiffies hasn't updated either. They are bound | |
81 | * together by xtime_lock. | |
82 | */ | |
83 | ||
84 | static inline unsigned int do_gettimeoffset_tsc(void) | |
85 | { | |
86 | unsigned long t; | |
87 | unsigned long x; | |
c818a181 | 88 | t = get_cycles_sync(); |
1da177e4 LT |
89 | if (t < vxtime.last_tsc) t = vxtime.last_tsc; /* hack */ |
90 | x = ((t - vxtime.last_tsc) * vxtime.tsc_quot) >> 32; | |
91 | return x; | |
92 | } | |
93 | ||
94 | static inline unsigned int do_gettimeoffset_hpet(void) | |
95 | { | |
a3a00751 JS |
96 | /* cap counter read to one tick to avoid inconsistencies */ |
97 | unsigned long counter = hpet_readl(HPET_COUNTER) - vxtime.last; | |
98 | return (min(counter,hpet_tick) * vxtime.quot) >> 32; | |
1da177e4 LT |
99 | } |
100 | ||
101 | unsigned int (*do_gettimeoffset)(void) = do_gettimeoffset_tsc; | |
102 | ||
103 | /* | |
104 | * This version of gettimeofday() has microsecond resolution and better than | |
105 | * microsecond precision, as we're using at least a 10 MHz (usually 14.31818 | |
106 | * MHz) HPET timer. | |
107 | */ | |
108 | ||
109 | void do_gettimeofday(struct timeval *tv) | |
110 | { | |
111 | unsigned long seq, t; | |
112 | unsigned int sec, usec; | |
113 | ||
114 | do { | |
115 | seq = read_seqbegin(&xtime_lock); | |
116 | ||
117 | sec = xtime.tv_sec; | |
118 | usec = xtime.tv_nsec / 1000; | |
119 | ||
120 | /* i386 does some correction here to keep the clock | |
121 | monotonous even when ntpd is fixing drift. | |
122 | But they didn't work for me, there is a non monotonic | |
123 | clock anyways with ntp. | |
124 | I dropped all corrections now until a real solution can | |
125 | be found. Note when you fix it here you need to do the same | |
126 | in arch/x86_64/kernel/vsyscall.c and export all needed | |
127 | variables in vmlinux.lds. -AK */ | |
128 | ||
129 | t = (jiffies - wall_jiffies) * (1000000L / HZ) + | |
130 | do_gettimeoffset(); | |
131 | usec += t; | |
132 | ||
133 | } while (read_seqretry(&xtime_lock, seq)); | |
134 | ||
135 | tv->tv_sec = sec + usec / 1000000; | |
136 | tv->tv_usec = usec % 1000000; | |
137 | } | |
138 | ||
139 | EXPORT_SYMBOL(do_gettimeofday); | |
140 | ||
141 | /* | |
142 | * settimeofday() first undoes the correction that gettimeofday would do | |
143 | * on the time, and then saves it. This is ugly, but has been like this for | |
144 | * ages already. | |
145 | */ | |
146 | ||
147 | int do_settimeofday(struct timespec *tv) | |
148 | { | |
149 | time_t wtm_sec, sec = tv->tv_sec; | |
150 | long wtm_nsec, nsec = tv->tv_nsec; | |
151 | ||
152 | if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) | |
153 | return -EINVAL; | |
154 | ||
155 | write_seqlock_irq(&xtime_lock); | |
156 | ||
157 | nsec -= do_gettimeoffset() * 1000 + | |
158 | (jiffies - wall_jiffies) * (NSEC_PER_SEC/HZ); | |
159 | ||
160 | wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec); | |
161 | wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec); | |
162 | ||
163 | set_normalized_timespec(&xtime, sec, nsec); | |
164 | set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); | |
165 | ||
b149ee22 | 166 | ntp_clear(); |
1da177e4 LT |
167 | |
168 | write_sequnlock_irq(&xtime_lock); | |
169 | clock_was_set(); | |
170 | return 0; | |
171 | } | |
172 | ||
173 | EXPORT_SYMBOL(do_settimeofday); | |
174 | ||
175 | unsigned long profile_pc(struct pt_regs *regs) | |
176 | { | |
177 | unsigned long pc = instruction_pointer(regs); | |
178 | ||
179 | /* Assume the lock function has either no stack frame or only a single word. | |
180 | This checks if the address on the stack looks like a kernel text address. | |
181 | There is a small window for false hits, but in that case the tick | |
182 | is just accounted to the spinlock function. | |
183 | Better would be to write these functions in assembler again | |
184 | and check exactly. */ | |
185 | if (in_lock_functions(pc)) { | |
186 | char *v = *(char **)regs->rsp; | |
187 | if ((v >= _stext && v <= _etext) || | |
188 | (v >= _sinittext && v <= _einittext) || | |
189 | (v >= (char *)MODULES_VADDR && v <= (char *)MODULES_END)) | |
190 | return (unsigned long)v; | |
191 | return ((unsigned long *)regs->rsp)[1]; | |
192 | } | |
193 | return pc; | |
194 | } | |
195 | EXPORT_SYMBOL(profile_pc); | |
196 | ||
197 | /* | |
198 | * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500 | |
199 | * ms after the second nowtime has started, because when nowtime is written | |
200 | * into the registers of the CMOS clock, it will jump to the next second | |
201 | * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data | |
202 | * sheet for details. | |
203 | */ | |
204 | ||
205 | static void set_rtc_mmss(unsigned long nowtime) | |
206 | { | |
207 | int real_seconds, real_minutes, cmos_minutes; | |
208 | unsigned char control, freq_select; | |
209 | ||
210 | /* | |
211 | * IRQs are disabled when we're called from the timer interrupt, | |
212 | * no need for spin_lock_irqsave() | |
213 | */ | |
214 | ||
215 | spin_lock(&rtc_lock); | |
216 | ||
217 | /* | |
218 | * Tell the clock it's being set and stop it. | |
219 | */ | |
220 | ||
221 | control = CMOS_READ(RTC_CONTROL); | |
222 | CMOS_WRITE(control | RTC_SET, RTC_CONTROL); | |
223 | ||
224 | freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
225 | CMOS_WRITE(freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT); | |
226 | ||
227 | cmos_minutes = CMOS_READ(RTC_MINUTES); | |
228 | BCD_TO_BIN(cmos_minutes); | |
229 | ||
230 | /* | |
231 | * since we're only adjusting minutes and seconds, don't interfere with hour | |
232 | * overflow. This avoids messing with unknown time zones but requires your RTC | |
233 | * not to be off by more than 15 minutes. Since we're calling it only when | |
234 | * our clock is externally synchronized using NTP, this shouldn't be a problem. | |
235 | */ | |
236 | ||
237 | real_seconds = nowtime % 60; | |
238 | real_minutes = nowtime / 60; | |
239 | if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1) | |
240 | real_minutes += 30; /* correct for half hour time zone */ | |
241 | real_minutes %= 60; | |
242 | ||
243 | #if 0 | |
244 | /* AMD 8111 is a really bad time keeper and hits this regularly. | |
245 | It probably was an attempt to avoid screwing up DST, but ignore | |
246 | that for now. */ | |
247 | if (abs(real_minutes - cmos_minutes) >= 30) { | |
248 | printk(KERN_WARNING "time.c: can't update CMOS clock " | |
249 | "from %d to %d\n", cmos_minutes, real_minutes); | |
250 | } else | |
251 | #endif | |
252 | ||
253 | { | |
0b91317e AK |
254 | BIN_TO_BCD(real_seconds); |
255 | BIN_TO_BCD(real_minutes); | |
1da177e4 LT |
256 | CMOS_WRITE(real_seconds, RTC_SECONDS); |
257 | CMOS_WRITE(real_minutes, RTC_MINUTES); | |
258 | } | |
259 | ||
260 | /* | |
261 | * The following flags have to be released exactly in this order, otherwise the | |
262 | * DS12887 (popular MC146818A clone with integrated battery and quartz) will | |
263 | * not reset the oscillator and will not update precisely 500 ms later. You | |
264 | * won't find this mentioned in the Dallas Semiconductor data sheets, but who | |
265 | * believes data sheets anyway ... -- Markus Kuhn | |
266 | */ | |
267 | ||
268 | CMOS_WRITE(control, RTC_CONTROL); | |
269 | CMOS_WRITE(freq_select, RTC_FREQ_SELECT); | |
270 | ||
271 | spin_unlock(&rtc_lock); | |
272 | } | |
273 | ||
274 | ||
275 | /* monotonic_clock(): returns # of nanoseconds passed since time_init() | |
276 | * Note: This function is required to return accurate | |
277 | * time even in the absence of multiple timer ticks. | |
278 | */ | |
279 | unsigned long long monotonic_clock(void) | |
280 | { | |
281 | unsigned long seq; | |
282 | u32 last_offset, this_offset, offset; | |
283 | unsigned long long base; | |
284 | ||
285 | if (vxtime.mode == VXTIME_HPET) { | |
286 | do { | |
287 | seq = read_seqbegin(&xtime_lock); | |
288 | ||
289 | last_offset = vxtime.last; | |
290 | base = monotonic_base; | |
a3a00751 | 291 | this_offset = hpet_readl(HPET_COUNTER); |
1da177e4 LT |
292 | } while (read_seqretry(&xtime_lock, seq)); |
293 | offset = (this_offset - last_offset); | |
294 | offset *=(NSEC_PER_SEC/HZ)/hpet_tick; | |
295 | return base + offset; | |
0b91317e | 296 | } else { |
1da177e4 LT |
297 | do { |
298 | seq = read_seqbegin(&xtime_lock); | |
299 | ||
300 | last_offset = vxtime.last_tsc; | |
301 | base = monotonic_base; | |
302 | } while (read_seqretry(&xtime_lock, seq)); | |
c818a181 | 303 | this_offset = get_cycles_sync(); |
1da177e4 LT |
304 | offset = (this_offset - last_offset)*1000/cpu_khz; |
305 | return base + offset; | |
306 | } | |
1da177e4 LT |
307 | } |
308 | EXPORT_SYMBOL(monotonic_clock); | |
309 | ||
310 | static noinline void handle_lost_ticks(int lost, struct pt_regs *regs) | |
311 | { | |
312 | static long lost_count; | |
313 | static int warned; | |
314 | ||
315 | if (report_lost_ticks) { | |
316 | printk(KERN_WARNING "time.c: Lost %d timer " | |
317 | "tick(s)! ", lost); | |
318 | print_symbol("rip %s)\n", regs->rip); | |
319 | } | |
320 | ||
321 | if (lost_count == 1000 && !warned) { | |
322 | printk(KERN_WARNING | |
323 | "warning: many lost ticks.\n" | |
324 | KERN_WARNING "Your time source seems to be instable or " | |
325 | "some driver is hogging interupts\n"); | |
326 | print_symbol("rip %s\n", regs->rip); | |
327 | if (vxtime.mode == VXTIME_TSC && vxtime.hpet_address) { | |
328 | printk(KERN_WARNING "Falling back to HPET\n"); | |
33042a9f CM |
329 | if (hpet_use_timer) |
330 | vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick; | |
331 | else | |
332 | vxtime.last = hpet_readl(HPET_COUNTER); | |
1da177e4 LT |
333 | vxtime.mode = VXTIME_HPET; |
334 | do_gettimeoffset = do_gettimeoffset_hpet; | |
335 | } | |
336 | /* else should fall back to PIT, but code missing. */ | |
337 | warned = 1; | |
338 | } else | |
339 | lost_count++; | |
340 | ||
341 | #ifdef CONFIG_CPU_FREQ | |
342 | /* In some cases the CPU can change frequency without us noticing | |
343 | (like going into thermal throttle) | |
344 | Give cpufreq a change to catch up. */ | |
345 | if ((lost_count+1) % 25 == 0) { | |
346 | cpufreq_delayed_get(); | |
347 | } | |
348 | #endif | |
349 | } | |
350 | ||
73dea47f | 351 | void main_timer_handler(struct pt_regs *regs) |
1da177e4 LT |
352 | { |
353 | static unsigned long rtc_update = 0; | |
354 | unsigned long tsc; | |
355 | int delay, offset = 0, lost = 0; | |
356 | ||
357 | /* | |
358 | * Here we are in the timer irq handler. We have irqs locally disabled (so we | |
359 | * don't need spin_lock_irqsave()) but we don't know if the timer_bh is running | |
360 | * on the other CPU, so we need a lock. We also need to lock the vsyscall | |
361 | * variables, because both do_timer() and us change them -arca+vojtech | |
362 | */ | |
363 | ||
364 | write_seqlock(&xtime_lock); | |
365 | ||
a3a00751 JS |
366 | if (vxtime.hpet_address) |
367 | offset = hpet_readl(HPET_COUNTER); | |
368 | ||
369 | if (hpet_use_timer) { | |
370 | /* if we're using the hpet timer functionality, | |
371 | * we can more accurately know the counter value | |
372 | * when the timer interrupt occured. | |
373 | */ | |
1da177e4 LT |
374 | offset = hpet_readl(HPET_T0_CMP) - hpet_tick; |
375 | delay = hpet_readl(HPET_COUNTER) - offset; | |
376 | } else { | |
377 | spin_lock(&i8253_lock); | |
378 | outb_p(0x00, 0x43); | |
379 | delay = inb_p(0x40); | |
380 | delay |= inb(0x40) << 8; | |
381 | spin_unlock(&i8253_lock); | |
382 | delay = LATCH - 1 - delay; | |
383 | } | |
384 | ||
c818a181 | 385 | tsc = get_cycles_sync(); |
1da177e4 LT |
386 | |
387 | if (vxtime.mode == VXTIME_HPET) { | |
388 | if (offset - vxtime.last > hpet_tick) { | |
389 | lost = (offset - vxtime.last) / hpet_tick - 1; | |
390 | } | |
391 | ||
392 | monotonic_base += | |
393 | (offset - vxtime.last)*(NSEC_PER_SEC/HZ) / hpet_tick; | |
394 | ||
395 | vxtime.last = offset; | |
312df5f1 AK |
396 | #ifdef CONFIG_X86_PM_TIMER |
397 | } else if (vxtime.mode == VXTIME_PMTMR) { | |
398 | lost = pmtimer_mark_offset(); | |
399 | #endif | |
1da177e4 LT |
400 | } else { |
401 | offset = (((tsc - vxtime.last_tsc) * | |
402 | vxtime.tsc_quot) >> 32) - (USEC_PER_SEC / HZ); | |
403 | ||
404 | if (offset < 0) | |
405 | offset = 0; | |
406 | ||
407 | if (offset > (USEC_PER_SEC / HZ)) { | |
408 | lost = offset / (USEC_PER_SEC / HZ); | |
409 | offset %= (USEC_PER_SEC / HZ); | |
410 | } | |
411 | ||
412 | monotonic_base += (tsc - vxtime.last_tsc)*1000000/cpu_khz ; | |
413 | ||
414 | vxtime.last_tsc = tsc - vxtime.quot * delay / vxtime.tsc_quot; | |
415 | ||
416 | if ((((tsc - vxtime.last_tsc) * | |
417 | vxtime.tsc_quot) >> 32) < offset) | |
418 | vxtime.last_tsc = tsc - | |
419 | (((long) offset << 32) / vxtime.tsc_quot) - 1; | |
420 | } | |
421 | ||
422 | if (lost > 0) { | |
423 | handle_lost_ticks(lost, regs); | |
424 | jiffies += lost; | |
425 | } | |
426 | ||
427 | /* | |
428 | * Do the timer stuff. | |
429 | */ | |
430 | ||
431 | do_timer(regs); | |
432 | #ifndef CONFIG_SMP | |
433 | update_process_times(user_mode(regs)); | |
434 | #endif | |
435 | ||
436 | /* | |
437 | * In the SMP case we use the local APIC timer interrupt to do the profiling, | |
438 | * except when we simulate SMP mode on a uniprocessor system, in that case we | |
439 | * have to call the local interrupt handler. | |
440 | */ | |
441 | ||
442 | #ifndef CONFIG_X86_LOCAL_APIC | |
443 | profile_tick(CPU_PROFILING, regs); | |
444 | #else | |
445 | if (!using_apic_timer) | |
446 | smp_local_timer_interrupt(regs); | |
447 | #endif | |
448 | ||
449 | /* | |
450 | * If we have an externally synchronized Linux clock, then update CMOS clock | |
451 | * accordingly every ~11 minutes. set_rtc_mmss() will be called in the jiffy | |
452 | * closest to exactly 500 ms before the next second. If the update fails, we | |
453 | * don't care, as it'll be updated on the next turn, and the problem (time way | |
454 | * off) isn't likely to go away much sooner anyway. | |
455 | */ | |
456 | ||
b149ee22 | 457 | if (ntp_synced() && xtime.tv_sec > rtc_update && |
1da177e4 LT |
458 | abs(xtime.tv_nsec - 500000000) <= tick_nsec / 2) { |
459 | set_rtc_mmss(xtime.tv_sec); | |
460 | rtc_update = xtime.tv_sec + 660; | |
461 | } | |
462 | ||
463 | write_sequnlock(&xtime_lock); | |
73dea47f | 464 | } |
1da177e4 | 465 | |
73dea47f AK |
466 | static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
467 | { | |
468 | if (apic_runs_main_timer > 1) | |
469 | return IRQ_HANDLED; | |
470 | main_timer_handler(regs); | |
d25bf7e5 VP |
471 | #ifdef CONFIG_X86_LOCAL_APIC |
472 | if (using_apic_timer) | |
473 | smp_send_timer_broadcast_ipi(); | |
474 | #endif | |
1da177e4 LT |
475 | return IRQ_HANDLED; |
476 | } | |
477 | ||
478 | static unsigned int cyc2ns_scale; | |
479 | #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ | |
480 | ||
dacb16b1 | 481 | static inline void set_cyc2ns_scale(unsigned long cpu_khz) |
1da177e4 | 482 | { |
dacb16b1 | 483 | cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz; |
1da177e4 LT |
484 | } |
485 | ||
486 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) | |
487 | { | |
488 | return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; | |
489 | } | |
490 | ||
491 | unsigned long long sched_clock(void) | |
492 | { | |
493 | unsigned long a = 0; | |
494 | ||
495 | #if 0 | |
496 | /* Don't do a HPET read here. Using TSC always is much faster | |
497 | and HPET may not be mapped yet when the scheduler first runs. | |
498 | Disadvantage is a small drift between CPUs in some configurations, | |
499 | but that should be tolerable. */ | |
500 | if (__vxtime.mode == VXTIME_HPET) | |
501 | return (hpet_readl(HPET_COUNTER) * vxtime.quot) >> 32; | |
502 | #endif | |
503 | ||
504 | /* Could do CPU core sync here. Opteron can execute rdtsc speculatively, | |
505 | which means it is not completely exact and may not be monotonous between | |
506 | CPUs. But the errors should be too small to matter for scheduling | |
507 | purposes. */ | |
508 | ||
509 | rdtscll(a); | |
510 | return cycles_2_ns(a); | |
511 | } | |
512 | ||
bdf2b1c9 | 513 | static unsigned long get_cmos_time(void) |
1da177e4 | 514 | { |
5329e13d JB |
515 | unsigned int timeout = 1000000, year, mon, day, hour, min, sec; |
516 | unsigned char uip = 0, this = 0; | |
1da177e4 LT |
517 | unsigned long flags; |
518 | ||
519 | /* | |
520 | * The Linux interpretation of the CMOS clock register contents: When the | |
521 | * Update-In-Progress (UIP) flag goes from 1 to 0, the RTC registers show the | |
522 | * second which has precisely just started. Waiting for this can take up to 1 | |
523 | * second, we timeout approximately after 2.4 seconds on a machine with | |
524 | * standard 8.3 MHz ISA bus. | |
525 | */ | |
526 | ||
527 | spin_lock_irqsave(&rtc_lock, flags); | |
528 | ||
5329e13d JB |
529 | while (timeout && (!uip || this)) { |
530 | uip |= this; | |
1da177e4 LT |
531 | this = CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP; |
532 | timeout--; | |
533 | } | |
534 | ||
0b91317e AK |
535 | /* |
536 | * Here we are safe to assume the registers won't change for a whole | |
537 | * second, so we just go ahead and read them. | |
538 | */ | |
539 | sec = CMOS_READ(RTC_SECONDS); | |
540 | min = CMOS_READ(RTC_MINUTES); | |
541 | hour = CMOS_READ(RTC_HOURS); | |
542 | day = CMOS_READ(RTC_DAY_OF_MONTH); | |
543 | mon = CMOS_READ(RTC_MONTH); | |
544 | year = CMOS_READ(RTC_YEAR); | |
1da177e4 LT |
545 | |
546 | spin_unlock_irqrestore(&rtc_lock, flags); | |
547 | ||
0b91317e AK |
548 | /* |
549 | * We know that x86-64 always uses BCD format, no need to check the | |
550 | * config register. | |
551 | */ | |
1da177e4 | 552 | |
0b91317e AK |
553 | BCD_TO_BIN(sec); |
554 | BCD_TO_BIN(min); | |
555 | BCD_TO_BIN(hour); | |
556 | BCD_TO_BIN(day); | |
557 | BCD_TO_BIN(mon); | |
558 | BCD_TO_BIN(year); | |
1da177e4 | 559 | |
0b91317e AK |
560 | /* |
561 | * x86-64 systems only exists since 2002. | |
562 | * This will work up to Dec 31, 2100 | |
563 | */ | |
1da177e4 LT |
564 | year += 2000; |
565 | ||
566 | return mktime(year, mon, day, hour, min, sec); | |
567 | } | |
568 | ||
569 | #ifdef CONFIG_CPU_FREQ | |
570 | ||
571 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
572 | changes. | |
573 | ||
574 | RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
575 | not that important because current Opteron setups do not support | |
576 | scaling on SMP anyroads. | |
577 | ||
578 | Should fix up last_tsc too. Currently gettimeofday in the | |
579 | first tick after the change will be slightly wrong. */ | |
580 | ||
581 | #include <linux/workqueue.h> | |
582 | ||
583 | static unsigned int cpufreq_delayed_issched = 0; | |
584 | static unsigned int cpufreq_init = 0; | |
585 | static struct work_struct cpufreq_delayed_get_work; | |
586 | ||
587 | static void handle_cpufreq_delayed_get(void *v) | |
588 | { | |
589 | unsigned int cpu; | |
590 | for_each_online_cpu(cpu) { | |
591 | cpufreq_get(cpu); | |
592 | } | |
593 | cpufreq_delayed_issched = 0; | |
594 | } | |
595 | ||
596 | /* if we notice lost ticks, schedule a call to cpufreq_get() as it tries | |
597 | * to verify the CPU frequency the timing core thinks the CPU is running | |
598 | * at is still correct. | |
599 | */ | |
600 | static void cpufreq_delayed_get(void) | |
601 | { | |
602 | static int warned; | |
603 | if (cpufreq_init && !cpufreq_delayed_issched) { | |
604 | cpufreq_delayed_issched = 1; | |
605 | if (!warned) { | |
606 | warned = 1; | |
607 | printk(KERN_DEBUG "Losing some ticks... checking if CPU frequency changed.\n"); | |
608 | } | |
609 | schedule_work(&cpufreq_delayed_get_work); | |
610 | } | |
611 | } | |
612 | ||
613 | static unsigned int ref_freq = 0; | |
614 | static unsigned long loops_per_jiffy_ref = 0; | |
615 | ||
616 | static unsigned long cpu_khz_ref = 0; | |
617 | ||
618 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
619 | void *data) | |
620 | { | |
621 | struct cpufreq_freqs *freq = data; | |
622 | unsigned long *lpj, dummy; | |
623 | ||
c29601e9 AK |
624 | if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC)) |
625 | return 0; | |
626 | ||
1da177e4 LT |
627 | lpj = &dummy; |
628 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
629 | #ifdef CONFIG_SMP | |
630 | lpj = &cpu_data[freq->cpu].loops_per_jiffy; | |
631 | #else | |
632 | lpj = &boot_cpu_data.loops_per_jiffy; | |
633 | #endif | |
634 | ||
1da177e4 LT |
635 | if (!ref_freq) { |
636 | ref_freq = freq->old; | |
637 | loops_per_jiffy_ref = *lpj; | |
638 | cpu_khz_ref = cpu_khz; | |
639 | } | |
640 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
641 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || | |
642 | (val == CPUFREQ_RESUMECHANGE)) { | |
643 | *lpj = | |
644 | cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); | |
645 | ||
646 | cpu_khz = cpufreq_scale(cpu_khz_ref, ref_freq, freq->new); | |
647 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
648 | vxtime.tsc_quot = (1000L << 32) / cpu_khz; | |
649 | } | |
650 | ||
dacb16b1 | 651 | set_cyc2ns_scale(cpu_khz_ref); |
1da177e4 LT |
652 | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static struct notifier_block time_cpufreq_notifier_block = { | |
657 | .notifier_call = time_cpufreq_notifier | |
658 | }; | |
659 | ||
660 | static int __init cpufreq_tsc(void) | |
661 | { | |
662 | INIT_WORK(&cpufreq_delayed_get_work, handle_cpufreq_delayed_get, NULL); | |
663 | if (!cpufreq_register_notifier(&time_cpufreq_notifier_block, | |
664 | CPUFREQ_TRANSITION_NOTIFIER)) | |
665 | cpufreq_init = 1; | |
666 | return 0; | |
667 | } | |
668 | ||
669 | core_initcall(cpufreq_tsc); | |
670 | ||
671 | #endif | |
672 | ||
673 | /* | |
674 | * calibrate_tsc() calibrates the processor TSC in a very simple way, comparing | |
675 | * it to the HPET timer of known frequency. | |
676 | */ | |
677 | ||
678 | #define TICK_COUNT 100000000 | |
679 | ||
680 | static unsigned int __init hpet_calibrate_tsc(void) | |
681 | { | |
682 | int tsc_start, hpet_start; | |
683 | int tsc_now, hpet_now; | |
684 | unsigned long flags; | |
685 | ||
686 | local_irq_save(flags); | |
687 | local_irq_disable(); | |
688 | ||
689 | hpet_start = hpet_readl(HPET_COUNTER); | |
690 | rdtscl(tsc_start); | |
691 | ||
692 | do { | |
693 | local_irq_disable(); | |
694 | hpet_now = hpet_readl(HPET_COUNTER); | |
c818a181 | 695 | tsc_now = get_cycles_sync(); |
1da177e4 LT |
696 | local_irq_restore(flags); |
697 | } while ((tsc_now - tsc_start) < TICK_COUNT && | |
698 | (hpet_now - hpet_start) < TICK_COUNT); | |
699 | ||
700 | return (tsc_now - tsc_start) * 1000000000L | |
701 | / ((hpet_now - hpet_start) * hpet_period / 1000); | |
702 | } | |
703 | ||
704 | ||
705 | /* | |
706 | * pit_calibrate_tsc() uses the speaker output (channel 2) of | |
707 | * the PIT. This is better than using the timer interrupt output, | |
708 | * because we can read the value of the speaker with just one inb(), | |
709 | * where we need three i/o operations for the interrupt channel. | |
710 | * We count how many ticks the TSC does in 50 ms. | |
711 | */ | |
712 | ||
713 | static unsigned int __init pit_calibrate_tsc(void) | |
714 | { | |
715 | unsigned long start, end; | |
716 | unsigned long flags; | |
717 | ||
718 | spin_lock_irqsave(&i8253_lock, flags); | |
719 | ||
720 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
721 | ||
722 | outb(0xb0, 0x43); | |
723 | outb((PIT_TICK_RATE / (1000 / 50)) & 0xff, 0x42); | |
724 | outb((PIT_TICK_RATE / (1000 / 50)) >> 8, 0x42); | |
c818a181 | 725 | start = get_cycles_sync(); |
1da177e4 | 726 | while ((inb(0x61) & 0x20) == 0); |
c818a181 | 727 | end = get_cycles_sync(); |
1da177e4 LT |
728 | |
729 | spin_unlock_irqrestore(&i8253_lock, flags); | |
730 | ||
731 | return (end - start) / 50; | |
732 | } | |
733 | ||
734 | #ifdef CONFIG_HPET | |
735 | static __init int late_hpet_init(void) | |
736 | { | |
737 | struct hpet_data hd; | |
738 | unsigned int ntimer; | |
739 | ||
740 | if (!vxtime.hpet_address) | |
0b91317e | 741 | return -1; |
1da177e4 LT |
742 | |
743 | memset(&hd, 0, sizeof (hd)); | |
744 | ||
745 | ntimer = hpet_readl(HPET_ID); | |
746 | ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; | |
747 | ntimer++; | |
748 | ||
749 | /* | |
750 | * Register with driver. | |
751 | * Timer0 and Timer1 is used by platform. | |
752 | */ | |
753 | hd.hd_phys_address = vxtime.hpet_address; | |
dd42b151 | 754 | hd.hd_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE); |
1da177e4 LT |
755 | hd.hd_nirqs = ntimer; |
756 | hd.hd_flags = HPET_DATA_PLATFORM; | |
757 | hpet_reserve_timer(&hd, 0); | |
758 | #ifdef CONFIG_HPET_EMULATE_RTC | |
759 | hpet_reserve_timer(&hd, 1); | |
760 | #endif | |
761 | hd.hd_irq[0] = HPET_LEGACY_8254; | |
762 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
763 | if (ntimer > 2) { | |
764 | struct hpet *hpet; | |
765 | struct hpet_timer *timer; | |
766 | int i; | |
767 | ||
768 | hpet = (struct hpet *) fix_to_virt(FIX_HPET_BASE); | |
769 | ||
770 | for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer; | |
771 | timer++, i++) | |
772 | hd.hd_irq[i] = (timer->hpet_config & | |
773 | Tn_INT_ROUTE_CNF_MASK) >> | |
774 | Tn_INT_ROUTE_CNF_SHIFT; | |
775 | ||
776 | } | |
777 | ||
778 | hpet_alloc(&hd); | |
779 | return 0; | |
780 | } | |
781 | fs_initcall(late_hpet_init); | |
782 | #endif | |
783 | ||
784 | static int hpet_timer_stop_set_go(unsigned long tick) | |
785 | { | |
786 | unsigned int cfg; | |
787 | ||
788 | /* | |
789 | * Stop the timers and reset the main counter. | |
790 | */ | |
791 | ||
792 | cfg = hpet_readl(HPET_CFG); | |
793 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); | |
794 | hpet_writel(cfg, HPET_CFG); | |
795 | hpet_writel(0, HPET_COUNTER); | |
796 | hpet_writel(0, HPET_COUNTER + 4); | |
797 | ||
798 | /* | |
799 | * Set up timer 0, as periodic with first interrupt to happen at hpet_tick, | |
800 | * and period also hpet_tick. | |
801 | */ | |
a3a00751 JS |
802 | if (hpet_use_timer) { |
803 | hpet_writel(HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | | |
1da177e4 | 804 | HPET_TN_32BIT, HPET_T0_CFG); |
a3a00751 JS |
805 | hpet_writel(hpet_tick, HPET_T0_CMP); |
806 | hpet_writel(hpet_tick, HPET_T0_CMP); /* AK: why twice? */ | |
807 | cfg |= HPET_CFG_LEGACY; | |
808 | } | |
1da177e4 LT |
809 | /* |
810 | * Go! | |
811 | */ | |
812 | ||
a3a00751 | 813 | cfg |= HPET_CFG_ENABLE; |
1da177e4 LT |
814 | hpet_writel(cfg, HPET_CFG); |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | static int hpet_init(void) | |
820 | { | |
821 | unsigned int id; | |
822 | ||
823 | if (!vxtime.hpet_address) | |
824 | return -1; | |
825 | set_fixmap_nocache(FIX_HPET_BASE, vxtime.hpet_address); | |
826 | __set_fixmap(VSYSCALL_HPET, vxtime.hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
827 | ||
828 | /* | |
829 | * Read the period, compute tick and quotient. | |
830 | */ | |
831 | ||
832 | id = hpet_readl(HPET_ID); | |
833 | ||
a3a00751 | 834 | if (!(id & HPET_ID_VENDOR) || !(id & HPET_ID_NUMBER)) |
1da177e4 LT |
835 | return -1; |
836 | ||
837 | hpet_period = hpet_readl(HPET_PERIOD); | |
838 | if (hpet_period < 100000 || hpet_period > 100000000) | |
839 | return -1; | |
840 | ||
841 | hpet_tick = (1000000000L * (USEC_PER_SEC / HZ) + hpet_period / 2) / | |
842 | hpet_period; | |
843 | ||
a3a00751 JS |
844 | hpet_use_timer = (id & HPET_ID_LEGSUP); |
845 | ||
1da177e4 LT |
846 | return hpet_timer_stop_set_go(hpet_tick); |
847 | } | |
848 | ||
849 | static int hpet_reenable(void) | |
850 | { | |
851 | return hpet_timer_stop_set_go(hpet_tick); | |
852 | } | |
853 | ||
73dea47f AK |
854 | #define PIT_MODE 0x43 |
855 | #define PIT_CH0 0x40 | |
856 | ||
857 | static void __init __pit_init(int val, u8 mode) | |
1da177e4 LT |
858 | { |
859 | unsigned long flags; | |
860 | ||
861 | spin_lock_irqsave(&i8253_lock, flags); | |
73dea47f AK |
862 | outb_p(mode, PIT_MODE); |
863 | outb_p(val & 0xff, PIT_CH0); /* LSB */ | |
864 | outb_p(val >> 8, PIT_CH0); /* MSB */ | |
1da177e4 LT |
865 | spin_unlock_irqrestore(&i8253_lock, flags); |
866 | } | |
867 | ||
73dea47f AK |
868 | void __init pit_init(void) |
869 | { | |
870 | __pit_init(LATCH, 0x34); /* binary, mode 2, LSB/MSB, ch 0 */ | |
871 | } | |
872 | ||
873 | void __init pit_stop_interrupt(void) | |
874 | { | |
875 | __pit_init(0, 0x30); /* mode 0 */ | |
876 | } | |
877 | ||
878 | void __init stop_timer_interrupt(void) | |
879 | { | |
880 | char *name; | |
881 | if (vxtime.hpet_address) { | |
882 | name = "HPET"; | |
883 | hpet_timer_stop_set_go(0); | |
884 | } else { | |
885 | name = "PIT"; | |
886 | pit_stop_interrupt(); | |
887 | } | |
888 | printk(KERN_INFO "timer: %s interrupt stopped.\n", name); | |
889 | } | |
890 | ||
1da177e4 LT |
891 | int __init time_setup(char *str) |
892 | { | |
893 | report_lost_ticks = 1; | |
894 | return 1; | |
895 | } | |
896 | ||
897 | static struct irqaction irq0 = { | |
898 | timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL | |
899 | }; | |
900 | ||
1da177e4 LT |
901 | void __init time_init(void) |
902 | { | |
903 | char *timename; | |
904 | ||
905 | #ifdef HPET_HACK_ENABLE_DANGEROUS | |
906 | if (!vxtime.hpet_address) { | |
907 | printk(KERN_WARNING "time.c: WARNING: Enabling HPET base " | |
908 | "manually!\n"); | |
909 | outl(0x800038a0, 0xcf8); | |
910 | outl(0xff000001, 0xcfc); | |
911 | outl(0x800038a0, 0xcf8); | |
912 | vxtime.hpet_address = inl(0xcfc) & 0xfffffffe; | |
913 | printk(KERN_WARNING "time.c: WARNING: Enabled HPET " | |
914 | "at %#lx.\n", vxtime.hpet_address); | |
915 | } | |
916 | #endif | |
917 | if (nohpet) | |
918 | vxtime.hpet_address = 0; | |
919 | ||
920 | xtime.tv_sec = get_cmos_time(); | |
921 | xtime.tv_nsec = 0; | |
922 | ||
923 | set_normalized_timespec(&wall_to_monotonic, | |
924 | -xtime.tv_sec, -xtime.tv_nsec); | |
925 | ||
a3a00751 | 926 | if (!hpet_init()) |
1da177e4 LT |
927 | vxtime_hz = (1000000000000000L + hpet_period / 2) / |
928 | hpet_period; | |
68e18891 AK |
929 | else |
930 | vxtime.hpet_address = 0; | |
a3a00751 JS |
931 | |
932 | if (hpet_use_timer) { | |
1da177e4 LT |
933 | cpu_khz = hpet_calibrate_tsc(); |
934 | timename = "HPET"; | |
312df5f1 | 935 | #ifdef CONFIG_X86_PM_TIMER |
fd495471 | 936 | } else if (pmtmr_ioport && !vxtime.hpet_address) { |
312df5f1 AK |
937 | vxtime_hz = PM_TIMER_FREQUENCY; |
938 | timename = "PM"; | |
939 | pit_init(); | |
940 | cpu_khz = pit_calibrate_tsc(); | |
941 | #endif | |
1da177e4 LT |
942 | } else { |
943 | pit_init(); | |
944 | cpu_khz = pit_calibrate_tsc(); | |
945 | timename = "PIT"; | |
946 | } | |
947 | ||
948 | printk(KERN_INFO "time.c: Using %ld.%06ld MHz %s timer.\n", | |
949 | vxtime_hz / 1000000, vxtime_hz % 1000000, timename); | |
950 | printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n", | |
951 | cpu_khz / 1000, cpu_khz % 1000); | |
952 | vxtime.mode = VXTIME_TSC; | |
953 | vxtime.quot = (1000000L << 32) / vxtime_hz; | |
954 | vxtime.tsc_quot = (1000L << 32) / cpu_khz; | |
c818a181 | 955 | vxtime.last_tsc = get_cycles_sync(); |
1da177e4 LT |
956 | setup_irq(0, &irq0); |
957 | ||
dacb16b1 | 958 | set_cyc2ns_scale(cpu_khz); |
a8ab26fe AK |
959 | |
960 | #ifndef CONFIG_SMP | |
961 | time_init_gtod(); | |
962 | #endif | |
1da177e4 LT |
963 | } |
964 | ||
312df5f1 AK |
965 | /* |
966 | * Make an educated guess if the TSC is trustworthy and synchronized | |
967 | * over all CPUs. | |
968 | */ | |
396bd50f | 969 | __cpuinit int unsynchronized_tsc(void) |
312df5f1 AK |
970 | { |
971 | #ifdef CONFIG_SMP | |
972 | if (oem_force_hpet_timer()) | |
973 | return 1; | |
974 | /* Intel systems are normally all synchronized. Exceptions | |
975 | are handled in the OEM check above. */ | |
976 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
977 | return 0; | |
312df5f1 AK |
978 | #endif |
979 | /* Assume multi socket systems are not synchronized */ | |
737c5c3b | 980 | return num_present_cpus() > 1; |
312df5f1 AK |
981 | } |
982 | ||
a8ab26fe AK |
983 | /* |
984 | * Decide after all CPUs are booted what mode gettimeofday should use. | |
985 | */ | |
986 | void __init time_init_gtod(void) | |
1da177e4 LT |
987 | { |
988 | char *timetype; | |
989 | ||
312df5f1 | 990 | if (unsynchronized_tsc()) |
1da177e4 LT |
991 | notsc = 1; |
992 | if (vxtime.hpet_address && notsc) { | |
a3a00751 | 993 | timetype = hpet_use_timer ? "HPET" : "PIT/HPET"; |
33042a9f CM |
994 | if (hpet_use_timer) |
995 | vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick; | |
996 | else | |
997 | vxtime.last = hpet_readl(HPET_COUNTER); | |
1da177e4 LT |
998 | vxtime.mode = VXTIME_HPET; |
999 | do_gettimeoffset = do_gettimeoffset_hpet; | |
312df5f1 AK |
1000 | #ifdef CONFIG_X86_PM_TIMER |
1001 | /* Using PM for gettimeofday is quite slow, but we have no other | |
1002 | choice because the TSC is too unreliable on some systems. */ | |
1003 | } else if (pmtmr_ioport && !vxtime.hpet_address && notsc) { | |
1004 | timetype = "PM"; | |
1005 | do_gettimeoffset = do_gettimeoffset_pm; | |
1006 | vxtime.mode = VXTIME_PMTMR; | |
1007 | sysctl_vsyscall = 0; | |
1008 | printk(KERN_INFO "Disabling vsyscall due to use of PM timer\n"); | |
1009 | #endif | |
1da177e4 | 1010 | } else { |
a3a00751 | 1011 | timetype = hpet_use_timer ? "HPET/TSC" : "PIT/TSC"; |
1da177e4 LT |
1012 | vxtime.mode = VXTIME_TSC; |
1013 | } | |
1014 | ||
1015 | printk(KERN_INFO "time.c: Using %s based timekeeping.\n", timetype); | |
1016 | } | |
1017 | ||
1018 | __setup("report_lost_ticks", time_setup); | |
1019 | ||
1020 | static long clock_cmos_diff; | |
1021 | static unsigned long sleep_start; | |
1022 | ||
0b91317e AK |
1023 | /* |
1024 | * sysfs support for the timer. | |
1025 | */ | |
1026 | ||
0b9c33a7 | 1027 | static int timer_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
1028 | { |
1029 | /* | |
1030 | * Estimate time zone so that set_time can update the clock | |
1031 | */ | |
1032 | long cmos_time = get_cmos_time(); | |
1033 | ||
1034 | clock_cmos_diff = -cmos_time; | |
1035 | clock_cmos_diff += get_seconds(); | |
1036 | sleep_start = cmos_time; | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int timer_resume(struct sys_device *dev) | |
1041 | { | |
1042 | unsigned long flags; | |
1043 | unsigned long sec; | |
1044 | unsigned long ctime = get_cmos_time(); | |
1045 | unsigned long sleep_length = (ctime - sleep_start) * HZ; | |
1046 | ||
1047 | if (vxtime.hpet_address) | |
1048 | hpet_reenable(); | |
1049 | else | |
1050 | i8254_timer_resume(); | |
1051 | ||
1052 | sec = ctime + clock_cmos_diff; | |
1053 | write_seqlock_irqsave(&xtime_lock,flags); | |
1054 | xtime.tv_sec = sec; | |
1055 | xtime.tv_nsec = 0; | |
0dd2ea9a SL |
1056 | if (vxtime.mode == VXTIME_HPET) { |
1057 | if (hpet_use_timer) | |
1058 | vxtime.last = hpet_readl(HPET_T0_CMP) - hpet_tick; | |
1059 | else | |
1060 | vxtime.last = hpet_readl(HPET_COUNTER); | |
1061 | #ifdef CONFIG_X86_PM_TIMER | |
1062 | } else if (vxtime.mode == VXTIME_PMTMR) { | |
1063 | pmtimer_resume(); | |
1064 | #endif | |
1065 | } else | |
1066 | vxtime.last_tsc = get_cycles_sync(); | |
1da177e4 LT |
1067 | write_sequnlock_irqrestore(&xtime_lock,flags); |
1068 | jiffies += sleep_length; | |
1069 | wall_jiffies += sleep_length; | |
0dd2ea9a | 1070 | monotonic_base += sleep_length * (NSEC_PER_SEC/HZ); |
8446f1d3 | 1071 | touch_softlockup_watchdog(); |
1da177e4 LT |
1072 | return 0; |
1073 | } | |
1074 | ||
1075 | static struct sysdev_class timer_sysclass = { | |
1076 | .resume = timer_resume, | |
1077 | .suspend = timer_suspend, | |
1078 | set_kset_name("timer"), | |
1079 | }; | |
1080 | ||
1da177e4 LT |
1081 | /* XXX this driverfs stuff should probably go elsewhere later -john */ |
1082 | static struct sys_device device_timer = { | |
1083 | .id = 0, | |
1084 | .cls = &timer_sysclass, | |
1085 | }; | |
1086 | ||
1087 | static int time_init_device(void) | |
1088 | { | |
1089 | int error = sysdev_class_register(&timer_sysclass); | |
1090 | if (!error) | |
1091 | error = sysdev_register(&device_timer); | |
1092 | return error; | |
1093 | } | |
1094 | ||
1095 | device_initcall(time_init_device); | |
1096 | ||
1097 | #ifdef CONFIG_HPET_EMULATE_RTC | |
1098 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
1099 | * is enabled, we support RTC interrupt functionality in software. | |
1100 | * RTC has 3 kinds of interrupts: | |
1101 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
1102 | * is updated | |
1103 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
1104 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
1105 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
1106 | * (1) and (2) above are implemented using polling at a frequency of | |
1107 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
1108 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
1109 | * For (3), we use interrupts at 64Hz or user specified periodic | |
1110 | * frequency, whichever is higher. | |
1111 | */ | |
1112 | #include <linux/rtc.h> | |
1113 | ||
1da177e4 LT |
1114 | #define DEFAULT_RTC_INT_FREQ 64 |
1115 | #define RTC_NUM_INTS 1 | |
1116 | ||
1117 | static unsigned long UIE_on; | |
1118 | static unsigned long prev_update_sec; | |
1119 | ||
1120 | static unsigned long AIE_on; | |
1121 | static struct rtc_time alarm_time; | |
1122 | ||
1123 | static unsigned long PIE_on; | |
1124 | static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ; | |
1125 | static unsigned long PIE_count; | |
1126 | ||
1127 | static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */ | |
7811fb8f | 1128 | static unsigned int hpet_t1_cmp; /* cached comparator register */ |
1da177e4 LT |
1129 | |
1130 | int is_hpet_enabled(void) | |
1131 | { | |
1132 | return vxtime.hpet_address != 0; | |
1133 | } | |
1134 | ||
1135 | /* | |
1136 | * Timer 1 for RTC, we do not use periodic interrupt feature, | |
1137 | * even if HPET supports periodic interrupts on Timer 1. | |
1138 | * The reason being, to set up a periodic interrupt in HPET, we need to | |
1139 | * stop the main counter. And if we do that everytime someone diables/enables | |
1140 | * RTC, we will have adverse effect on main kernel timer running on Timer 0. | |
1141 | * So, for the time being, simulate the periodic interrupt in software. | |
1142 | * | |
1143 | * hpet_rtc_timer_init() is called for the first time and during subsequent | |
1144 | * interuppts reinit happens through hpet_rtc_timer_reinit(). | |
1145 | */ | |
1146 | int hpet_rtc_timer_init(void) | |
1147 | { | |
1148 | unsigned int cfg, cnt; | |
1149 | unsigned long flags; | |
1150 | ||
1151 | if (!is_hpet_enabled()) | |
1152 | return 0; | |
1153 | /* | |
1154 | * Set the counter 1 and enable the interrupts. | |
1155 | */ | |
1156 | if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ)) | |
1157 | hpet_rtc_int_freq = PIE_freq; | |
1158 | else | |
1159 | hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ; | |
1160 | ||
1161 | local_irq_save(flags); | |
1162 | cnt = hpet_readl(HPET_COUNTER); | |
1163 | cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq); | |
1164 | hpet_writel(cnt, HPET_T1_CMP); | |
7811fb8f | 1165 | hpet_t1_cmp = cnt; |
1da177e4 LT |
1166 | local_irq_restore(flags); |
1167 | ||
1168 | cfg = hpet_readl(HPET_T1_CFG); | |
5f819949 CL |
1169 | cfg &= ~HPET_TN_PERIODIC; |
1170 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1da177e4 LT |
1171 | hpet_writel(cfg, HPET_T1_CFG); |
1172 | ||
1173 | return 1; | |
1174 | } | |
1175 | ||
1176 | static void hpet_rtc_timer_reinit(void) | |
1177 | { | |
1178 | unsigned int cfg, cnt; | |
1179 | ||
f00c96f3 CL |
1180 | if (unlikely(!(PIE_on | AIE_on | UIE_on))) { |
1181 | cfg = hpet_readl(HPET_T1_CFG); | |
1182 | cfg &= ~HPET_TN_ENABLE; | |
1183 | hpet_writel(cfg, HPET_T1_CFG); | |
1da177e4 | 1184 | return; |
f00c96f3 | 1185 | } |
1da177e4 LT |
1186 | |
1187 | if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ)) | |
1188 | hpet_rtc_int_freq = PIE_freq; | |
1189 | else | |
1190 | hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ; | |
1191 | ||
1192 | /* It is more accurate to use the comparator value than current count.*/ | |
7811fb8f | 1193 | cnt = hpet_t1_cmp; |
1da177e4 LT |
1194 | cnt += hpet_tick*HZ/hpet_rtc_int_freq; |
1195 | hpet_writel(cnt, HPET_T1_CMP); | |
7811fb8f | 1196 | hpet_t1_cmp = cnt; |
1da177e4 LT |
1197 | } |
1198 | ||
1199 | /* | |
1200 | * The functions below are called from rtc driver. | |
1201 | * Return 0 if HPET is not being used. | |
1202 | * Otherwise do the necessary changes and return 1. | |
1203 | */ | |
1204 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1205 | { | |
1206 | if (!is_hpet_enabled()) | |
1207 | return 0; | |
1208 | ||
1209 | if (bit_mask & RTC_UIE) | |
1210 | UIE_on = 0; | |
1211 | if (bit_mask & RTC_PIE) | |
1212 | PIE_on = 0; | |
1213 | if (bit_mask & RTC_AIE) | |
1214 | AIE_on = 0; | |
1215 | ||
1216 | return 1; | |
1217 | } | |
1218 | ||
1219 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1220 | { | |
1221 | int timer_init_reqd = 0; | |
1222 | ||
1223 | if (!is_hpet_enabled()) | |
1224 | return 0; | |
1225 | ||
1226 | if (!(PIE_on | AIE_on | UIE_on)) | |
1227 | timer_init_reqd = 1; | |
1228 | ||
1229 | if (bit_mask & RTC_UIE) { | |
1230 | UIE_on = 1; | |
1231 | } | |
1232 | if (bit_mask & RTC_PIE) { | |
1233 | PIE_on = 1; | |
1234 | PIE_count = 0; | |
1235 | } | |
1236 | if (bit_mask & RTC_AIE) { | |
1237 | AIE_on = 1; | |
1238 | } | |
1239 | ||
1240 | if (timer_init_reqd) | |
1241 | hpet_rtc_timer_init(); | |
1242 | ||
1243 | return 1; | |
1244 | } | |
1245 | ||
1246 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
1247 | { | |
1248 | if (!is_hpet_enabled()) | |
1249 | return 0; | |
1250 | ||
1251 | alarm_time.tm_hour = hrs; | |
1252 | alarm_time.tm_min = min; | |
1253 | alarm_time.tm_sec = sec; | |
1254 | ||
1255 | return 1; | |
1256 | } | |
1257 | ||
1258 | int hpet_set_periodic_freq(unsigned long freq) | |
1259 | { | |
1260 | if (!is_hpet_enabled()) | |
1261 | return 0; | |
1262 | ||
1263 | PIE_freq = freq; | |
1264 | PIE_count = 0; | |
1265 | ||
1266 | return 1; | |
1267 | } | |
1268 | ||
1269 | int hpet_rtc_dropped_irq(void) | |
1270 | { | |
1271 | if (!is_hpet_enabled()) | |
1272 | return 0; | |
1273 | ||
1274 | return 1; | |
1275 | } | |
1276 | ||
1277 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
1278 | { | |
1279 | struct rtc_time curr_time; | |
1280 | unsigned long rtc_int_flag = 0; | |
1281 | int call_rtc_interrupt = 0; | |
1282 | ||
1283 | hpet_rtc_timer_reinit(); | |
1284 | ||
1285 | if (UIE_on | AIE_on) { | |
1286 | rtc_get_rtc_time(&curr_time); | |
1287 | } | |
1288 | if (UIE_on) { | |
1289 | if (curr_time.tm_sec != prev_update_sec) { | |
1290 | /* Set update int info, call real rtc int routine */ | |
1291 | call_rtc_interrupt = 1; | |
1292 | rtc_int_flag = RTC_UF; | |
1293 | prev_update_sec = curr_time.tm_sec; | |
1294 | } | |
1295 | } | |
1296 | if (PIE_on) { | |
1297 | PIE_count++; | |
1298 | if (PIE_count >= hpet_rtc_int_freq/PIE_freq) { | |
1299 | /* Set periodic int info, call real rtc int routine */ | |
1300 | call_rtc_interrupt = 1; | |
1301 | rtc_int_flag |= RTC_PF; | |
1302 | PIE_count = 0; | |
1303 | } | |
1304 | } | |
1305 | if (AIE_on) { | |
1306 | if ((curr_time.tm_sec == alarm_time.tm_sec) && | |
1307 | (curr_time.tm_min == alarm_time.tm_min) && | |
1308 | (curr_time.tm_hour == alarm_time.tm_hour)) { | |
1309 | /* Set alarm int info, call real rtc int routine */ | |
1310 | call_rtc_interrupt = 1; | |
1311 | rtc_int_flag |= RTC_AF; | |
1312 | } | |
1313 | } | |
1314 | if (call_rtc_interrupt) { | |
1315 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1316 | rtc_interrupt(rtc_int_flag, dev_id, regs); | |
1317 | } | |
1318 | return IRQ_HANDLED; | |
1319 | } | |
1320 | #endif | |
1321 | ||
1da177e4 LT |
1322 | static int __init nohpet_setup(char *s) |
1323 | { | |
1324 | nohpet = 1; | |
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | __setup("nohpet", nohpet_setup); | |
1329 | ||
1330 | ||
1331 | static int __init notsc_setup(char *s) | |
1332 | { | |
1333 | notsc = 1; | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | __setup("notsc", notsc_setup); |