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66701b14 1config ZONE_DMA
35f9cd08 2 def_bool y
66701b14 3
8e1a6dd2 4config XTENSA
35f9cd08 5 def_bool y
07c75d7a 6 select ARCH_NO_COHERENT_DMA_MMAP if !MMU
8f371c75 7 select ARCH_WANT_FRAME_POINTERS
e969161b 8 select ARCH_WANT_IPC_PARSE_VERSION
25df8198 9 select BUILDTIME_EXTABLE_SORT
3e41f9ba 10 select CLONE_BACKWARDS
920f8a39
MF
11 select COMMON_CLK
12 select GENERIC_ATOMIC64
13 select GENERIC_CLOCKEVENTS
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SCHED_CLOCK
0e46c111 17 select HAVE_DEBUG_KMEMLEAK
c75959a6 18 select HAVE_DMA_API_DEBUG
9d2ffe5c 19 select HAVE_DMA_CONTIGUOUS
5f56a5df 20 select HAVE_EXIT_THREAD
478ba61a 21 select HAVE_FUNCTION_TRACER
d951ba21 22 select HAVE_FUTEX_CMPXCHG if !MMU
c91e02bd 23 select HAVE_HW_BREAKPOINT if PERF_EVENTS
496543c4 24 select HAVE_IRQ_TIME_ACCOUNTING
0e46c111 25 select HAVE_MEMBLOCK
920f8a39 26 select HAVE_OPROFILE
a6f3eefa 27 select HAVE_PERF_EVENTS
920f8a39
MF
28 select IRQ_DOMAIN
29 select MODULES_USE_ELF_RELA
0e46c111 30 select NO_BOOTMEM
db8165f5 31 select PERF_USE_VMALLOC
920f8a39 32 select VIRT_TO_BUS
8e1a6dd2
CZ
33 help
34 Xtensa processors are 32-bit RISC machines designed by Tensilica
35 primarily for embedded systems. These processors are both
36 configurable and extensible. The Linux port to the Xtensa
37 architecture supports all processor configurations and extensions,
38 with reasonable minimum requirements. The Xtensa Linux project has
0ada4490 39 a home page at <http://www.linux-xtensa.org/>.
8e1a6dd2 40
8e1a6dd2 41config RWSEM_XCHGADD_ALGORITHM
35f9cd08 42 def_bool y
8e1a6dd2 43
d4337aa5 44config GENERIC_HWEIGHT
35f9cd08 45 def_bool y
d4337aa5 46
f0d1b0b3 47config ARCH_HAS_ILOG2_U32
35f9cd08 48 def_bool n
f0d1b0b3
DH
49
50config ARCH_HAS_ILOG2_U64
35f9cd08 51 def_bool n
f0d1b0b3 52
ce816fa8 53config NO_IOPORT_MAP
d046f77e 54 def_bool n
5ea81769 55
bdc80787
PA
56config HZ
57 int
58 default 100
59
8e1a6dd2 60source "init/Kconfig"
dc52ddc0 61source "kernel/Kconfig.freezer"
8e1a6dd2 62
8f371c75
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63config LOCKDEP_SUPPORT
64 def_bool y
65
3e4196a5
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66config STACKTRACE_SUPPORT
67 def_bool y
68
c92931b2
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69config TRACE_IRQFLAGS_SUPPORT
70 def_bool y
71
35f9cd08 72config MMU
de7c1c78 73 def_bool n
35f9cd08 74
4c0d2141
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75config VARIANT_IRQ_SWITCH
76 def_bool n
77
a1a2bdec
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78config HAVE_XTENSA_GPIO32
79 def_bool n
80
8e1a6dd2
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81menu "Processor type and features"
82
83choice
84 prompt "Xtensa Processor Configuration"
173d6681 85 default XTENSA_VARIANT_FSF
8e1a6dd2 86
173d6681 87config XTENSA_VARIANT_FSF
0025427e 88 bool "fsf - default (not generic) configuration"
35f9cd08 89 select MMU
0025427e
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90
91config XTENSA_VARIANT_DC232B
92 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
35f9cd08 93 select MMU
a1a2bdec 94 select HAVE_XTENSA_GPIO32
0025427e 95 help
35f9cd08 96 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
000af2c5 97
d0b73b48
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98config XTENSA_VARIANT_DC233C
99 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
100 select MMU
a1a2bdec 101 select HAVE_XTENSA_GPIO32
d0b73b48
PD
102 help
103 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
104
420ae951
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105config XTENSA_VARIANT_CUSTOM
106 bool "Custom Xtensa processor configuration"
420ae951
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107 select HAVE_XTENSA_GPIO32
108 help
109 Select this variant to use a custom Xtensa processor configuration.
110 You will be prompted for a processor variant CORENAME.
8e1a6dd2
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111endchoice
112
420ae951
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113config XTENSA_VARIANT_CUSTOM_NAME
114 string "Xtensa Processor Custom Core Variant Name"
115 depends on XTENSA_VARIANT_CUSTOM
116 help
117 Provide the name of a custom Xtensa processor variant.
118 This CORENAME selects arch/xtensa/variant/CORENAME.
119 Dont forget you have to select MMU if you have one.
120
121config XTENSA_VARIANT_NAME
122 string
123 default "dc232b" if XTENSA_VARIANT_DC232B
124 default "dc233c" if XTENSA_VARIANT_DC233C
125 default "fsf" if XTENSA_VARIANT_FSF
420ae951
MF
126 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
127
128config XTENSA_VARIANT_MMU
129 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
130 depends on XTENSA_VARIANT_CUSTOM
131 default y
de7c1c78 132 select MMU
420ae951
MF
133 help
134 Build a Conventional Kernel with full MMU support,
135 ie: it supports a TLB with auto-loading, page protection.
136
9bd46da4
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137config XTENSA_VARIANT_HAVE_PERF_EVENTS
138 bool "Core variant has Performance Monitor Module"
139 depends on XTENSA_VARIANT_CUSTOM
140 default n
141 help
142 Enable if core variant has Performance Monitor Module with
143 External Registers Interface.
144
145 If unsure, say N.
146
e4629194
MF
147config XTENSA_FAKE_NMI
148 bool "Treat PMM IRQ as NMI"
149 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
150 default n
151 help
152 If PMM IRQ is the only IRQ at EXCM level it is safe to
153 treat it as NMI, which improves accuracy of profiling.
154
155 If there are other interrupts at or above PMM IRQ priority level
156 but not above the EXCM level, PMM IRQ still may be treated as NMI,
157 but only if these IRQs are not used. There will be a build warning
158 saying that this is not safe, and a bugcheck if one of these IRQs
159 actually fire.
160
161 If unsure, say N.
162
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163config XTENSA_UNALIGNED_USER
164 bool "Unaligned memory access in use space"
35f9cd08
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165 help
166 The Xtensa architecture currently does not handle unaligned
167 memory accesses in hardware but through an exception handler.
168 Per default, unaligned memory accesses are disabled in user space.
8e1a6dd2 169
35f9cd08 170 Say Y here to enable unaligned memory access in user space.
8e1a6dd2 171
bd96efe1 172source "kernel/Kconfig.preempt"
8e1a6dd2 173
f615136c
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174config HAVE_SMP
175 bool "System Supports SMP (MX)"
de7c1c78 176 depends on XTENSA_VARIANT_CUSTOM
f615136c
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177 select XTENSA_MX
178 help
179 This option is use to indicate that the system-on-a-chip (SOC)
180 supports Multiprocessing. Multiprocessor support implemented above
181 the CPU core definition and currently needs to be selected manually.
182
183 Multiprocessor support in implemented with external cache and
769a12a9 184 interrupt controllers.
f615136c
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185
186 The MX interrupt distributer adds Interprocessor Interrupts
187 and causes the IRQ numbers to be increased by 4 for devices
188 like the open cores ethernet driver and the serial interface.
189
190 You still have to select "Enable SMP" to enable SMP on this SOC.
191
192config SMP
193 bool "Enable Symmetric multi-processing support"
194 depends on HAVE_SMP
f615136c
MF
195 select GENERIC_SMP_IDLE_THREAD
196 help
197 Enabled SMP Software; allows more than one CPU/CORE
198 to be activated during startup.
199
200config NR_CPUS
201 depends on SMP
202 int "Maximum number of CPUs (2-32)"
203 range 2 32
204 default "4"
205
49b424fe
MF
206config HOTPLUG_CPU
207 bool "Enable CPU hotplug support"
208 depends on SMP
209 help
210 Say Y here to allow turning CPUs off and on. CPUs can be
211 controlled through /sys/devices/system/cpu.
212
213 Say N if you want to disable CPU hotplug.
214
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MF
215config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
216 bool "Initialize Xtensa MMU inside the Linux kernel code"
a4c6be5a 217 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
73a3eed0 218 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
e85e335f
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219 help
220 Earlier version initialized the MMU in the exception vector
221 before jumping to _startup in head.S and had an advantage that
222 it was possible to place a software breakpoint at 'reset' and
223 then enter your normal kernel breakpoints once the MMU was mapped
224 to the kernel mappings (0XC0000000).
225
226 This unfortunately doesn't work for U-Boot and likley also wont
227 work for using KEXEC to have a hot kernel ready for doing a
228 KDUMP.
229
230 So now the MMU is initialized in head.S but it's necessary to
231 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
232 xt-gdb can't place a Software Breakpoint in the 0XD region prior
233 to mapping the MMU and after mapping even if the area of low memory
234 was mapped gdb wouldn't remove the breakpoint on hitting it as the
235 PC wouldn't match. Since Hardware Breakpoints are recommended for
236 Linux configurations it seems reasonable to just assume they exist
237 and leave this older mechanism for unfortunate souls that choose
238 not to follow Tensilica's recommendation.
239
240 Selecting this will cause U-Boot to set the KERNEL Load and Entry
241 address at 0x00003000 instead of the mapped std of 0xD0003000.
242
243 If in doubt, say Y.
244
d39af902
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245config KSEG_PADDR
246 hex "Physical address of the KSEG mapping"
247 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
248 default 0x00000000
249 help
250 This is the physical address where KSEG is mapped. Please refer to
251 the chosen KSEG layout help for the required address alignment.
252 Unpacked kernel image (including vectors) must be located completely
253 within KSEG.
254 Physical memory below this address is not available to linux.
255
256 If unsure, leave the default value here.
257
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258config KERNEL_LOAD_ADDRESS
259 hex "Kernel load address"
73a3eed0
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260 default 0x60003000 if !MMU
261 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
262 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
a9f2fc62
MF
263 help
264 This is the address where the kernel is loaded.
265 It is virtual address for MMUv2 configurations and physical address
266 for all other configurations.
267
268 If unsure, leave the default value here.
269
270config VECTORS_OFFSET
271 hex "Kernel vectors offset"
272 default 0x00003000
273 help
274 This is the offset of the kernel image from the relocatable vectors
275 base.
276
277 If unsure, leave the default value here.
278
d39af902
MF
279choice
280 prompt "KSEG layout"
281 depends on MMU
282 default XTENSA_KSEG_MMU_V2
283
284config XTENSA_KSEG_MMU_V2
285 bool "MMUv2: 128MB cached + 128MB uncached"
286 help
287 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
288 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
289 without cache.
290 KSEG_PADDR must be aligned to 128MB.
291
292config XTENSA_KSEG_256M
293 bool "256MB cached + 256MB uncached"
294 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
295 help
296 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
297 with cache and to 0xc0000000 without cache.
298 KSEG_PADDR must be aligned to 256MB.
299
300config XTENSA_KSEG_512M
301 bool "512MB cached + 512MB uncached"
302 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
303 help
304 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
305 with cache and to 0xc0000000 without cache.
306 KSEG_PADDR must be aligned to 256MB.
307
308endchoice
309
65559100
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310config HIGHMEM
311 bool "High Memory Support"
8a9de059 312 depends on MMU
65559100
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313 help
314 Linux can use the full amount of RAM in the system by
315 default. However, the default MMUv2 setup only maps the
316 lowermost 128 MB of memory linearly to the areas starting
317 at 0xd0000000 (cached) and 0xd8000000 (uncached).
318 When there are more than 128 MB memory in the system not
319 all of it can be "permanently mapped" by the kernel.
320 The physical memory that's not permanently mapped is called
321 "high memory".
322
323 If you are compiling a kernel which will never run on a
324 machine with more than 128 MB total physical RAM, answer
325 N here.
326
327 If unsure, say Y.
328
9184289c
MF
329config FAST_SYSCALL_XTENSA
330 bool "Enable fast atomic syscalls"
331 default n
332 help
333 fast_syscall_xtensa is a syscall that can make atomic operations
334 on UP kernel when processor has no s32c1i support.
335
336 This syscall is deprecated. It may have issues when called with
337 invalid arguments. It is provided only for backwards compatibility.
338 Only enable it if your userspace software requires it.
339
340 If unsure, say N.
341
342config FAST_SYSCALL_SPILL_REGISTERS
343 bool "Enable spill registers syscall"
344 default n
345 help
346 fast_syscall_spill_registers is a syscall that spills all active
347 register windows of a calling userspace task onto its stack.
348
349 This syscall is deprecated. It may have issues when called with
350 invalid arguments. It is provided only for backwards compatibility.
351 Only enable it if your userspace software requires it.
352
353 If unsure, say N.
354
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355endmenu
356
35f9cd08
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357config XTENSA_CALIBRATE_CCOUNT
358 def_bool n
359 help
360 On some platforms (XT2000, for example), the CPU clock rate can
361 vary. The frequency can be determined, however, by measuring
362 against a well known, fixed frequency, such as an UART oscillator.
363
364config SERIAL_CONSOLE
365 def_bool n
366
35f9cd08
JW
367menu "Bus options"
368
369config PCI
370 bool "PCI support"
371 default y
372 help
373 Find out whether you have a PCI motherboard. PCI is the name of a
374 bus system, i.e. the way the CPU talks to the other stuff inside
375 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
376 VESA. If you have PCI, say Y, otherwise N.
377
378source "drivers/pci/Kconfig"
379
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380endmenu
381
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382menu "Platform options"
383
384choice
385 prompt "Xtensa System Type"
386 default XTENSA_PLATFORM_ISS
387
388config XTENSA_PLATFORM_ISS
389 bool "ISS"
35f9cd08
JW
390 select XTENSA_CALIBRATE_CCOUNT
391 select SERIAL_CONSOLE
8e1a6dd2
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392 help
393 ISS is an acronym for Tensilica's Instruction Set Simulator.
394
395config XTENSA_PLATFORM_XT2000
396 bool "XT2000"
4964527d 397 select HAVE_IDE
8e1a6dd2
CZ
398 help
399 XT2000 is the name of Tensilica's feature-rich emulation platform.
400 This hardware is capable of running a full Linux distribution.
401
0d456bad
MF
402config XTENSA_PLATFORM_XTFPGA
403 bool "XTFPGA"
61e47e9b 404 select ETHOC if ETHERNET
3de00482 405 select PLATFORM_WANT_DEFAULT_MEM if !MMU
0d456bad 406 select SERIAL_CONSOLE
0d456bad
MF
407 select XTENSA_CALIBRATE_CCOUNT
408 help
409 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
410 This hardware is capable of running a full Linux distribution.
411
8e1a6dd2
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412endchoice
413
414
8e1a6dd2
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415config XTENSA_CPU_CLOCK
416 int "CPU clock rate [MHz]"
417 depends on !XTENSA_CALIBRATE_CCOUNT
35f9cd08 418 default 16
8e1a6dd2
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419
420config GENERIC_CALIBRATE_DELAY
421 bool "Auto calibration of the BogoMIPS value"
35f9cd08 422 help
82300bf4 423 The BogoMIPS value can easily be derived from the CPU frequency.
8e1a6dd2
CZ
424
425config CMDLINE_BOOL
426 bool "Default bootloader kernel arguments"
427
428config CMDLINE
429 string "Initial kernel command string"
430 depends on CMDLINE_BOOL
431 default "console=ttyS0,38400 root=/dev/ram"
432 help
433 On some architectures (EBSA110 and CATS), there is currently no way
434 for the boot loader to pass arguments to the kernel. For these
435 architectures, you should supply some command-line options at build
436 time by entering them here. As a minimum, you should specify the
437 memory size and the root device (e.g., mem=64M root=/dev/nfs).
438
da844a81
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439config USE_OF
440 bool "Flattened Device Tree support"
441 select OF
442 select OF_EARLY_FLATTREE
4e7c84ec 443 select OF_RESERVED_MEM
da844a81
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444 help
445 Include support for flattened device tree machine descriptions.
446
447config BUILTIN_DTB
448 string "DTB to build into the kernel image"
449 depends on OF
450
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451config BLK_DEV_SIMDISK
452 tristate "Host file-based simulated block device support"
453 default n
7a0684cd 454 depends on XTENSA_PLATFORM_ISS && BLOCK
b6c7e873
VP
455 help
456 Create block devices that map to files in the host file system.
457 Device binding to host file may be changed at runtime via proc
458 interface provided the device is not in use.
459
460config BLK_DEV_SIMDISK_COUNT
461 int "Number of host file-based simulated block devices"
462 range 1 10
463 depends on BLK_DEV_SIMDISK
464 default 2
465 help
466 This is the default minimal number of created block devices.
467 Kernel/module parameter 'simdisk_count' may be used to change this
468 value at runtime. More file names (but no more than 10) may be
469 specified as parameters, simdisk_count grows accordingly.
470
471config SIMDISK0_FILENAME
472 string "Host filename for the first simulated device"
473 depends on BLK_DEV_SIMDISK = y
474 default ""
475 help
476 Attach a first simdisk to a host file. Conventionally, this file
477 contains a root file system.
478
479config SIMDISK1_FILENAME
480 string "Host filename for the second simulated device"
481 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
482 default ""
483 help
484 Another simulated disk in a host file for a buildroot-independent
485 storage.
486
82300bf4
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487source "mm/Kconfig"
488
a9df9338
MF
489config FORCE_MAX_ZONEORDER
490 int "Maximum zone order"
491 default "11"
492 help
493 The kernel memory allocator divides physically contiguous memory
494 blocks into "zones", where each zone is a power of two number of
495 pages. This option selects the largest power of two that the kernel
496 keeps in the memory allocator. If you need to allocate very large
497 blocks of physically contiguous memory, then you may need to
498 increase this value.
499
500 This config option is actually maximum order plus one. For example,
501 a value of 11 means that the largest free memory block is 2^10 pages.
502
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503source "drivers/pcmcia/Kconfig"
504
3932b9ca
MF
505config PLATFORM_WANT_DEFAULT_MEM
506 def_bool n
507
508config DEFAULT_MEM_START
509 hex "Physical address of the default memory area start"
510 depends on PLATFORM_WANT_DEFAULT_MEM
511 default 0x00000000 if MMU
d9eb3cb2 512 default 0x60000000 if !MMU
3932b9ca 513 help
3de00482
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514 This is the base address of the default memory area.
515 Default memory area has platform-specific meaning, it may be used
516 for e.g. early cache initialization.
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517
518 If unsure, leave the default value here.
519
520config DEFAULT_MEM_SIZE
521 hex "Maximal size of the default memory area"
522 depends on PLATFORM_WANT_DEFAULT_MEM
523 default 0x04000000
524 help
3de00482
MF
525 This is the size of the default memory area.
526 Default memory area has platform-specific meaning, it may be used
527 for e.g. early cache initialization.
3932b9ca
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528
529 If unsure, leave the default value here.
530
4949009e
MF
531config XTFPGA_LCD
532 bool "Enable XTFPGA LCD driver"
533 depends on XTENSA_PLATFORM_XTFPGA
534 default n
535 help
536 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
537 progress messages there during bootup/shutdown. It may be useful
538 during board bringup.
539
540 If unsure, say N.
541
542config XTFPGA_LCD_BASE_ADDR
543 hex "XTFPGA LCD base address"
544 depends on XTFPGA_LCD
545 default "0x0d0c0000"
546 help
547 Base address of the LCD controller inside KIO region.
548 Different boards from XTFPGA family have LCD controller at different
549 addresses. Please consult prototyping user guide for your board for
550 the correct address. Wrong address here may lead to hardware lockup.
551
552config XTFPGA_LCD_8BIT_ACCESS
553 bool "Use 8-bit access to XTFPGA LCD"
554 depends on XTFPGA_LCD
555 default n
556 help
557 LCD may be connected with 4- or 8-bit interface, 8-bit access may
558 only be used with 8-bit interface. Please consult prototyping user
559 guide for your board for the correct interface width.
560
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561endmenu
562
cab00891 563menu "Executable file formats"
8e1a6dd2 564
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565source "fs/Kconfig.binfmt"
566
567endmenu
568
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569menu "Power management options"
570
571source "kernel/power/Kconfig"
572
573endmenu
574
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575source "net/Kconfig"
576
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577source "drivers/Kconfig"
578
579source "fs/Kconfig"
580
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581source "arch/xtensa/Kconfig.debug"
582
583source "security/Kconfig"
584
585source "crypto/Kconfig"
586
587source "lib/Kconfig"
588
589