[mirror_ubuntu-bionic-kernel.git] / arch / xtensa / include / asm / coprocessor.h

/*
 * include/asm-xtensa/coprocessor.h
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 - 2007 Tensilica Inc.
 */


#ifndef _XTENSA_COPROCESSOR_H
#define _XTENSA_COPROCESSOR_H

#include <linux/stringify.h>
#include <variant/core.h>
#include <variant/tie.h>
#include <asm/types.h>

#ifdef __ASSEMBLY__
# include <variant/tie-asm.h>

.macro	xchal_sa_start  a b
	.set .Lxchal_pofs_, 0
	.set .Lxchal_ofs_, 0
.endm

.macro	xchal_sa_align  ptr minofs maxofs ofsalign totalign
	.set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
	.set	.Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
.endm

#define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
		 | XTHAL_SAS_CC \
		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )

.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
	.if XTREGS_OPT_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm

.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
	.if XTREGS_OPT_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm
#undef _SELECT

#define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
		 | XTHAL_SAS_NOCC \
		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )

.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
	.if XTREGS_USER_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm

.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
	.if XTREGS_USER_SIZE > 0
		addi	\clb, \ptr, \offset
		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	.endif
.endm
#undef _SELECT


#endif	/* __ASSEMBLY__ */

/*
 * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
 *
 * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
 *
 */

#define XTENSA_HAVE_COPROCESSOR(x)					\
	((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
#define XTENSA_HAVE_COPROCESSORS					\
	(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
#define XTENSA_HAVE_IO_PORT(x)						\
	(XCHAL_CP_PORT_MASK & (1 << (x)))
#define XTENSA_HAVE_IO_PORTS						\
	XCHAL_CP_PORT_MASK

#ifndef __ASSEMBLY__


#if XCHAL_HAVE_CP

#define RSR_CPENABLE(x)	do {						  \
	__asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
	} while(0);
#define WSR_CPENABLE(x)	do {						  \
  	__asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" 	  \
	    		     :: "a" (x));				  \
	} while(0);

#endif /* XCHAL_HAVE_CP */


/*
 * Additional registers.
 * We define three types of additional registers:
 *  ext: extra registers that are used by the compiler
 *  cpn: optional registers that can be used by a user application
 *  cpX: coprocessor registers that can only be used if the corresponding
 *       CPENABLE bit is set.
 */

#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...)	\
	__REG ## list (cc, abi, type, name, size, align)

#define __REG0(cc,abi,t,name,s,a)	__REG0_ ## cc (abi,name)
#define __REG1(cc,abi,t,name,s,a)	__REG1_ ## cc (name)
#define __REG2(cc,abi,type,...)		__REG2_ ## type (__VA_ARGS__)

#define __REG0_0(abi,name)
#define __REG0_1(abi,name)		__REG0_1 ## abi (name)
#define __REG0_10(name)	__u32 name;
#define __REG0_11(name)	__u32 name;
#define __REG0_12(name)

#define __REG1_0(name)	__u32 name;
#define __REG1_1(name)

#define __REG2_0(n,s,a)	__u32 name;
#define __REG2_1(n,s,a)	unsigned char n[s] __attribute__ ((aligned(a)));
#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));

typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));

#if XTENSA_HAVE_COPROCESSORS

typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
	__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
	__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
	__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
	__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
	__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
	__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
	__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
	__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));

extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
extern void coprocessor_save(void*, int);
extern void coprocessor_load(void*, int);
extern void coprocessor_flush(struct thread_info*, int);
extern void coprocessor_restore(struct thread_info*, int);

extern void coprocessor_release_all(struct thread_info*);
extern void coprocessor_flush_all(struct thread_info*);

static inline void coprocessor_clear_cpenable(void)
{
	unsigned long i = 0;
	WSR_CPENABLE(i);
}

#endif	/* XTENSA_HAVE_COPROCESSORS */

#endif	/* !__ASSEMBLY__ */
#endif	/* _XTENSA_COPROCESSOR_H */
Commit	Line	Data
9a8fd558	1	/*
f30c2269	2	* include/asm-xtensa/coprocessor.h
9a8fd558 CZ	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
c658eac6	8	* Copyright (C) 2003 - 2007 Tensilica Inc.
9a8fd558 CZ	9	*/
9a8fd558 CZ	10
c658eac6	11
9a8fd558 CZ	12	#ifndef _XTENSA_COPROCESSOR_H
	13	#define _XTENSA_COPROCESSOR_H
	14
c658eac6	15	#include <linux/stringify.h>
d1eca29e	16	#include <variant/core.h>
367b8112	17	#include <variant/tie.h>
c658eac6 CZ	18	#include <asm/types.h>
	19
	20	#ifdef __ASSEMBLY__
367b8112	21	# include <variant/tie-asm.h>
c658eac6 CZ	22
	23	.macro xchal_sa_start a b
	24	.set .Lxchal_pofs_, 0
	25	.set .Lxchal_ofs_, 0
	26	.endm
	27
	28	.macro xchal_sa_align ptr minofs maxofs ofsalign totalign
	29	.set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
	30	.set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
	31	.endm
	32
	33	#define _SELECT ( XTHAL_SAS_TIE \| XTHAL_SAS_OPT \
	34	\| XTHAL_SAS_CC \
67926257	35	\| XTHAL_SAS_CALR \| XTHAL_SAS_CALE )
c658eac6 CZ	36
	37	.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
	38	.if XTREGS_OPT_SIZE > 0
	39	addi \clb, \ptr, \offset
	40	xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	41	.endif
	42	.endm
	43
	44	.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
	45	.if XTREGS_OPT_SIZE > 0
	46	addi \clb, \ptr, \offset
	47	xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	48	.endif
	49	.endm
	50	#undef _SELECT
	51
	52	#define _SELECT ( XTHAL_SAS_TIE \| XTHAL_SAS_OPT \
	53	\| XTHAL_SAS_NOCC \
	54	\| XTHAL_SAS_CALR \| XTHAL_SAS_CALE \| XTHAL_SAS_GLOB )
	55
	56	.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
	57	.if XTREGS_USER_SIZE > 0
	58	addi \clb, \ptr, \offset
	59	xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
	60	.endif
	61	.endm
	62
	63	.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
	64	.if XTREGS_USER_SIZE > 0
	65	addi \clb, \ptr, \offset
	66	xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
	67	.endif
	68	.endm
	69	#undef _SELECT
	70
	71
	72
	73	#endif /* __ASSEMBLY__ */
173d6681	74
9a8fd558	75	/*
c658eac6 CZ	76	* XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
	77	*
	78	* XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
	79	*
9a8fd558	80	*/
9a8fd558	81
c658eac6 CZ	82	#define XTENSA_HAVE_COPROCESSOR(x) \
	83	((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
	84	#define XTENSA_HAVE_COPROCESSORS \
	85	(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
	86	#define XTENSA_HAVE_IO_PORT(x) \
	87	(XCHAL_CP_PORT_MASK & (1 << (x)))
	88	#define XTENSA_HAVE_IO_PORTS \
	89	XCHAL_CP_PORT_MASK
9a8fd558 CZ	90
9a8fd558 CZ	91	#ifndef __ASSEMBLY__
9a8fd558	92
29c4dfd9	93
c658eac6	94	#if XCHAL_HAVE_CP
29c4dfd9	95
c658eac6 CZ	96	#define RSR_CPENABLE(x) do { \
	97	__asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
	98	} while(0);
	99	#define WSR_CPENABLE(x) do { \
	100	__asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \
	101	:: "a" (x)); \
	102	} while(0);
173d6681	103
c658eac6 CZ	104	#endif /* XCHAL_HAVE_CP */
	105
	106
	107	/*
	108	* Additional registers.
	109	* We define three types of additional registers:
	110	* ext: extra registers that are used by the compiler
	111	* cpn: optional registers that can be used by a user application
	112	* cpX: coprocessor registers that can only be used if the corresponding
	113	* CPENABLE bit is set.
	114	*/
	115
67926257 CZ	116	#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \
	117	__REG ## list (cc, abi, type, name, size, align)
	118
	119	#define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name)
	120	#define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name)
	121	#define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__)
c658eac6	122
67926257 CZ	123	#define __REG0_0(abi,name)
	124	#define __REG0_1(abi,name) __REG0_1 ## abi (name)
	125	#define __REG0_10(name) __u32 name;
	126	#define __REG0_11(name) __u32 name;
	127	#define __REG0_12(name)
c658eac6	128
c658eac6 CZ	129	#define __REG1_0(name) __u32 name;
c658eac6 CZ	130	#define __REG1_1(name)
67926257	131
c658eac6 CZ	132	#define __REG2_0(n,s,a) __u32 name;
	133	#define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
	134	#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
	135
	136	typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
	137	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
	138	typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
	139	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
	140
	141	#if XTENSA_HAVE_COPROCESSORS
	142
	143	typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
	144	__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
	145	typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
	146	__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
	147	typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
	148	__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
	149	typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
	150	__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
	151	typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
	152	__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
	153	typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
	154	__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
	155	typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
	156	__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
	157	typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
	158	__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
	159
	160	extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
	161	extern void coprocessor_save(void*, int);
	162	extern void coprocessor_load(void*, int);
	163	extern void coprocessor_flush(struct thread_info*, int);
	164	extern void coprocessor_restore(struct thread_info*, int);
	165
	166	extern void coprocessor_release_all(struct thread_info*);
	167	extern void coprocessor_flush_all(struct thread_info*);
	168
	169	static inline void coprocessor_clear_cpenable(void)
	170	{
	171	unsigned long i = 0;
	172	WSR_CPENABLE(i);
	173	}
	174
	175	#endif /* XTENSA_HAVE_COPROCESSORS */
	176
	177	#endif /* !__ASSEMBLY__ */
9a8fd558	178	#endif /* _XTENSA_COPROCESSOR_H */