[mirror_ubuntu-jammy-kernel.git] / arch / xtensa / include / asm / pgtable.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * include/asm-xtensa/pgtable.h
 *
 * Copyright (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_PGTABLE_H
#define _XTENSA_PGTABLE_H

#include <asm/page.h>
#include <asm/kmem_layout.h>
#include <asm-generic/pgtable-nopmd.h>

/*
 * We only use two ring levels, user and kernel space.
 */

#ifdef CONFIG_MMU
#define USER_RING		1	/* user ring level */
#else
#define USER_RING		0
#endif
#define KERNEL_RING		0	/* kernel ring level */

/*
 * The Xtensa architecture port of Linux has a two-level page table system,
 * i.e. the logical three-level Linux page table layout is folded.
 * Each task has the following memory page tables:
 *
 *   PGD table (page directory), ie. 3rd-level page table:
 *	One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
 *	(Architectures that don't have the PMD folded point to the PMD tables)
 *
 *	The pointer to the PGD table for a given task can be retrieved from
 *	the task structure (struct task_struct*) t, e.g. current():
 *	  (t->mm ? t->mm : t->active_mm)->pgd
 *
 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
 *	Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
 *
 *   PTE tables (page table entry), ie. 1st-level page tables:
 *	One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
 *	invalid_pte_table for absent mappings.
 *
 * The individual pages are 4 kB big with special pages for the empty_zero_page.
 */

#define PGDIR_SHIFT	22
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PMD directory physically.
 */
#define PTRS_PER_PTE		1024
#define PTRS_PER_PTE_SHIFT	10
#define PTRS_PER_PGD		1024
#define PGD_ORDER		0
#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0UL
#define FIRST_USER_PGD_NR	(FIRST_USER_ADDRESS >> PGDIR_SHIFT)

#ifdef CONFIG_MMU
/*
 * Virtual memory area. We keep a distance to other memory regions to be
 * on the safe side. We also use this area for cache aliasing.
 */
#define VMALLOC_START		(XCHAL_KSEG_CACHED_VADDR - 0x10000000)
#define VMALLOC_END		(VMALLOC_START + 0x07FEFFFF)
#define TLBTEMP_BASE_1		(VMALLOC_END + 1)
#define TLBTEMP_BASE_2		(TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
#define TLBTEMP_SIZE		(2 * DCACHE_WAY_SIZE)
#else
#define TLBTEMP_SIZE		ICACHE_WAY_SIZE
#endif

#else

#define VMALLOC_START		__XTENSA_UL_CONST(0)
#define VMALLOC_END		__XTENSA_UL_CONST(0xffffffff)

#endif

/*
 * For the Xtensa architecture, the PTE layout is as follows:
 *
 *		31------12  11  10-9   8-6  5-4  3-2  1-0
 *		+-----------------------------------------+
 *		|           |   Software   |   HARDWARE   |
 *		|    PPN    |          ADW | RI |Attribute|
 *		+-----------------------------------------+
 *   pte_none	|             MBZ          | 01 | 11 | 00 |
 *		+-----------------------------------------+
 *   present	|    PPN    | 0 | 00 | ADW | RI | CA | wx |
 *		+- - - - - - - - - - - - - - - - - - - - -+
 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
 *		+-----------------------------------------+
 *   swap	|     index     |   type   | 01 | 11 | 00 |
 *		+-----------------------------------------+
 *
 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
 *		+-----------------------------------------+
 *   present	|    PPN    | 0 | 00 | ADW | RI | CA | w1 |
 *		+-----------------------------------------+
 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
 *		+-----------------------------------------+
 *
 *  Legend:
 *   PPN        Physical Page Number
 *   ADW	software: accessed (young) / dirty / writable
 *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
 *   CA		cache attribute: 00 bypass, 01 writeback, 10 writethrough
 *		(11 is invalid and used to mark pages that are not present)
 *   w		page is writable (hw)
 *   x		page is executable (hw)
 *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
 *		(note that the index is always non-zero)
 *   type       swap type (5 bits -> 32 types)
 *
 *  Notes:
 *   - (PROT_NONE) is a special case of 'present' but causes an exception for
 *     any access (read, write, and execute).
 *   - 'multihit-exception' has the highest priority of all MMU exceptions,
 *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
 *   - on older hardware, the exectuable flag was not supported and
 *     used as a 'valid' flag, so it needs to be always set.
 *   - we need to keep track of certain flags in software (dirty and young)
 *     to do this, we use write exceptions and have a separate software w-flag.
 *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
 */

#define _PAGE_ATTRIB_MASK	0xf

#define _PAGE_HW_EXEC		(1<<0)	/* hardware: page is executable */
#define _PAGE_HW_WRITE		(1<<1)	/* hardware: page is writable */

#define _PAGE_CA_BYPASS		(0<<2)	/* bypass, non-speculative */
#define _PAGE_CA_WB		(1<<2)	/* write-back */
#define _PAGE_CA_WT		(2<<2)	/* write-through */
#define _PAGE_CA_MASK		(3<<2)
#define _PAGE_CA_INVALID	(3<<2)

/* We use invalid attribute values to distinguish special pte entries */
#if XCHAL_HW_VERSION_MAJOR < 2000
#define _PAGE_HW_VALID		0x01	/* older HW needed this bit set */
#define _PAGE_NONE		0x04
#else
#define _PAGE_HW_VALID		0x00
#define _PAGE_NONE		0x0f
#endif

#define _PAGE_USER		(1<<4)	/* user access (ring=1) */

/* Software */
#define _PAGE_WRITABLE_BIT	6
#define _PAGE_WRITABLE		(1<<6)	/* software: page writable */
#define _PAGE_DIRTY		(1<<7)	/* software: page dirty */
#define _PAGE_ACCESSED		(1<<8)	/* software: page accessed (read) */

#ifdef CONFIG_MMU

#define _PAGE_CHG_MASK	   (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_PRESENT	   (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)

#define PAGE_NONE	   __pgprot(_PAGE_NONE | _PAGE_USER)
#define PAGE_COPY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_COPY_EXEC	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_READONLY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_SHARED	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
#define PAGE_SHARED_EXEC \
	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
#define PAGE_KERNEL	   __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
#define PAGE_KERNEL_RO	   __pgprot(_PAGE_PRESENT)
#define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)

#if (DCACHE_WAY_SIZE > PAGE_SIZE)
# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
#else
# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
#endif

#else /* no mmu */

# define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
# define PAGE_NONE       __pgprot(0)
# define PAGE_SHARED     __pgprot(0)
# define PAGE_COPY       __pgprot(0)
# define PAGE_READONLY   __pgprot(0)
# define PAGE_KERNEL     __pgprot(0)

#endif

/*
 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 * the MMU can't do page protection for execute, and considers that the same as
 * read.  Also, write permissions may imply read permissions.
 * What follows is the closest we can get by reasonable means..
 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 */
#define __P000	PAGE_NONE		/* private --- */
#define __P001	PAGE_READONLY		/* private --r */
#define __P010	PAGE_COPY		/* private -w- */
#define __P011	PAGE_COPY		/* private -wr */
#define __P100	PAGE_READONLY_EXEC	/* private x-- */
#define __P101	PAGE_READONLY_EXEC	/* private x-r */
#define __P110	PAGE_COPY_EXEC		/* private xw- */
#define __P111	PAGE_COPY_EXEC		/* private xwr */

#define __S000	PAGE_NONE		/* shared  --- */
#define __S001	PAGE_READONLY		/* shared  --r */
#define __S010	PAGE_SHARED		/* shared  -w- */
#define __S011	PAGE_SHARED		/* shared  -wr */
#define __S100	PAGE_READONLY_EXEC	/* shared  x-- */
#define __S101	PAGE_READONLY_EXEC	/* shared  x-r */
#define __S110	PAGE_SHARED_EXEC	/* shared  xw- */
#define __S111	PAGE_SHARED_EXEC	/* shared  xwr */

#ifndef __ASSEMBLY__

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern unsigned long empty_zero_page[1024];

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

#ifdef CONFIG_MMU
extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
extern void paging_init(void);
#else
# define swapper_pg_dir NULL
static inline void paging_init(void) { }
#endif

/*
 * The pmd contains the kernel virtual address of the pte page.
 */
#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) virt_to_page(pmd_val(pmd))

/*
 * pte status.
 */
# define pte_none(pte)	 (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
#if XCHAL_HW_VERSION_MAJOR < 2000
# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
#else
# define pte_present(pte)						\
	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)		\
	 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
#endif
#define pte_clear(mm,addr,ptep)						\
	do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)

#define pmd_none(pmd)	 (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
#define pmd_bad(pmd)	 (pmd_val(pmd) & ~PAGE_MASK)
#define pmd_clear(pmdp)	 do { set_pmd(pmdp, __pmd(0)); } while (0)

static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }

static inline pte_t pte_wrprotect(pte_t pte)	
	{ pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkclean(pte_t pte)
	{ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkold(pte_t pte)
	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkdirty(pte_t pte)
	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte)
	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite(pte_t pte)
	{ pte_val(pte) |= _PAGE_WRITABLE; return pte; }

#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */

#define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
#define pte_same(a,b)		(pte_val(a) == pte_val(b))
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}

/*
 * Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
static inline void update_pte(pte_t *ptep, pte_t pteval)
{
	*ptep = pteval;
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
#endif

}

struct mm_struct;

static inline void
set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}

static inline void set_pte(pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}

static inline void
set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
	*pmdp = pmdval;
}

struct vm_area_struct;

static inline int
ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
			  pte_t *ptep)
{
	pte_t pte = *ptep;
	if (!pte_young(pte))
		return 0;
	update_pte(ptep, pte_mkold(pte));
	return 1;
}

static inline pte_t
ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	pte_clear(mm, addr, ptep);
	return pte;
}

static inline void
ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	update_pte(ptep, pte_wrprotect(pte));
}

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address)	pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm,address)	((mm)->pgd + pgd_index(address))

#define pgd_index(address)	((address) >> PGDIR_SHIFT)

/* Find an entry in the third-level page table.. */
#define pte_index(address)	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir,addr) 					\
	((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir,addr)	pte_offset_kernel((dir),(addr))
#define pte_unmap(pte)		do { } while (0)


/*
 * Encode and decode a swap and file entry.
 */
#define SWP_TYPE_BITS		5
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)

#define __swp_type(entry)	(((entry).val >> 6) & 0x1f)
#define __swp_offset(entry)	((entry).val >> 11)
#define __swp_entry(type,offs)	\
	((swp_entry_t){((type) << 6) | ((offs) << 11) | \
	 _PAGE_CA_INVALID | _PAGE_USER})
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#endif /*  !defined (__ASSEMBLY__) */


#ifdef __ASSEMBLY__

/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 *
 * Note: We require an additional temporary register which can be the same as
 *       the register that holds the address.
 *
 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 *
 */
#define _PGD_INDEX(rt,rs)	extui	rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
#define _PTE_INDEX(rt,rs)	extui	rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT

#define _PGD_OFFSET(mm,adr,tmp)		l32i	mm, mm, MM_PGD;		\
					_PGD_INDEX(tmp, adr);		\
					addx4	mm, tmp, mm

#define _PTE_OFFSET(pmd,adr,tmp)	_PTE_INDEX(tmp, adr);		\
					srli	pmd, pmd, PAGE_SHIFT;	\
					slli	pmd, pmd, PAGE_SHIFT;	\
					addx4	pmd, tmp, pmd

#else

#define kern_addr_valid(addr)	(1)

extern  void update_mmu_cache(struct vm_area_struct * vma,
			      unsigned long address, pte_t *ptep);

typedef pte_t *pte_addr_t;

#endif /* !defined (__ASSEMBLY__) */

#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTEP_MKDIRTY
#define __HAVE_ARCH_PTE_SAME
/* We provide our own get_unmapped_area to cope with
 * SHM area cache aliasing for userland.
 */
#define HAVE_ARCH_UNMAPPED_AREA

#endif /* _XTENSA_PGTABLE_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
9a8fd558	2	/*
6656920b	3	* include/asm-xtensa/pgtable.h
9a8fd558	4	*
7711ece9	5	* Copyright (C) 2001 - 2013 Tensilica Inc.
9a8fd558 CZ	6	*/
	7
	8	#ifndef _XTENSA_PGTABLE_H
	9	#define _XTENSA_PGTABLE_H
	10
9a8fd558	11	#include <asm/page.h>
f1883aa7	12	#include <asm/kmem_layout.h>
c633544a	13	#include <asm-generic/pgtable-nopmd.h>
9a8fd558	14
9a8fd558 CZ	15	/*
	16	* We only use two ring levels, user and kernel space.
	17	*/
	18
cfedf08b	19	#ifdef CONFIG_MMU
9a8fd558	20	#define USER_RING 1 /* user ring level */
cfedf08b MF	21	#else
	22	#define USER_RING 0
	23	#endif
9a8fd558 CZ	24	#define KERNEL_RING 0 /* kernel ring level */
	25
	26	/*
	27	* The Xtensa architecture port of Linux has a two-level page table system,
01858d1b	28	* i.e. the logical three-level Linux page table layout is folded.
9a8fd558 CZ	29	* Each task has the following memory page tables:
	30	*
	31	* PGD table (page directory), ie. 3rd-level page table:
	32	* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
	33	* (Architectures that don't have the PMD folded point to the PMD tables)
	34	*
	35	* The pointer to the PGD table for a given task can be retrieved from
	36	* the task structure (struct task_struct*) t, e.g. current():
	37	* (t->mm ? t->mm : t->active_mm)->pgd
	38	*
	39	* PMD tables (page middle-directory), ie. 2nd-level page tables:
	40	* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
	41	*
	42	* PTE tables (page table entry), ie. 1st-level page tables:
	43	* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
	44	* invalid_pte_table for absent mappings.
	45	*
	46	* The individual pages are 4 kB big with special pages for the empty_zero_page.
	47	*/
01858d1b	48
9a8fd558 CZ	49	#define PGDIR_SHIFT 22
	50	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	51	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	52
	53	/*
	54	* Entries per page directory level: we use two-level, so
	55	* we don't really have any PMD directory physically.
	56	*/
	57	#define PTRS_PER_PTE 1024
	58	#define PTRS_PER_PTE_SHIFT 10
9a8fd558 CZ	59	#define PTRS_PER_PGD 1024
9a8fd558 CZ	60	#define PGD_ORDER 0
9a8fd558	61	#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
d016bf7e	62	#define FIRST_USER_ADDRESS 0UL
9a8fd558 CZ	63	#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
9a8fd558 CZ	64
2cc15e80	65	#ifdef CONFIG_MMU
6656920b CZ	66	/*
6656920b CZ	67	* Virtual memory area. We keep a distance to other memory regions to be
9a8fd558 CZ	68	* on the safe side. We also use this area for cache aliasing.
9a8fd558 CZ	69	*/
f1883aa7 MF	70	#define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
	71	#define VMALLOC_END (VMALLOC_START + 0x07FEFFFF)
	72	#define TLBTEMP_BASE_1 (VMALLOC_END + 1)
7128039f MF	73	#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
	74	#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
	75	#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
	76	#else
	77	#define TLBTEMP_SIZE ICACHE_WAY_SIZE
	78	#endif
9a8fd558	79
2cc15e80 MF	80	#else
	81
	82	#define VMALLOC_START __XTENSA_UL_CONST(0)
	83	#define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
	84
	85	#endif
	86
6656920b	87	/*
7711ece9 CZ	88	* For the Xtensa architecture, the PTE layout is as follows:
	89	*
	90	* 31------12 11 10-9 8-6 5-4 3-2 1-0
	91	* +-----------------------------------------+
	92	* \| \| Software \| HARDWARE \|
	93	* \| PPN \| ADW \| RI \|Attribute\|
	94	* +-----------------------------------------+
	95	* pte_none \| MBZ \| 01 \| 11 \| 00 \|
	96	* +-----------------------------------------+
	97	* present \| PPN \| 0 \| 00 \| ADW \| RI \| CA \| wx \|
	98	* +- - - - - - - - - - - - - - - - - - - - -+
	99	* (PAGE_NONE)\| PPN \| 0 \| 00 \| ADW \| 01 \| 11 \| 11 \|
	100	* +-----------------------------------------+
	101	* swap \| index \| type \| 01 \| 11 \| 00 \|
7711ece9 CZ	102	* +-----------------------------------------+
	103	*
	104	* For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
	105	* +-----------------------------------------+
	106	* present \| PPN \| 0 \| 00 \| ADW \| RI \| CA \| w1 \|
	107	* +-----------------------------------------+
	108	* (PAGE_NONE)\| PPN \| 0 \| 00 \| ADW \| 01 \| 01 \| 00 \|
	109	* +-----------------------------------------+
9a8fd558	110	*
7711ece9 CZ	111	* Legend:
	112	* PPN Physical Page Number
	113	* ADW software: accessed (young) / dirty / writable
	114	* RI ring (0=privileged, 1=user, 2 and 3 are unused)
	115	* CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
	116	* (11 is invalid and used to mark pages that are not present)
	117	* w page is writable (hw)
	118	* x page is executable (hw)
	119	* index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
	120	* (note that the index is always non-zero)
	121	* type swap type (5 bits -> 32 types)
9a8fd558	122	*
7711ece9 CZ	123	* Notes:
	124	* - (PROT_NONE) is a special case of 'present' but causes an exception for
	125	* any access (read, write, and execute).
	126	* - 'multihit-exception' has the highest priority of all MMU exceptions,
	127	* so the ring must be set to 'RING_USER' even for 'non-present' pages.
	128	* - on older hardware, the exectuable flag was not supported and
	129	* used as a 'valid' flag, so it needs to be always set.
	130	* - we need to keep track of certain flags in software (dirty and young)
	131	* to do this, we use write exceptions and have a separate software w-flag.
	132	* - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
9a8fd558 CZ	133	*/
9a8fd558 CZ	134
7711ece9 CZ	135	#define _PAGE_ATTRIB_MASK 0xf
7711ece9 CZ	136
01858d1b CZ	137	#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
	138	#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
	139
01858d1b CZ	140	#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
	141	#define _PAGE_CA_WB (1<<2) /* write-back */
	142	#define _PAGE_CA_WT (2<<2) /* write-through */
	143	#define _PAGE_CA_MASK (3<<2)
7711ece9 CZ	144	#define _PAGE_CA_INVALID (3<<2)
	145
	146	/* We use invalid attribute values to distinguish special pte entries */
	147	#if XCHAL_HW_VERSION_MAJOR < 2000
	148	#define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
	149	#define _PAGE_NONE 0x04
	150	#else
	151	#define _PAGE_HW_VALID 0x00
	152	#define _PAGE_NONE 0x0f
	153	#endif
9a8fd558 CZ	154
9a8fd558 CZ	155	#define _PAGE_USER (1<<4) /* user access (ring=1) */
9a8fd558 CZ	156
9a8fd558 CZ	157	/* Software */
01858d1b CZ	158	#define _PAGE_WRITABLE_BIT 6
01858d1b CZ	159	#define _PAGE_WRITABLE (1<<6) /* software: page writable */
9a8fd558 CZ	160	#define _PAGE_DIRTY (1<<7) /* software: page dirty */
9a8fd558 CZ	161	#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
9a8fd558	162
9a8fd558 CZ	163	#ifdef CONFIG_MMU
9a8fd558 CZ	164
7711ece9 CZ	165	#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
	166	#define _PAGE_PRESENT (_PAGE_HW_VALID \| _PAGE_CA_WB \| _PAGE_ACCESSED)
	167
	168	#define PAGE_NONE __pgprot(_PAGE_NONE \| _PAGE_USER)
01858d1b CZ	169	#define PAGE_COPY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	170	#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	171	#define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	172	#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	173	#define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE)
	174	#define PAGE_SHARED_EXEC \
	175	__pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE \| _PAGE_HW_EXEC)
6656920b	176	#define PAGE_KERNEL __pgprot(_PAGE_PRESENT \| _PAGE_HW_WRITE)
c633544a	177	#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT)
6656920b	178	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT\|_PAGE_HW_WRITE\|_PAGE_HW_EXEC)
01858d1b CZ	179
01858d1b CZ	180	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
7711ece9	181	# define _PAGE_DIRECTORY (_PAGE_HW_VALID \| _PAGE_ACCESSED \| _PAGE_CA_BYPASS)
01858d1b	182	#else
7711ece9	183	# define _PAGE_DIRECTORY (_PAGE_HW_VALID \| _PAGE_ACCESSED \| _PAGE_CA_WB)
01858d1b	184	#endif
9a8fd558 CZ	185
	186	#else /* no mmu */
	187
972c55bf	188	# define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
9a8fd558 CZ	189	# define PAGE_NONE __pgprot(0)
	190	# define PAGE_SHARED __pgprot(0)
	191	# define PAGE_COPY __pgprot(0)
	192	# define PAGE_READONLY __pgprot(0)
	193	# define PAGE_KERNEL __pgprot(0)
	194
	195	#endif
	196
	197	/*
	198	* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
	199	* the MMU can't do page protection for execute, and considers that the same as
	200	* read. Also, write permissions may imply read permissions.
	201	* What follows is the closest we can get by reasonable means..
	202	* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
	203	*/
01858d1b CZ	204	#define __P000 PAGE_NONE /* private --- */
	205	#define __P001 PAGE_READONLY /* private --r */
	206	#define __P010 PAGE_COPY /* private -w- */
	207	#define __P011 PAGE_COPY /* private -wr */
	208	#define __P100 PAGE_READONLY_EXEC /* private x-- */
	209	#define __P101 PAGE_READONLY_EXEC /* private x-r */
	210	#define __P110 PAGE_COPY_EXEC /* private xw- */
	211	#define __P111 PAGE_COPY_EXEC /* private xwr */
	212
	213	#define __S000 PAGE_NONE /* shared --- */
	214	#define __S001 PAGE_READONLY /* shared --r */
	215	#define __S010 PAGE_SHARED /* shared -w- */
	216	#define __S011 PAGE_SHARED /* shared -wr */
	217	#define __S100 PAGE_READONLY_EXEC /* shared x-- */
	218	#define __S101 PAGE_READONLY_EXEC /* shared x-r */
	219	#define __S110 PAGE_SHARED_EXEC /* shared xw- */
	220	#define __S111 PAGE_SHARED_EXEC /* shared xwr */
9a8fd558 CZ	221
	222	#ifndef __ASSEMBLY__
	223
	224	#define pte_ERROR(e) \
	225	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	226	#define pgd_ERROR(e) \
	227	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	228
	229	extern unsigned long empty_zero_page[1024];
	230
	231	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	232
e5083a63	233	#ifdef CONFIG_MMU
9a8fd558	234	extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
e5083a63	235	extern void paging_init(void);
e5083a63 JW	236	#else
	237	# define swapper_pg_dir NULL
	238	static inline void paging_init(void) { }
e5083a63	239	#endif
9a8fd558 CZ	240
	241	/*
	242	* The pmd contains the kernel virtual address of the pte page.
	243	*/
46a82b2d	244	#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
9a8fd558 CZ	245	#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
	246
	247	/*
01858d1b	248	* pte status.
9a8fd558	249	*/
7711ece9 CZ	250	# define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID \| _PAGE_USER))
	251	#if XCHAL_HW_VERSION_MAJOR < 2000
	252	# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
	253	#else
	254	# define pte_present(pte) \
	255	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
	256	\|\| ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
	257	#endif
9a8fd558	258	#define pte_clear(mm,addr,ptep) \
7711ece9	259	do { update_pte(ptep, __pte(_PAGE_CA_INVALID \| _PAGE_USER)); } while (0)
9a8fd558 CZ	260
	261	#define pmd_none(pmd) (!pmd_val(pmd))
	262	#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
9a8fd558	263	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
01858d1b	264	#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
9a8fd558	265
01858d1b	266	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
9a8fd558 CZ	267	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
9a8fd558 CZ	268	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
7e675137	269
01858d1b CZ	270	static inline pte_t pte_wrprotect(pte_t pte)
	271	{ pte_val(pte) &= ~(_PAGE_WRITABLE \| _PAGE_HW_WRITE); return pte; }
	272	static inline pte_t pte_mkclean(pte_t pte)
	273	{ pte_val(pte) &= ~(_PAGE_DIRTY \| _PAGE_HW_WRITE); return pte; }
	274	static inline pte_t pte_mkold(pte_t pte)
	275	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
	276	static inline pte_t pte_mkdirty(pte_t pte)
	277	{ pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	278	static inline pte_t pte_mkyoung(pte_t pte)
	279	{ pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
	280	static inline pte_t pte_mkwrite(pte_t pte)
	281	{ pte_val(pte) \|= _PAGE_WRITABLE; return pte; }
9a8fd558	282
a211276a MF	283	#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
a211276a MF	284
9a8fd558 CZ	285	/*
	286	* Conversion functions: convert a page and protection to a page entry,
	287	* and a page entry and page directory to the page they refer to.
	288	*/
01858d1b	289
9a8fd558 CZ	290	#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
	291	#define pte_same(a,b) (pte_val(a) == pte_val(b))
	292	#define pte_page(x) pfn_to_page(pte_pfn(x))
	293	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	294	#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
	295
d99cf715	296	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
9a8fd558 CZ	297	{
	298	return __pte((pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot));
	299	}
	300
	301	/*
	302	* Certain architectures need to do special things when pte's
	303	* within a page table are directly modified. Thus, the following
	304	* hook is made available.
	305	*/
	306	static inline void update_pte(pte_t *ptep, pte_t pteval)
	307	{
	308	*ptep = pteval;
6656920b CZ	309	#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	310	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
	311	#endif
	312
9a8fd558 CZ	313	}
9a8fd558 CZ	314
8c65b4a6 TS	315	struct mm_struct;
8c65b4a6 TS	316
d99cf715	317	static inline void
9a8fd558 CZ	318	set_pte_at(struct mm_struct mm, unsigned long addr, pte_t ptep, pte_t pteval)
	319	{
	320	update_pte(ptep, pteval);
	321	}
	322
65559100 MF	323	static inline void set_pte(pte_t *ptep, pte_t pteval)
	324	{
	325	update_pte(ptep, pteval);
	326	}
9a8fd558	327
d99cf715	328	static inline void
9a8fd558 CZ	329	set_pmd(pmd_t *pmdp, pmd_t pmdval)
	330	{
	331	*pmdp = pmdval;
9a8fd558 CZ	332	}
9a8fd558 CZ	333
8c65b4a6	334	struct vm_area_struct;
9a8fd558 CZ	335
	336	static inline int
	337	ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
c4c4594b	338	pte_t *ptep)
9a8fd558 CZ	339	{
	340	pte_t pte = *ptep;
	341	if (!pte_young(pte))
	342	return 0;
	343	update_pte(ptep, pte_mkold(pte));
	344	return 1;
	345	}
	346
9a8fd558 CZ	347	static inline pte_t
	348	ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	349	{
	350	pte_t pte = *ptep;
	351	pte_clear(mm, addr, ptep);
	352	return pte;
	353	}
	354
	355	static inline void
	356	ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
	357	{
c4c4594b CZ	358	pte_t pte = *ptep;
c4c4594b CZ	359	update_pte(ptep, pte_wrprotect(pte));
9a8fd558 CZ	360	}
	361
	362	/* to find an entry in a kernel page-table-directory */
	363	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	364
	365	/* to find an entry in a page-table-directory */
	366	#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
	367
	368	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	369
9a8fd558 CZ	370	/* Find an entry in the third-level page table.. */
	371	#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	372	#define pte_offset_kernel(dir,addr) \
46a82b2d	373	((pte_t) pmd_page_vaddr((dir)) + pte_index(addr))
9a8fd558	374	#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
9a8fd558	375	#define pte_unmap(pte) do { } while (0)
9a8fd558 CZ	376
	377
	378	/*
7711ece9	379	* Encode and decode a swap and file entry.
9a8fd558	380	*/
7711ece9 CZ	381	#define SWP_TYPE_BITS 5
7711ece9 CZ	382	#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
9a8fd558	383
01858d1b CZ	384	#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
	385	#define __swp_offset(entry) ((entry).val >> 11)
	386	#define __swp_entry(type,offs) \
7711ece9 CZ	387	((swp_entry_t){((type) << 6) \| ((offs) << 11) \| \
7711ece9 CZ	388	_PAGE_CA_INVALID \| _PAGE_USER})
9a8fd558 CZ	389	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	390	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	391
9a8fd558 CZ	392	#endif /* !defined (__ASSEMBLY__) */
	393
	394
	395	#ifdef __ASSEMBLY__
	396
	397	/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
	398	* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
	399	* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
	400	* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
	401	*
	402	* Note: We require an additional temporary register which can be the same as
	403	* the register that holds the address.
	404	*
	405	* ((pte_t) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) + pte_index(addr))
	406	*
	407	*/
	408	#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
	409	#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
	410
	411	#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
	412	_PGD_INDEX(tmp, adr); \
	413	addx4 mm, tmp, mm
	414
	415	#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
	416	srli pmd, pmd, PAGE_SHIFT; \
	417	slli pmd, pmd, PAGE_SHIFT; \
	418	addx4 pmd, tmp, pmd
	419
	420	#else
	421
9a8fd558 CZ	422	#define kern_addr_valid(addr) (1)
	423
	424	extern void update_mmu_cache(struct vm_area_struct * vma,
4b3073e1	425	unsigned long address, pte_t *ptep);
9a8fd558	426
9a8fd558 CZ	427	typedef pte_t *pte_addr_t;
	428
	429	#endif /* !defined (__ASSEMBLY__) */
	430
	431	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
9a8fd558 CZ	432	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	433	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	434	#define __HAVE_ARCH_PTEP_MKDIRTY
	435	#define __HAVE_ARCH_PTE_SAME
de73b6b1 MF	436	/* We provide our own get_unmapped_area to cope with
	437	* SHM area cache aliasing for userland.
	438	*/
	439	#define HAVE_ARCH_UNMAPPED_AREA
9a8fd558	440
9a8fd558	441	#endif /* _XTENSA_PGTABLE_H */