[mirror_ubuntu-artful-kernel.git] / arch / xtensa / include / asm / pgtable.h

/*
 * include/asm-xtensa/pgtable.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright (C) 2001 - 2013 Tensilica Inc.
 */

#ifndef _XTENSA_PGTABLE_H
#define _XTENSA_PGTABLE_H

#include <asm-generic/pgtable-nopmd.h>
#include <asm/page.h>

/*
 * We only use two ring levels, user and kernel space.
 */

#ifdef CONFIG_MMU
#define USER_RING		1	/* user ring level */
#else
#define USER_RING		0
#endif
#define KERNEL_RING		0	/* kernel ring level */

/*
 * The Xtensa architecture port of Linux has a two-level page table system,
 * i.e. the logical three-level Linux page table layout is folded.
 * Each task has the following memory page tables:
 *
 *   PGD table (page directory), ie. 3rd-level page table:
 *	One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
 *	(Architectures that don't have the PMD folded point to the PMD tables)
 *
 *	The pointer to the PGD table for a given task can be retrieved from
 *	the task structure (struct task_struct*) t, e.g. current():
 *	  (t->mm ? t->mm : t->active_mm)->pgd
 *
 *   PMD tables (page middle-directory), ie. 2nd-level page tables:
 *	Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
 *
 *   PTE tables (page table entry), ie. 1st-level page tables:
 *	One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
 *	invalid_pte_table for absent mappings.
 *
 * The individual pages are 4 kB big with special pages for the empty_zero_page.
 */

#define PGDIR_SHIFT	22
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level: we use two-level, so
 * we don't really have any PMD directory physically.
 */
#define PTRS_PER_PTE		1024
#define PTRS_PER_PTE_SHIFT	10
#define PTRS_PER_PGD		1024
#define PGD_ORDER		0
#define USER_PTRS_PER_PGD	(TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0UL
#define FIRST_USER_PGD_NR	(FIRST_USER_ADDRESS >> PGDIR_SHIFT)

/*
 * Virtual memory area. We keep a distance to other memory regions to be
 * on the safe side. We also use this area for cache aliasing.
 */
#define VMALLOC_START		0xC0000000
#define VMALLOC_END		0xC7FEFFFF
#define TLBTEMP_BASE_1		0xC7FF0000
#define TLBTEMP_BASE_2		(TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
#define TLBTEMP_SIZE		(2 * DCACHE_WAY_SIZE)
#else
#define TLBTEMP_SIZE		ICACHE_WAY_SIZE
#endif

/*
 * For the Xtensa architecture, the PTE layout is as follows:
 *
 *		31------12  11  10-9   8-6  5-4  3-2  1-0
 *		+-----------------------------------------+
 *		|           |   Software   |   HARDWARE   |
 *		|    PPN    |          ADW | RI |Attribute|
 *		+-----------------------------------------+
 *   pte_none	|             MBZ          | 01 | 11 | 00 |
 *		+-----------------------------------------+
 *   present	|    PPN    | 0 | 00 | ADW | RI | CA | wx |
 *		+- - - - - - - - - - - - - - - - - - - - -+
 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
 *		+-----------------------------------------+
 *   swap	|     index     |   type   | 01 | 11 | 00 |
 *		+-----------------------------------------+
 *
 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
 *		+-----------------------------------------+
 *   present	|    PPN    | 0 | 00 | ADW | RI | CA | w1 |
 *		+-----------------------------------------+
 *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
 *		+-----------------------------------------+
 *
 *  Legend:
 *   PPN        Physical Page Number
 *   ADW	software: accessed (young) / dirty / writable
 *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
 *   CA		cache attribute: 00 bypass, 01 writeback, 10 writethrough
 *		(11 is invalid and used to mark pages that are not present)
 *   w		page is writable (hw)
 *   x		page is executable (hw)
 *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
 *		(note that the index is always non-zero)
 *   type       swap type (5 bits -> 32 types)
 *
 *  Notes:
 *   - (PROT_NONE) is a special case of 'present' but causes an exception for
 *     any access (read, write, and execute).
 *   - 'multihit-exception' has the highest priority of all MMU exceptions,
 *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
 *   - on older hardware, the exectuable flag was not supported and
 *     used as a 'valid' flag, so it needs to be always set.
 *   - we need to keep track of certain flags in software (dirty and young)
 *     to do this, we use write exceptions and have a separate software w-flag.
 *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
 */

#define _PAGE_ATTRIB_MASK	0xf

#define _PAGE_HW_EXEC		(1<<0)	/* hardware: page is executable */
#define _PAGE_HW_WRITE		(1<<1)	/* hardware: page is writable */

#define _PAGE_CA_BYPASS		(0<<2)	/* bypass, non-speculative */
#define _PAGE_CA_WB		(1<<2)	/* write-back */
#define _PAGE_CA_WT		(2<<2)	/* write-through */
#define _PAGE_CA_MASK		(3<<2)
#define _PAGE_CA_INVALID	(3<<2)

/* We use invalid attribute values to distinguish special pte entries */
#if XCHAL_HW_VERSION_MAJOR < 2000
#define _PAGE_HW_VALID		0x01	/* older HW needed this bit set */
#define _PAGE_NONE		0x04
#else
#define _PAGE_HW_VALID		0x00
#define _PAGE_NONE		0x0f
#endif

#define _PAGE_USER		(1<<4)	/* user access (ring=1) */

/* Software */
#define _PAGE_WRITABLE_BIT	6
#define _PAGE_WRITABLE		(1<<6)	/* software: page writable */
#define _PAGE_DIRTY		(1<<7)	/* software: page dirty */
#define _PAGE_ACCESSED		(1<<8)	/* software: page accessed (read) */

#ifdef CONFIG_MMU

#define _PAGE_CHG_MASK	   (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_PRESENT	   (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)

#define PAGE_NONE	   __pgprot(_PAGE_NONE | _PAGE_USER)
#define PAGE_COPY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_COPY_EXEC	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_READONLY	   __pgprot(_PAGE_PRESENT | _PAGE_USER)
#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
#define PAGE_SHARED	   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
#define PAGE_SHARED_EXEC \
	__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
#define PAGE_KERNEL	   __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
#define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)

#if (DCACHE_WAY_SIZE > PAGE_SIZE)
# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
#else
# define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
#endif

#else /* no mmu */

# define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
# define PAGE_NONE       __pgprot(0)
# define PAGE_SHARED     __pgprot(0)
# define PAGE_COPY       __pgprot(0)
# define PAGE_READONLY   __pgprot(0)
# define PAGE_KERNEL     __pgprot(0)

#endif

/*
 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 * the MMU can't do page protection for execute, and considers that the same as
 * read.  Also, write permissions may imply read permissions.
 * What follows is the closest we can get by reasonable means..
 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 */
#define __P000	PAGE_NONE		/* private --- */
#define __P001	PAGE_READONLY		/* private --r */
#define __P010	PAGE_COPY		/* private -w- */
#define __P011	PAGE_COPY		/* private -wr */
#define __P100	PAGE_READONLY_EXEC	/* private x-- */
#define __P101	PAGE_READONLY_EXEC	/* private x-r */
#define __P110	PAGE_COPY_EXEC		/* private xw- */
#define __P111	PAGE_COPY_EXEC		/* private xwr */

#define __S000	PAGE_NONE		/* shared  --- */
#define __S001	PAGE_READONLY		/* shared  --r */
#define __S010	PAGE_SHARED		/* shared  -w- */
#define __S011	PAGE_SHARED		/* shared  -wr */
#define __S100	PAGE_READONLY_EXEC	/* shared  x-- */
#define __S101	PAGE_READONLY_EXEC	/* shared  x-r */
#define __S110	PAGE_SHARED_EXEC	/* shared  xw- */
#define __S111	PAGE_SHARED_EXEC	/* shared  xwr */

#ifndef __ASSEMBLY__

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))

extern unsigned long empty_zero_page[1024];

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

#ifdef CONFIG_MMU
extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
extern void paging_init(void);
#else
# define swapper_pg_dir NULL
static inline void paging_init(void) { }
#endif
static inline void pgtable_cache_init(void) { }

/*
 * The pmd contains the kernel virtual address of the pte page.
 */
#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) virt_to_page(pmd_val(pmd))

/*
 * pte status.
 */
# define pte_none(pte)	 (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
#if XCHAL_HW_VERSION_MAJOR < 2000
# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
#else
# define pte_present(pte)						\
	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)		\
	 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
#endif
#define pte_clear(mm,addr,ptep)						\
	do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)

#define pmd_none(pmd)	 (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
#define pmd_bad(pmd)	 (pmd_val(pmd) & ~PAGE_MASK)
#define pmd_clear(pmdp)	 do { set_pmd(pmdp, __pmd(0)); } while (0)

static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
static inline int pte_special(pte_t pte) { return 0; }

static inline pte_t pte_wrprotect(pte_t pte)	
	{ pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkclean(pte_t pte)
	{ pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
static inline pte_t pte_mkold(pte_t pte)
	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkdirty(pte_t pte)
	{ pte_val(pte) |= _PAGE_DIRTY; return pte; }
static inline pte_t pte_mkyoung(pte_t pte)
	{ pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkwrite(pte_t pte)
	{ pte_val(pte) |= _PAGE_WRITABLE; return pte; }
static inline pte_t pte_mkspecial(pte_t pte)
	{ return pte; }

#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */

#define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
#define pte_same(a,b)		(pte_val(a) == pte_val(b))
#define pte_page(x)		pfn_to_page(pte_pfn(x))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define mk_pte(page, prot)	pfn_pte(page_to_pfn(page), prot)

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}

/*
 * Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
static inline void update_pte(pte_t *ptep, pte_t pteval)
{
	*ptep = pteval;
#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
#endif

}

struct mm_struct;

static inline void
set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}

static inline void set_pte(pte_t *ptep, pte_t pteval)
{
	update_pte(ptep, pteval);
}

static inline void
set_pmd(pmd_t *pmdp, pmd_t pmdval)
{
	*pmdp = pmdval;
}

struct vm_area_struct;

static inline int
ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
			  pte_t *ptep)
{
	pte_t pte = *ptep;
	if (!pte_young(pte))
		return 0;
	update_pte(ptep, pte_mkold(pte));
	return 1;
}

static inline pte_t
ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	pte_clear(mm, addr, ptep);
	return pte;
}

static inline void
ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_t pte = *ptep;
	update_pte(ptep, pte_wrprotect(pte));
}

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address)	pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm,address)	((mm)->pgd + pgd_index(address))

#define pgd_index(address)	((address) >> PGDIR_SHIFT)

/* Find an entry in the second-level page table.. */
#define pmd_offset(dir,address) ((pmd_t*)(dir))

/* Find an entry in the third-level page table.. */
#define pte_index(address)	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir,addr) 					\
	((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir,addr)	pte_offset_kernel((dir),(addr))
#define pte_unmap(pte)		do { } while (0)


/*
 * Encode and decode a swap and file entry.
 */
#define SWP_TYPE_BITS		5
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)

#define __swp_type(entry)	(((entry).val >> 6) & 0x1f)
#define __swp_offset(entry)	((entry).val >> 11)
#define __swp_entry(type,offs)	\
	((swp_entry_t){((type) << 6) | ((offs) << 11) | \
	 _PAGE_CA_INVALID | _PAGE_USER})
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#endif /*  !defined (__ASSEMBLY__) */


#ifdef __ASSEMBLY__

/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 *
 * Note: We require an additional temporary register which can be the same as
 *       the register that holds the address.
 *
 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 *
 */
#define _PGD_INDEX(rt,rs)	extui	rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
#define _PTE_INDEX(rt,rs)	extui	rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT

#define _PGD_OFFSET(mm,adr,tmp)		l32i	mm, mm, MM_PGD;		\
					_PGD_INDEX(tmp, adr);		\
					addx4	mm, tmp, mm

#define _PTE_OFFSET(pmd,adr,tmp)	_PTE_INDEX(tmp, adr);		\
					srli	pmd, pmd, PAGE_SHIFT;	\
					slli	pmd, pmd, PAGE_SHIFT;	\
					addx4	pmd, tmp, pmd

#else

#define kern_addr_valid(addr)	(1)

extern  void update_mmu_cache(struct vm_area_struct * vma,
			      unsigned long address, pte_t *ptep);

typedef pte_t *pte_addr_t;

#endif /* !defined (__ASSEMBLY__) */

#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
#define __HAVE_ARCH_PTEP_MKDIRTY
#define __HAVE_ARCH_PTE_SAME
/* We provide our own get_unmapped_area to cope with
 * SHM area cache aliasing for userland.
 */
#define HAVE_ARCH_UNMAPPED_AREA

#include <asm-generic/pgtable.h>

#endif /* _XTENSA_PGTABLE_H */
Commit	Line	Data
9a8fd558	1	/*
6656920b	2	* include/asm-xtensa/pgtable.h
9a8fd558 CZ	3	*
9a8fd558 CZ	4	* This program is free software; you can redistribute it and/or modify
01858d1b	5	* it under the terms of the GNU General Public License version 2 as
9a8fd558 CZ	6	* published by the Free Software Foundation.
9a8fd558 CZ	7	*
7711ece9	8	* Copyright (C) 2001 - 2013 Tensilica Inc.
9a8fd558 CZ	9	*/
	10
	11	#ifndef _XTENSA_PGTABLE_H
	12	#define _XTENSA_PGTABLE_H
	13
	14	#include <asm-generic/pgtable-nopmd.h>
	15	#include <asm/page.h>
	16
9a8fd558 CZ	17	/*
	18	* We only use two ring levels, user and kernel space.
	19	*/
	20
cfedf08b	21	#ifdef CONFIG_MMU
9a8fd558	22	#define USER_RING 1 /* user ring level */
cfedf08b MF	23	#else
	24	#define USER_RING 0
	25	#endif
9a8fd558 CZ	26	#define KERNEL_RING 0 /* kernel ring level */
	27
	28	/*
	29	* The Xtensa architecture port of Linux has a two-level page table system,
01858d1b	30	* i.e. the logical three-level Linux page table layout is folded.
9a8fd558 CZ	31	* Each task has the following memory page tables:
	32	*
	33	* PGD table (page directory), ie. 3rd-level page table:
	34	* One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
	35	* (Architectures that don't have the PMD folded point to the PMD tables)
	36	*
	37	* The pointer to the PGD table for a given task can be retrieved from
	38	* the task structure (struct task_struct*) t, e.g. current():
	39	* (t->mm ? t->mm : t->active_mm)->pgd
	40	*
	41	* PMD tables (page middle-directory), ie. 2nd-level page tables:
	42	* Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
	43	*
	44	* PTE tables (page table entry), ie. 1st-level page tables:
	45	* One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
	46	* invalid_pte_table for absent mappings.
	47	*
	48	* The individual pages are 4 kB big with special pages for the empty_zero_page.
	49	*/
01858d1b	50
9a8fd558 CZ	51	#define PGDIR_SHIFT 22
	52	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	53	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	54
	55	/*
	56	* Entries per page directory level: we use two-level, so
	57	* we don't really have any PMD directory physically.
	58	*/
	59	#define PTRS_PER_PTE 1024
	60	#define PTRS_PER_PTE_SHIFT 10
9a8fd558 CZ	61	#define PTRS_PER_PGD 1024
9a8fd558 CZ	62	#define PGD_ORDER 0
9a8fd558	63	#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
d016bf7e	64	#define FIRST_USER_ADDRESS 0UL
9a8fd558 CZ	65	#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
9a8fd558 CZ	66
6656920b CZ	67	/*
6656920b CZ	68	* Virtual memory area. We keep a distance to other memory regions to be
9a8fd558 CZ	69	* on the safe side. We also use this area for cache aliasing.
9a8fd558 CZ	70	*/
9a8fd558	71	#define VMALLOC_START 0xC0000000
3b4a49e2 CZ	72	#define VMALLOC_END 0xC7FEFFFF
3b4a49e2 CZ	73	#define TLBTEMP_BASE_1 0xC7FF0000
7128039f MF	74	#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
	75	#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
	76	#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
	77	#else
	78	#define TLBTEMP_SIZE ICACHE_WAY_SIZE
	79	#endif
9a8fd558	80
6656920b	81	/*
7711ece9 CZ	82	* For the Xtensa architecture, the PTE layout is as follows:
	83	*
	84	* 31------12 11 10-9 8-6 5-4 3-2 1-0
	85	* +-----------------------------------------+
	86	* \| \| Software \| HARDWARE \|
	87	* \| PPN \| ADW \| RI \|Attribute\|
	88	* +-----------------------------------------+
	89	* pte_none \| MBZ \| 01 \| 11 \| 00 \|
	90	* +-----------------------------------------+
	91	* present \| PPN \| 0 \| 00 \| ADW \| RI \| CA \| wx \|
	92	* +- - - - - - - - - - - - - - - - - - - - -+
	93	* (PAGE_NONE)\| PPN \| 0 \| 00 \| ADW \| 01 \| 11 \| 11 \|
	94	* +-----------------------------------------+
	95	* swap \| index \| type \| 01 \| 11 \| 00 \|
7711ece9 CZ	96	* +-----------------------------------------+
	97	*
	98	* For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
	99	* +-----------------------------------------+
	100	* present \| PPN \| 0 \| 00 \| ADW \| RI \| CA \| w1 \|
	101	* +-----------------------------------------+
	102	* (PAGE_NONE)\| PPN \| 0 \| 00 \| ADW \| 01 \| 01 \| 00 \|
	103	* +-----------------------------------------+
9a8fd558	104	*
7711ece9 CZ	105	* Legend:
	106	* PPN Physical Page Number
	107	* ADW software: accessed (young) / dirty / writable
	108	* RI ring (0=privileged, 1=user, 2 and 3 are unused)
	109	* CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
	110	* (11 is invalid and used to mark pages that are not present)
	111	* w page is writable (hw)
	112	* x page is executable (hw)
	113	* index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
	114	* (note that the index is always non-zero)
	115	* type swap type (5 bits -> 32 types)
9a8fd558	116	*
7711ece9 CZ	117	* Notes:
	118	* - (PROT_NONE) is a special case of 'present' but causes an exception for
	119	* any access (read, write, and execute).
	120	* - 'multihit-exception' has the highest priority of all MMU exceptions,
	121	* so the ring must be set to 'RING_USER' even for 'non-present' pages.
	122	* - on older hardware, the exectuable flag was not supported and
	123	* used as a 'valid' flag, so it needs to be always set.
	124	* - we need to keep track of certain flags in software (dirty and young)
	125	* to do this, we use write exceptions and have a separate software w-flag.
	126	* - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
9a8fd558 CZ	127	*/
9a8fd558 CZ	128
7711ece9 CZ	129	#define _PAGE_ATTRIB_MASK 0xf
7711ece9 CZ	130
01858d1b CZ	131	#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
	132	#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
	133
01858d1b CZ	134	#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
	135	#define _PAGE_CA_WB (1<<2) /* write-back */
	136	#define _PAGE_CA_WT (2<<2) /* write-through */
	137	#define _PAGE_CA_MASK (3<<2)
7711ece9 CZ	138	#define _PAGE_CA_INVALID (3<<2)
	139
	140	/* We use invalid attribute values to distinguish special pte entries */
	141	#if XCHAL_HW_VERSION_MAJOR < 2000
	142	#define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
	143	#define _PAGE_NONE 0x04
	144	#else
	145	#define _PAGE_HW_VALID 0x00
	146	#define _PAGE_NONE 0x0f
	147	#endif
9a8fd558 CZ	148
9a8fd558 CZ	149	#define _PAGE_USER (1<<4) /* user access (ring=1) */
9a8fd558 CZ	150
9a8fd558 CZ	151	/* Software */
01858d1b CZ	152	#define _PAGE_WRITABLE_BIT 6
01858d1b CZ	153	#define _PAGE_WRITABLE (1<<6) /* software: page writable */
9a8fd558 CZ	154	#define _PAGE_DIRTY (1<<7) /* software: page dirty */
9a8fd558 CZ	155	#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
9a8fd558	156
9a8fd558 CZ	157	#ifdef CONFIG_MMU
9a8fd558 CZ	158
7711ece9 CZ	159	#define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
	160	#define _PAGE_PRESENT (_PAGE_HW_VALID \| _PAGE_CA_WB \| _PAGE_ACCESSED)
	161
	162	#define PAGE_NONE __pgprot(_PAGE_NONE \| _PAGE_USER)
01858d1b CZ	163	#define PAGE_COPY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	164	#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	165	#define PAGE_READONLY __pgprot(_PAGE_PRESENT \| _PAGE_USER)
	166	#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_HW_EXEC)
	167	#define PAGE_SHARED __pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE)
	168	#define PAGE_SHARED_EXEC \
	169	__pgprot(_PAGE_PRESENT \| _PAGE_USER \| _PAGE_WRITABLE \| _PAGE_HW_EXEC)
6656920b CZ	170	#define PAGE_KERNEL __pgprot(_PAGE_PRESENT \| _PAGE_HW_WRITE)
6656920b CZ	171	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT\|_PAGE_HW_WRITE\|_PAGE_HW_EXEC)
01858d1b CZ	172
01858d1b CZ	173	#if (DCACHE_WAY_SIZE > PAGE_SIZE)
7711ece9	174	# define _PAGE_DIRECTORY (_PAGE_HW_VALID \| _PAGE_ACCESSED \| _PAGE_CA_BYPASS)
01858d1b	175	#else
7711ece9	176	# define _PAGE_DIRECTORY (_PAGE_HW_VALID \| _PAGE_ACCESSED \| _PAGE_CA_WB)
01858d1b	177	#endif
9a8fd558 CZ	178
	179	#else /* no mmu */
	180
972c55bf	181	# define _PAGE_CHG_MASK (PAGE_MASK \| _PAGE_ACCESSED \| _PAGE_DIRTY)
9a8fd558 CZ	182	# define PAGE_NONE __pgprot(0)
	183	# define PAGE_SHARED __pgprot(0)
	184	# define PAGE_COPY __pgprot(0)
	185	# define PAGE_READONLY __pgprot(0)
	186	# define PAGE_KERNEL __pgprot(0)
	187
	188	#endif
	189
	190	/*
	191	* On certain configurations of Xtensa MMUs (eg. the initial Linux config),
	192	* the MMU can't do page protection for execute, and considers that the same as
	193	* read. Also, write permissions may imply read permissions.
	194	* What follows is the closest we can get by reasonable means..
	195	* See linux/mm/mmap.c for protection_map[] array that uses these definitions.
	196	*/
01858d1b CZ	197	#define __P000 PAGE_NONE /* private --- */
	198	#define __P001 PAGE_READONLY /* private --r */
	199	#define __P010 PAGE_COPY /* private -w- */
	200	#define __P011 PAGE_COPY /* private -wr */
	201	#define __P100 PAGE_READONLY_EXEC /* private x-- */
	202	#define __P101 PAGE_READONLY_EXEC /* private x-r */
	203	#define __P110 PAGE_COPY_EXEC /* private xw- */
	204	#define __P111 PAGE_COPY_EXEC /* private xwr */
	205
	206	#define __S000 PAGE_NONE /* shared --- */
	207	#define __S001 PAGE_READONLY /* shared --r */
	208	#define __S010 PAGE_SHARED /* shared -w- */
	209	#define __S011 PAGE_SHARED /* shared -wr */
	210	#define __S100 PAGE_READONLY_EXEC /* shared x-- */
	211	#define __S101 PAGE_READONLY_EXEC /* shared x-r */
	212	#define __S110 PAGE_SHARED_EXEC /* shared xw- */
	213	#define __S111 PAGE_SHARED_EXEC /* shared xwr */
9a8fd558 CZ	214
	215	#ifndef __ASSEMBLY__
	216
	217	#define pte_ERROR(e) \
	218	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
	219	#define pgd_ERROR(e) \
	220	printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	221
	222	extern unsigned long empty_zero_page[1024];
	223
	224	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
	225
e5083a63	226	#ifdef CONFIG_MMU
9a8fd558	227	extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
e5083a63	228	extern void paging_init(void);
e5083a63 JW	229	#else
	230	# define swapper_pg_dir NULL
	231	static inline void paging_init(void) { }
e5083a63	232	#endif
f820e280	233	static inline void pgtable_cache_init(void) { }
9a8fd558 CZ	234
	235	/*
	236	* The pmd contains the kernel virtual address of the pte page.
	237	*/
46a82b2d	238	#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
9a8fd558 CZ	239	#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
	240
	241	/*
01858d1b	242	* pte status.
9a8fd558	243	*/
7711ece9 CZ	244	# define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID \| _PAGE_USER))
	245	#if XCHAL_HW_VERSION_MAJOR < 2000
	246	# define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
	247	#else
	248	# define pte_present(pte) \
	249	(((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
	250	\|\| ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
	251	#endif
9a8fd558	252	#define pte_clear(mm,addr,ptep) \
7711ece9	253	do { update_pte(ptep, __pte(_PAGE_CA_INVALID \| _PAGE_USER)); } while (0)
9a8fd558 CZ	254
	255	#define pmd_none(pmd) (!pmd_val(pmd))
	256	#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
9a8fd558	257	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
01858d1b	258	#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
9a8fd558	259
01858d1b	260	static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
9a8fd558 CZ	261	static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
9a8fd558 CZ	262	static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
7e675137 NP	263	static inline int pte_special(pte_t pte) { return 0; }
7e675137 NP	264
01858d1b CZ	265	static inline pte_t pte_wrprotect(pte_t pte)
	266	{ pte_val(pte) &= ~(_PAGE_WRITABLE \| _PAGE_HW_WRITE); return pte; }
	267	static inline pte_t pte_mkclean(pte_t pte)
	268	{ pte_val(pte) &= ~(_PAGE_DIRTY \| _PAGE_HW_WRITE); return pte; }
	269	static inline pte_t pte_mkold(pte_t pte)
	270	{ pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
	271	static inline pte_t pte_mkdirty(pte_t pte)
	272	{ pte_val(pte) \|= _PAGE_DIRTY; return pte; }
	273	static inline pte_t pte_mkyoung(pte_t pte)
	274	{ pte_val(pte) \|= _PAGE_ACCESSED; return pte; }
	275	static inline pte_t pte_mkwrite(pte_t pte)
	276	{ pte_val(pte) \|= _PAGE_WRITABLE; return pte; }
7e675137 NP	277	static inline pte_t pte_mkspecial(pte_t pte)
7e675137 NP	278	{ return pte; }
9a8fd558	279
a211276a MF	280	#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
a211276a MF	281
9a8fd558 CZ	282	/*
	283	* Conversion functions: convert a page and protection to a page entry,
	284	* and a page entry and page directory to the page they refer to.
	285	*/
01858d1b	286
9a8fd558 CZ	287	#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
	288	#define pte_same(a,b) (pte_val(a) == pte_val(b))
	289	#define pte_page(x) pfn_to_page(pte_pfn(x))
	290	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	291	#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
	292
d99cf715	293	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
9a8fd558 CZ	294	{
	295	return __pte((pte_val(pte) & _PAGE_CHG_MASK) \| pgprot_val(newprot));
	296	}
	297
	298	/*
	299	* Certain architectures need to do special things when pte's
	300	* within a page table are directly modified. Thus, the following
	301	* hook is made available.
	302	*/
	303	static inline void update_pte(pte_t *ptep, pte_t pteval)
	304	{
	305	*ptep = pteval;
6656920b CZ	306	#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
	307	__asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
	308	#endif
	309
9a8fd558 CZ	310	}
9a8fd558 CZ	311
8c65b4a6 TS	312	struct mm_struct;
8c65b4a6 TS	313
d99cf715	314	static inline void
9a8fd558 CZ	315	set_pte_at(struct mm_struct mm, unsigned long addr, pte_t ptep, pte_t pteval)
	316	{
	317	update_pte(ptep, pteval);
	318	}
	319
65559100 MF	320	static inline void set_pte(pte_t *ptep, pte_t pteval)
	321	{
	322	update_pte(ptep, pteval);
	323	}
9a8fd558	324
d99cf715	325	static inline void
9a8fd558 CZ	326	set_pmd(pmd_t *pmdp, pmd_t pmdval)
	327	{
	328	*pmdp = pmdval;
9a8fd558 CZ	329	}
9a8fd558 CZ	330
8c65b4a6	331	struct vm_area_struct;
9a8fd558 CZ	332
	333	static inline int
	334	ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
c4c4594b	335	pte_t *ptep)
9a8fd558 CZ	336	{
	337	pte_t pte = *ptep;
	338	if (!pte_young(pte))
	339	return 0;
	340	update_pte(ptep, pte_mkold(pte));
	341	return 1;
	342	}
	343
9a8fd558 CZ	344	static inline pte_t
	345	ptep_get_and_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	346	{
	347	pte_t pte = *ptep;
	348	pte_clear(mm, addr, ptep);
	349	return pte;
	350	}
	351
	352	static inline void
	353	ptep_set_wrprotect(struct mm_struct mm, unsigned long addr, pte_t ptep)
	354	{
c4c4594b CZ	355	pte_t pte = *ptep;
c4c4594b CZ	356	update_pte(ptep, pte_wrprotect(pte));
9a8fd558 CZ	357	}
	358
	359	/* to find an entry in a kernel page-table-directory */
	360	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	361
	362	/* to find an entry in a page-table-directory */
	363	#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
	364
	365	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	366
	367	/* Find an entry in the second-level page table.. */
	368	#define pmd_offset(dir,address) ((pmd_t*)(dir))
	369
	370	/* Find an entry in the third-level page table.. */
	371	#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	372	#define pte_offset_kernel(dir,addr) \
46a82b2d	373	((pte_t) pmd_page_vaddr((dir)) + pte_index(addr))
9a8fd558	374	#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
9a8fd558	375	#define pte_unmap(pte) do { } while (0)
9a8fd558 CZ	376
	377
	378	/*
7711ece9	379	* Encode and decode a swap and file entry.
9a8fd558	380	*/
7711ece9 CZ	381	#define SWP_TYPE_BITS 5
7711ece9 CZ	382	#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
9a8fd558	383
01858d1b CZ	384	#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
	385	#define __swp_offset(entry) ((entry).val >> 11)
	386	#define __swp_entry(type,offs) \
7711ece9 CZ	387	((swp_entry_t){((type) << 6) \| ((offs) << 11) \| \
7711ece9 CZ	388	_PAGE_CA_INVALID \| _PAGE_USER})
9a8fd558 CZ	389	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	390	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	391
9a8fd558 CZ	392	#endif /* !defined (__ASSEMBLY__) */
	393
	394
	395	#ifdef __ASSEMBLY__
	396
	397	/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
	398	* _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
	399	* _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
	400	* _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
	401	*
	402	* Note: We require an additional temporary register which can be the same as
	403	* the register that holds the address.
	404	*
	405	* ((pte_t) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) + pte_index(addr))
	406	*
	407	*/
	408	#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
	409	#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
	410
	411	#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
	412	_PGD_INDEX(tmp, adr); \
	413	addx4 mm, tmp, mm
	414
	415	#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
	416	srli pmd, pmd, PAGE_SHIFT; \
	417	slli pmd, pmd, PAGE_SHIFT; \
	418	addx4 pmd, tmp, pmd
	419
	420	#else
	421
9a8fd558 CZ	422	#define kern_addr_valid(addr) (1)
	423
	424	extern void update_mmu_cache(struct vm_area_struct * vma,
4b3073e1	425	unsigned long address, pte_t *ptep);
9a8fd558	426
9a8fd558 CZ	427	typedef pte_t *pte_addr_t;
	428
	429	#endif /* !defined (__ASSEMBLY__) */
	430
	431	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
9a8fd558 CZ	432	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	433	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	434	#define __HAVE_ARCH_PTEP_MKDIRTY
	435	#define __HAVE_ARCH_PTE_SAME
de73b6b1 MF	436	/* We provide our own get_unmapped_area to cope with
	437	* SHM area cache aliasing for userland.
	438	*/
	439	#define HAVE_ARCH_UNMAPPED_AREA
9a8fd558 CZ	440
	441	#include <asm-generic/pgtable.h>
	442
	443	#endif /* _XTENSA_PGTABLE_H */