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9a8fd558 | 1 | /* |
9a8fd558 CZ |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
2d1c645c | 6 | * Copyright (C) 2001 - 2008 Tensilica Inc. |
38fef73c | 7 | * Copyright (C) 2015 Cadence Design Systems Inc. |
9a8fd558 CZ |
8 | */ |
9 | ||
10 | #ifndef _XTENSA_PROCESSOR_H | |
11 | #define _XTENSA_PROCESSOR_H | |
12 | ||
367b8112 | 13 | #include <variant/core.h> |
e5083a63 | 14 | #include <platform/hardware.h> |
9a8fd558 | 15 | |
f6dc8c5b | 16 | #include <linux/compiler.h> |
9a8fd558 CZ |
17 | #include <asm/ptrace.h> |
18 | #include <asm/types.h> | |
173d6681 | 19 | #include <asm/regs.h> |
9a8fd558 CZ |
20 | |
21 | /* Assertions. */ | |
22 | ||
23 | #if (XCHAL_HAVE_WINDOWED != 1) | |
173d6681 | 24 | # error Linux requires the Xtensa Windowed Registers Option. |
9a8fd558 CZ |
25 | #endif |
26 | ||
a81cbd2d OS |
27 | #define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH |
28 | ||
9a8fd558 CZ |
29 | /* |
30 | * User space process size: 1 GB. | |
31 | * Windowed call ABI requires caller and callee to be located within the same | |
32 | * 1 GB region. The C compiler places trampoline code on the stack for sources | |
33 | * that take the address of a nested C function (a feature used by glibc), so | |
34 | * the 1 GB requirement applies to the stack as well. | |
35 | */ | |
36 | ||
e5083a63 | 37 | #ifdef CONFIG_MMU |
24a9ab7f | 38 | #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) |
e5083a63 JW |
39 | #else |
40 | #define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE) | |
41 | #endif | |
42 | ||
922a70d3 DH |
43 | #define STACK_TOP TASK_SIZE |
44 | #define STACK_TOP_MAX STACK_TOP | |
9a8fd558 | 45 | |
38fef73c MF |
46 | /* |
47 | * General exception cause assigned to fake NMI. Fake NMI needs to be handled | |
48 | * differently from other interrupts, but it uses common kernel entry/exit | |
49 | * code. | |
50 | */ | |
51 | ||
52 | #define EXCCAUSE_MAPPED_NMI 62 | |
53 | ||
9a8fd558 CZ |
54 | /* |
55 | * General exception cause assigned to debug exceptions. Debug exceptions go | |
56 | * to their own vector, rather than the general exception vectors (user, | |
57 | * kernel, double); and their specific causes are reported via DEBUGCAUSE | |
58 | * rather than EXCCAUSE. However it is sometimes convenient to redirect debug | |
59 | * exceptions to the general exception mechanism. To do this, an otherwise | |
60 | * unused EXCCAUSE value was assigned to debug exceptions for this purpose. | |
61 | */ | |
62 | ||
63 | #define EXCCAUSE_MAPPED_DEBUG 63 | |
64 | ||
65 | /* | |
66 | * We use DEPC also as a flag to distinguish between double and regular | |
67 | * exceptions. For performance reasons, DEPC might contain the value of | |
68 | * EXCCAUSE for regular exceptions, so we use this definition to mark a | |
69 | * valid double exception address. | |
70 | * (Note: We use it in bgeui, so it should be 64, 128, or 256) | |
71 | */ | |
72 | ||
73 | #define VALID_DOUBLE_EXCEPTION_ADDRESS 64 | |
74 | ||
38fef73c MF |
75 | #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno) |
76 | #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL | |
77 | ||
78 | #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) | |
79 | #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) | |
80 | ||
81 | #define IS_POW2(v) (((v) & ((v) - 1)) == 0) | |
82 | ||
83 | #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) | |
84 | ||
9a8fd558 CZ |
85 | /* LOCKLEVEL defines the interrupt level that masks all |
86 | * general-purpose interrupts. | |
87 | */ | |
38fef73c MF |
88 | #if defined(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) && \ |
89 | defined(XCHAL_PROFILING_INTERRUPT) && \ | |
90 | PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \ | |
91 | XCHAL_EXCM_LEVEL > 1 && \ | |
92 | IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL)) | |
93 | #define LOCKLEVEL (XCHAL_EXCM_LEVEL - 1) | |
94 | #else | |
2d1c645c | 95 | #define LOCKLEVEL XCHAL_EXCM_LEVEL |
38fef73c MF |
96 | #endif |
97 | #define TOPLEVEL XCHAL_EXCM_LEVEL | |
98 | #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) | |
9a8fd558 CZ |
99 | |
100 | /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE | |
101 | * registers | |
102 | */ | |
103 | #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */ | |
104 | #define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */ | |
105 | ||
106 | #ifndef __ASSEMBLY__ | |
107 | ||
108 | /* Build a valid return address for the specified call winsize. | |
109 | * winsize must be 1 (call4), 2 (call8), or 3 (call12) | |
110 | */ | |
111 | #define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30) | |
112 | ||
113 | /* Convert return address to a valid pc | |
114 | * Note: We assume that the stack pointer is in the same 1GB ranges as the ra | |
115 | */ | |
116 | #define MAKE_PC_FROM_RA(ra,sp) (((ra) & 0x3fffffff) | ((sp) & 0xc0000000)) | |
117 | ||
118 | typedef struct { | |
c4c4594b | 119 | unsigned long seg; |
9a8fd558 CZ |
120 | } mm_segment_t; |
121 | ||
122 | struct thread_struct { | |
123 | ||
124 | /* kernel's return address and stack pointer for context switching */ | |
125 | unsigned long ra; /* kernel's a0: return address and window call size */ | |
126 | unsigned long sp; /* kernel's a1: stack pointer */ | |
127 | ||
128 | mm_segment_t current_ds; /* see uaccess.h for example uses */ | |
129 | ||
130 | /* struct xtensa_cpuinfo info; */ | |
131 | ||
132 | unsigned long bad_vaddr; /* last user fault */ | |
133 | unsigned long bad_uaddr; /* last kernel fault accessing user space */ | |
134 | unsigned long error_code; | |
135 | ||
136 | unsigned long ibreak[XCHAL_NUM_IBREAK]; | |
137 | unsigned long dbreaka[XCHAL_NUM_DBREAK]; | |
138 | unsigned long dbreakc[XCHAL_NUM_DBREAK]; | |
139 | ||
9a8fd558 CZ |
140 | /* Make structure 16 bytes aligned. */ |
141 | int align[0] __attribute__ ((aligned(16))); | |
142 | }; | |
143 | ||
144 | ||
145 | /* | |
146 | * Default implementation of macro that returns current | |
147 | * instruction pointer ("program counter"). | |
148 | */ | |
149 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | |
150 | ||
151 | ||
152 | /* This decides where the kernel will search for a free chunk of vm | |
153 | * space during mmap's. | |
154 | */ | |
155 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) | |
156 | ||
157 | #define INIT_THREAD \ | |
158 | { \ | |
159 | ra: 0, \ | |
160 | sp: sizeof(init_stack) + (long) &init_stack, \ | |
161 | current_ds: {0}, \ | |
162 | /*info: {0}, */ \ | |
163 | bad_vaddr: 0, \ | |
164 | bad_uaddr: 0, \ | |
165 | error_code: 0, \ | |
166 | } | |
167 | ||
168 | ||
169 | /* | |
170 | * Do necessary setup to start up a newly executed thread. | |
171 | * Note: We set-up ps as if we did a call4 to the new pc. | |
172 | * set_thread_state in signal.c depends on it. | |
173 | */ | |
173d6681 | 174 | #define USER_PS_VALUE ((1 << PS_WOE_BIT) | \ |
c4c4594b CZ |
175 | (1 << PS_CALLINC_SHIFT) | \ |
176 | (USER_RING << PS_RING_SHIFT) | \ | |
177 | (1 << PS_UM_BIT) | \ | |
178 | (1 << PS_EXCM_BIT)) | |
9a8fd558 CZ |
179 | |
180 | /* Clearing a0 terminates the backtrace. */ | |
181 | #define start_thread(regs, new_pc, new_sp) \ | |
3306a726 | 182 | memset(regs, 0, sizeof(*regs)); \ |
9a8fd558 CZ |
183 | regs->pc = new_pc; \ |
184 | regs->ps = USER_PS_VALUE; \ | |
185 | regs->areg[1] = new_sp; \ | |
186 | regs->areg[0] = 0; \ | |
187 | regs->wmask = 1; \ | |
188 | regs->depc = 0; \ | |
189 | regs->windowbase = 0; \ | |
190 | regs->windowstart = 1; | |
191 | ||
192 | /* Forward declaration */ | |
193 | struct task_struct; | |
194 | struct mm_struct; | |
195 | ||
9a8fd558 CZ |
196 | /* Free all resources held by a thread. */ |
197 | #define release_thread(thread) do { } while(0) | |
198 | ||
9a8fd558 | 199 | /* Copy and release all segment info associated with a VM */ |
9a8fd558 CZ |
200 | #define copy_segments(p, mm) do { } while(0) |
201 | #define release_segments(mm) do { } while(0) | |
202 | #define forget_segments() do { } while (0) | |
203 | ||
04fe6faf | 204 | #define thread_saved_pc(tsk) (task_pt_regs(tsk)->pc) |
9a8fd558 CZ |
205 | |
206 | extern unsigned long get_wchan(struct task_struct *p); | |
207 | ||
04fe6faf AV |
208 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) |
209 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1]) | |
9a8fd558 | 210 | |
f6dc8c5b | 211 | #define cpu_relax() barrier() |
3a6bfbc9 | 212 | #define cpu_relax_lowlatency() cpu_relax() |
9a8fd558 CZ |
213 | |
214 | /* Special register access. */ | |
215 | ||
216 | #define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v)); | |
217 | #define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v)); | |
218 | ||
219 | #define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);}) | |
220 | #define get_sr(sr) ({unsigned int v; RSR(v,sr); v; }) | |
221 | ||
26a8e96a MF |
222 | #ifndef XCHAL_HAVE_EXTERN_REGS |
223 | #define XCHAL_HAVE_EXTERN_REGS 0 | |
224 | #endif | |
225 | ||
226 | #if XCHAL_HAVE_EXTERN_REGS | |
227 | ||
228 | static inline void set_er(unsigned long value, unsigned long addr) | |
229 | { | |
230 | asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory"); | |
231 | } | |
232 | ||
233 | static inline unsigned long get_er(unsigned long addr) | |
234 | { | |
235 | register unsigned long value; | |
236 | asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory"); | |
237 | return value; | |
238 | } | |
239 | ||
240 | #endif /* XCHAL_HAVE_EXTERN_REGS */ | |
241 | ||
9a8fd558 CZ |
242 | #endif /* __ASSEMBLY__ */ |
243 | #endif /* _XTENSA_PROCESSOR_H */ |