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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
5a0015d6 | 2 | /* |
f30c2269 | 3 | * arch/xtensa/kernel/pci.c |
5a0015d6 CZ |
4 | * |
5 | * PCI bios-type initialisation for PCI machines | |
6 | * | |
5a0015d6 CZ |
7 | * Copyright (C) 2001-2005 Tensilica Inc. |
8 | * | |
9 | * Based largely on work from Cort (ppc/kernel/pci.c) | |
10 | * IO functions copied from sparc. | |
11 | * | |
12 | * Chris Zankel <chris@zankel.net> | |
5a0015d6 CZ |
13 | */ |
14 | ||
5a0015d6 CZ |
15 | #include <linux/kernel.h> |
16 | #include <linux/pci.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/errno.h> | |
57c8a661 | 22 | #include <linux/memblock.h> |
5a0015d6 CZ |
23 | |
24 | #include <asm/pci-bridge.h> | |
25 | #include <asm/platform.h> | |
26 | ||
5a0015d6 CZ |
27 | /* PCI Controller */ |
28 | ||
29 | ||
30 | /* | |
31 | * pcibios_alloc_controller | |
32 | * pcibios_enable_device | |
33 | * pcibios_fixups | |
34 | * pcibios_align_resource | |
35 | * pcibios_fixup_bus | |
5a0015d6 | 36 | * pci_bus_add_device |
5a0015d6 CZ |
37 | */ |
38 | ||
f242132b BH |
39 | static struct pci_controller *pci_ctrl_head; |
40 | static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head; | |
5a0015d6 CZ |
41 | |
42 | static int pci_bus_count; | |
43 | ||
5a0015d6 CZ |
44 | /* |
45 | * We need to avoid collisions with `mirrored' VGA ports | |
46 | * and other strange ISA hardware, so we always want the | |
47 | * addresses to be allocated in the 0x000-0x0ff region | |
48 | * modulo 0x400. | |
49 | * | |
50 | * Why? Because some silly external IO cards only decode | |
51 | * the low 10 bits of the IO address. The 0x00-0xff region | |
52 | * is reserved for motherboard devices that decode all 16 | |
53 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
54 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
55 | * which might have be mirrored at 0x0100-0x03ff.. | |
56 | */ | |
b26b2d49 | 57 | resource_size_t |
3b7a17fc DB |
58 | pcibios_align_resource(void *data, const struct resource *res, |
59 | resource_size_t size, resource_size_t align) | |
5a0015d6 CZ |
60 | { |
61 | struct pci_dev *dev = data; | |
b26b2d49 | 62 | resource_size_t start = res->start; |
5a0015d6 CZ |
63 | |
64 | if (res->flags & IORESOURCE_IO) { | |
5a0015d6 | 65 | if (size > 0x100) { |
fd95ee73 MF |
66 | pr_err("PCI: I/O Region %s/%d too large (%u bytes)\n", |
67 | pci_name(dev), dev->resource - res, | |
68 | size); | |
5a0015d6 CZ |
69 | } |
70 | ||
b26b2d49 | 71 | if (start & 0x300) |
5a0015d6 | 72 | start = (start + 0x3ff) & ~0x3ff; |
5a0015d6 | 73 | } |
b26b2d49 DB |
74 | |
75 | return start; | |
5a0015d6 CZ |
76 | } |
77 | ||
7ec303a7 BH |
78 | static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, |
79 | struct list_head *resources) | |
80 | { | |
81 | struct resource *res; | |
82 | unsigned long io_offset; | |
83 | int i; | |
84 | ||
85 | io_offset = (unsigned long)pci_ctrl->io_space.base; | |
86 | res = &pci_ctrl->io_resource; | |
87 | if (!res->flags) { | |
88 | if (io_offset) | |
c130d3be MF |
89 | pr_err("I/O resource not set for host bridge %d\n", |
90 | pci_ctrl->index); | |
7ec303a7 BH |
91 | res->start = 0; |
92 | res->end = IO_SPACE_LIMIT; | |
93 | res->flags = IORESOURCE_IO; | |
94 | } | |
95 | res->start += io_offset; | |
96 | res->end += io_offset; | |
4ba2aef3 | 97 | pci_add_resource_offset(resources, res, io_offset); |
7ec303a7 BH |
98 | |
99 | for (i = 0; i < 3; i++) { | |
100 | res = &pci_ctrl->mem_resources[i]; | |
101 | if (!res->flags) { | |
102 | if (i > 0) | |
103 | continue; | |
c130d3be MF |
104 | pr_err("Memory resource not set for host bridge %d\n", |
105 | pci_ctrl->index); | |
7ec303a7 BH |
106 | res->start = 0; |
107 | res->end = ~0U; | |
108 | res->flags = IORESOURCE_MEM; | |
109 | } | |
110 | pci_add_resource(resources, res); | |
111 | } | |
112 | } | |
113 | ||
5a0015d6 CZ |
114 | static int __init pcibios_init(void) |
115 | { | |
116 | struct pci_controller *pci_ctrl; | |
7ec303a7 | 117 | struct list_head resources; |
5a0015d6 | 118 | struct pci_bus *bus; |
b97ea289 | 119 | int next_busno = 0, ret; |
5a0015d6 | 120 | |
c130d3be | 121 | pr_info("PCI: Probing PCI hardware\n"); |
5a0015d6 CZ |
122 | |
123 | /* Scan all of the recorded PCI controllers. */ | |
124 | for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { | |
125 | pci_ctrl->last_busno = 0xff; | |
7ec303a7 BH |
126 | INIT_LIST_HEAD(&resources); |
127 | pci_controller_apertures(pci_ctrl, &resources); | |
128 | bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, | |
129 | pci_ctrl->ops, pci_ctrl, &resources); | |
b97ea289 YW |
130 | if (!bus) |
131 | continue; | |
132 | ||
5a0015d6 | 133 | pci_ctrl->bus = bus; |
b918c62e | 134 | pci_ctrl->last_busno = bus->busn_res.end; |
5a0015d6 CZ |
135 | if (next_busno <= pci_ctrl->last_busno) |
136 | next_busno = pci_ctrl->last_busno+1; | |
137 | } | |
138 | pci_bus_count = next_busno; | |
b97ea289 YW |
139 | ret = platform_pcibios_fixup(); |
140 | if (ret) | |
141 | return ret; | |
5a0015d6 | 142 | |
b97ea289 YW |
143 | for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { |
144 | if (pci_ctrl->bus) | |
145 | pci_bus_add_devices(pci_ctrl->bus); | |
146 | } | |
147 | ||
148 | return 0; | |
5a0015d6 CZ |
149 | } |
150 | ||
151 | subsys_initcall(pcibios_init); | |
152 | ||
fd95ee73 | 153 | void pcibios_fixup_bus(struct pci_bus *bus) |
5a0015d6 | 154 | { |
237865f1 BH |
155 | if (bus->parent) { |
156 | /* This is a subordinate bridge */ | |
157 | pci_read_bridge_bases(bus); | |
158 | } | |
5a0015d6 CZ |
159 | } |
160 | ||
9cdce18d MS |
161 | void pcibios_set_master(struct pci_dev *dev) |
162 | { | |
163 | /* No special bus mastering setup handling */ | |
164 | } | |
165 | ||
5a0015d6 CZ |
166 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
167 | { | |
168 | u16 cmd, old_cmd; | |
169 | int idx; | |
170 | struct resource *r; | |
171 | ||
172 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
173 | old_cmd = cmd; | |
174 | for (idx=0; idx<6; idx++) { | |
175 | r = &dev->resource[idx]; | |
176 | if (!r->start && r->end) { | |
78f7aada | 177 | pci_err(dev, "can't enable device: resource collisions\n"); |
5a0015d6 CZ |
178 | return -EINVAL; |
179 | } | |
180 | if (r->flags & IORESOURCE_IO) | |
181 | cmd |= PCI_COMMAND_IO; | |
182 | if (r->flags & IORESOURCE_MEM) | |
183 | cmd |= PCI_COMMAND_MEMORY; | |
184 | } | |
185 | if (cmd != old_cmd) { | |
78f7aada | 186 | pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); |
5a0015d6 CZ |
187 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
188 | } | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
5a0015d6 | 193 | /* |
46e15a2a | 194 | * Platform support for /proc/bus/pci/X/Y mmap()s. |
5a0015d6 CZ |
195 | * -- paulus. |
196 | */ | |
197 | ||
46e15a2a | 198 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) |
5a0015d6 | 199 | { |
46e15a2a DW |
200 | struct pci_controller *pci_ctrl = (struct pci_controller*) pdev->sysdata; |
201 | resource_size_t ioaddr = pci_resource_start(pdev, bar); | |
5a0015d6 CZ |
202 | |
203 | if (pci_ctrl == 0) | |
204 | return -EINVAL; /* should never happen */ | |
205 | ||
46e15a2a DW |
206 | /* Convert to an offset within this PCI controller */ |
207 | ioaddr -= (unsigned long)pci_ctrl->io_space.base; | |
5a0015d6 | 208 | |
46e15a2a DW |
209 | vma->vm_pgoff += (ioaddr + pci_ctrl->io_space.start) >> PAGE_SHIFT; |
210 | return 0; | |
5a0015d6 | 211 | } |