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xtensa: keep sysmem banks ordered in mem_reserve
[mirror_ubuntu-artful-kernel.git] / arch / xtensa / kernel / setup.c
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5a0015d6 1/*
f30c2269 2 * arch/xtensa/kernel/setup.c
5a0015d6
CZ		 3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 *
11 * Chris Zankel <chris@zankel.net>
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
13 * Kevin Chea
14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15 */
16
5a0015d6
CZ		 17#include <linux/errno.h>
18#include <linux/init.h>
27ac792c 19#include <linux/mm.h>
5a0015d6 20#include <linux/proc_fs.h>
894673ee 21#include <linux/screen_info.h>
5a0015d6
CZ		 22#include <linux/bootmem.h>
23#include <linux/kernel.h>
f615136c 24#include <linux/percpu.h>
bda8932d 25#include <linux/clk-provider.h>
f615136c 26#include <linux/cpu.h>
da844a81
MF		 27#include <linux/of_fdt.h>
28#include <linux/of_platform.h>
da844a81 29
5a0015d6
CZ		 30#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31# include <linux/console.h>
32#endif
33
34#ifdef CONFIG_RTC
35# include <linux/timex.h>
36#endif
37
38#ifdef CONFIG_PROC_FS
39# include <linux/seq_file.h>
40#endif
41
5a0015d6 42#include <asm/bootparam.h>
c8f3a7dc 43#include <asm/mmu_context.h>
5a0015d6
CZ		 44#include <asm/pgtable.h>
45#include <asm/processor.h>
46#include <asm/timex.h>
47#include <asm/platform.h>
48#include <asm/page.h>
49#include <asm/setup.h>
de4f6e5b 50#include <asm/param.h>
00273125 51#include <asm/traps.h>
f615136c 52#include <asm/smp.h>
9ba067f9 53#include <asm/sysmem.h>
5a0015d6 54
5a891ed5
AD		 55#include <platform/hardware.h>
56
5a0015d6
CZ		 57#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
59#endif
60
61#ifdef CONFIG_BLK_DEV_FD
62extern struct fd_ops no_fd_ops;
63struct fd_ops *fd_ops;
64#endif
65
5a0015d6
CZ		 66extern struct rtc_ops no_rtc_ops;
67struct rtc_ops *rtc_ops;
68
5a0015d6 69#ifdef CONFIG_BLK_DEV_INITRD
29eb45a9
RH		 70extern unsigned long initrd_start;
71extern unsigned long initrd_end;
5a0015d6
CZ		 72int initrd_is_mapped = 0;
73extern int initrd_below_start_ok;
74#endif
75
da844a81
MF		 76#ifdef CONFIG_OF
77extern u32 __dtb_start[];
78void *dtb_start = __dtb_start;
79#endif
80
5a0015d6
CZ		 81unsigned char aux_device_present;
82extern unsigned long loops_per_jiffy;
83
84/* Command line specified as configuration option. */
85
d3e9ccea 86static char __initdata command_line[COMMAND_LINE_SIZE];
5a0015d6
CZ		 87
88#ifdef CONFIG_CMDLINE_BOOL
89static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
90#endif
91
5a0015d6
CZ		 92/*
93 * Boot parameter parsing.
94 *
95 * The Xtensa port uses a list of variable-sized tags to pass data to
96 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
97 * to be recognised. The list is terminated with a zero-sized
98 * BP_TAG_LAST tag.
99 */
100
101typedef struct tagtable {
102 u32 tag;
103 int (*parse)(const bp_tag_t*);
104} tagtable_t;
105
106#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
f4349b6e 107 __attribute__((used, section(".taglist"))) = { tag, fn }
5a0015d6
CZ		 108
109/* parse current tag */
110
da844a81
MF		 111static int __init parse_tag_mem(const bp_tag_t *tag)
112{
9ba067f9 113 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
da844a81
MF		 114
115 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
116 return -1;
117
9ba067f9 118 return add_sysmem_bank(mi->start, mi->end);
da844a81
MF		 119}
120
5a0015d6
CZ		 121__tagtable(BP_TAG_MEMORY, parse_tag_mem);
122
123#ifdef CONFIG_BLK_DEV_INITRD
124
125static int __init parse_tag_initrd(const bp_tag_t* tag)
126{
9ba067f9
MF		 127 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
128
29eb45a9
RH		 129 initrd_start = (unsigned long)__va(mi->start);
130 initrd_end = (unsigned long)__va(mi->end);
5a0015d6
CZ		 131
132 return 0;
133}
134
135__tagtable(BP_TAG_INITRD, parse_tag_initrd);
136
da844a81
MF		 137#ifdef CONFIG_OF
138
139static int __init parse_tag_fdt(const bp_tag_t *tag)
140{
c5a771d0 141 dtb_start = __va(tag->data[0]);
da844a81
MF		 142 return 0;
143}
144
145__tagtable(BP_TAG_FDT, parse_tag_fdt);
146
da844a81
MF		 147#endif /* CONFIG_OF */
148
5a0015d6
CZ		 149#endif /* CONFIG_BLK_DEV_INITRD */
150
151static int __init parse_tag_cmdline(const bp_tag_t* tag)
152{
da844a81 153 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
5a0015d6
CZ		 154 return 0;
155}
156
157__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
158
159static int __init parse_bootparam(const bp_tag_t* tag)
160{
161 extern tagtable_t __tagtable_begin, __tagtable_end;
162 tagtable_t *t;
163
164 /* Boot parameters must start with a BP_TAG_FIRST tag. */
165
166 if (tag->id != BP_TAG_FIRST) {
167 printk(KERN_WARNING "Invalid boot parameters!\n");
168 return 0;
169 }
170
171 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
172
173 /* Parse all tags. */
174
175 while (tag != NULL && tag->id != BP_TAG_LAST) {
176 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
177 if (tag->id == t->tag) {
178 t->parse(tag);
179 break;
180 }
181 }
182 if (t == &__tagtable_end)
183 printk(KERN_WARNING "Ignoring tag "
184 "0x%08x\n", tag->id);
185 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
186 }
187
188 return 0;
189}
190
da844a81 191#ifdef CONFIG_OF
7745fc1f 192bool __initdata dt_memory_scan = false;
da844a81 193
6cb97111
BS		 194#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
195unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
196EXPORT_SYMBOL(xtensa_kio_paddr);
197
198static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
199 int depth, void *data)
200{
201 const __be32 *ranges;
202 unsigned long len;
203
204 if (depth > 1)
205 return 0;
206
207 if (!of_flat_dt_is_compatible(node, "simple-bus"))
208 return 0;
209
210 ranges = of_get_flat_dt_prop(node, "ranges", &len);
211 if (!ranges)
212 return 1;
213 if (len == 0)
214 return 1;
215
216 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
217 /* round down to nearest 256MB boundary */
218 xtensa_kio_paddr &= 0xf0000000;
219
220 return 1;
221}
222#else
223static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
224 int depth, void *data)
225{
226 return 1;
227}
228#endif
229
da844a81
MF		 230void __init early_init_dt_add_memory_arch(u64 base, u64 size)
231{
7745fc1f
RH		 232 if (!dt_memory_scan)
233 return;
234
da844a81 235 size &= PAGE_MASK;
9ba067f9 236 add_sysmem_bank(base, base + size);
da844a81
MF		 237}
238
239void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
240{
241 return __alloc_bootmem(size, align, 0);
242}
243
244void __init early_init_devtree(void *params)
245{
7745fc1f
RH		 246 if (sysmem.nr_banks == 0)
247 dt_memory_scan = true;
da844a81 248
7745fc1f 249 early_init_dt_scan(params);
6cb97111 250 of_scan_flat_dt(xtensa_dt_io_area, NULL);
da844a81 251
7745fc1f
RH		 252 if (!command_line[0])
253 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
da844a81
MF		 254}
255
da844a81
MF		 256static int __init xtensa_device_probe(void)
257{
bda8932d 258 of_clk_init(NULL);
f8935f30 259 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
da844a81
MF		 260 return 0;
261}
262
263device_initcall(xtensa_device_probe);
264
265#endif /* CONFIG_OF */
266
5a0015d6
CZ		 267/*
268 * Initialize architecture. (Early stage)
269 */
270
271void __init init_arch(bp_tag_t *bp_start)
272{
5a0015d6
CZ		 273 /* Parse boot parameters */
274
c4c4594b 275 if (bp_start)
da844a81
MF		 276 parse_bootparam(bp_start);
277
278#ifdef CONFIG_OF
279 early_init_devtree(dtb_start);
280#endif
5a0015d6
CZ		 281
282 if (sysmem.nr_banks == 0) {
9ba067f9
MF		 283 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
284 PLATFORM_DEFAULT_MEM_START +
285 PLATFORM_DEFAULT_MEM_SIZE);
5a0015d6
CZ		 286 }
287
da844a81
MF		 288#ifdef CONFIG_CMDLINE_BOOL
289 if (!command_line[0])
290 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
291#endif
292
5a0015d6
CZ		 293 /* Early hook for platforms */
294
295 platform_init(bp_start);
296
297 /* Initialize MMU. */
298
299 init_mmu();
300}
301
302/*
303 * Initialize system. Setup memory and reserve regions.
304 */
305
306extern char _end;
307extern char _stext;
308extern char _WindowVectors_text_start;
309extern char _WindowVectors_text_end;
310extern char _DebugInterruptVector_literal_start;
311extern char _DebugInterruptVector_text_end;
312extern char _KernelExceptionVector_literal_start;
313extern char _KernelExceptionVector_text_end;
314extern char _UserExceptionVector_literal_start;
315extern char _UserExceptionVector_text_end;
316extern char _DoubleExceptionVector_literal_start;
317extern char _DoubleExceptionVector_text_end;
2d1c645c
MG		 318#if XCHAL_EXCM_LEVEL >= 2
319extern char _Level2InterruptVector_text_start;
320extern char _Level2InterruptVector_text_end;
321#endif
322#if XCHAL_EXCM_LEVEL >= 3
323extern char _Level3InterruptVector_text_start;
324extern char _Level3InterruptVector_text_end;
325#endif
326#if XCHAL_EXCM_LEVEL >= 4
327extern char _Level4InterruptVector_text_start;
328extern char _Level4InterruptVector_text_end;
329#endif
330#if XCHAL_EXCM_LEVEL >= 5
331extern char _Level5InterruptVector_text_start;
332extern char _Level5InterruptVector_text_end;
333#endif
334#if XCHAL_EXCM_LEVEL >= 6
335extern char _Level6InterruptVector_text_start;
336extern char _Level6InterruptVector_text_end;
337#endif
338
5a0015d6 339
00273125
MF		 340
341#ifdef CONFIG_S32C1I_SELFTEST
342#if XCHAL_HAVE_S32C1I
343
344static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
345
346/*
347 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
348 *
349 * If *v == cmp, set *v = set. Return previous *v.
350 */
351static inline int probed_compare_swap(int *v, int cmp, int set)
352{
353 int tmp;
354
355 __asm__ __volatile__(
356 " movi %1, 1f\n"
357 " s32i %1, %4, 0\n"
358 " wsr %2, scompare1\n"
359 "1: s32c1i %0, %3, 0\n"
360 : "=a" (set), "=&a" (tmp)
361 : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
362 : "memory"
363 );
364 return set;
365}
366
367/* Handle probed exception */
368
59970753
MF		 369static void __init do_probed_exception(struct pt_regs *regs,
370 unsigned long exccause)
00273125
MF		 371{
372 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
373 regs->pc += 3; /* skip the s32c1i instruction */
374 rcw_exc = exccause;
375 } else {
376 do_unhandled(regs, exccause);
377 }
378}
379
380/* Simple test of S32C1I (soc bringup assist) */
381
59970753 382static int __init check_s32c1i(void)
00273125
MF		 383{
384 int n, cause1, cause2;
385 void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
386
387 rcw_probe_pc = 0;
388 handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
389 do_probed_exception);
390 handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
391 do_probed_exception);
392 handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
393 do_probed_exception);
394
395 /* First try an S32C1I that does not store: */
396 rcw_exc = 0;
397 rcw_word = 1;
398 n = probed_compare_swap(&rcw_word, 0, 2);
399 cause1 = rcw_exc;
400
401 /* took exception? */
402 if (cause1 != 0) {
403 /* unclean exception? */
404 if (n != 2 || rcw_word != 1)
405 panic("S32C1I exception error");
406 } else if (rcw_word != 1 || n != 1) {
407 panic("S32C1I compare error");
408 }
409
410 /* Then an S32C1I that stores: */
411 rcw_exc = 0;
412 rcw_word = 0x1234567;
413 n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
414 cause2 = rcw_exc;
415
416 if (cause2 != 0) {
417 /* unclean exception? */
418 if (n != 0xabcde || rcw_word != 0x1234567)
419 panic("S32C1I exception error (b)");
420 } else if (rcw_word != 0xabcde || n != 0x1234567) {
421 panic("S32C1I store error");
422 }
423
424 /* Verify consistency of exceptions: */
425 if (cause1 || cause2) {
426 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
427 /* If emulation of S32C1I upon bus error gets implemented,
428 we can get rid of this panic for single core (not SMP) */
429 panic("S32C1I exceptions not currently supported");
430 }
431 if (cause1 != cause2)
432 panic("inconsistent S32C1I exceptions");
433
434 trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
435 trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
436 trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
59970753 437 return 0;
00273125
MF		 438}
439
440#else /* XCHAL_HAVE_S32C1I */
441
442/* This condition should not occur with a commercially deployed processor.
443 Display reminder for early engr test or demo chips / FPGA bitstreams */
59970753 444static int __init check_s32c1i(void)
00273125
MF		 445{
446 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
59970753 447 return 0;
00273125
MF		 448}
449
450#endif /* XCHAL_HAVE_S32C1I */
59970753 451early_initcall(check_s32c1i);
00273125
MF		 452#endif /* CONFIG_S32C1I_SELFTEST */
453
454
5a0015d6
CZ		 455void __init setup_arch(char **cmdline_p)
456{
da844a81 457 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
5a0015d6
CZ		 458 *cmdline_p = command_line;
459
460 /* Reserve some memory regions */
461
462#ifdef CONFIG_BLK_DEV_INITRD
463 if (initrd_start < initrd_end) {
464 initrd_is_mapped = mem_reserve(__pa(initrd_start),
62327918 465 __pa(initrd_end), 0) == 0;
5a0015d6 466 initrd_below_start_ok = 1;
c4c4594b 467 } else {
5a0015d6
CZ		 468 initrd_start = 0;
469 }
470#endif
471
472 mem_reserve(__pa(&_stext),__pa(&_end), 1);
473
474 mem_reserve(__pa(&_WindowVectors_text_start),
475 __pa(&_WindowVectors_text_end), 0);
476
477 mem_reserve(__pa(&_DebugInterruptVector_literal_start),
478 __pa(&_DebugInterruptVector_text_end), 0);
479
480 mem_reserve(__pa(&_KernelExceptionVector_literal_start),
481 __pa(&_KernelExceptionVector_text_end), 0);
482
483 mem_reserve(__pa(&_UserExceptionVector_literal_start),
484 __pa(&_UserExceptionVector_text_end), 0);
485
486 mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
487 __pa(&_DoubleExceptionVector_text_end), 0);
488
2d1c645c
MG		 489#if XCHAL_EXCM_LEVEL >= 2
490 mem_reserve(__pa(&_Level2InterruptVector_text_start),
491 __pa(&_Level2InterruptVector_text_end), 0);
492#endif
493#if XCHAL_EXCM_LEVEL >= 3
494 mem_reserve(__pa(&_Level3InterruptVector_text_start),
495 __pa(&_Level3InterruptVector_text_end), 0);
496#endif
497#if XCHAL_EXCM_LEVEL >= 4
498 mem_reserve(__pa(&_Level4InterruptVector_text_start),
499 __pa(&_Level4InterruptVector_text_end), 0);
500#endif
501#if XCHAL_EXCM_LEVEL >= 5
502 mem_reserve(__pa(&_Level5InterruptVector_text_start),
503 __pa(&_Level5InterruptVector_text_end), 0);
504#endif
505#if XCHAL_EXCM_LEVEL >= 6
506 mem_reserve(__pa(&_Level6InterruptVector_text_start),
507 __pa(&_Level6InterruptVector_text_end), 0);
508#endif
509
5a0015d6
CZ		 510 bootmem_init();
511
3104021c 512 unflatten_and_copy_device_tree();
5a0015d6 513
da844a81 514 platform_setup(cmdline_p);
5a0015d6 515
f615136c
MF		 516#ifdef CONFIG_SMP
517 smp_init_cpus();
518#endif
519
5a0015d6 520 paging_init();
e5083a63 521 zones_init();
5a0015d6
CZ		 522
523#ifdef CONFIG_VT
524# if defined(CONFIG_VGA_CONSOLE)
525 conswitchp = &vga_con;
526# elif defined(CONFIG_DUMMY_CONSOLE)
527 conswitchp = &dummy_con;
528# endif
529#endif
530
288a60cf 531#ifdef CONFIG_PCI
5a0015d6
CZ		 532 platform_pcibios_init();
533#endif
534}
535
f615136c
MF		 536static DEFINE_PER_CPU(struct cpu, cpu_data);
537
538static int __init topology_init(void)
539{
540 int i;
541
542 for_each_possible_cpu(i) {
543 struct cpu *cpu = &per_cpu(cpu_data, i);
49b424fe 544 cpu->hotpluggable = !!i;
f615136c
MF		 545 register_cpu(cpu, i);
546 }
547
548 return 0;
549}
550subsys_initcall(topology_init);
551
5a0015d6
CZ		 552void machine_restart(char * cmd)
553{
554 platform_restart();
555}
556
557void machine_halt(void)
558{
559 platform_halt();
560 while (1);
561}
562
563void machine_power_off(void)
564{
565 platform_power_off();
566 while (1);
567}
568#ifdef CONFIG_PROC_FS
569
570/*
571 * Display some core information through /proc/cpuinfo.
572 */
573
574static int
575c_show(struct seq_file *f, void *slot)
576{
f615136c
MF		 577 char buf[NR_CPUS * 5];
578
579 cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
5a0015d6 580 /* high-level stuff */
f615136c
MF		 581 seq_printf(f, "CPU count\t: %u\n"
582 "CPU list\t: %s\n"
583 "vendor_id\t: Tensilica\n"
584 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
585 "core ID\t\t: " XCHAL_CORE_ID "\n"
586 "build ID\t: 0x%x\n"
587 "byte order\t: %s\n"
588 "cpu MHz\t\t: %lu.%02lu\n"
589 "bogomips\t: %lu.%02lu\n",
590 num_online_cpus(),
591 buf,
592 XCHAL_BUILD_UNIQUE_ID,
593 XCHAL_HAVE_BE ? "big" : "little",
594 ccount_freq/1000000,
595 (ccount_freq/10000) % 100,
596 loops_per_jiffy/(500000/HZ),
597 (loops_per_jiffy/(5000/HZ)) % 100);
5a0015d6
CZ		 598
599 seq_printf(f,"flags\t\t: "
600#if XCHAL_HAVE_NMI
601 "nmi "
602#endif
603#if XCHAL_HAVE_DEBUG
604 "debug "
605# if XCHAL_HAVE_OCD
606 "ocd "
607# endif
608#endif
609#if XCHAL_HAVE_DENSITY
610 "density "
611#endif
612#if XCHAL_HAVE_BOOLEANS
613 "boolean "
614#endif
615#if XCHAL_HAVE_LOOPS
616 "loop "
617#endif
618#if XCHAL_HAVE_NSA
619 "nsa "
620#endif
621#if XCHAL_HAVE_MINMAX
622 "minmax "
623#endif
624#if XCHAL_HAVE_SEXT
625 "sext "
626#endif
627#if XCHAL_HAVE_CLAMPS
628 "clamps "
629#endif
630#if XCHAL_HAVE_MAC16
631 "mac16 "
632#endif
633#if XCHAL_HAVE_MUL16
634 "mul16 "
635#endif
636#if XCHAL_HAVE_MUL32
637 "mul32 "
638#endif
639#if XCHAL_HAVE_MUL32_HIGH
640 "mul32h "
641#endif
642#if XCHAL_HAVE_FP
643 "fpu "
2f6ea6a7
MF		 644#endif
645#if XCHAL_HAVE_S32C1I
646 "s32c1i "
5a0015d6
CZ		 647#endif
648 "\n");
649
650 /* Registers. */
651 seq_printf(f,"physical aregs\t: %d\n"
652 "misc regs\t: %d\n"
653 "ibreak\t\t: %d\n"
654 "dbreak\t\t: %d\n",
655 XCHAL_NUM_AREGS,
656 XCHAL_NUM_MISC_REGS,
657 XCHAL_NUM_IBREAK,
658 XCHAL_NUM_DBREAK);
659
660
661 /* Interrupt. */
662 seq_printf(f,"num ints\t: %d\n"
663 "ext ints\t: %d\n"
664 "int levels\t: %d\n"
665 "timers\t\t: %d\n"
666 "debug level\t: %d\n",
667 XCHAL_NUM_INTERRUPTS,
668 XCHAL_NUM_EXTINTERRUPTS,
669 XCHAL_NUM_INTLEVELS,
670 XCHAL_NUM_TIMERS,
671 XCHAL_DEBUGLEVEL);
672
5a0015d6
CZ		 673 /* Cache */
674 seq_printf(f,"icache line size: %d\n"
675 "icache ways\t: %d\n"
676 "icache size\t: %d\n"
677 "icache flags\t: "
678#if XCHAL_ICACHE_LINE_LOCKABLE
415217ef 679 "lock "
5a0015d6
CZ		 680#endif
681 "\n"
682 "dcache line size: %d\n"
683 "dcache ways\t: %d\n"
684 "dcache size\t: %d\n"
685 "dcache flags\t: "
686#if XCHAL_DCACHE_IS_WRITEBACK
415217ef 687 "writeback "
5a0015d6
CZ		 688#endif
689#if XCHAL_DCACHE_LINE_LOCKABLE
415217ef 690 "lock "
5a0015d6
CZ		 691#endif
692 "\n",
693 XCHAL_ICACHE_LINESIZE,
694 XCHAL_ICACHE_WAYS,
695 XCHAL_ICACHE_SIZE,
696 XCHAL_DCACHE_LINESIZE,
697 XCHAL_DCACHE_WAYS,
698 XCHAL_DCACHE_SIZE);
699
5a0015d6
CZ		 700 return 0;
701}
702
703/*
704 * We show only CPU #0 info.
705 */
706static void *
707c_start(struct seq_file *f, loff_t *pos)
708{
f615136c 709 return (*pos == 0) ? (void *)1 : NULL;
5a0015d6
CZ		 710}
711
712static void *
713c_next(struct seq_file *f, void *v, loff_t *pos)
714{
715 return NULL;
716}
717
718static void
719c_stop(struct seq_file *f, void *v)
720{
721}
722
03a44825 723const struct seq_operations cpuinfo_op =
5a0015d6 724{
f615136c
MF		 725 .start = c_start,
726 .next = c_next,
727 .stop = c_stop,
728 .show = c_show,
5a0015d6
CZ		 729};
730
731#endif /* CONFIG_PROC_FS */
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