[mirror_ubuntu-artful-kernel.git] / arch / xtensa / kernel / setup.c

/*
 * arch/xtensa/kernel/setup.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 2001 - 2005  Tensilica Inc.
 * Copyright (C) 2014 - 2016  Cadence Design Systems Inc.
 *
 * Chris Zankel	<chris@zankel.net>
 * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
 * Kevin Chea
 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/screen_info.h>
#include <linux/bootmem.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_fdt.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
# include <linux/console.h>
#endif

#ifdef CONFIG_PROC_FS
# include <linux/seq_file.h>
#endif

#include <asm/bootparam.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/timex.h>
#include <asm/platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/param.h>
#include <asm/smp.h>
#include <asm/sysmem.h>

#include <platform/hardware.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = {
	.orig_x = 0,
	.orig_y = 24,
	.orig_video_cols = 80,
	.orig_video_lines = 24,
	.orig_video_isVGA = 1,
	.orig_video_points = 16,
};
#endif

#ifdef CONFIG_BLK_DEV_INITRD
extern unsigned long initrd_start;
extern unsigned long initrd_end;
int initrd_is_mapped = 0;
extern int initrd_below_start_ok;
#endif

#ifdef CONFIG_OF
void *dtb_start = __dtb_start;
#endif

extern unsigned long loops_per_jiffy;

/* Command line specified as configuration option. */

static char __initdata command_line[COMMAND_LINE_SIZE];

#ifdef CONFIG_CMDLINE_BOOL
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
#endif

/*
 * Boot parameter parsing.
 *
 * The Xtensa port uses a list of variable-sized tags to pass data to
 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
 * to be recognised. The list is terminated with a zero-sized
 * BP_TAG_LAST tag.
 */

typedef struct tagtable {
	u32 tag;
	int (*parse)(const bp_tag_t*);
} tagtable_t;

#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
	__attribute__((used, section(".taglist"))) = { tag, fn }

/* parse current tag */

static int __init parse_tag_mem(const bp_tag_t *tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
		return -1;

	return memblock_add(mi->start, mi->end - mi->start);
}

__tagtable(BP_TAG_MEMORY, parse_tag_mem);

#ifdef CONFIG_BLK_DEV_INITRD

static int __init parse_tag_initrd(const bp_tag_t* tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	initrd_start = (unsigned long)__va(mi->start);
	initrd_end = (unsigned long)__va(mi->end);

	return 0;
}

__tagtable(BP_TAG_INITRD, parse_tag_initrd);

#endif /* CONFIG_BLK_DEV_INITRD */

#ifdef CONFIG_OF

static int __init parse_tag_fdt(const bp_tag_t *tag)
{
	dtb_start = __va(tag->data[0]);
	return 0;
}

__tagtable(BP_TAG_FDT, parse_tag_fdt);

#endif /* CONFIG_OF */

static int __init parse_tag_cmdline(const bp_tag_t* tag)
{
	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
	return 0;
}

__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);

static int __init parse_bootparam(const bp_tag_t* tag)
{
	extern tagtable_t __tagtable_begin, __tagtable_end;
	tagtable_t *t;

	/* Boot parameters must start with a BP_TAG_FIRST tag. */

	if (tag->id != BP_TAG_FIRST) {
		printk(KERN_WARNING "Invalid boot parameters!\n");
		return 0;
	}

	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);

	/* Parse all tags. */

	while (tag != NULL && tag->id != BP_TAG_LAST) {
	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
			if (tag->id == t->tag) {
				t->parse(tag);
				break;
			}
		}
		if (t == &__tagtable_end)
			printk(KERN_WARNING "Ignoring tag "
			       "0x%08x\n", tag->id);
		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	}

	return 0;
}

#ifdef CONFIG_OF

#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
EXPORT_SYMBOL(xtensa_kio_paddr);

static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	const __be32 *ranges;
	int len;

	if (depth > 1)
		return 0;

	if (!of_flat_dt_is_compatible(node, "simple-bus"))
		return 0;

	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	if (!ranges)
		return 1;
	if (len == 0)
		return 1;

	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	/* round down to nearest 256MB boundary */
	xtensa_kio_paddr &= 0xf0000000;

	return 1;
}
#else
static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	return 1;
}
#endif

void __init early_init_dt_add_memory_arch(u64 base, u64 size)
{
	size &= PAGE_MASK;
	memblock_add(base, size);
}

void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
{
	return __alloc_bootmem(size, align, 0);
}

void __init early_init_devtree(void *params)
{
	early_init_dt_scan(params);
	of_scan_flat_dt(xtensa_dt_io_area, NULL);

	if (!command_line[0])
		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
}

#endif /* CONFIG_OF */

/*
 * Initialize architecture. (Early stage)
 */

void __init init_arch(bp_tag_t *bp_start)
{
	/* Parse boot parameters */

	if (bp_start)
		parse_bootparam(bp_start);

#ifdef CONFIG_OF
	early_init_devtree(dtb_start);
#endif

#ifdef CONFIG_CMDLINE_BOOL
	if (!command_line[0])
		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
#endif

	/* Early hook for platforms */

	platform_init(bp_start);

	/* Initialize MMU. */

	init_mmu();
}

/*
 * Initialize system. Setup memory and reserve regions.
 */

extern char _end;
extern char _stext;
extern char _WindowVectors_text_start;
extern char _WindowVectors_text_end;
extern char _DebugInterruptVector_literal_start;
extern char _DebugInterruptVector_text_end;
extern char _KernelExceptionVector_literal_start;
extern char _KernelExceptionVector_text_end;
extern char _UserExceptionVector_literal_start;
extern char _UserExceptionVector_text_end;
extern char _DoubleExceptionVector_literal_start;
extern char _DoubleExceptionVector_text_end;
#if XCHAL_EXCM_LEVEL >= 2
extern char _Level2InterruptVector_text_start;
extern char _Level2InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 3
extern char _Level3InterruptVector_text_start;
extern char _Level3InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 4
extern char _Level4InterruptVector_text_start;
extern char _Level4InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 5
extern char _Level5InterruptVector_text_start;
extern char _Level5InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 6
extern char _Level6InterruptVector_text_start;
extern char _Level6InterruptVector_text_end;
#endif
#ifdef CONFIG_SMP
extern char _SecondaryResetVector_text_start;
extern char _SecondaryResetVector_text_end;
#endif

static inline int mem_reserve(unsigned long start, unsigned long end)
{
	return memblock_reserve(start, end - start);
}

void __init setup_arch(char **cmdline_p)
{
	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
	*cmdline_p = command_line;

	/* Reserve some memory regions */

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start < initrd_end) {
		initrd_is_mapped = mem_reserve(__pa(initrd_start),
					       __pa(initrd_end)) == 0;
		initrd_below_start_ok = 1;
	} else {
		initrd_start = 0;
	}
#endif

	mem_reserve(__pa(&_stext), __pa(&_end));

#ifdef CONFIG_VECTORS_OFFSET
	mem_reserve(__pa(&_WindowVectors_text_start),
		    __pa(&_WindowVectors_text_end));

	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
		    __pa(&_DebugInterruptVector_text_end));

	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
		    __pa(&_KernelExceptionVector_text_end));

	mem_reserve(__pa(&_UserExceptionVector_literal_start),
		    __pa(&_UserExceptionVector_text_end));

	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
		    __pa(&_DoubleExceptionVector_text_end));

#if XCHAL_EXCM_LEVEL >= 2
	mem_reserve(__pa(&_Level2InterruptVector_text_start),
		    __pa(&_Level2InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 3
	mem_reserve(__pa(&_Level3InterruptVector_text_start),
		    __pa(&_Level3InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 4
	mem_reserve(__pa(&_Level4InterruptVector_text_start),
		    __pa(&_Level4InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 5
	mem_reserve(__pa(&_Level5InterruptVector_text_start),
		    __pa(&_Level5InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 6
	mem_reserve(__pa(&_Level6InterruptVector_text_start),
		    __pa(&_Level6InterruptVector_text_end));
#endif

#endif /* CONFIG_VECTORS_OFFSET */

#ifdef CONFIG_SMP
	mem_reserve(__pa(&_SecondaryResetVector_text_start),
		    __pa(&_SecondaryResetVector_text_end));
#endif
	parse_early_param();
	bootmem_init();

	unflatten_and_copy_device_tree();

	platform_setup(cmdline_p);

#ifdef CONFIG_SMP
	smp_init_cpus();
#endif

	paging_init();
	zones_init();

#ifdef CONFIG_VT
# if defined(CONFIG_VGA_CONSOLE)
	conswitchp = &vga_con;
# elif defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
# endif
#endif

#ifdef CONFIG_PCI
	platform_pcibios_init();
#endif
}

static DEFINE_PER_CPU(struct cpu, cpu_data);

static int __init topology_init(void)
{
	int i;

	for_each_possible_cpu(i) {
		struct cpu *cpu = &per_cpu(cpu_data, i);
		cpu->hotpluggable = !!i;
		register_cpu(cpu, i);
	}

	return 0;
}
subsys_initcall(topology_init);

void cpu_reset(void)
{
#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
	local_irq_disable();
	/*
	 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
	 * be flushed.
	 * Way 4 is not currently used by linux.
	 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
	 * Way 5 shall be flushed and way 6 shall be set to identity mapping
	 * on MMUv3.
	 */
	local_flush_tlb_all();
	invalidate_page_directory();
#if XCHAL_HAVE_SPANNING_WAY
	/* MMU v3 */
	{
		unsigned long vaddr = (unsigned long)cpu_reset;
		unsigned long paddr = __pa(vaddr);
		unsigned long tmpaddr = vaddr + SZ_512M;
		unsigned long tmp0, tmp1, tmp2, tmp3;

		/*
		 * Find a place for the temporary mapping. It must not be
		 * in the same 512MB region with vaddr or paddr, otherwise
		 * there may be multihit exception either on entry to the
		 * temporary mapping, or on entry to the identity mapping.
		 * (512MB is the biggest page size supported by TLB.)
		 */
		while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
			tmpaddr += SZ_512M;

		/* Invalidate mapping in the selected temporary area */
		if (itlb_probe(tmpaddr) & 0x8)
			invalidate_itlb_entry(itlb_probe(tmpaddr));
		if (itlb_probe(tmpaddr + PAGE_SIZE) & 0x8)
			invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));

		/*
		 * Map two consecutive pages starting at the physical address
		 * of this function to the temporary mapping area.
		 */
		write_itlb_entry(__pte((paddr & PAGE_MASK) |
				       _PAGE_HW_VALID |
				       _PAGE_HW_EXEC |
				       _PAGE_CA_BYPASS),
				 tmpaddr & PAGE_MASK);
		write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
				       _PAGE_HW_VALID |
				       _PAGE_HW_EXEC |
				       _PAGE_CA_BYPASS),
				 (tmpaddr & PAGE_MASK) + PAGE_SIZE);

		/* Reinitialize TLB */
		__asm__ __volatile__ ("movi	%0, 1f\n\t"
				      "movi	%3, 2f\n\t"
				      "add	%0, %0, %4\n\t"
				      "add	%3, %3, %5\n\t"
				      "jx	%0\n"
				      /*
				       * No literal, data or stack access
				       * below this point
				       */
				      "1:\n\t"
				      /* Initialize *tlbcfg */
				      "movi	%0, 0\n\t"
				      "wsr	%0, itlbcfg\n\t"
				      "wsr	%0, dtlbcfg\n\t"
				      /* Invalidate TLB way 5 */
				      "movi	%0, 4\n\t"
				      "movi	%1, 5\n"
				      "1:\n\t"
				      "iitlb	%1\n\t"
				      "idtlb	%1\n\t"
				      "add	%1, %1, %6\n\t"
				      "addi	%0, %0, -1\n\t"
				      "bnez	%0, 1b\n\t"
				      /* Initialize TLB way 6 */
				      "movi	%0, 7\n\t"
				      "addi	%1, %9, 3\n\t"
				      "addi	%2, %9, 6\n"
				      "1:\n\t"
				      "witlb	%1, %2\n\t"
				      "wdtlb	%1, %2\n\t"
				      "add	%1, %1, %7\n\t"
				      "add	%2, %2, %7\n\t"
				      "addi	%0, %0, -1\n\t"
				      "bnez	%0, 1b\n\t"
				      /* Jump to identity mapping */
				      "jx	%3\n"
				      "2:\n\t"
				      /* Complete way 6 initialization */
				      "witlb	%1, %2\n\t"
				      "wdtlb	%1, %2\n\t"
				      /* Invalidate temporary mapping */
				      "sub	%0, %9, %7\n\t"
				      "iitlb	%0\n\t"
				      "add	%0, %0, %8\n\t"
				      "iitlb	%0"
				      : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
					"=&a"(tmp3)
				      : "a"(tmpaddr - vaddr),
					"a"(paddr - vaddr),
					"a"(SZ_128M), "a"(SZ_512M),
					"a"(PAGE_SIZE),
					"a"((tmpaddr + SZ_512M) & PAGE_MASK)
				      : "memory");
	}
#endif
#endif
	__asm__ __volatile__ ("movi	a2, 0\n\t"
			      "wsr	a2, icountlevel\n\t"
			      "movi	a2, 0\n\t"
			      "wsr	a2, icount\n\t"
#if XCHAL_NUM_IBREAK > 0
			      "wsr	a2, ibreakenable\n\t"
#endif
#if XCHAL_HAVE_LOOPS
			      "wsr	a2, lcount\n\t"
#endif
			      "movi	a2, 0x1f\n\t"
			      "wsr	a2, ps\n\t"
			      "isync\n\t"
			      "jx	%0\n\t"
			      :
			      : "a" (XCHAL_RESET_VECTOR_VADDR)
			      : "a2");
	for (;;)
		;
}

void machine_restart(char * cmd)
{
	platform_restart();
}

void machine_halt(void)
{
	platform_halt();
	while (1);
}

void machine_power_off(void)
{
	platform_power_off();
	while (1);
}
#ifdef CONFIG_PROC_FS

/*
 * Display some core information through /proc/cpuinfo.
 */

static int
c_show(struct seq_file *f, void *slot)
{
	/* high-level stuff */
	seq_printf(f, "CPU count\t: %u\n"
		      "CPU list\t: %*pbl\n"
		      "vendor_id\t: Tensilica\n"
		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
		      "core ID\t\t: " XCHAL_CORE_ID "\n"
		      "build ID\t: 0x%x\n"
		      "byte order\t: %s\n"
		      "cpu MHz\t\t: %lu.%02lu\n"
		      "bogomips\t: %lu.%02lu\n",
		      num_online_cpus(),
		      cpumask_pr_args(cpu_online_mask),
		      XCHAL_BUILD_UNIQUE_ID,
		      XCHAL_HAVE_BE ?  "big" : "little",
		      ccount_freq/1000000,
		      (ccount_freq/10000) % 100,
		      loops_per_jiffy/(500000/HZ),
		      (loops_per_jiffy/(5000/HZ)) % 100);

	seq_printf(f,"flags\t\t: "
#if XCHAL_HAVE_NMI
		     "nmi "
#endif
#if XCHAL_HAVE_DEBUG
		     "debug "
# if XCHAL_HAVE_OCD
		     "ocd "
# endif
#endif
#if XCHAL_HAVE_DENSITY
	    	     "density "
#endif
#if XCHAL_HAVE_BOOLEANS
		     "boolean "
#endif
#if XCHAL_HAVE_LOOPS
		     "loop "
#endif
#if XCHAL_HAVE_NSA
		     "nsa "
#endif
#if XCHAL_HAVE_MINMAX
		     "minmax "
#endif
#if XCHAL_HAVE_SEXT
		     "sext "
#endif
#if XCHAL_HAVE_CLAMPS
		     "clamps "
#endif
#if XCHAL_HAVE_MAC16
		     "mac16 "
#endif
#if XCHAL_HAVE_MUL16
		     "mul16 "
#endif
#if XCHAL_HAVE_MUL32
		     "mul32 "
#endif
#if XCHAL_HAVE_MUL32_HIGH
		     "mul32h "
#endif
#if XCHAL_HAVE_FP
		     "fpu "
#endif
#if XCHAL_HAVE_S32C1I
		     "s32c1i "
#endif
		     "\n");

	/* Registers. */
	seq_printf(f,"physical aregs\t: %d\n"
		     "misc regs\t: %d\n"
		     "ibreak\t\t: %d\n"
		     "dbreak\t\t: %d\n",
		     XCHAL_NUM_AREGS,
		     XCHAL_NUM_MISC_REGS,
		     XCHAL_NUM_IBREAK,
		     XCHAL_NUM_DBREAK);


	/* Interrupt. */
	seq_printf(f,"num ints\t: %d\n"
		     "ext ints\t: %d\n"
		     "int levels\t: %d\n"
		     "timers\t\t: %d\n"
		     "debug level\t: %d\n",
		     XCHAL_NUM_INTERRUPTS,
		     XCHAL_NUM_EXTINTERRUPTS,
		     XCHAL_NUM_INTLEVELS,
		     XCHAL_NUM_TIMERS,
		     XCHAL_DEBUGLEVEL);

	/* Cache */
	seq_printf(f,"icache line size: %d\n"
		     "icache ways\t: %d\n"
		     "icache size\t: %d\n"
		     "icache flags\t: "
#if XCHAL_ICACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n"
		     "dcache line size: %d\n"
		     "dcache ways\t: %d\n"
		     "dcache size\t: %d\n"
		     "dcache flags\t: "
#if XCHAL_DCACHE_IS_WRITEBACK
		     "writeback "
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n",
		     XCHAL_ICACHE_LINESIZE,
		     XCHAL_ICACHE_WAYS,
		     XCHAL_ICACHE_SIZE,
		     XCHAL_DCACHE_LINESIZE,
		     XCHAL_DCACHE_WAYS,
		     XCHAL_DCACHE_SIZE);

	return 0;
}

/*
 * We show only CPU #0 info.
 */
static void *
c_start(struct seq_file *f, loff_t *pos)
{
	return (*pos == 0) ? (void *)1 : NULL;
}

static void *
c_next(struct seq_file *f, void *v, loff_t *pos)
{
	return NULL;
}

static void
c_stop(struct seq_file *f, void *v)
{
}

const struct seq_operations cpuinfo_op =
{
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show,
};

#endif /* CONFIG_PROC_FS */
Commit	Line	Data
5a0015d6	1	/*
f30c2269	2	* arch/xtensa/kernel/setup.c
5a0015d6 CZ	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1995 Linus Torvalds
	9	* Copyright (C) 2001 - 2005 Tensilica Inc.
0e46c111	10	* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
5a0015d6 CZ	11	*
	12	* Chris Zankel <chris@zankel.net>
	13	* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
	14	* Kevin Chea
	15	* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
	16	*/
	17
5a0015d6 CZ	18	#include <linux/errno.h>
5a0015d6 CZ	19	#include <linux/init.h>
27ac792c	20	#include <linux/mm.h>
5a0015d6	21	#include <linux/proc_fs.h>
894673ee	22	#include <linux/screen_info.h>
5a0015d6 CZ	23	#include <linux/bootmem.h>
5a0015d6 CZ	24	#include <linux/kernel.h>
f615136c MF	25	#include <linux/percpu.h>
f615136c MF	26	#include <linux/cpu.h>
d02014b2	27	#include <linux/of.h>
da844a81	28	#include <linux/of_fdt.h>
da844a81	29
5a0015d6 CZ	30	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
	31	# include <linux/console.h>
	32	#endif
	33
5a0015d6 CZ	34	#ifdef CONFIG_PROC_FS
	35	# include <linux/seq_file.h>
	36	#endif
	37
5a0015d6	38	#include <asm/bootparam.h>
c8f3a7dc	39	#include <asm/mmu_context.h>
5a0015d6 CZ	40	#include <asm/pgtable.h>
	41	#include <asm/processor.h>
	42	#include <asm/timex.h>
	43	#include <asm/platform.h>
	44	#include <asm/page.h>
	45	#include <asm/setup.h>
de4f6e5b	46	#include <asm/param.h>
f615136c	47	#include <asm/smp.h>
9ba067f9	48	#include <asm/sysmem.h>
5a0015d6	49
5a891ed5 AD	50	#include <platform/hardware.h>
5a891ed5 AD	51
5a0015d6	52	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
03eae3ac MF	53	struct screen_info screen_info = {
	54	.orig_x = 0,
	55	.orig_y = 24,
	56	.orig_video_cols = 80,
	57	.orig_video_lines = 24,
	58	.orig_video_isVGA = 1,
	59	.orig_video_points = 16,
	60	};
5a0015d6 CZ	61	#endif
5a0015d6 CZ	62
5a0015d6	63	#ifdef CONFIG_BLK_DEV_INITRD
29eb45a9 RH	64	extern unsigned long initrd_start;
29eb45a9 RH	65	extern unsigned long initrd_end;
5a0015d6 CZ	66	int initrd_is_mapped = 0;
	67	extern int initrd_below_start_ok;
	68	#endif
	69
da844a81	70	#ifdef CONFIG_OF
da844a81 MF	71	void *dtb_start = __dtb_start;
	72	#endif
	73
5a0015d6 CZ	74	extern unsigned long loops_per_jiffy;
	75
	76	/* Command line specified as configuration option. */
	77
d3e9ccea	78	static char __initdata command_line[COMMAND_LINE_SIZE];
5a0015d6 CZ	79
	80	#ifdef CONFIG_CMDLINE_BOOL
	81	static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
	82	#endif
	83
5a0015d6 CZ	84	/*
	85	* Boot parameter parsing.
	86	*
	87	* The Xtensa port uses a list of variable-sized tags to pass data to
	88	* the kernel. The first tag must be a BP_TAG_FIRST tag for the list
	89	* to be recognised. The list is terminated with a zero-sized
	90	* BP_TAG_LAST tag.
	91	*/
	92
	93	typedef struct tagtable {
	94	u32 tag;
	95	int (parse)(const bp_tag_t);
	96	} tagtable_t;
	97
	98	#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
f4349b6e	99	__attribute__((used, section(".taglist"))) = { tag, fn }
5a0015d6 CZ	100
	101	/* parse current tag */
	102
da844a81 MF	103	static int __init parse_tag_mem(const bp_tag_t *tag)
da844a81 MF	104	{
9ba067f9	105	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
da844a81 MF	106
	107	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
	108	return -1;
	109
0e46c111	110	return memblock_add(mi->start, mi->end - mi->start);
da844a81 MF	111	}
da844a81 MF	112
5a0015d6 CZ	113	__tagtable(BP_TAG_MEMORY, parse_tag_mem);
	114
	115	#ifdef CONFIG_BLK_DEV_INITRD
	116
	117	static int __init parse_tag_initrd(const bp_tag_t* tag)
	118	{
9ba067f9 MF	119	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
9ba067f9 MF	120
29eb45a9 RH	121	initrd_start = (unsigned long)__va(mi->start);
29eb45a9 RH	122	initrd_end = (unsigned long)__va(mi->end);
5a0015d6 CZ	123
	124	return 0;
	125	}
	126
	127	__tagtable(BP_TAG_INITRD, parse_tag_initrd);
	128
4ab18701 MF	129	#endif /* CONFIG_BLK_DEV_INITRD */
4ab18701 MF	130
da844a81 MF	131	#ifdef CONFIG_OF
	132
	133	static int __init parse_tag_fdt(const bp_tag_t *tag)
	134	{
c5a771d0	135	dtb_start = __va(tag->data[0]);
da844a81 MF	136	return 0;
	137	}
	138
	139	__tagtable(BP_TAG_FDT, parse_tag_fdt);
	140
da844a81 MF	141	#endif /* CONFIG_OF */
da844a81 MF	142
5a0015d6 CZ	143	static int __init parse_tag_cmdline(const bp_tag_t* tag)
5a0015d6 CZ	144	{
da844a81	145	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
5a0015d6 CZ	146	return 0;
	147	}
	148
	149	__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
	150
	151	static int __init parse_bootparam(const bp_tag_t* tag)
	152	{
	153	extern tagtable_t __tagtable_begin, __tagtable_end;
	154	tagtable_t *t;
	155
	156	/* Boot parameters must start with a BP_TAG_FIRST tag. */
	157
	158	if (tag->id != BP_TAG_FIRST) {
	159	printk(KERN_WARNING "Invalid boot parameters!\n");
	160	return 0;
	161	}
	162
	163	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
	164
	165	/* Parse all tags. */
	166
	167	while (tag != NULL && tag->id != BP_TAG_LAST) {
	168	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
	169	if (tag->id == t->tag) {
	170	t->parse(tag);
	171	break;
	172	}
	173	}
	174	if (t == &__tagtable_end)
	175	printk(KERN_WARNING "Ignoring tag "
	176	"0x%08x\n", tag->id);
	177	tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	178	}
	179
	180	return 0;
	181	}
	182
da844a81 MF	183	#ifdef CONFIG_OF
da844a81 MF	184
260c64bb	185	#if !XCHAL_HAVE_PTP_MMU \|\| XCHAL_HAVE_SPANNING_WAY
6cb97111 BS	186	unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
	187	EXPORT_SYMBOL(xtensa_kio_paddr);
	188
	189	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	190	int depth, void *data)
	191	{
	192	const __be32 *ranges;
9d0c4dfe	193	int len;
6cb97111 BS	194
	195	if (depth > 1)
	196	return 0;
	197
	198	if (!of_flat_dt_is_compatible(node, "simple-bus"))
	199	return 0;
	200
	201	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	202	if (!ranges)
	203	return 1;
	204	if (len == 0)
	205	return 1;
	206
	207	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	208	/* round down to nearest 256MB boundary */
	209	xtensa_kio_paddr &= 0xf0000000;
	210
	211	return 1;
	212	}
	213	#else
	214	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	215	int depth, void *data)
	216	{
	217	return 1;
	218	}
	219	#endif
	220
da844a81 MF	221	void __init early_init_dt_add_memory_arch(u64 base, u64 size)
	222	{
	223	size &= PAGE_MASK;
0e46c111	224	memblock_add(base, size);
da844a81 MF	225	}
	226
	227	void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
	228	{
	229	return __alloc_bootmem(size, align, 0);
	230	}
	231
	232	void __init early_init_devtree(void *params)
	233	{
7745fc1f	234	early_init_dt_scan(params);
6cb97111	235	of_scan_flat_dt(xtensa_dt_io_area, NULL);
da844a81	236
7745fc1f RH	237	if (!command_line[0])
7745fc1f RH	238	strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
da844a81 MF	239	}
da844a81 MF	240
da844a81 MF	241	#endif /* CONFIG_OF */
da844a81 MF	242
5a0015d6 CZ	243	/*
	244	* Initialize architecture. (Early stage)
	245	*/
	246
	247	void __init init_arch(bp_tag_t *bp_start)
	248	{
5a0015d6 CZ	249	/* Parse boot parameters */
5a0015d6 CZ	250
c4c4594b	251	if (bp_start)
da844a81 MF	252	parse_bootparam(bp_start);
	253
	254	#ifdef CONFIG_OF
	255	early_init_devtree(dtb_start);
	256	#endif
5a0015d6	257
da844a81 MF	258	#ifdef CONFIG_CMDLINE_BOOL
	259	if (!command_line[0])
	260	strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
	261	#endif
	262
5a0015d6 CZ	263	/* Early hook for platforms */
	264
	265	platform_init(bp_start);
	266
	267	/* Initialize MMU. */
	268
	269	init_mmu();
	270	}
	271
	272	/*
	273	* Initialize system. Setup memory and reserve regions.
	274	*/
	275
	276	extern char _end;
	277	extern char _stext;
	278	extern char _WindowVectors_text_start;
	279	extern char _WindowVectors_text_end;
	280	extern char _DebugInterruptVector_literal_start;
	281	extern char _DebugInterruptVector_text_end;
	282	extern char _KernelExceptionVector_literal_start;
	283	extern char _KernelExceptionVector_text_end;
	284	extern char _UserExceptionVector_literal_start;
	285	extern char _UserExceptionVector_text_end;
	286	extern char _DoubleExceptionVector_literal_start;
	287	extern char _DoubleExceptionVector_text_end;
2d1c645c MG	288	#if XCHAL_EXCM_LEVEL >= 2
	289	extern char _Level2InterruptVector_text_start;
	290	extern char _Level2InterruptVector_text_end;
	291	#endif
	292	#if XCHAL_EXCM_LEVEL >= 3
	293	extern char _Level3InterruptVector_text_start;
	294	extern char _Level3InterruptVector_text_end;
	295	#endif
	296	#if XCHAL_EXCM_LEVEL >= 4
	297	extern char _Level4InterruptVector_text_start;
	298	extern char _Level4InterruptVector_text_end;
	299	#endif
	300	#if XCHAL_EXCM_LEVEL >= 5
	301	extern char _Level5InterruptVector_text_start;
	302	extern char _Level5InterruptVector_text_end;
	303	#endif
	304	#if XCHAL_EXCM_LEVEL >= 6
	305	extern char _Level6InterruptVector_text_start;
	306	extern char _Level6InterruptVector_text_end;
	307	#endif
ab45fb14 MF	308	#ifdef CONFIG_SMP
	309	extern char _SecondaryResetVector_text_start;
	310	extern char _SecondaryResetVector_text_end;
	311	#endif
5a0015d6	312
0e46c111 MF	313	static inline int mem_reserve(unsigned long start, unsigned long end)
	314	{
	315	return memblock_reserve(start, end - start);
	316	}
00273125	317
5a0015d6 CZ	318	void __init setup_arch(char **cmdline_p)
5a0015d6 CZ	319	{
da844a81	320	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
5a0015d6 CZ	321	*cmdline_p = command_line;
	322
	323	/* Reserve some memory regions */
	324
	325	#ifdef CONFIG_BLK_DEV_INITRD
	326	if (initrd_start < initrd_end) {
	327	initrd_is_mapped = mem_reserve(__pa(initrd_start),
0e46c111	328	__pa(initrd_end)) == 0;
5a0015d6	329	initrd_below_start_ok = 1;
c4c4594b	330	} else {
5a0015d6 CZ	331	initrd_start = 0;
	332	}
	333	#endif
	334
0e46c111	335	mem_reserve(__pa(&_stext), __pa(&_end));
5a0015d6	336
b46dcfa3	337	#ifdef CONFIG_VECTORS_OFFSET
5a0015d6	338	mem_reserve(__pa(&_WindowVectors_text_start),
0e46c111	339	__pa(&_WindowVectors_text_end));
5a0015d6 CZ	340
5a0015d6 CZ	341	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
0e46c111	342	__pa(&_DebugInterruptVector_text_end));
5a0015d6 CZ	343
5a0015d6 CZ	344	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
0e46c111	345	__pa(&_KernelExceptionVector_text_end));
5a0015d6 CZ	346
5a0015d6 CZ	347	mem_reserve(__pa(&_UserExceptionVector_literal_start),
0e46c111	348	__pa(&_UserExceptionVector_text_end));
5a0015d6 CZ	349
5a0015d6 CZ	350	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
0e46c111	351	__pa(&_DoubleExceptionVector_text_end));
5a0015d6	352
2d1c645c MG	353	#if XCHAL_EXCM_LEVEL >= 2
2d1c645c MG	354	mem_reserve(__pa(&_Level2InterruptVector_text_start),
0e46c111	355	__pa(&_Level2InterruptVector_text_end));
2d1c645c MG	356	#endif
	357	#if XCHAL_EXCM_LEVEL >= 3
	358	mem_reserve(__pa(&_Level3InterruptVector_text_start),
0e46c111	359	__pa(&_Level3InterruptVector_text_end));
2d1c645c MG	360	#endif
	361	#if XCHAL_EXCM_LEVEL >= 4
	362	mem_reserve(__pa(&_Level4InterruptVector_text_start),
0e46c111	363	__pa(&_Level4InterruptVector_text_end));
2d1c645c MG	364	#endif
	365	#if XCHAL_EXCM_LEVEL >= 5
	366	mem_reserve(__pa(&_Level5InterruptVector_text_start),
0e46c111	367	__pa(&_Level5InterruptVector_text_end));
2d1c645c MG	368	#endif
	369	#if XCHAL_EXCM_LEVEL >= 6
	370	mem_reserve(__pa(&_Level6InterruptVector_text_start),
0e46c111	371	__pa(&_Level6InterruptVector_text_end));
2d1c645c MG	372	#endif
2d1c645c MG	373
b46dcfa3 MF	374	#endif /* CONFIG_VECTORS_OFFSET */
b46dcfa3 MF	375
ab45fb14 MF	376	#ifdef CONFIG_SMP
ab45fb14 MF	377	mem_reserve(__pa(&_SecondaryResetVector_text_start),
0e46c111	378	__pa(&_SecondaryResetVector_text_end));
ab45fb14	379	#endif
06bd2824	380	parse_early_param();
5a0015d6 CZ	381	bootmem_init();
5a0015d6 CZ	382
3104021c	383	unflatten_and_copy_device_tree();
5a0015d6	384
da844a81	385	platform_setup(cmdline_p);
5a0015d6	386
f615136c MF	387	#ifdef CONFIG_SMP
	388	smp_init_cpus();
	389	#endif
	390
5a0015d6	391	paging_init();
e5083a63	392	zones_init();
5a0015d6 CZ	393
	394	#ifdef CONFIG_VT
	395	# if defined(CONFIG_VGA_CONSOLE)
	396	conswitchp = &vga_con;
	397	# elif defined(CONFIG_DUMMY_CONSOLE)
	398	conswitchp = &dummy_con;
	399	# endif
	400	#endif
	401
288a60cf	402	#ifdef CONFIG_PCI
5a0015d6 CZ	403	platform_pcibios_init();
	404	#endif
	405	}
	406
f615136c MF	407	static DEFINE_PER_CPU(struct cpu, cpu_data);
	408
	409	static int __init topology_init(void)
	410	{
	411	int i;
	412
	413	for_each_possible_cpu(i) {
	414	struct cpu *cpu = &per_cpu(cpu_data, i);
49b424fe	415	cpu->hotpluggable = !!i;
f615136c MF	416	register_cpu(cpu, i);
	417	}
	418
	419	return 0;
	420	}
	421	subsys_initcall(topology_init);
	422
4f205687 MF	423	void cpu_reset(void)
4f205687 MF	424	{
4b3e6f2e	425	#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
bf15f86b MF	426	local_irq_disable();
	427	/*
	428	* We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
	429	* be flushed.
	430	* Way 4 is not currently used by linux.
	431	* Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
	432	* Way 5 shall be flushed and way 6 shall be set to identity mapping
	433	* on MMUv3.
	434	*/
	435	local_flush_tlb_all();
	436	invalidate_page_directory();
	437	#if XCHAL_HAVE_SPANNING_WAY
	438	/* MMU v3 */
	439	{
	440	unsigned long vaddr = (unsigned long)cpu_reset;
	441	unsigned long paddr = __pa(vaddr);
	442	unsigned long tmpaddr = vaddr + SZ_512M;
	443	unsigned long tmp0, tmp1, tmp2, tmp3;
	444
	445	/*
	446	* Find a place for the temporary mapping. It must not be
	447	* in the same 512MB region with vaddr or paddr, otherwise
	448	* there may be multihit exception either on entry to the
	449	* temporary mapping, or on entry to the identity mapping.
	450	* (512MB is the biggest page size supported by TLB.)
	451	*/
	452	while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
	453	tmpaddr += SZ_512M;
	454
	455	/* Invalidate mapping in the selected temporary area */
	456	if (itlb_probe(tmpaddr) & 0x8)
	457	invalidate_itlb_entry(itlb_probe(tmpaddr));
	458	if (itlb_probe(tmpaddr + PAGE_SIZE) & 0x8)
	459	invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
	460
	461	/*
	462	* Map two consecutive pages starting at the physical address
	463	* of this function to the temporary mapping area.
	464	*/
	465	write_itlb_entry(__pte((paddr & PAGE_MASK) \|
	466	_PAGE_HW_VALID \|
	467	_PAGE_HW_EXEC \|
	468	_PAGE_CA_BYPASS),
	469	tmpaddr & PAGE_MASK);
	470	write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) \|
	471	_PAGE_HW_VALID \|
	472	_PAGE_HW_EXEC \|
	473	_PAGE_CA_BYPASS),
	474	(tmpaddr & PAGE_MASK) + PAGE_SIZE);
	475
	476	/* Reinitialize TLB */
	477	__asm__ __volatile__ ("movi %0, 1f\n\t"
	478	"movi %3, 2f\n\t"
	479	"add %0, %0, %4\n\t"
	480	"add %3, %3, %5\n\t"
	481	"jx %0\n"
	482	/*
	483	* No literal, data or stack access
	484	* below this point
	485	*/
	486	"1:\n\t"
	487	/* Initialize tlbcfg /
	488	"movi %0, 0\n\t"
	489	"wsr %0, itlbcfg\n\t"
490	"wsr %0, dtlbcfg\n\t"
491	/* Invalidate TLB way 5 */
492	"movi %0, 4\n\t"
493	"movi %1, 5\n"
494	"1:\n\t"
495	"iitlb %1\n\t"
496	"idtlb %1\n\t"
497	"add %1, %1, %6\n\t"
498	"addi %0, %0, -1\n\t"
499	"bnez %0, 1b\n\t"
500	/* Initialize TLB way 6 */
501	"movi %0, 7\n\t"
502	"addi %1, %9, 3\n\t"
503	"addi %2, %9, 6\n"
504	"1:\n\t"
505	"witlb %1, %2\n\t"
506	"wdtlb %1, %2\n\t"
507	"add %1, %1, %7\n\t"
508	"add %2, %2, %7\n\t"
509	"addi %0, %0, -1\n\t"
510	"bnez %0, 1b\n\t"
511	/* Jump to identity mapping */
512	"jx %3\n"
513	"2:\n\t"
514	/* Complete way 6 initialization */
515	"witlb %1, %2\n\t"
516	"wdtlb %1, %2\n\t"
517	/* Invalidate temporary mapping */
518	"sub %0, %9, %7\n\t"
519	"iitlb %0\n\t"
520	"add %0, %0, %8\n\t"
521	"iitlb %0"
522	: "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
523	"=&a"(tmp3)
524	: "a"(tmpaddr - vaddr),
525	"a"(paddr - vaddr),
526	"a"(SZ_128M), "a"(SZ_512M),
527	"a"(PAGE_SIZE),
528	"a"((tmpaddr + SZ_512M) & PAGE_MASK)
529	: "memory");
530	}
531	#endif
532	#endif
ea951c34	533	__asm__ __volatile__ ("movi a2, 0\n\t"
4f205687 MF	534	"wsr a2, icountlevel\n\t"
	535	"movi a2, 0\n\t"
	536	"wsr a2, icount\n\t"
	537	#if XCHAL_NUM_IBREAK > 0
	538	"wsr a2, ibreakenable\n\t"
	539	#endif
	540	#if XCHAL_HAVE_LOOPS
	541	"wsr a2, lcount\n\t"
	542	#endif
	543	"movi a2, 0x1f\n\t"
	544	"wsr a2, ps\n\t"
	545	"isync\n\t"
	546	"jx %0\n\t"
	547	:
	548	: "a" (XCHAL_RESET_VECTOR_VADDR)
	549	: "a2");
	550	for (;;)
	551	;
	552	}
	553
5a0015d6 CZ	554	void machine_restart(char * cmd)
	555	{
	556	platform_restart();
	557	}
	558
	559	void machine_halt(void)
	560	{
	561	platform_halt();
	562	while (1);
	563	}
	564
	565	void machine_power_off(void)
	566	{
	567	platform_power_off();
	568	while (1);
	569	}
	570	#ifdef CONFIG_PROC_FS
	571
	572	/*
	573	* Display some core information through /proc/cpuinfo.
	574	*/
	575
	576	static int
	577	c_show(struct seq_file f, void slot)
	578	{
	579	/* high-level stuff */
f615136c	580	seq_printf(f, "CPU count\t: %u\n"
62518994	581	"CPU list\t: %*pbl\n"
f615136c MF	582	"vendor_id\t: Tensilica\n"
	583	"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
	584	"core ID\t\t: " XCHAL_CORE_ID "\n"
	585	"build ID\t: 0x%x\n"
	586	"byte order\t: %s\n"
	587	"cpu MHz\t\t: %lu.%02lu\n"
	588	"bogomips\t: %lu.%02lu\n",
	589	num_online_cpus(),
62518994	590	cpumask_pr_args(cpu_online_mask),
f615136c MF	591	XCHAL_BUILD_UNIQUE_ID,
	592	XCHAL_HAVE_BE ? "big" : "little",
	593	ccount_freq/1000000,
	594	(ccount_freq/10000) % 100,
	595	loops_per_jiffy/(500000/HZ),
	596	(loops_per_jiffy/(5000/HZ)) % 100);
5a0015d6 CZ	597
	598	seq_printf(f,"flags\t\t: "
	599	#if XCHAL_HAVE_NMI
	600	"nmi "
	601	#endif
	602	#if XCHAL_HAVE_DEBUG
	603	"debug "
	604	# if XCHAL_HAVE_OCD
	605	"ocd "
	606	# endif
	607	#endif
	608	#if XCHAL_HAVE_DENSITY
	609	"density "
	610	#endif
	611	#if XCHAL_HAVE_BOOLEANS
	612	"boolean "
	613	#endif
	614	#if XCHAL_HAVE_LOOPS
	615	"loop "
	616	#endif
	617	#if XCHAL_HAVE_NSA
	618	"nsa "
	619	#endif
	620	#if XCHAL_HAVE_MINMAX
	621	"minmax "
	622	#endif
	623	#if XCHAL_HAVE_SEXT
	624	"sext "
	625	#endif
	626	#if XCHAL_HAVE_CLAMPS
	627	"clamps "
	628	#endif
	629	#if XCHAL_HAVE_MAC16
	630	"mac16 "
	631	#endif
	632	#if XCHAL_HAVE_MUL16
	633	"mul16 "
	634	#endif
	635	#if XCHAL_HAVE_MUL32
	636	"mul32 "
	637	#endif
	638	#if XCHAL_HAVE_MUL32_HIGH
	639	"mul32h "
	640	#endif
	641	#if XCHAL_HAVE_FP
	642	"fpu "
2f6ea6a7 MF	643	#endif
	644	#if XCHAL_HAVE_S32C1I
	645	"s32c1i "
5a0015d6 CZ	646	#endif
	647	"\n");
	648
	649	/* Registers. */
	650	seq_printf(f,"physical aregs\t: %d\n"
	651	"misc regs\t: %d\n"
	652	"ibreak\t\t: %d\n"
	653	"dbreak\t\t: %d\n",
	654	XCHAL_NUM_AREGS,
	655	XCHAL_NUM_MISC_REGS,
	656	XCHAL_NUM_IBREAK,
	657	XCHAL_NUM_DBREAK);
	658
	659
	660	/* Interrupt. */
	661	seq_printf(f,"num ints\t: %d\n"
	662	"ext ints\t: %d\n"
	663	"int levels\t: %d\n"
	664	"timers\t\t: %d\n"
	665	"debug level\t: %d\n",
	666	XCHAL_NUM_INTERRUPTS,
	667	XCHAL_NUM_EXTINTERRUPTS,
	668	XCHAL_NUM_INTLEVELS,
	669	XCHAL_NUM_TIMERS,
	670	XCHAL_DEBUGLEVEL);
	671
5a0015d6 CZ	672	/* Cache */
	673	seq_printf(f,"icache line size: %d\n"
	674	"icache ways\t: %d\n"
	675	"icache size\t: %d\n"
	676	"icache flags\t: "
	677	#if XCHAL_ICACHE_LINE_LOCKABLE
415217ef	678	"lock "
5a0015d6 CZ	679	#endif
	680	"\n"
	681	"dcache line size: %d\n"
	682	"dcache ways\t: %d\n"
	683	"dcache size\t: %d\n"
	684	"dcache flags\t: "
	685	#if XCHAL_DCACHE_IS_WRITEBACK
415217ef	686	"writeback "
5a0015d6 CZ	687	#endif
5a0015d6 CZ	688	#if XCHAL_DCACHE_LINE_LOCKABLE
415217ef	689	"lock "
5a0015d6 CZ	690	#endif
	691	"\n",
	692	XCHAL_ICACHE_LINESIZE,
	693	XCHAL_ICACHE_WAYS,
	694	XCHAL_ICACHE_SIZE,
	695	XCHAL_DCACHE_LINESIZE,
	696	XCHAL_DCACHE_WAYS,
	697	XCHAL_DCACHE_SIZE);
	698
5a0015d6 CZ	699	return 0;
	700	}
	701
	702	/*
	703	* We show only CPU #0 info.
	704	*/
	705	static void *
	706	c_start(struct seq_file f, loff_t pos)
	707	{
f615136c	708	return (pos == 0) ? (void )1 : NULL;
5a0015d6 CZ	709	}
	710
	711	static void *
	712	c_next(struct seq_file f, void v, loff_t *pos)
	713	{
	714	return NULL;
	715	}
	716
	717	static void
	718	c_stop(struct seq_file f, void v)
	719	{
	720	}
	721
03a44825	722	const struct seq_operations cpuinfo_op =
5a0015d6	723	{
f615136c MF	724	.start = c_start,
	725	.next = c_next,
	726	.stop = c_stop,
	727	.show = c_show,
5a0015d6 CZ	728	};
	729
	730	#endif /* CONFIG_PROC_FS */